Multilayer ceramic electronic component and method of manufacturing the same
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-26
- Publication Date
- 2026-08-11
AI Technical Summary
[0010]根据本公开,能够提供抑制氢向坯体扩散的层叠陶瓷电子部件及其制造方法。
Smart Images

Figure CN122552352A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to laminated ceramic electronic components and methods for manufacturing the same. Background Technology
[0002] The external electrode of a multilayer ceramic electronic component, such as a multilayer ceramic capacitor, has a base metal layer in contact with the blank and a plating layer covering the base metal layer. It is known that in the external electrode, the outermost plating layer contains at least one of the elements that form covalent hydrides with hydrogen and elements that form hydrides with hydrogen boundary regions between the outermost plating layer and the blank (e.g., Patent Document 1). It is known that there is a region of Sn precipitation between the base metal layer and the Ni plating layer (e.g., Patent Document 2).
[0003] Patent Document 1: Japanese Patent Application Publication No. 2016-058719
[0004] Patent Document 2: International Publication No. 2024 / 047980
[0005] The coating contains a large amount of hydrogen. When the hydrogen in the coating diffuses into the preform, the insulation resistance of the dielectric layer decreases, and the reliability of the laminated ceramic electronic components is reduced when voltage is applied. Summary of the Invention
[0006] The purpose of this disclosure is to provide a laminated ceramic electronic component that suppresses hydrogen diffusion into the preform and a method for manufacturing the same.
[0007] An embodiment of this disclosure is a laminated ceramic electronic component comprising: a blank having alternately laminated a plurality of internal electrodes and a plurality of dielectric layers mainly composed of ceramic, the blank having end faces opposed in the length direction; a base metal layer disposed on the end face in such a manner as to contact at least a portion of the plurality of internal electrodes exposed from the end face; a cladding layer covering the base metal layer; and a plating layer covering the cladding layer, wherein the plating layer, the base metal layer, and the cladding layer form an external electrode.
[0008] An embodiment of this disclosure is a laminated ceramic electronic component comprising: a preform having alternately laminated a plurality of internal electrodes and a plurality of dielectric layers, the preform having opposing end faces in the longitudinal direction; a base metal layer disposed on the end face in contact with at least a portion of the plurality of internal electrodes exposed from the end face, the base metal layer having an opening; a cladding layer covering the base metal layer, the cladding layer being a sputtered layer; and a plating layer covering the cladding layer, the plating layer forming an external electrode together with the base metal layer and the cladding layer.
[0009] This disclosure discloses a method for manufacturing a laminated ceramic electronic component, comprising the following steps: preparing a blank having alternating layers of multiple internal electrodes and multiple dielectric layers primarily composed of ceramic, the blank having end faces facing each other along its length; forming a base metal layer disposed on the end face in contact with at least a portion of the multiple internal electrodes exposed from the end face, the base metal layer having an opening; forming a cladding layer covering the base metal layer using a sputtering method; and forming a plating layer covering the cladding layer using a plating method, the plating layer forming an external electrode together with the base metal layer and the cladding layer.
[0010] According to this disclosure, a laminated ceramic electronic component that suppresses hydrogen diffusion into the preform and a method for manufacturing the same can be provided. Attached Figure Description
[0011] Figure 1 This is a partial cross-sectional perspective view of the multilayer ceramic capacitor 100 according to the first embodiment.
[0012] Figure 2 It is along Figure 1 A cross-sectional view along line AA.
[0013] Figure 3 It is along Figure 1 A cross-sectional view of the BB line.
[0014] Figure 4 This is a flowchart illustrating a method for manufacturing a multilayer ceramic capacitor according to the first embodiment.
[0015] Figure 5 (A) to Figure 5 (D) is a perspective view showing a method for manufacturing a multilayer ceramic capacitor according to the first embodiment.
[0016] Figure 6 This is a cross-sectional view of the multilayer ceramic capacitor in comparison method 1.
[0017] Figure 7 This is a cross-sectional view of the multilayer ceramic capacitor in comparison method 2.
[0018] Figure 8 This is a cross-sectional view of the laminated ceramic capacitor of Example 1 of the first embodiment.
[0019] Figure 9 This is a cross-sectional view of the stacked ceramic capacitor of Example 2 of the first embodiment.
[0020] Figure 10 This is an enlarged cross-sectional view near the opening 46B in Example 2 of the first embodiment.
[0021] Figure 11This is an enlarged cross-sectional view near the opening 46A of Example 2 of the first embodiment.
[0022] Figure 12 This is a side view of the stacked ceramic capacitor according to the first embodiment.
[0023] Figure 13 This is an enlarged cross-sectional view of the area near the cladding layer of the stacked ceramic capacitor of the first embodiment.
[0024] Label Explanation
[0025] 10: Blank; 12A, 12B: Internal electrodes; 14: Dielectric layer; 16: Covering dielectric layer; 18: Side edge region; 20A, 20B: External electrodes; 21: Base metal layer; 22: Coating layer; 22A: 4th layer; 22B: 5th layer; 23: Plating layer; 23A: 1st layer; 23B: 2nd layer; 23C: 3rd layer; 30: Grain boundary; 32: Grain; 40: End; 41, 42: End; 46A, 46B: Opening; 51, 52: End face; 53, 54: Side face; 55: Lower surface; 56: Upper surface. Detailed Implementation
[0026] The embodiments of this disclosure will be described in detail below, but this disclosure is not limited thereto. Furthermore, in this specification and accompanying drawings, elements having substantially the same functional structure are sometimes omitted from repeated descriptions by using the same reference numerals.
[0027] (First Embodiment)
[0028] As a multilayer ceramic electronic component, the multilayer ceramic capacitor will be used as an example for explanation. Figure 1 This is a partial cross-sectional perspective view of the multilayer ceramic capacitor 100 according to the first embodiment. Figure 2 It is along Figure 1 A cross-sectional view along line AA. Figure 3 It is along Figure 1 A cross-sectional view of the BB line.
[0029] exist Figures 1 to 3 In this context, the Z direction (first direction) is the stacking direction of the dielectric layer 14, the internal electrode 12A, and the internal electrode 12B, and is the direction opposite to the lower surface 55 and the upper surface 56 of the billet 10. The X direction (second direction) is the length direction of the billet 10, and is the direction opposite to the pair of end faces 51 and 52 of the billet 10. The Y direction (third direction) is the width direction of the internal electrodes 12A and 12B, and is the direction opposite to the pair of side faces 53 and 54 of the billet 10. The X, Y, and Z directions intersect or are perpendicular to each other.
[0030] The multilayer ceramic capacitor 100 has a blank 10 and external electrodes 20A and 20B. The blank 10 has a generally cuboid shape. The blank 10 has a plurality of dielectric layers 14, a plurality of internal electrodes 12A and a plurality of internal electrodes 12B, and a covering dielectric layer 16. The plurality of internal electrodes 12A and the plurality of internal electrodes 12B are stacked alternately. One of the plurality of dielectric layers 14 is disposed between one of the plurality of internal electrodes 12A and one of the plurality of internal electrodes 12B. The outermost layer in the Z direction of the multilayer obtained by stacking the dielectric layer 14, the internal electrodes 12A and the internal electrodes 12B is the internal electrodes 12A and the internal electrodes 12B. The lower and upper surfaces of the multilayer are covered by the covering dielectric layer 16. The region in the Y direction where the plurality of internal electrodes 12A and the plurality of internal electrodes 12B are sandwiched is the side edge region 18.
[0031] Internal electrodes 12A and 12B are alternately exposed on end faces 51 and 52. Internal electrode 12A is exposed from end face 51, while internal electrode 12B is not exposed from end face 51. Internal electrode 12B is exposed from end face 52, while internal electrode 12A is not exposed from end face 52. That is, internal electrodes 12A and 12B are connected to different end faces 51 and 52.
[0032] External electrode 20A contacts internal electrode 12A exposed from billet 10 at end face 51. External electrode 20B contacts internal electrode 12B exposed from billet 10 at end face 52. External electrode 20A covers end face 51, as well as side faces 53 and 54, lower surface 55, and end portion 40 of upper surface 56 in the -X direction. End portion 40 is the portion of the billet 10 on the side of end face 51 and end face 52 that connects to end face 51 and end face 52. External electrode 20B contacts internal electrode 12B at end face 52. External electrode 20B covers end face 52, as well as side faces 53 and 54, lower surface 55, and end portion 40 of upper surface 56 in the +X direction.
[0033] External electrodes 20A and 20B each have a base metal layer 21, a cladding layer 22, and a plating layer 23. The cladding layer 22 covers the base metal layer 21. The plating layer 23 covers the cladding layer 22. On the sides 53 and 54, the lower surface 55, and the upper surface 56, the cladding layer 22 contacts the blank 10 at a position slightly outer from the end of the base metal layer 21. The plating layer 23 contacts the blank 10 at a position slightly outer from the end of the cladding layer 22.
[0034] The dimensions of the multilayer ceramic capacitor 100 are, for example, a length (length in the X direction) of 0.25 mm, a width (width in the Y direction) of 0.125 mm, and a height (height in the Z direction) of 0.125 mm, or a length of 0.4 mm, a width of 0.2 mm, and a height of 0.2 mm, or a length of 0.6 mm, a width of 0.3 mm, and a height of 0.3 mm, or a length of 1.0 mm, a width of 0.5 mm, and a height of 0.5 mm, or a length of 3.2 mm, a width of 1.6 mm, and a height of 1.6 mm, or a length of 4.5 mm, a width of 3.2 mm, and a height of 2.5 mm, but are not limited to these dimensions.
[0035] The internal electrodes 12A and 12B are primarily composed of base metals such as nickel (Ni), copper (Cu), and tin (Sn). Noble metals such as platinum (Pt), palladium (Pd), silver (Ag), or gold (Au), or alloys containing them, may also be used as the internal electrodes 12A and 12B. The thickness of the internal electrodes 12A and 12B is, for example, 0.1 μm or more and 1 μm or less.
[0036] The dielectric layer 14 is, for example, a ceramic material having a perovskite structure represented by the general formula ABO3 as the main phase. Furthermore, this perovskite structure contains a non-stoichiometric composition of ABO3. 3-α For example, as this ceramic material, barium titanate (BaTiO3), calcium zirconate (CaZrO3), calcium titanate (CaTiO3), strontium titanate (SrTiO3), magnesium titanate (MgTiO3), and Ba, which forms a perovskite structure, can be used. 1-x-y Ca x Sr y Ti 1-z Zr z Use at least one of the following: O3 (0≤x≤1, 0≤y≤1, 0≤z≤1), etc. Ba 1-x-y Ca x Sr y Ti 1-z Zr z O3 can be barium strontium titanate, barium calcium titanate, barium zirconate, barium zirconate titanate, calcium zirconate titanate, or barium calcium zirconate titanate. For example, the dielectric layer 14 contains at least 90 atomic percent of the main component ceramic. The thickness of the dielectric layer 14 is, for example, 0.3 μm or more and 2 μm or less.
[0037] Additives may be added to the dielectric layer 14. Examples of additives for the dielectric layer 14 include oxides of zirconium (Zr), hafnium (Hf), magnesium (Mg), manganese (Mn), molybdenum (Mo), vanadium (V), chromium (Cr), oxides of rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb)), oxides containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), or silicon (Si), or glasses containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon.
[0038] The composition of the main component ceramic covering the dielectric layer 16 can be the same as or different from that of the main component ceramic covering the dielectric layer 14.
[0039] The base metal layer 21 is primarily composed of metals such as copper, nickel, aluminum (Al), and zinc (Zn), or alloys of two or more of them (e.g., an alloy of copper and nickel), and contains a glass component for densifying the base metal layer 21, a common ceramic material for controlling the sinterability of the external electrodes 20A and 20B, etc. The glass component is an oxide of barium (Ba), strontium (Sr), calcium (Ca), zinc, aluminum, silicon, or boron. The thickness of the base metal layer 21 is, for example, 3 μm to 50 μm.
[0040] The cladding layer 22 is, for example, a laminate of metals such as copper, titanium, molybdenum, tantalum, chromium, aluminum, aluminum oxide, or tin, or having two or more of these metal layers. The cladding layer 22, for example, does not contain nickel as a main component. The cladding layer 22 is, for example, a layer formed by sputtering. The thickness of the cladding layer 22 is, for example, 3 nm to 2 μm.
[0041] The plating layer 23 is primarily composed of metals such as copper, nickel, aluminum, zinc, or tin, or alloys of two or more of them. The plating layer 23 can be a single-metal plating layer or multiple plating layers with different metal compositions. Furthermore, a film of conductive resin such as epoxy resin or polyurethane resin can be formed on the surface of the plating layer 23. The thickness of the plating layer 23 is, for example, 5 μm to 15 μm.
[0042] (Manufacturing method of the first embodiment)
[0043] The manufacturing method of the multilayer ceramic capacitor 100 is described. Figure 4 This is a flowchart illustrating a method for manufacturing a multilayer ceramic capacitor according to the first embodiment.
[0044] (Green slice formation process)
[0045] First, a green sheet is formed (step S10). In step S10, a dielectric material is prepared, for example, by adding various additive compounds (sintering aids, etc.) to ceramic powder. A slurry is generated by adding a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer to the prepared dielectric material and performing wet mixing. Using the generated slurry, the green sheet is coated onto a substrate, for example, by a die-coating method or a doctor blade method. The substrate is, for example, a PET (polyethylene terephthalate) film. Then, the green sheet is dried.
[0046] (Pattern forming process)
[0047] Next, metal patterns serving as internal electrodes 12A and 12B are formed on the green sheet (step S12). In step S12, a conductive paste containing an organic binder for forming the internal electrodes is printed onto the green sheet on a substrate using, for example, gravure printing. Thus, multiple metal patterns corresponding to the internal electrodes 12A and 12B are formed into a film on the green sheet, separated from each other. The conductive paste contains metal powder, such as nickel powder, as a main component, a binder, and an organic solvent. Ceramic particles may also be added to the conductive paste as a common material.
[0048] (Layering process)
[0049] Next, the green sheets are stacked (step S14). In step S14, a stacked sheet is formed by stacking green sheets printed with metal patterns as internal electrodes 12A and 12B. Green sheets corresponding to the covering dielectric layer 16 are stacked on both ends of the stacked sheet in the stacking direction.
[0050] (Crimping process)
[0051] Next, the laminated sheets are crimped (step S16). In step S16, multiple green sheets are crimped together by applying pressure to the laminated sheets formed in step S14. As a crimping method, isostatic pressing is used, for example.
[0052] (Cutting process)
[0053] Next, the laminated sheets are cut (step S18). In step S18, the laminated sheets are cut along a predetermined cutting line in the lamination direction using a cutting blade, thereby preparing multiple blanks 10. In the blanks 10, the internal electrode 12A is exposed from the end face 51, and the internal electrode 12B is exposed from the end face 52. After step S18, the blanks 10 can be ground by methods such as tumbling. As a result, the corners of the blanks 10 are rounded.
[0054] (Firing process)
[0055] Next, the green body 10 is fired (step S20). In step S20, the green body 10 is subjected to a binder removal treatment in a nitrogen atmosphere at 250°C to 500°C, and then fired in a reducing atmosphere at 1300°C to 1400°C for about 1 hour. As a result, the green body 10 and the individual particles of the internal electrodes 12A and 12B are sintered.
[0056] (External electrode formation process)
[0057] Next, external electrodes 20A and 20B are formed (step S26). Step S26 includes steps S21 to S25. Figure 5 (A) to Figure 5 (D) is a perspective view showing a method for manufacturing a multilayer ceramic capacitor according to the first embodiment.
[0058] First, a paste is applied to the blank 10 (step S21). For example, the paste is applied to the end 40 and end face 51 of the blank 10 using, for example, an impregnation method. The paste contains metal particles, glass particles (glass frit), binder, and organic solvent as its main components.
[0059] Next, the paste is sintered (step S22). In step S22, the paste, which serves as the raw material for the base metal layer 21, is sintered in a nitrogen atmosphere at a temperature of 750°C to 850°C, which is lower than the firing temperature in step S20. Thus, as... Figure 5 As shown in (A), the paste is sintered to form a base metal layer 21 on the green body 10. Alternatively, the green body 10 and the paste can be sintered in step S22 without performing the firing process S20. In this case, the firing conditions are the same as in step S20.
[0060] Next, a cladding layer 22 is formed on the blank 10 and the base metal layer 21 (step S23). For example... Figure 5 As shown in (B), the coating layer 22 is formed on all six faces of the blank 10. The coating layer 22 is formed using a sputtering method. For example, powder sputtering is used as the sputtering method. Powder sputtering is a method of forming a sputtered film on the surface of powder. By using powder sputtering, even if the object to be sputtered is small in shape and area, it is possible to sputter uniformly over the entire surface. Thus, the coating layer 22 is formed on all six faces of the blank 10. Furthermore, for example, by masking any part of the hexahedron before sputtering, the coating layer 22 can be sputtered at any part of the hexahedron.
[0061] Next, the covering layer 22 at the center of the blank 10 in the X direction is removed (step S24). For example... Figure 5As shown in (C), the cladding layer 22 at the center of the blank 10 in the X direction is removed. The distance L2 in the X direction between the end 42 of the cladding layer 22 and the end face 52 is made greater than the distance L1 in the X direction between the end 41 of the base metal layer 21 and the end face 52. As a result, the front end of the cladding layer 22 contacts the blank 10. As part of the method for removing the cladding layer 22, a laser can be used, for example. When the cladding layer 22 is formed at any location on the hexahedron by masking, step S24 can be omitted.
[0062] Next, coating 23 is formed (process S25). For example... Figure 5 As shown in (D), a plating layer 23 is formed by covering the cladding layer 22. The base metal layer 21, the cladding layer 22, and the plating layer 23 form the external electrode 20A and the external electrode 20B.
[0063] (Comparison with multilayer ceramic capacitors in method 1)
[0064] Figure 6 This is a cross-sectional view of the multilayer ceramic capacitor used in comparison method 1. (Example) Figure 6 As shown, the multilayer ceramic capacitor 110 of Comparison Method 1 does not have a covering layer 22. The base metal layer 21 is mainly composed of nickel. The plating layer 23 has a first layer 23A, a second layer 23B, and a third layer 23C. The first layer 23A covers the base metal layer 21. The second layer 23B covers the first layer 23A. The third layer 23C covers the second layer 23B. The first layer 23A is mainly composed of copper. The second layer 23B is mainly composed of nickel. The third layer 23C is mainly composed of tin.
[0065] The third layer 23C is used for solder bonding during solder mounting of the multilayer ceramic capacitor 110. The second layer 23B is a barrier layer between the first layer 23A and the third layer 23C. Regarding the first layer 23A, since the base metal layer 21 is mainly composed of nickel, it is difficult to directly plate the second layer 23B, which is mainly composed of nickel, onto the base metal layer 21. Therefore, the first layer 23A is mainly composed of copper, which is easy to directly plate onto the base metal layer 21. The second layer 23B, which is mainly composed of nickel, is easy to plate onto the first layer 23A, which is mainly composed of copper.
[0066] The plating layer 23 contains a large amount of hydrogen. With the base metal layer 21 being predominantly nickel, hydrogen readily diffuses and is easily stored within it. Therefore, as indicated by arrow 44A, it is considered that hydrogen (or hydrogen ions H+)... + Hydrogen will diffuse from plating 23 into the base metal layer 21 and the blank 10 to reach the internal electrode 12A or 12B. Furthermore, as indicated by arrow 44B, hydrogen will diffuse from plating 23 through the base metal layer 21 to the internal electrode 12A. It is believed that hydrogen will also diffuse into the adjacent dielectric layer 14. Consequently, the insulation resistance of the dielectric layer 14 decreases.
[0067] (Comparison with multilayer ceramic capacitors in method 2)
[0068] Figure 7 This is a cross-sectional view of the multilayer ceramic capacitor used in comparison method 2. (Example) Figure 7 As shown, the multilayer ceramic capacitor 112 of Comparison Method 2 does not have a cladding layer 22. The base metal layer 21 is mainly composed of copper. The plating layer 23 has a second layer 23B and a third layer 23C. The second layer 23B covers the base metal layer 21. The third layer 23C covers the second layer 23B. The second layer 23B is mainly composed of nickel. The third layer 23C is mainly composed of tin.
[0069] In the multilayer ceramic capacitor 112 of Comparison Method 2, the base metal layer 21 is mainly composed of copper. Therefore, it is easy to plate a second layer 23B, which is mainly composed of nickel, onto the base metal layer 21. Thus, the first layer 23A may not be provided.
[0070] In Comparative Method 2, the base metal layer 21 is mainly composed of copper, therefore hydrogen is less likely to diffuse in the base metal layer 21 compared to Comparative Method 1. However, as the base metal layer 21 becomes thinner with the miniaturization of the multilayer ceramic capacitor, openings 46A and 46B are easily formed in the base metal layer 21. Sometimes, the plating layer 23 contacts the blank 10 on the bottom surface of openings 46A and 46B. Opening 46A is an opening formed at the corner of the end face 51 and end face 52 of the blank 10 and the side faces 53, 54, lower surface 55, and upper surface 56. The base metal layer 21 at the corner of the blank 10 is thin, therefore opening 46A is easily formed at the corner. Opening 46B is an opening formed on the end face 51 of the blank 10.
[0071] As indicated by arrow 44C, at opening 46A, hydrogen diffuses from plating 23 within the blank 10 to reach internal electrode 12A or internal electrode 12B. Furthermore, as indicated by arrow 44D, hydrogen reaches internal electrode 12A from plating 23. Hydrogen diffuses within internal electrodes 12A and 12B, penetrating into the dielectric layer 14 opposite to internal electrodes 12A and 12B. Consequently, similar to Comparative Embodiment 1, the insulation resistance of the dielectric layer decreases.
[0072] (Example 1 of the first embodiment)
[0073] Figure 8 This is a cross-sectional view of the multilayer ceramic capacitor of Example 1 of the first embodiment. Figure 8As shown, in the multilayer ceramic capacitor 102 of Example 1 of the first embodiment, a cladding layer 22 is provided between the base metal layer 21 and the plating layer 23. The end 42 of the cladding layer 22 is located at a position +X side closer than the end 41 of the base metal layer 21. The cladding layer 22, from the base metal layer 21 side, consists of, for example, a fourth layer 22A and a fifth layer 22B. The fourth layer 22A is a bonding layer between the base metal layer 21 and the fifth layer 22B, and is primarily composed of titanium, tantalum, or chromium; for example, titanium is the primary component. The fifth layer 22B is a layer on which the plating layer 23 can be easily plated, and is primarily composed of copper, for example. Other structures are the same as in Comparative Embodiment 1, except that the base metal layer 21 is primarily composed of nickel.
[0074] The coating layer 22 formed by sputtering has a low hydrogen content. Compared to nickel, the hydrogen diffusion coefficient in the coating layer 22 is small, and hydrogen is less likely to be stored in it. Therefore, hydrogen within the plating layer 23 does not easily diffuse to the base metal layer 21. Thus, as shown by arrows 45A and 45B, the coating layer 22 acts as a hydrogen barrier, preventing hydrogen from easily diffusing through the base metal layer 21 and the blank 10 to the internal electrodes 12A and 12B, thereby suppressing a decrease in the insulation resistance of the dielectric layer 14.
[0075] (Example 2 of the first embodiment)
[0076] Figure 9 This is a cross-sectional view of the multilayer ceramic capacitor of Example 2 of the first embodiment. Figure 9 As shown, in the multilayer ceramic capacitor 104 of Example 2 of the first embodiment, a cladding layer 22 is provided between the base metal layer 21 and the plating layer 23. The structure of the cladding layer 22 is the same as that of Example 1 of the first embodiment. Other structures are the same as those in Comparative Example 2, and the base metal layer 21 is mainly composed of copper.
[0077] The coating layer 22 covers the inner surfaces of openings 46A and 46B. Therefore, as shown by arrows 45C and 45D, the coating layer 22 acts as a barrier against hydrogen, preventing hydrogen from easily diffusing from the blank 10 at openings 46A and 46B to the inner electrodes 12A and 12B. Consequently, hydrogen does not easily diffuse from the inner electrodes 12A and 12B into the dielectric layer 14, thus suppressing a decrease in the insulation resistance of the dielectric layer 14.
[0078] Figure 10 This is an enlarged cross-sectional view near opening 46B in Example 2 of the first embodiment. (See attached image.) Figure 10 As shown, the cladding layer 22 covers the entire inner surface of the opening 46B. The maximum width of the billet 10 exposed from the opening 46B is W1. Furthermore, the maximum width W1 is the maximum width of the area of the billet 10 exposed from the base metal layer 21. The thickness of the cladding layer 22 outside the opening 46A is T1. The thickness of the base metal layer 21 outside the opening 46A is T2.
[0079] Figure 11 This is an enlarged cross-sectional view near opening 46A in Example 2 of the first embodiment. (See attached image.) Figure 11 As shown, the cladding layer 22 completely covers the inner surface of the opening 46A. The maximum width of the blank 10 exposed from the opening 46A along the surface is W1. The thickness of the cladding layer 22 outside the opening 46A is T1. The thickness of the base metal layer 21 outside the opening 46A is T2.
[0080] When the cladding layer 22 is formed using a sputtering method, it can be formed in a way that covers the entire inner surface of openings 46A and 46B. Furthermore, the cladding layer 22 can be made relatively thin. For example, when a plating method is used to form a coating that covers the inner surfaces of openings 46A and 46B, the thickness of the coating is at least half the maximum width W1. When the cladding layer 22 is formed using a sputtering method, the thickness T1 of the cladding layer 22 can be smaller than half the maximum width W1.
[0081] According to the first embodiment, such as Figure 4 Similar to steps S23 and S24, a coating layer 22 covering the base metal layer 21 is formed using a sputtering method. As in step S25, a plating layer 23 covering the coating layer 22 is formed. Thus, a sputtered layer is used as the coating layer 22. Compared to the plating layer 23, the sputtered layer has a lower hydrogen concentration. This suppresses hydrogen diffusion from the plating layer 23 to the blank 10, and suppresses the decrease in the insulation resistance of the dielectric layer 14. Furthermore, by making the coating layer 22 a metal layer, the base metal layer 21 can be in electrical contact with the plating layer 23. The coating layer 22 is preferably configured so that the base metal layer 21 is not exposed. When the coating layer 22 is provided on a portion of the surface of the base metal layer 21 and has a contact area between the base metal layer 21 and the plating layer 23, the coating layer 22 can also be an insulating layer.
[0082] like Figure 7 As shown, when the base metal layer 21 has openings 46A and 46B that expose the blank 10, hydrogen in the plating layer 23 can easily diffuse into the blank 10. Therefore, the cladding layer 22 is configured to cover the inner surfaces of openings 46A and 46B. This suppresses the diffusion of hydrogen from the plating layer 23 into the blank 10 via openings 46A and 46B. Consequently, the degradation of the characteristics of the multilayer ceramic capacitor can be suppressed.
[0083] It is possible Figure 10 and Figure 11As shown, the thickness T1 of the cladding layer 22 is less than half the maximum width W1 of the bottom surfaces of openings 46A and 46B. This allows the cladding layer 22 to be relatively thin. The thickness T1 can be less than 1 / 5 or less than 1 / 10 of the maximum width W1. The thickness T1 is, for example, less than 1 / 10 or less than 1 / 20 of the thickness T2 of the base metal layer 21. From the viewpoint that the cladding layer 22 functions as a hydrogen diffusion prevention layer, the thickness T1 is preferably 3 nm or more, more preferably 10 nm or more.
[0084] If the maximum width W1 is too large, the resistance of the external electrodes 20A and 20B will increase. From this point of view, the maximum width W1 is preferably 5 times or less than, for example, the thickness T2 of the base metal layer 21, and more preferably 2 times or less. When the maximum width W1 is small, it hardly affects the diffusion of hydrogen from the coating 23 to the blank 10. From this point of view, the maximum width W1 is, for example, 1 / 100 or more of the thickness T2 of the base metal layer 21.
[0085] like Figure 5 As shown in (B), a coating layer 22 is formed on the base metal layer 21 and the side surfaces 53, 54, lower surface 55, and upper surface 56 (the surface connected to the end faces 51 and 52) of the blank 10 exposed from the base metal layer 21 using a sputtering method. Figure 5 As shown in (C), the coating layer 22 in the central part of the sides 53, 54, the lower surface 55, and the upper surface 56 in the X direction is removed. Thus, the coating layer 22 can be formed at the end 40 of the blank 10.
[0086] When the cladding layer 22 is primarily composed of nickel, hydrogen readily diffuses within it. Therefore, the cladding layer 22 is primarily composed of a metallic element other than nickel. Metallic elements that suppress hydrogen diffusion include, for example, copper, titanium, molybdenum, tantalum, chromium, aluminum, or tin.
[0087] It is possible Figure 8 and Figure 9 As shown, the cladding layer 22 has a fourth layer 22A and a fifth layer 22B. By using titanium, molybdenum, or chromium as the main components of the fourth layer 22A, the adhesion between the base metal layer 21 and the fifth layer 22B can be improved. By using copper as the main component of the fifth layer 22B, it is easy to plate the coating layer 23.
[0088] Figure 12 This is a side view of the multilayer ceramic capacitor according to the first embodiment. Figure 12 The diagram illustrates the end 41 of the base metal layer 21 and the end 42 of the cladding layer 22 on the surface (side 53) of the blank 10. Figure 12 As shown, if like Figure 4If the base metal layer 21 is formed by applying paste and sintering as in processes S21 and S22, it is difficult to form the end 41 with good precision. Therefore, the end 42 of the side surface 53 has unevenness in the X direction. The shortest distance between the end face 51 and the end 41 is L1A, and the longest distance is L1B. The difference between distance L1A and distance L1B is L3.
[0089] like Figure 2 , Figure 3 as well as Figure 5 As in (A), the base metal layer 21 has a portion disposed on the end face 51 and an extension that wraps around the surface of the blank 10 adjacent to the end face 51 (i.e., the portion of the base metal layer 21 at the end 40). Figure 5 As shown in (B), a cladding layer 22 is formed using a sputtering method on the base metal layer 21 and the side surfaces 53, 54, lower surface 55, and upper surface 56 (the surfaces adjacent to end faces 51 and 52) of the blank 10 exposed from the base metal layer 21. Figure 5 As shown in (C), the cladding layer 22 is removed from the central portion of the sides 53, 54, the lower surface 55, and the upper surface 56 in the X direction. This allows the cladding layer 22 to be formed at the end 40 of the blank 10. The end 42 (end) of the cladding layer 22 is located on the side opposite to the end face 51, closer to the end 41 of the base metal layer 21. Therefore, the cladding layer 22 is in contact with the blank 10. That is, the end of the cladding layer 22 extends further in the X direction than the extension at the end 40 of the base metal layer 21. The surface of the end of the cladding layer 22 that extends further in the X direction than the extension of the base metal layer 21 is at least one of the sides 53, 54, the lower surface 55, and the upper surface 56 of the blank 10.
[0090] By making the distance L2 greater than the distance L1B, the area of the external electrodes 20A and 20B at the end 40 can be increased. This increases the area for bonding with the mounting substrate using solder when mounting the multilayer ceramic capacitor. Consequently, peeling of the multilayer ceramic capacitor from the mounting substrate can be suppressed. The distance L2 is preferably at least 1.1 times the distance L1B, more preferably at least 1.2 times. For example, the distance L2 to distance L1B is 10 μm to 100 μm.
[0091] Furthermore, such as process S24 and Figure 5 As shown in (C), by removing a portion of the coating layer 22, the end 42 can be formed with good precision. Therefore, the distance L2 between the end face 51 and the end 42 can be made accurate and approximately constant. For example, in the process of removing a portion of the coating layer 22, a laser is used to remove the coating layer 22, thereby enabling the end 42 to be formed with good precision.
[0092] In the sides 53, 54, the lower surface 55, and the upper surface 56, the unevenness of the end 42 (end point) of the cladding layer 22 is smaller than that of the end 41 (end point) of the base metal layer. This allows for the precise formation of the area at the ends 40 of the external electrodes 20A and 20B. For example, the distance L3 is 10 μm to 250 μm.
[0093] Figure 13 This is an enlarged cross-sectional view of the area near the cladding layer of the stacked ceramic capacitor of the first embodiment. Figure 13 This is an enlarged cross-sectional view of the external electrode 20A disposed on the end face 51, with the thickness direction of the coating layer 22 designated as the X direction, and the surface directions of the coating layer 22 designated as the Y and Z directions. For example... Figure 13 As shown, the coating layer 22 formed by sputtering mostly has a columnar structure. That is, the coating layer 22 mostly contains columnar grains 32. The interface of the grains 32 is a grain boundary 30.
[0094] In the columnar structure, for at least one of the grains 32, the width WX in the X direction of grain 32 is at least 1.2 times, at least 2 times, or at least 5 times the width WY in the Y direction of grain 32. The grains 32 can be observed, for example, using a TEM (Transmission Electron Microscope).
[0095] In the first embodiment, "a certain layer uses a certain element as the main component" means that as long as a certain component contains an element to a degree that can achieve the effect of the embodiment, the concentration of the element in the component is, for example, 50 mol% or more, 80 mol% or more, or 90 mol% or more.
[0096] The embodiments have been described in detail above, but this disclosure is not limited to the specific embodiments and various modifications and alterations can be made within the scope of the claims.
[0097] The embodiments disclosed above include, for example, the following methods.
[0098] <1>
[0099] A laminated ceramic electronic component includes: a blank having a plurality of internal electrodes and a plurality of dielectric layers, primarily composed of ceramic, alternately stacked thereon, the blank having opposing end faces in the longitudinal direction; a base metal layer disposed on the end faces in contact with at least a portion of the plurality of internal electrodes exposed from the end faces; a cladding layer covering the base metal layer; and a plating layer covering the cladding layer, wherein the plating layer, the base metal layer, and the cladding layer form external electrodes.
[0100] <2>
[0101] According to the laminated ceramic electronic component of <1>, the base metal layer has a portion disposed on the end face and an extension portion extending around the surface of the blank adjacent to the end face, and the end of the cladding layer extends much further than the extension portion of the base metal layer in the length direction.
[0102] <3>
[0103] According to the laminated ceramic electronic component described in <2>, on the surface adjacent to the end face, the end of the cladding layer has a smaller unevenness compared to the end of the base metal layer.
[0104] <4>
[0105] The laminated ceramic electronic component according to any one of <1> to <3>, wherein the cladding layer comprises columnar grains.
[0106] <5>
[0107] The laminated ceramic electronic component according to any one of <1> to <4>, wherein the cladding layer is mainly composed of a metallic element other than nickel.
[0108] <6>
[0109] The laminated ceramic electronic component according to any one of <1> to <5>, wherein the base metal layer has an opening that exposes the blank, and the cladding layer covers the inner surface of the opening.
[0110] <7>
[0111] According to the stacked ceramic electronic component described in <6>, the thickness of the cladding layer is less than 1 / 2 of the maximum width of the bottom surface of the opening.
[0112] <8>
[0113] According to the stacked ceramic electronic component described in <6> or <7>, the opening is provided at the corner of the end face and the face connected to the end face.
[0114] <9>
[0115] A laminated ceramic electronic component comprising: a preform having alternately laminated a plurality of internal electrodes and a plurality of dielectric layers, the preform having opposing end faces in the longitudinal direction; a base metal layer disposed on the end faces in contact with at least a portion of the plurality of internal electrodes exposed from the end faces, the base metal layer having an opening; a cladding layer covering the base metal layer, the cladding layer being a sputtered layer; and a plating layer covering the cladding layer, the plating layer forming an external electrode together with the base metal layer and the cladding layer.
[0116] <10>
[0117] A method for manufacturing a laminated ceramic electronic component includes the following steps: preparing a blank having alternating layers of multiple internal electrodes and multiple dielectric layers of ceramic as the main component, the blank having end faces facing each other in the length direction; forming a base metal layer disposed on the end face in such a way as to contact at least a portion of the multiple internal electrodes exposed from the end face, the base metal layer having an opening; forming a cladding layer covering the base metal layer using a sputtering method; and forming a plating layer covering the cladding layer using a plating method, the plating layer, the base metal layer, and the cladding layer forming an external electrode.
[0118] <11>
[0119] According to the manufacturing method of the laminated ceramic electronic component described in <10>, the step of forming the cladding layer includes the following steps: forming the cladding layer on the substrate metal layer and on the surface of the blank exposed from the substrate metal layer adjacent to the end face using the sputtering method; and removing the cladding layer from the central portion of the surface adjacent to the end face in the direction opposite to the end face.
Claims
1. A laminated ceramic electronic component, comprising: A blank having multiple internal electrodes and multiple dielectric layers of ceramic as the main component stacked alternately, the blank having end faces facing each other in the length direction; A base metal layer is disposed on the end face in such a way that it contacts at least a portion of the plurality of internal electrodes exposed from the end face; A covering layer that covers the base metal layer; as well as A plating layer that covers the cladding layer, forming an external electrode together with the base metal layer and the cladding layer.
2. The laminated ceramic electronic component according to claim 1, wherein, The base metal layer has a portion disposed on the end face and an extension portion that wraps around the surface of the blank adjacent to the end face. The end of the cladding layer extends much further in the length direction than the extension of the base metal layer.
3. The laminated ceramic electronic component according to claim 2, wherein, On the surface adjacent to the end face, the end of the cladding layer has less unevenness compared to the end of the base metal layer.
4. The laminated ceramic electronic component according to any one of claims 1 to 3, wherein, The coating layer comprises columnar grains.
5. The laminated ceramic electronic component according to any one of claims 1 to 3, wherein, The coating layer is mainly composed of metallic elements other than nickel.
6. The laminated ceramic electronic component according to any one of claims 1 to 3, wherein, The base metal layer has an opening that exposes the blank. The covering layer covers the inner surface of the opening.
7. The laminated ceramic electronic component according to claim 6, wherein, The thickness of the covering layer is less than 1 / 2 of the maximum width of the bottom surface of the opening.
8. The laminated ceramic electronic component according to claim 6, wherein, The opening is located at the corner of the end face and the face connected to the end face.
9. A laminated ceramic electronic component, comprising: A blank having multiple internal electrodes and multiple dielectric layers of ceramic as the main component stacked alternately, the blank having end faces facing each other in the length direction; A base metal layer is disposed on the end face in such a way that it contacts at least a portion of the plurality of internal electrodes exposed from the end face, the base metal layer having an opening; A coating layer that covers the substrate metal layer, the coating layer being a sputtered layer; as well as A plating layer that covers the cladding layer, forming an external electrode together with the base metal layer and the cladding layer.
10. A method for manufacturing a laminated ceramic electronic component, comprising the following steps: Prepare a blank, which has multiple internal electrodes and multiple dielectric layers with ceramic as the main component stacked alternately, and the blank has end faces that are opposite each other in the length direction. A base metal layer is formed on the end face in such a way that it contacts at least a portion of the plurality of internal electrodes exposed from the end face, the base metal layer having an opening; A coating layer covering the base metal layer is formed using a sputtering method; as well as A plating method is used to form a plating layer covering the cladding layer, and the plating layer, together with the base metal layer and the cladding layer, forms an external electrode.
11. The method for manufacturing a laminated ceramic electronic component according to claim 10, wherein, The process of forming the coating layer includes the following steps: Using the sputtering method, the cladding layer is formed on the base metal layer and on the surface of the blank exposed from the base metal layer adjacent to the end face; and Remove the covering layer from the central portion of the face opposite the end face of the face adjacent to the end face.
Citation Information
Patent Citations
Multilayer ceramic capacitor
JP2016058719A
Multilayer ceramic capacitor
WO2024047980A1