A battery charge management control system, method, device, and media

Abstract

The application provides a battery charging management control system, method, device and medium, and belongs to the technical field of battery management. The system comprises: a first battery CELL1 and a second battery CELL2 connected in series; a first capacitor module connected in parallel across the first battery CELL1; a second capacitor module connected in parallel across the second battery CELL2; a first equalization circuit connected in parallel between the first capacitor module and the first battery CELL1; a second equalization circuit connected in parallel between the second capacitor module and the second battery CELL2; a first voltage detection circuit connected in parallel across the first battery CELL1; a second voltage detection circuit connected in parallel across the second battery CELL2; and a microcontroller MCU connected with the first equalization circuit, the second equalization circuit, the first voltage detection circuit and the second voltage detection circuit respectively. Intelligent management of multiple series-connected batteries is realized.

Description

Technical Field

[0001] This invention belongs to the field of battery management technology, and particularly relates to a battery charging management control system, method, device and medium. Background Technology

[0002] With the rapid development of portable electronic devices, new energy vehicles, and energy storage systems, lithium-ion batteries have been widely used due to their advantages such as high energy density and long cycle life. In battery packs composed of multiple cells connected in series, precise management of the battery's state of charge is required to ensure the overall performance and safety of the battery pack.

[0003] Existing technologies still have several shortcomings in practical applications. On the one hand, conventional battery state detection circuits are often complex in structure and have weak common-mode interference immunity, making them prone to increased measurement errors due to voltage fluctuations during charging and discharging, thus affecting the accuracy of voltage and current sampling. On the other hand, most systems fail to highly integrate equalization control, state detection, and temperature acquisition in their hardware architecture, resulting in system response delays and decreased reliability.

[0004] Therefore, the present invention provides a battery charging management and control system, method, device and medium. Summary of the Invention

[0005] This invention provides a battery charging management and control system, method, device, and medium to at least solve the problems of insufficient measurement accuracy and delayed equalization control response caused by the complex detection circuit structure in the prior art.

[0006] In a first aspect, embodiments of this application provide a battery charging management and control system, the system comprising: The first battery CELL1 and the second battery CELL2 are connected in series. The first capacitor module is connected in parallel across the positive and negative terminals of the first battery CELL1. The second capacitor module is connected in parallel across the positive and negative terminals of the second battery CELL2; The first equalization circuit is connected in parallel between the first capacitor module and the first battery CELL1; The second equalization circuit is connected in parallel between the second capacitor module and the second battery CELL2. The first voltage detection circuit is connected in parallel across the positive and negative terminals of the first battery CELL1; The second voltage detection circuit is connected in parallel across the positive and negative terminals of the second battery CELL2; The microcontroller MCU is connected to the first equalization circuit, the second equalization circuit, the first voltage detection circuit, and the second voltage detection circuit.

[0007] Furthermore, the first equalization circuit includes a first Zener diode D1, a first NPN transistor Q2, a first equalization transistor Q3, equalization resistors R1, R2, R3, R4, R5, and R6. The negative terminal of the first Zener diode D1, the source terminal of the first NPN transistor Q2, the first end of resistor R3, and the first end of resistor R6 are all connected to the positive terminal of the first battery CELL1. The drain of the first NPN transistor Q2 is connected to the first terminal of the equalizing resistor R1, and the second terminal of the equalizing resistor R1, the positive terminal of the first Zener diode D1, and the first terminal of the resistor R4 are all connected to the negative terminal of the first battery CELL1. The gate (G) of the first NPN transistor Q2 is connected to the first terminal of the resistor R2, and the second terminal of the resistor R2 is connected to the second terminal of the resistor R6 and the collector (C) of the first equalizing transistor Q3. The base (B) of the first equalizing transistor Q3 is connected to the first end of resistor R5, the emitter (E) of the first equalizing transistor Q3 is grounded, and the second end of resistor R5 is connected to the microcontroller MCU.

[0008] Furthermore, the second equalization circuit includes a second Zener diode D2, a third NPN transistor Q4, a second equalization transistor Q5, equalization resistors R14, R15, R16, R17, R18, and R19. The negative terminal of the second Zener diode D2, the source terminal of the third NPN transistor Q4, the first terminal of resistor R16, and the first terminal of resistor R19 are all connected to the positive terminal of the second battery CELL2. The drain of the third NPN transistor Q4 is connected to the first terminal of the equalizing resistor R14, and the second terminal of the equalizing resistor R14, the positive terminal of the second Zener diode D2, and the first terminal of the resistor R17 are all connected to the negative terminal of the second battery CELL2. The gate (G) of the third NPN transistor Q4 is connected to the first terminal of the resistor R15, and the second terminal of the resistor R15 is connected to the second terminal of the resistor R19 and the collector (C) of the second equalizing transistor Q5. The base (B) of the second equalizing transistor Q5 is connected to the first end of the resistor R18, the emitter (E) of the second equalizing transistor Q5 is grounded, and the second end of the resistor R18 is connected to the microcontroller MCU.

[0009] Furthermore, the first voltage detection circuit includes a first operational amplifier U1, a second operational amplifier U2, a third operational amplifier U3, resistors R7, R8, R9, R10, R11, R12, and R13. The non-inverting input terminal of the first operational amplifier U1 is connected to the second terminal of resistor R3, and the non-inverting input terminal of the second operational amplifier U2 is connected to the second terminal of resistor R4. The inverting input terminal of the first operational amplifier U1 is connected to the first terminal of resistor R7 and the first terminal of resistor R8, and the second terminal of resistor R7 is connected to the first terminal of resistor R9 and the inverting input terminal of the second operational amplifier U2. The output terminal of the first operational amplifier U1 and the second terminal of resistor R8 are both connected to the first terminal of resistor R10. The second terminal of resistor R10 is connected to the first terminal of resistor R13 and the non-inverting input terminal of the third operational amplifier U3. The second terminal of resistor R13 is grounded. The output of the second operational amplifier U2 and the second end of resistor R9 are both connected to the first end of resistor R11. The second end of resistor R11 is connected to the first end of resistor R12 and the inverting input of the third operational amplifier U3. The second end of resistor R12 is connected to the output of the third operational amplifier U3. The output of the third operational amplifier U3 is connected to the microcontroller MCU.

[0010] Furthermore, the second voltage detection circuit includes: a fourth operational amplifier U4, a fifth operational amplifier U5, a sixth operational amplifier U6, resistors R20, R21, R22, R23, R24, R25, and R26. The non-inverting input terminal of the fourth operational amplifier U4 is connected to the second terminal of resistor R16, and the non-inverting input terminal of the fifth operational amplifier U5 is connected to the second terminal of resistor R17. The inverting input terminal of the fourth operational amplifier U4 is connected to the first terminal of resistor R20 and the first terminal of resistor R21. The second terminal of resistor R20 is connected to the first terminal of resistor R22 and the inverting input terminal of the fifth operational amplifier U5. The output terminal of the fourth operational amplifier U4 and the second terminal of resistor R21 are both connected to the first terminal of resistor R23. The second terminal of resistor R23 is connected to the first terminal of resistor R26 and the non-inverting input terminal of the sixth operational amplifier U6. The second terminal of resistor R26 is grounded. The output terminal of the fifth operational amplifier U5 and the second terminal of resistor R22 are both connected to the first terminal of resistor R24. The second terminal of resistor R24 ​​is connected to the first terminal of resistor R25 and the inverting input terminal of the sixth operational amplifier U6. The second terminal of resistor R25 is connected to the output terminal of the sixth operational amplifier U6. The output terminal of the sixth operational amplifier U6 is connected to the microcontroller MCU.

[0011] Furthermore, the system includes a current detection circuit connected in series in the battery's main circuit; The current detection circuit includes resistors R27, R28, R29, R30, R31, a seventh operational amplifier U7, capacitors C5, C6, and C7. The first end of resistor R27 is connected to the negative terminal BAT- of the battery, and the second end of resistor R27 is connected to the negative terminal of the second battery CELL2. The first terminal of capacitor C5 is connected to the first terminal of capacitor C6 and the first terminal of resistor R27. The second terminal of capacitor C6 is grounded. The second terminal of capacitor C5 is connected to the first terminal of capacitor C7 and the second terminal of resistor R27. The second terminal of capacitor C7 is grounded. The first terminal of resistor R28 is connected to the first terminal of capacitor C5 and the first terminal of capacitor C6. The second terminal of resistor R28 is connected to the inverting input terminal of the seventh operational amplifier U7 and the first terminal of resistor R31. The output terminal of the seventh operational amplifier U7 is connected to the microcontroller MCU. The non-inverting input terminal of the seventh operational amplifier U7 is connected to the first terminal of resistor R29 and the first terminal of resistor R30. The second terminal of resistor R30 is grounded. The second terminal of resistor R29 is connected to the second terminal of capacitor C5 and the first terminal of capacitor C7. The second terminal of resistor R31 is connected to the output terminal of the seventh operational amplifier U7. The output terminal of the seventh operational amplifier U7 is connected to the microcontroller MCU.

[0012] Furthermore, the system also includes a temperature sensor mounted on the battery and electrically connected to the microcontroller (MCU).

[0013] Secondly, embodiments of this application also provide a method for a battery charging management and control system as described above, the method comprising: Step S1: The microcontroller MCU detects the voltage of the first battery CELL1 through the first voltage detection circuit and detects the voltage of the second battery CELL2 through the second voltage detection circuit; Step S2: The microcontroller MCU calculates the voltage difference between the first battery CELL1 and the second battery CELL2. When the voltage difference exceeds a set threshold, the equalization circuit corresponding to the battery with the higher voltage is turned on.

[0014] Thirdly, an electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, performs the steps of the methods described in the preceding aspects.

[0015] Fourthly, a storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the methods described in the preceding aspects.

[0016] As can be seen from the above technical solutions, the present invention has the following advantages: The battery charging management and control system provided in this application realizes real-time high-precision acquisition and centralized management of the status of multiple batteries by including a microcontroller (MCU), an equalization circuit, and a voltage detection circuit. The equalization resistor and equalization transistor are connected in series and then in parallel across each battery. The MCU directly controls the on and off of the equalization transistor, thereby quickly starting passive equalization when voltage imbalance is detected, effectively improving the system response speed and equalization efficiency.

[0017] The voltage detection circuit can achieve stable sampling of the total voltage, realize multi-parameter fusion monitoring, improve the integrity and reliability of status information, and provide a good foundation for the accurate formulation of charging strategies.

[0018] By integrating the equalization circuit and battery status detection circuit into the same management system and scheduling them uniformly by the microcontroller (MCU), efficient collaboration between functional modules can be achieved at the hardware level, reducing system complexity and enhancing adaptability and robustness under varying operating conditions. Attached Figure Description

[0019] To more clearly illustrate the technical solution of this application, the accompanying drawings used in the description will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a circuit diagram of the battery charging management and control system described in this invention. Detailed Implementation

[0021] To make the purpose, features, and advantages of this application more apparent and understandable, specific embodiments and accompanying drawings will be used to clearly and completely describe the technical solution protected by this application. Obviously, the embodiments described below are only some embodiments of this application, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0022] This application provides a battery charging management and control system, method, device, and medium, which solves the current urgent technical problem of achieving high-precision battery status monitoring, rapid dynamic equalization control, and multi-module collaborative management to improve battery pack safety and service life.

[0023] The technical solutions proposed in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0024] Figure 1This is a circuit diagram of a battery charging management and control system provided in an embodiment of this application. Figure 1 As shown in the embodiment of this application, a battery charging management and control system is provided, the system comprising: The first battery CELL1 and the second battery CELL2 are connected in series. The first capacitor module is connected in parallel across the positive and negative terminals of the first battery CELL1. The second capacitor module is connected in parallel across the positive and negative terminals of the second battery CELL2; The first equalization circuit is connected in parallel between the first capacitor module and the first battery CELL1; The second equalization circuit is connected in parallel between the second capacitor module and the second battery CELL2. The first voltage detection circuit is connected in parallel across the positive and negative terminals of the first battery CELL1; The second voltage detection circuit is connected in parallel across the positive and negative terminals of the second battery CELL2; The microcontroller MCU is connected to the first equalization circuit, the second equalization circuit, the first voltage detection circuit, and the second voltage detection circuit.

[0025] It should be noted that the first equalization circuit includes a first Zener diode D1, a first NPN transistor Q2, a first equalization transistor Q3, equalization resistors R1, R2, R3, R4, R5, and R6. The negative terminal of the first Zener diode D1, the source terminal of the first NPN transistor Q2, the first end of resistor R3, and the first end of resistor R6 are all connected to the positive terminal of the first battery CELL1. The drain of the first NPN transistor Q2 is connected to the first terminal of the equalizing resistor R1, and the second terminal of the equalizing resistor R1, the positive terminal of the first Zener diode D1, and the first terminal of the resistor R4 are all connected to the negative terminal of the first battery CELL1. The gate (G) of the first NPN transistor Q2 is connected to the first terminal of the resistor R2, and the second terminal of the resistor R2 is connected to the second terminal of the resistor R6 and the collector (C) of the first equalizing transistor Q3. The base (B) of the first equalizing transistor Q3 is connected to the first end of resistor R5, the emitter (E) of the first equalizing transistor Q3 is grounded, and the second end of resistor R5 is connected to the microcontroller MCU.

[0026] In this embodiment, the second equalization circuit includes a second Zener diode D2, a third NPN transistor Q4, a second equalization transistor Q5, equalization resistors R14, R15, R16, R17, R18, and R19. The negative terminal of the second Zener diode D2, the source terminal of the third NPN transistor Q4, the first terminal of resistor R16, and the first terminal of resistor R19 are all connected to the positive terminal of the second battery CELL2. The drain of the third NPN transistor Q4 is connected to the first terminal of the equalizing resistor R14, and the second terminal of the equalizing resistor R14, the positive terminal of the second Zener diode D2, and the first terminal of the resistor R17 are all connected to the negative terminal of the second battery CELL2. The gate (G) of the third NPN transistor Q4 is connected to the first terminal of the resistor R15, and the second terminal of the resistor R15 is connected to the second terminal of the resistor R19 and the collector (C) of the second equalizing transistor Q5. The base (B) of the second equalizing transistor Q5 is connected to the first end of the resistor R18, the emitter (E) of the second equalizing transistor Q5 is grounded, and the second end of the resistor R18 is connected to the microcontroller MCU.

[0027] According to an embodiment of the present invention, the first voltage detection circuit includes a first operational amplifier U1, a second operational amplifier U2, a third operational amplifier U3, resistors R7, R8, R9, R10, R11, R12, and R13. The non-inverting input terminal of the first operational amplifier U1 is connected to the second terminal of resistor R3, and the non-inverting input terminal of the second operational amplifier U2 is connected to the second terminal of resistor R4. The inverting input terminal of the first operational amplifier U1 is connected to the first terminal of resistor R7 and the first terminal of resistor R8, and the second terminal of resistor R7 is connected to the first terminal of resistor R9 and the inverting input terminal of the second operational amplifier U2. The output terminal of the first operational amplifier U1 and the second terminal of resistor R8 are both connected to the first terminal of resistor R10. The second terminal of resistor R10 is connected to the first terminal of resistor R13 and the non-inverting input terminal of the third operational amplifier U3. The second terminal of resistor R13 is grounded. The output of the second operational amplifier U2 and the second end of resistor R9 are both connected to the first end of resistor R11. The second end of resistor R11 is connected to the first end of resistor R12 and the inverting input of the third operational amplifier U3. The second end of resistor R12 is connected to the output of the third operational amplifier U3. The output of the third operational amplifier U3 is connected to the microcontroller MCU.

[0028] According to another embodiment of the present invention, the second voltage detection circuit includes: a fourth operational amplifier U4, a fifth operational amplifier U5, a sixth operational amplifier U6, a resistor R20, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a resistor R25, and a resistor R26. The non-inverting input terminal of the fourth operational amplifier U4 is connected to the second terminal of resistor R16, and the non-inverting input terminal of the fifth operational amplifier U5 is connected to the second terminal of resistor R17. The inverting input terminal of the fourth operational amplifier U4 is connected to the first terminal of resistor R20 and the first terminal of resistor R21. The second terminal of resistor R20 is connected to the first terminal of resistor R22 and the inverting input terminal of the fifth operational amplifier U5. The output terminal of the fourth operational amplifier U4 and the second terminal of resistor R21 are both connected to the first terminal of resistor R23. The second terminal of resistor R23 is connected to the first terminal of resistor R26 and the non-inverting input terminal of the sixth operational amplifier U6. The second terminal of resistor R26 is grounded. The output terminal of the fifth operational amplifier U5 and the second terminal of resistor R22 are both connected to the first terminal of resistor R24. The second terminal of resistor R24 ​​is connected to the first terminal of resistor R25 and the inverting input terminal of the sixth operational amplifier U6. The second terminal of resistor R25 is connected to the output terminal of the sixth operational amplifier U6. The output terminal of the sixth operational amplifier U6 is connected to the microcontroller MCU.

[0029] Furthermore, the system includes a current detection circuit connected in series in the battery's main circuit; The current detection circuit includes resistors R27, R28, R29, R30, R31, a seventh operational amplifier U7, capacitors C5, C6, and C7. The first end of resistor R27 is connected to the negative terminal BAT- of the battery, and the second end of resistor R27 is connected to the negative terminal of the second battery CELL2. The first terminal of capacitor C5 is connected to the first terminal of capacitor C6 and the first terminal of resistor R27. The second terminal of capacitor C6 is grounded. The second terminal of capacitor C5 is connected to the first terminal of capacitor C7 and the second terminal of resistor R27. The second terminal of capacitor C7 is grounded. The first terminal of resistor R28 is connected to the first terminal of capacitor C5 and the first terminal of capacitor C6. The second terminal of resistor R28 is connected to the inverting input terminal of the seventh operational amplifier U7 and the first terminal of resistor R31. The output terminal of the seventh operational amplifier U7 is connected to the microcontroller MCU. The non-inverting input terminal of the seventh operational amplifier U7 is connected to the first terminal of resistor R29 and the first terminal of resistor R30. The second terminal of resistor R30 is grounded. The second terminal of resistor R29 is connected to the second terminal of capacitor C5 and the first terminal of capacitor C7. The second terminal of resistor R31 is connected to the output terminal of the seventh operational amplifier U7. The output terminal of the seventh operational amplifier U7 is connected to the microcontroller MCU.

[0030] For example, the system also includes a temperature sensor disposed on the battery and electrically connected to the microcontroller MCU.

[0031] The present invention also provides a method for applying to a battery charging management and control system as described in the above embodiments, the method comprising: Step S1: The microcontroller MCU detects the voltage of the first battery CELL1 through the first voltage detection circuit and detects the voltage of the second battery CELL2 through the second voltage detection circuit; Step S2: The microcontroller MCU calculates the voltage difference between the first battery CELL1 and the second battery CELL2. When the voltage difference exceeds a set threshold, the equalization circuit corresponding to the battery with the higher voltage is turned on.

[0032] Specifically, the microcontroller (MCU) calculates the voltage difference between the first battery CELL1 and the second battery CELL2. When the voltage difference exceeds a set threshold, the equalizing transistor corresponding to the battery with the higher voltage is turned on, causing the equalizing resistor to consume the energy of that battery until the voltage difference returns to the preset voltage difference range.

[0033] Combination Figure 1 The microcontroller (MCU) receives the CELL1_VOL signal output from the output terminal of the third operational amplifier U3 and the CELL2_VOL signal output from the output terminal of the sixth operational amplifier U6. The MCU compares the voltages of the first battery CELL1 and the second battery CELL2 based on the CELL1_VOL and CELL2_VOL signals. When the voltage of the first battery CELL1 is higher than the voltage of the second battery CELL2, the MCU outputs a high-level signal to the control pin CELL1_CTL of the first equalization circuit, the first equalization transistor Q3 is turned on, and the equalization resistor R1 is connected in parallel with the first battery CELL1. The equalization resistor R1 passes through... The formula converts excess energy into heat energy dissipation, where, The current flowing through the balancing resistor, To balance the resistance value, when the voltage of the first battery CELL1 drops to the threshold, the control pin CELL1_CTL of the first equalization circuit for the voltage of the first battery CELL1 is set to a low level, turning off the first equalization transistor Q3. The first battery CELL1 continues to charge the first capacitor module. This charging equalization control method has the advantages of low hardware cost, simple control, and high reliability. Meanwhile, to prevent overvoltage caused by abnormally high charging voltage, a 4.2V Zener diode is connected in parallel across each battery cell.

[0034] The first capacitor module includes capacitor C1 and capacitor C2, which are connected in series and then in parallel across the positive and negative terminals of the first battery CELL1. The first capacitor module includes capacitor C3 and capacitor C4, which are connected in series and then in parallel across the positive and negative terminals of the second battery CELL2.

[0035] The battery charging management and control method provided in this application can be applied to electronic devices. Those skilled in the art will understand that the electronic device structure involved in the embodiments of this invention does not constitute a limitation on the electronic device. An electronic device may include more or fewer components than illustrated, or combine certain components, or have different component arrangements. In the embodiments of this invention, the electronic device includes, but is not limited to, laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the embodiments of this application described and / or claimed herein.

[0036] Electronic devices may include processors, external memory interfaces, internal memory, universal serial bus (USB) interfaces, charging management modules, power management modules, batteries, wireless communication modules, audio modules, speakers, microphones, sensor modules, buttons, cameras, displays, and SIM card interfaces, etc.

[0037] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device. In other embodiments of this application, the electronic device may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0038] A processor may include one or more processing units, such as: a central processing unit (CPU), an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural network processing unit (NPU). Different processing units may be independent devices or integrated into one or more processors.

[0039] The processor can serve as the nerve center and command center of an electronic device. The controller can generate operation control signals based on the instruction opcode and timing signals to control the fetching and execution of instructions.

[0040] The processor may also include memory for storing instructions and data. In some embodiments, the memory in the processor is a cache memory. This memory can store instructions or data that the processor has just used or that are used repeatedly. If the processor needs to use the instruction or data again, it can retrieve it directly from this memory. This avoids repeated accesses, reduces processor latency, and thus improves system efficiency.

[0041] An external storage interface (ESI) can be used to connect external memory cards, such as microSD cards, to expand the storage capacity of electronic devices. The external memory card communicates with the processor through the ESI to perform data storage functions, such as saving music and video files on the external memory card.

[0042] Internal memory can be used to store computer executable program code, which includes instructions. The processor executes various functional applications and data processing of electronic devices by running the instructions stored in internal memory. Internal memory can include a program storage area and a data storage area. Internal memory can include high-speed random access memory, and can also include non-volatile memory, such as at least one disk storage device, flash memory device, universal flash storage (UFS), etc.

[0043] Wireless communication functionality in electronic devices can be achieved through antennas, wireless communication modules, modem processors, and baseband processors.

[0044] Wireless communication modules can provide solutions for wireless communication applications in electronic devices, including wireless local area networks (WLANs) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), and infrared (IR) technologies.

[0045] Electronic devices can implement audio functions through audio modules, speakers, receivers, microphones, headphone jacks, and application processors.

[0046] Electronic devices can achieve shooting functions through ISPs, cameras, video codecs, GPUs, displays, and application processors.

[0047] Electronic devices can achieve display functions through GPUs, displays, and application processors.

[0048] A GPU is a microprocessor for image processing, connected to the display screen and application processor. GPUs perform mathematical and geometric calculations for graphics rendering. A processor may include one or more GPUs, which execute program instructions to generate or modify display information.

[0049] A display screen is used to display images, videos, etc. A display screen includes a display panel.

[0050] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0051] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of devices, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0052] In the embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections through some interfaces, apparatuses, or units, or they may be electrical, mechanical, or other forms of connection.

[0053] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a full understanding of embodiments of the invention. However, those skilled in the art will recognize that the technical solutions of the invention can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of the invention.

[0054] The aforementioned electronic device implements the battery charging management control method of this application. The microcontroller (MCU) detects the voltage of the first battery CELL1 through a first voltage detection circuit and the voltage of the second battery CELL2 through a second voltage detection circuit. The microcontroller (MCU) calculates the voltage difference between the first battery CELL1 and the second battery CELL2. When the voltage difference exceeds a set threshold, the balancing circuit corresponding to the battery with the higher voltage is turned on, so that the balancing resistor consumes the energy of that battery until the voltage difference returns to the preset voltage difference range, thereby realizing intelligent management of multiple series-connected batteries.

[0055] The storage medium provided in this application stores a program product capable of implementing a battery charging management and control method.

[0056] The battery charging management control method includes: Step S1: The microcontroller MCU detects the voltage of the first battery CELL1 through the first voltage detection circuit, and detects the voltage of the second battery CELL2 through the second voltage detection circuit; Step S2: The microcontroller MCU calculates the voltage difference between the first battery CELL1 and the second battery CELL2. When the voltage difference exceeds a set threshold, the equalization circuit corresponding to the battery with the higher voltage is turned on.

[0057] By incorporating a microcontroller (MCU), an equalization circuit, and a voltage detection circuit, the system achieves real-time, high-precision acquisition and centralized management of the status of multiple battery cells. The equalization resistor and equalization transistor are connected in series and then in parallel across each battery cell. The MCU directly controls the switching on and off of the equalization transistor, thereby quickly initiating passive equalization when voltage imbalance is detected, effectively improving the system's response speed and equalization efficiency.

[0058] In some possible implementations, the battery charging management control method of this disclosure can be implemented as a program product including program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure.

[0059] The storage medium disclosed herein may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.

[0060] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0061] For those skilled in the art, designing different forms of control circuits according to the teachings of this invention does not require creative effort. Changes, modifications, substitutions, and variations made to the embodiments without departing from the principles and spirit of this invention still fall within the scope of protection of this invention.

Claims

1. A battery charge management control system, characterized by, The system includes: The first battery CELL1 and the second battery CELL2 are connected in series. The first capacitor module is connected in parallel across the positive and negative terminals of the first battery CELL1. The second capacitor module is connected in parallel across the positive and negative terminals of the second battery CELL2; The first equalization circuit is connected in parallel between the first capacitor module and the first battery CELL1; The second equalization circuit is connected in parallel between the second capacitor module and the second battery CELL2. The first voltage detection circuit is connected in parallel across the positive and negative terminals of the first battery CELL1; The second voltage detection circuit is connected in parallel across the positive and negative terminals of the second battery CELL2; The microcontroller MCU is connected to the first equalization circuit, the second equalization circuit, the first voltage detection circuit, and the second voltage detection circuit.

2. The system of claim 1, wherein, The first equalization circuit includes a first Zener diode D1, a first NPN transistor Q2, a first equalization transistor Q3, equalization resistors R1, R2, R3, R4, R5, and R6. The negative terminal of the first Zener diode D1, the source terminal of the first NPN transistor Q2, the first end of resistor R3, and the first end of resistor R6 are all connected to the positive terminal of the first battery CELL1. The drain of the first NPN transistor Q2 is connected to the first terminal of the equalizing resistor R1, and the second terminal of the equalizing resistor R1, the positive terminal of the first Zener diode D1, and the first terminal of the resistor R4 are all connected to the negative terminal of the first battery CELL1. The gate (G) of the first NPN transistor Q2 is connected to the first end of the resistor R2, and the second end of the resistor R2 is connected to the second end of the resistor R6 and the collector (C) of the first equalizing transistor Q3. The base (B) of the first equalizing transistor Q3 is connected to the first end of the resistor R5, the emitter (E) of the first equalizing transistor Q3 is grounded, and the second end of the resistor R5 is connected to the microcontroller MCU.

3. The system of claim 2, wherein, The second equalization circuit includes a second Zener diode D2, a third NPN transistor Q4, a second equalization transistor Q5, equalization resistors R14, R15, R16, R17, R18, and R19. The negative terminal of the second Zener diode D2, the source terminal of the third NPN transistor Q4, the first terminal of resistor R16, and the first terminal of resistor R19 are all connected to the positive terminal of the second battery CELL2. The drain of the third NPN transistor Q4 is connected to the first terminal of the equalizing resistor R14, and the second terminal of the equalizing resistor R14, the positive terminal of the second Zener diode D2, and the first terminal of the resistor R17 are all connected to the negative terminal of the second battery CELL2. The gate (G) of the third NPN transistor Q4 is connected to the first terminal of the resistor R15, and the second terminal of the resistor R15 is connected to the second terminal of the resistor R19 and the collector (C) of the second equalizing transistor Q5. The base (B) of the second equalizing transistor Q5 is connected to the first end of the resistor R18, the emitter (E) of the second equalizing transistor Q5 is grounded, and the second end of the resistor R18 is connected to the microcontroller MCU.

4. The system of claim 3, wherein, The first voltage detection circuit includes a first operational amplifier U1, a second operational amplifier U2, a third operational amplifier U3, resistors R7, R8, R9, R10, R11, R12, and R13; The non-inverting input terminal of the first operational amplifier U1 is connected to the second terminal of resistor R3, and the non-inverting input terminal of the second operational amplifier U2 is connected to the second terminal of resistor R4. The inverting input terminal of the first operational amplifier U1 is connected to the first terminal of resistor R7 and the first terminal of resistor R8, and the second terminal of resistor R7 is connected to the first terminal of resistor R9 and the inverting input terminal of the second operational amplifier U2. The output terminal of the first operational amplifier U1 and the second terminal of resistor R8 are both connected to the first terminal of resistor R10. The second terminal of resistor R10 is connected to the first terminal of resistor R13 and the non-inverting input terminal of the third operational amplifier U3. The second terminal of resistor R13 is grounded. The output of the second operational amplifier U2 and the second end of resistor R9 are both connected to the first end of resistor R11. The second end of resistor R11 is connected to the first end of resistor R12 and the inverting input of the third operational amplifier U3. The second end of resistor R12 is connected to the output of the third operational amplifier U3. The output of the third operational amplifier U3 is connected to the microcontroller MCU.

5. The system of claim 4, wherein, The second voltage detection circuit includes: a fourth operational amplifier U4, a fifth operational amplifier U5, a sixth operational amplifier U6, resistors R20, R21, R22, R23, R24, R25, and R26. The non-inverting input terminal of the fourth operational amplifier U4 is connected to the second terminal of resistor R16, and the non-inverting input terminal of the fifth operational amplifier U5 is connected to the second terminal of resistor R17. The inverting input terminal of the fourth operational amplifier U4 is connected to the first terminal of resistor R20 and the first terminal of resistor R21. The second terminal of resistor R20 is connected to the first terminal of resistor R22 and the inverting input terminal of the fifth operational amplifier U5. The output terminal of the fourth operational amplifier U4 and the second terminal of resistor R21 are both connected to the first terminal of resistor R23. The second terminal of resistor R23 is connected to the first terminal of resistor R26 and the non-inverting input terminal of the sixth operational amplifier U6. The second terminal of resistor R26 is grounded. The output terminal of the fifth operational amplifier U5 and the second terminal of resistor R22 are both connected to the first terminal of resistor R24. The second terminal of resistor R24 ​​is connected to the first terminal of resistor R25 and the inverting input terminal of the sixth operational amplifier U6. The second terminal of resistor R25 is connected to the output terminal of the sixth operational amplifier U6. The output terminal of the sixth operational amplifier U6 is connected to the microcontroller MCU.

6. The system of claim 5, wherein, The system includes a current detection circuit connected in series in the main circuit of the battery. The current detection circuit includes resistors R27, R28, R29, R30, R31, a seventh operational amplifier U7, capacitors C5, C6, and C7. The first end of resistor R27 is connected to the negative terminal BAT- of the battery, and the second end of resistor R27 is connected to the negative terminal of the second battery CELL2. The first terminal of capacitor C5 is connected to the first terminal of capacitor C6 and the first terminal of resistor R27. The second terminal of capacitor C6 is grounded. The second terminal of capacitor C5 is connected to the first terminal of capacitor C7 and the second terminal of resistor R27. The second terminal of capacitor C7 is grounded. The first terminal of resistor R28 is connected to the first terminal of capacitor C5 and the first terminal of capacitor C6. The second terminal of resistor R28 is connected to the inverting input terminal of the seventh operational amplifier U7 and the first terminal of resistor R31. The output terminal of the seventh operational amplifier U7 is connected to the microcontroller MCU. The non-inverting input terminal of the seventh operational amplifier U7 is connected to the first terminal of resistor R29 and the first terminal of resistor R30. The second terminal of resistor R30 is grounded. The second terminal of resistor R29 is connected to the second terminal of capacitor C5 and the first terminal of capacitor C7. The second terminal of resistor R31 is connected to the output terminal of the seventh operational amplifier U7. The output terminal of the seventh operational amplifier U7 is connected to the microcontroller MCU.

7. The system of claim 6, wherein, The system also includes a temperature sensor mounted on the battery and electrically connected to the microcontroller (MCU).

8. A method applied to the battery charge management control system according to any one of claims 1 to 7, characterized in that, The method includes: Step S1: The microcontroller MCU detects the voltage of the first battery CELL1 through the first voltage detection circuit and detects the voltage of the second battery CELL2 through the second voltage detection circuit; Step S2: The microcontroller MCU calculates the voltage difference between the first battery CELL1 and the second battery CELL2. When the voltage difference exceeds a set threshold, the equalization circuit corresponding to the battery with the higher voltage is turned on.

9. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method as described in claim 8.

10. A storage medium having stored thereon a computer program, characterized in that When the computer program is executed by a processor, it implements the steps of the method as described in claim 8.

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