Data fitting method, device and computer equipment for application-specific integrated circuit implementation

Abstract

The present disclosure provides a data fitting method, device and computer equipment for application-specific integrated circuit, relates to the technical field of computer and artificial intelligence, and the scheme is: a self-defined floating-point number model is constructed; fitting control parameters are initialized; based on the self-defined floating-point number model and the fitting control parameters, segmented fitting processing is performed on a target continuous function to obtain a segmented fitting result; based on the self-defined floating-point number model and fitting related parameters, verification processing is performed on the segmented fitting result to obtain a verification result; iterative optimization processing is performed on the fitting related parameters to obtain optimized fitting related parameters; the segmented fitting result is updated based on the optimized fitting related parameters, and error compensation processing is performed on the segmented fitting result to obtain compensated fitting related parameters; and the compensated fitting related parameters are mapped to hardware implementation code, so that the precision, hardware cost and delay can be considered, and the function fitting and hardware implementation efficiency are improved.

Description

Technical Field

[0001] This disclosure relates to the fields of computer and artificial intelligence (AI) technology, particularly to the fields of digital computing and application-specific integrated circuit (ASIC) design, and especially to a data fitting method, apparatus, computer device, computer-readable storage medium, and computer program product for implementation of ASICs. Background Technology

[0002] In related technologies, in digital computing and application-specific integrated circuit design, lookup tables, polynomial approximation, iterative algorithms and other methods are often used to implement arbitrary continuous smooth functions, including but not limited to activation functions such as swish and sigmoid, which are widely used in digital signal processing, artificial intelligence accelerators and embedded systems. Summary of the Invention

[0003] This disclosure provides a data fitting method, apparatus, computer device, computer-readable storage medium, and computer program product for implementation of application-specific integrated circuits.

[0004] According to one aspect of this disclosure, a data fitting method for application-specific integrated circuit (ASIC) implementation is provided, comprising: Construct a custom floating-point numerical model that matches the bit-level operations of the target hardware; Initialize the fitting control parameters, which include the segmentation interval division method and the smoothness constraint weights; Based on a custom floating-point numerical model and fitting control parameters, piecewise fitting is performed on the target continuous function to obtain piecewise fitting results. The piecewise fitting results include information on the segment interval division and / or local approximation function parameters. The piecewise fitting results and the fitting control parameters constitute fitting-related parameters. In response to obtaining the piecewise fitting results, a validation process is performed on the piecewise fitting results based on a custom floating-point numerical model and fitting-related parameters. The validation process includes a first validation and a second validation, wherein: The first verification is used to evaluate the accuracy of the numerical fitting within each segment interval in order to obtain accuracy evaluation data; The second verification is used to verify the continuity of the multi-order derivatives at the boundaries of adjacent segment intervals based on the smoothness constraint weights in the fitting related parameters, so as to obtain continuity verification data. The accuracy assessment data is integrated with the continuous verification data to obtain the verification results of the verification process; In response to obtaining the verification results, iterative optimization is performed on the fitting parameters to obtain the optimized fitting parameters; The piecewise fitting results are updated based on the optimized fitting parameters, and error compensation is performed on the piecewise fitting results to obtain the compensated fitting parameters. The compensated fitting parameters are mapped to hardware implementation code that matches the bit-level operations of the custom floating-point numerical model, so that the target hardware implementation can fit the target continuous function.

[0005] In some embodiments, the custom floating-point numerical model achieves bit-level operation matching with the target hardware through one or more of the following: configurable numerical precision, target hardware floating-point operation logic, target hardware rounding rules, and target hardware special value processing rules.

[0006] In some embodiments, the piecewise fitting process includes: performing uniform or non-uniform segmentation on the domain of the target continuous function to obtain multiple non-overlapping segment intervals, and constructing a local approximation function for each segment interval; wherein, the evaluation of numerical fitting accuracy is a pointwise absolute error or relative error evaluation, and the verification of the continuity of multiple derivatives is a first-order and second-order derivative continuity verification.

[0007] In some embodiments, the iterative optimization process terminates when any of the following conditions are met: the preset number of iterations is reached, the numerical fitting accuracy reaches a preset threshold, or the change in the fitting related parameters is less than a preset threshold.

[0008] In some embodiments, there are multiple target continuous functions, and piecewise fitting and verification processes are performed on the multiple target continuous functions respectively to obtain multiple piecewise fitting results and multiple verification results; wherein, the iterative optimization process is a multi-function joint optimization, including performing iterative optimization on the fitting-related parameters of the multiple target continuous functions based on the multiple verification results; wherein, the error compensation process includes identifying error hotspot regions in the multiple updated piecewise fitting results where the numerical error exceeds a preset threshold, and performing compensation operations on the error hotspot regions.

[0009] In some embodiments, mapping the compensated fitting correlation parameters to hardware implementation code that matches the bit-level operations of a custom floating-point numerical model includes: converting the compensated fitting correlation parameters into one or more of a hardware computation structure, interval selection logic, or special value bypass processing logic; wherein the method further includes: providing the verification result as input to the iterative optimization process for use in the next round of iterative optimization of the fitting correlation parameters.

[0010] According to another aspect of this disclosure, a data fitting apparatus for implementation using an application-specific integrated circuit is provided, comprising: The numerical modeling module is configured to build custom floating-point numerical models that match the bit-level operations of the target hardware. The piecewise fitting module is configured to initialize fitting control parameters, which include the segmentation interval division method and smoothness constraint weights. Based on a custom floating-point numerical model and fitting control parameters, it performs piecewise fitting processing on the target continuous function to obtain piecewise fitting results. The piecewise fitting results include segmentation interval division information and / or local approximation function parameters. The piecewise fitting results and fitting control parameters constitute fitting-related parameters. The validation module is configured to perform validation processing on the piecewise fitting results in response to obtaining the results, based on a custom floating-point numerical model and fitting-related parameters. The validation processing includes a first validation unit and a second validation unit. The first verification unit is configured to evaluate the accuracy of the numerical fitting within each segment interval to obtain accuracy evaluation data. The second verification unit is configured to verify the continuity of the multi-order derivatives at the boundaries of adjacent segment intervals based on the smoothness constraint weights in the fitting relevant parameters to obtain continuity verification data. The verification module is also configured to integrate accuracy assessment data with continuity verification data to obtain verification results; The optimization module is configured to perform iterative optimization on the fitting parameters in response to obtaining the validation results, so as to obtain the optimized fitting parameters. The error compensation module is configured to update the piecewise fitting results based on the optimized fitting correlation parameters and perform error compensation processing on the piecewise fitting results to obtain the compensated fitting correlation parameters. The code generation module is configured to map the compensated fitting parameters to hardware implementation code that matches the bit-level operations of a custom floating-point numerical model, so that the target hardware implementation can fit the target continuous function.

[0011] According to another aspect of this disclosure, a computer device is provided, comprising: a processor; and a memory having a computer program stored thereon, wherein when executed by the processor, the computer program causes the processor to perform the methods provided above in this disclosure.

[0012] According to another aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, causes the processor to perform the methods provided above in this disclosure.

[0013] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, causes the processor to perform the methods provided above in this disclosure.

[0014] According to one or more embodiments of this disclosure, by constructing a custom floating-point numerical model that matches the bit-level operations of the target hardware, the fitting control parameters are initialized sequentially, piecewise fitting is performed, two-dimensional verification is performed, iterative optimization is performed, piecewise result updates and error compensation are performed, and hardware code is generated. This eliminates the differences between software and hardware numerical values, balances accuracy, smoothness and hardware cost, and achieves efficient and automated hardware implementation of continuous functions, thereby improving stability and resource utilization.

[0015] These and other aspects of this disclosure will be apparent from the embodiments described below, and will be elucidated with reference to the embodiments described below. Attached Figure Description

[0016] The accompanying drawings exemplify embodiments and form part of the specification, serving together with the textual description to explain exemplary implementations of the embodiments. The illustrated embodiments are for illustrative purposes only and do not limit the scope of this disclosure. Throughout the drawings, the same reference numerals refer to similar but not necessarily identical elements.

[0017] Figure 1 This is a flowchart illustrating a data fitting method for application-specific integrated circuits according to some embodiments of this disclosure.

[0018] Figure 2 This is a schematic diagram of the structure of an RTL generation system in some embodiments of this disclosure.

[0019] Figure 3 This is a schematic diagram of the structure of a data fitting device for implementation using an application-specific integrated circuit according to some embodiments of this disclosure.

[0020] Figure 4 An example computer device is shown in which any of the embodiments described herein may be implemented. Detailed Implementation

[0021] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0022] In this disclosure, unless otherwise stated, the use of terms such as "first," "second," etc., to describe various elements is not intended to limit the positional, temporal, or importance relationships of these elements; such terms are merely used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of that element, while in other cases, based on the context, they may refer to different instances.

[0023] The terminology used in the description of the various examples described in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context explicitly indicates otherwise, an element may be one or more unless the number of elements is specifically limited. As used herein, the term "multiple" means two or more, and the term "based on" should be interpreted as "at least partially based on". Furthermore, the terms "and / or" and "at least one of..." cover any one of the listed items and all possible combinations thereof.

[0024] As mentioned earlier, in digital computing and application-specific integrated circuit design, related technologies often employ lookup tables, polynomial approximation, iterative algorithms, and other methods to implement arbitrary continuous smooth functions, including but not limited to activation functions such as swish and sigmoid.

[0025] However, existing hardware implementation methods for continuous functions are mostly designed and verified based on standard floating-point formats, which have semantic differences from the actual floating-point operation behavior of hardware. This results in software simulation accuracy failing to reflect the real hardware errors, and the fitting results are prone to performance degradation in hardware. At the same time, algorithm fitting, accuracy verification, and hardware implementation are usually completed in different toolchains, lacking a unified modeling and evaluation system. Parameter selection relies on experience, and repeated iterations are costly.

[0026] Furthermore, existing fitting methods struggle to achieve a globally optimal balance between accuracy, hardware area, and latency. They typically focus only on numerical errors within intervals, lacking systematic constraints on the continuity of derivatives at piecewise boundaries, which can easily introduce function non-smoothness issues and affect the stability of practical systems. Additionally, existing methods are mostly designed for single-function optimization, lacking the ability to jointly optimize multiple functions and the capability for automated hardware generation.

[0027] To address this, this disclosure proposes a data fitting method for application-specific integrated circuit (ASIC) implementation. The method first constructs a custom floating-point numerical model that matches the bit-level operations of the target hardware, and initializes fitting control parameters including the segmented interval partitioning method and smoothness constraint weights. Based on this model and control parameters, a piecewise fitting process is performed on the target continuous function to obtain a piecewise fitting result containing segmented interval partitioning information and / or local approximation function parameters. The piecewise fitting result and the fitting control parameters together constitute the fitting-related parameters. Then, based on the same model and fitting-related parameters, a two-dimensional verification process is performed on the piecewise fitting result to obtain the verification result. The fitting-related parameters are iteratively optimized based on the verification result. Subsequently, the piecewise fitting result is updated based on the optimized parameters, and error compensation processing is performed. Finally, the compensated fitting-related parameters are mapped to hardware implementation code that matches the bit-level operations of the custom floating-point numerical model.

[0028] This method eliminates the numerical semantic differences between software simulation and hardware implementation, while balancing fitting accuracy within intervals and function smoothness at segment boundaries, achieving a globally optimal balance between accuracy, hardware area, and latency. By constructing an integrated workflow for fitting, verification, optimization, compensation, and code generation, it enables fully automated processing from function definition to hardware implementation, significantly reducing development costs and improving system stability and resource utilization.

[0029] Exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0030] Figure 1 This is a flowchart illustrating a data fitting method 100 for application-specific integrated circuit (ASIC) implementation according to some embodiments of this disclosure. It will be understood that method 100 includes steps S110, S115, S120, S130, S140, S150, and S160.

[0031] In step S110, a custom floating-point numerical model matching the bit-level operations of the target hardware is constructed.

[0032] As used in this article, when referring to a custom floating-point numerical model, it can refer to a numerical computation model that can reproduce the semantics of floating-point operations in the target hardware. This model serves as a unified numerical computation foundation throughout the entire process, replacing the numerical representation of traditional software floating-point numbers in function fitting and verification. The semantic differences between traditional software floating-point numbers and hardware floating-point operations can lead to inconsistencies between software simulation results and actual hardware performance. A custom floating-point numerical model can eliminate this difference.

[0033] In some implementations, a custom floating-point numerical model is used throughout all stages of the fitting process. All numerical calculations and logical judgments are performed within the numerical framework of this model, ensuring consistent numerical behavior across the entire chain from function input to hardware output. This unified numerical model easily avoids error propagation across stages, ensuring consistency between algorithm design and hardware implementation.

[0034] In step S115, the fitting control parameters are initialized, including the segmentation interval division method and the smoothness constraint weight.

[0035] The fitting control parameters are the basic input parameters that drive the subsequent piecewise fitting and verification processes. The piecewise interval division method is used to define the splitting rules of the domain of the target continuous function, and the smoothness constraint weight is used to set the verification criteria for the continuity of derivatives at the boundaries of adjacent piecewise intervals.

[0036] In step S120, based on the custom floating-point numerical model and the fitting control parameters, a piecewise fitting process is performed on the target continuous function to obtain a piecewise fitting result. The piecewise fitting result includes segment interval division information and / or local approximation function parameters. The piecewise fitting result and the fitting control parameters together constitute fitting-related parameters.

[0037] As used in this article, piecewise fitting refers to dividing the complete domain of the target continuous function into multiple independent intervals, constructing an approximate function within each interval, and thus achieving an approximate representation of the global continuous function. For continuous functions with complex shapes that are difficult to fit accurately with a single function over their entire domain, piecewise fitting can effectively reduce the fitting difficulty.

[0038] In some implementations, piecewise fitting breaks down a complex global fitting problem into multiple relatively simple local fitting problems, each of which only needs to fit the function shape within its corresponding interval. As an example, and not a limitation, the target continuous function may include exponential functions, logarithmic functions, activation functions, etc., commonly used in artificial intelligence accelerators and digital signal processors, which can achieve better performance in hardware implementations through piecewise fitting.

[0039] In step S130, in response to obtaining the piecewise fitting result, a verification process is performed on the piecewise fitting result based on the custom floating-point numerical model and the fitting-related parameters. The verification process includes a first verification and a second verification, wherein: in sub-step S131, the first verification is used to evaluate the numerical fitting accuracy within each piecewise interval to obtain accuracy evaluation data; in sub-step S132, the second verification is used to verify the continuity of multi-order derivatives at the boundaries of adjacent piecewise intervals according to the smoothness constraint weights in the fitting-related parameters to obtain continuity verification data; the accuracy evaluation data and the continuity verification data are integrated to obtain the verification result of the verification process.

[0040] As used in this article, when referring to verification processing, it can refer to the process of evaluating the quality of the approximate function obtained by piecewise fitting. The output verification results are the core basis for subsequent parameter optimization. The accuracy of verification processing directly affects the performance of the function in the final hardware implementation.

[0041] In some implementations, the verification process simultaneously focuses on two core dimensions of the fitting results: numerical accuracy, i.e., the degree of deviation between the approximate function value and the true function value; and function continuity, i.e., the transition characteristics of the function at the boundaries of adjacent segmented intervals. It is understandable that ensuring only numerical accuracy while neglecting continuity may lead to abrupt changes in the function after hardware implementation, affecting system stability.

[0042] In step S140, in response to obtaining the verification result, an iterative optimization process is performed on the fitting correlation parameters to obtain the optimized fitting correlation parameters.

[0043] As used in this article, when iterative optimization is mentioned, it refers to the process of using validation results as input and gradually improving the overall performance of the fitting scheme by repeatedly adjusting the relevant fitting parameters. Iterative optimization can find the optimal balance point among multiple mutually constraining performance indicators.

[0044] In some implementations, iterative optimization no longer solely pursues the highest fitting accuracy, but rather comprehensively considers the fitting effect and the actual cost of hardware implementation. By continuously adjusting parameters, the final solution adapts to the resource constraints and performance requirements of the target hardware. In simple terms, the iterative optimization process gradually converges to the optimal parameter combination that meets the design requirements.

[0045] In step S150, the piecewise fitting result is updated based on the optimized fitting correlation parameters, and error compensation processing is performed on the piecewise fitting result to obtain the compensated fitting correlation parameters.

[0046] As used in this article, error compensation refers to the process of specifically correcting regions with relatively prominent errors in the piecewise fitting results, thereby improving the overall fitting accuracy. Error compensation can solve local accuracy bottlenecks without significantly increasing global hardware resource consumption.

[0047] In some implementations, error compensation focuses on high-error regions in piecewise fitting that are difficult to address through general parameter optimization. By adjusting these regions individually, the overall fitting accuracy is improved. Understandably, this targeted compensation approach is more hardware-efficient than simply increasing the overall fitting complexity.

[0048] In step S160, the compensated fitting parameters are mapped to hardware implementation code that matches the bit-level operations of the custom floating-point numerical model, so that the target hardware can implement the fitting of the target continuous function.

[0049] As used in this article, when referring to hardware implementation code, it can refer to hardware description language code that can be directly used in subsequent processes such as hardware synthesis, placement and routing, and whose numerical behavior is completely consistent with the simulation results of the custom floating-point numerical model. The generation of hardware implementation code is a crucial step connecting algorithm design and hardware implementation.

[0050] In some implementations, the mapping process of the hardware implementation code strictly follows the operational rules and semantics of the custom floating-point numerical model, ensuring that the generated hardware circuit can reproduce all numerical behaviors of the software simulation at runtime. As an example, and not a limitation, the generated hardware implementation code can be directly imported into integrated circuit design tools to complete subsequent hardware development processes.

[0051] The beneficial effects of the method 100 disclosed herein are as follows: by constructing a custom floating-point numerical model that matches the bit-level operations of the target hardware, the numerical semantic differences between software simulation and hardware implementation in traditional methods are eliminated, ensuring that the algorithm results can be directly mapped to the hardware; by adopting a process of initializing fitting control parameters, piecewise fitting combined with dual-dimensional verification and iterative optimization, the resource consumption and latency of hardware implementation can be effectively controlled while ensuring fitting accuracy and function continuity; and the automated processing from function input to hardware implementation code is realized, solving the problem of the separation between algorithm, verification and hardware implementation in traditional processes, and significantly improving the development efficiency of continuous function hardware implementation.

[0052] It should be noted that the above embodiments of this disclosure use hardware implementation fitting of continuous functions as an example for illustration only, and are not intended to limit the scope of protection of this disclosure. Based on the core technical concept of this disclosure, those skilled in the art can apply the method of this disclosure to other scenarios that require numerical fitting and hardware mapping, and can also reasonably adjust or combine the execution order and specific implementation method of each step. All such adjustments and combinations should fall within the scope of protection of this disclosure.

[0053] For practical applications such as digital computing and application-specific integrated circuit design, this disclosure aims to provide a unified method and system for numerical modeling, piecewise fitting, accuracy analysis, joint optimization, and hardware generation.

[0054] This integrated method and system can achieve the following objectives: provide a numerical computation model that matches the bit-level operation of hardware; automatically complete function segmentation and fitting; introduce a multi-function joint optimization mechanism to achieve collective optimality; introduce a lookup table compensation mechanism in error hotspot regions; construct a complete process chain of fitting-optimization-verification-generation; and support model-level accuracy verification and hardware verification.

[0055] Therefore, exemplary embodiments of other aspects of this disclosure are provided below.

[0056] In some embodiments, the custom floating-point numerical model achieves bit-level arithmetic matching with the target hardware through one or more of the following: configurable numerical precision, target hardware floating-point arithmetic logic, target hardware rounding rules, and target hardware special value handling rules. As an example, and not a limitation, configurable numerical precision can be achieved by adjusting the exponent and mantissa bit widths, for example, by configuring different precision combinations such as e5m10, e8m7, and e8m23 to adapt to the precision requirements and resource constraints of different hardware. As an example, and not a limitation, the target hardware floating-point arithmetic logic can reproduce the complete process of operations such as addition and multiplication, including exponent alignment, mantissa shifting, and normalization. As an example, and not a limitation, the target hardware rounding rules can use Guard bits, Round bits, and Sticky bits in conjunction with round-to-nearest-even hardware standard rounding logic. As an example, and not a limitation, the target hardware special value handling rules can cover the arithmetic and propagation rules for zero, infinity, and non-numbers, such as zero value propagation, infinity participation in arithmetic rules, and non-number priority propagation. This ensures that the numerical behavior of each stage of the process is consistent with the target hardware, eliminates the numerical semantic differences between software simulation and hardware implementation, and avoids performance degradation of the fitting results in the hardware.

[0057] In some implementations, a unified, custom floating-point numerical modeling system can be constructed to replace the traditional software-based floating-point representation of numbers in function fitting and verification. This not only provides basic numerical representation capabilities but also fully replicates the hardware floating-point arithmetic path, ensuring consistency throughout the subsequent fitting, error analysis, and hardware generation processes. In the example, the custom floating-point numerical modeling system can refer to a data structure system containing one sign bit, a configurable exponent bit, and a configurable mantissa bit. In some implementations, this system can support arbitrary precision combinations, such as e5m10, e8m7, e8m23, etc.; the exponent uses an offset representation, and the mantissa implicitly contains the highest-order bit; it also supports special value encodings for zero, infinity, and NOT numbers.

[0058] In some implementations, a custom floating-point numerical modeling system can simulate the complete hardware computation process. For example, for addition, the steps of exponent alignment, mantissa shift, mantissa addition / subtraction, normalization, and rounding are executed sequentially; for multiplication, the steps of mantissa multiplication, exponent addition, normalization, and rounding are executed sequentially.

[0059] In some implementations, hardware standard rounding logic can be used to perform round-to-nearest-even rounding by using the Guard bit, Round bit, and Sticky bit.

[0060] In some implementations, a custom floating-point numerical modeling system handles special cases uniformly, including zero-value propagation, infinite participation rules, and non-number priority propagation, ensuring consistency with hardware style (such as IEEE standards) and making behavior predictable in boundary cases.

[0061] In some implementations, a custom floating-point numerical modeling system is used for the internal numerical computation of the fitted target function. Its operational behavior is perfectly matched with the bit-level operations of the target hardware, ensuring that the numerical behavior of the final generated hardware implementation code is completely consistent with the function calculation results in the fitting stage, achieving a WYSIWYG design. Meanwhile, evaluation stages such as error analysis, derivative calculation, and model verification are performed using higher-precision floating-point formats (such as fp64 and fp128) supported by the computer system to eliminate benchmark error deviations across stages.

[0062] In some implementations, the custom floating-point numerical modeling system is used only for calculating the function values ​​of the fitted function to reproduce the computational results of the target hardware. First-order and second-order derivative calculations are performed in the aforementioned higher-precision floating-point format. Derivative calculations can be achieved through symbolic differentiation combined with high-precision floating-point arithmetic, or through approximate calculations in the high-precision floating-point numerical space using finite differences. Since continuous functions cannot be represented with completely accurate numerical precision in a computer, their gold standard representation must be obtained through high-precision floating-point approximation. The derivative calculated based on this gold standard can be used to accurately analyze the smoothness of the bounding point of the fitted function.

[0063] Additionally or alternatively, custom floating-point numerical modeling systems can be converted to standard floating-point formats, such as float16, bfloat16, and float32, by padding or rounding. These formats can be mapped to deep learning frameworks to replace model operators and perform inference verification, thereby achieving unified verification of the algorithm, model, and hardware and providing system-level accuracy evaluation capabilities.

[0064] In some embodiments, the piecewise fitting process includes: dividing the domain of the target continuous function into uniform or non-uniform segments to obtain multiple non-overlapping segmented intervals, and constructing a local approximation function for each segmented interval; wherein the evaluation of the numerical fitting accuracy is a point-by-point absolute error or relative error evaluation, and the verification of the continuity of multiple derivatives is a verification of the continuity of the first and second derivatives. Dividing the domain into segments can decompose the complex global fitting problem into multiple simple local fitting problems, thereby reducing the overall fitting difficulty and improving the local fitting accuracy. Constructing a local approximation function for each segmented interval allows for the selection of appropriate approximation methods based on the function shape of different intervals. The verification process evaluates the fitting quality from both numerical accuracy and function smoothness dimensions, avoiding focusing only on the error within the interval while ignoring boundary transitions. Thus, while ensuring fitting accuracy, the computational complexity of hardware implementation can be reduced, while improving the smoothness of the function and ensuring the operational stability of the system after hardware implementation.

[0065] In some implementations, a piecewise fitting and accuracy analysis method for continuous functions in hardware is proposed. This involves constructing an optimization system that simultaneously satisfies both numerical accuracy and function continuity constraints. This system not only evaluates the approximate accuracy within the interval but also rigorously verifies and constrains the smoothness of the function at the boundaries of each segment.

[0066] In some implementations, the fitting interval of the target continuous function is divided into multiple sub-intervals, and fitting is performed separately within each interval. The segmentation of the function's domain can employ methods such as equal-width segmentation, adaptive segmentation, or error-driven segmentation. In this way, a locally approximating function can be constructed within each interval, and all calculations are performed under a custom floating-point numerical model. This reduces the difficulty of fitting complex functions, improves local fitting accuracy, and provides structured modeling capabilities.

[0067] In some embodiments, the segmentation can be achieved by at least one of equal-width segmentation, adaptive segmentation, or error-driven segmentation; the local approximation function is based on polynomial approximation, and the polynomial parameters can be calculated by at least one of least squares method, minimax approximation, interpolation method, Chebyshev polynomial expansion, orthogonal polynomial expansion such as Legendre / Hermite / Bernstein, gradient descent method, Gauss-Newton method, or machine learning training.

[0068] Equal-width segmentation is simple to implement, has low control logic complexity, and is suitable for regions where the function shape changes gently; adaptive segmentation can adjust the size of the interval according to the rate of change of the function, dividing the interval into finer intervals in regions where the function changes drastically and dividing the interval into wider intervals in regions where the change is gentle; error-driven segmentation can dynamically adjust the interval division according to the fitting error distribution, increasing the number of segments in regions with large errors.

[0069] Polynomial approximation has a regular computational structure, is easy to implement in hardware, and is suitable for fitting most smooth functions. It can improve the batch accuracy of a large number of sampling points by iteratively optimizing polynomial parameters or the number of terms. However, it has the limitation that a small number of stubborn error points require extremely high hardware costs to optimize. Lookup table compensation can achieve error-free or near-error-free compensation for a small number of error points, but the hardware implementation cost increases quadratically with the number of compensation points.

[0070] In some implementations, a hybrid approach combining lookup tables and polynomial approximation can be used, combining the advantages of both: polynomial approximation processes most of the function region to control the overall hardware cost, while lookup table compensation precisely corrects a small number of stubborn error points, significantly improving the overall fitting accuracy without significantly increasing global resource consumption, flexibly adapting to different forms of target continuous functions, and achieving the optimal match between fitting effect and hardware cost.

[0071] In some embodiments, the verification process may include a first verification and a second verification. The first verification evaluates the numerical fitting accuracy within the piecewise intervals, and the second verification verifies the continuity of multiple derivatives at the boundaries of adjacent piecewise intervals. The first verification ensures that the deviation between the approximate function value and the true value within each piecewise interval is within an acceptable range, thereby guaranteeing the fitting quality. The second verification ensures a smooth transition of the piecewise function at connection points to avoid abrupt changes in function values ​​or derivatives, which could lead to stability problems in control systems or artificial intelligence models. Thus, both the numerical accuracy of the fit and the continuity of the function can be considered simultaneously, improving the quality of the fitting results.

[0072] In some implementations, error assessment is performed not only within the interval but also across the entire range. For example, input points can be sampled in a custom floating-point numerical space, and the fitted values ​​and true values ​​can be calculated separately. The difference between the two values ​​in hexadecimal representation is used to calculate the ULP (Unit in the Last Place) error, and the maximum error, average error, or error distribution can be statistically analyzed.

[0073] In some implementations, strict continuity constraints can be introduced at interval junctions to verify the smoothness of the fitted function. Specifically, for example, for each segment boundary point, not only the function values ​​are checked, but also the derivative behavior (e.g., this includes requiring that derivatives of each order are numerically approximate, with thresholds configured via smoothness constraint weights), and the difference results are statistically analyzed.

[0074] In some embodiments, the first verification may include statistical analysis of the errors of sampling points within each segment interval; the second verification may include verifying at least one of the continuity of function values, first derivative continuity, or second derivative continuity at the boundaries of adjacent segment intervals. As an example, and not a limitation, the error statistical analysis may calculate the ULP error, maximum error, average error, or error distribution of the sampling points to evaluate the fitting accuracy within the interval, wherein the ULP error can be obtained by calculating the difference between the fitted value and the true value in hexadecimal representation. As an example, and not a limitation, the derivative continuity verification may calculate the derivative values ​​of adjacent segments at the boundaries by sign differentiation or finite difference, and determine whether their difference is within a preset threshold. The threshold can be configured according to actual application requirements through smoothness constraint weights. Thus, a quantitative evaluation of the fitting results can be achieved, accurately locating problem areas in the fitting process and providing a clear basis for subsequent optimization.

[0075] In some implementations, verifying the continuity of function values ​​requires that the function values ​​of adjacent segments at the boundary points be approximately the same; verifying the continuity of the first derivative requires that the first derivative values ​​of adjacent segments at the boundary points be approximately the same; and verifying the continuity of the second derivative requires that the second derivative values ​​of adjacent segments at the boundary points be approximately the same. Derivatives can be approximated by sign differentiation of a polynomial or by finite difference in a custom floating-point numerical space. This approach ensures that the piecewise function is smooth at connection points, avoids jumps in hardware implementation, and improves the stability of the function in control systems or artificial intelligence models.

[0076] In some embodiments, parameter optimization can be performed by combining accuracy metrics and hardware cost metrics during iterative optimization. It's important to note that the iterative optimization process no longer solely pursues the highest fitting accuracy, nor blindly reduces hardware cost; instead, it considers the combined impact of both, seeking the optimal balance between accuracy and hardware cost by adjusting relevant fitting parameters. Therefore, as an example rather than a limitation, the optimization process can employ an optimization metric centered on gain, comprehensively quantifying the net benefit of improved accuracy versus increased cost. This avoids wasting hardware resources due to excessive pursuit of accuracy, and also avoids insufficient accuracy due to excessive resource conservation, achieving a globally optimal design.

[0077] In some implementations, gain is used as the core optimization metric. Gain can be equal to the accuracy metric multiplied by a first weight minus the hardware cost metric multiplied by a second weight. The accuracy metric includes ULP error or boundary smoothness error, etc.; the hardware cost metric includes hardware area, latency, or lookup table resources, etc.

[0078] In some embodiments, the accuracy metric may encompass the numerical fitting accuracy within the segmented interval and the smoothness accuracy of the segmented boundaries; the hardware cost metric may encompass at least one of hardware area, latency, or storage resources; and the fitting-related parameters may include at least one of the number of segments, the interval division method, the parameters of the local approximation function, or the weight of the smoothness constraint. As an example, and not a limitation, the numerical fitting accuracy within the interval can be quantified by metrics such as the maximum ULP error, and the smoothness accuracy of the segmented boundaries can be quantified by the maximum value of the derivative difference at the boundaries. As an example, and not a limitation, the hardware area may correspond to the number of hardware units such as multiply-accumulators and registers, the latency may correspond to the number of clock cycles of the operation, and the storage resources may correspond to the size of the lookup table. Thus, the optimization objectives and parameters can be quantified, enabling a configurable and traceable multi-objective optimization process, thereby making the optimization results more closely match actual hardware capabilities or requirements.

[0079] In some implementations, the optimization may include at least one of the following: polynomial order, number of segments, lookup table size, interval partitioning method, and smoothness constraint weights. This approach can automatically balance accuracy and hardware cost, incorporate continuity into the optimization objective, and support multi-objective optimization.

[0080] In some embodiments, the iterative optimization process terminates when any of the following conditions are met: a preset number of iterations is reached, the numerical fitting accuracy reaches a preset threshold, or the change in the fitted parameters is less than a preset threshold. Reaching the preset number of iterations prevents the optimization process from looping indefinitely, ensuring development efficiency and is suitable for scenarios with strict requirements on the development cycle; reaching the preset threshold ensures the accuracy requirements of the design and is an important termination condition; the change in the fitted parameters being less than the preset threshold indicates that the optimization process has converged, and further iterations will not significantly improve the effect. Therefore, the termination time of iterative optimization can be flexibly controlled, balancing optimization effectiveness and time cost.

[0081] In some embodiments, there are multiple target continuous functions. Piecewise fitting and verification processes are performed on each of the multiple target continuous functions to obtain multiple piecewise fitting results and multiple verification results. The iterative optimization process is a multi-function joint optimization, which includes jointly performing iterative optimization on the fitting-related parameters of the multiple target continuous functions based on the multiple verification results. The error compensation process includes identifying error hotspot regions in the multiple updated piecewise fitting results where the numerical error exceeds a preset threshold, and performing compensation operations on the error hotspot regions. It is important to note that multi-function joint optimization no longer optimizes the parameters of each function individually, but rather considers the accuracy requirements and hardware costs of all functions uniformly, utilizing the commonalities between different functions for parameter optimization. The hardware implementation covers the common parts of all functions, rather than designing separately for each function. Therefore, hardware resource sharing among multiple functions can be achieved, improving the overall system resource utilization and performance, and avoiding local optima.

[0082] In some implementations, multiple functions can be jointly optimized. Let the set of functions be {f1, f2, ..., f...} n The system uses the same set of parameters for multiple functions to calculate the overall performance index. The objective function is that the total gain equals the sum of the gains of each function multiplied by their corresponding weights. This allows for cross-function resource sharing, avoids local optima, and improves overall system performance.

[0083] In some embodiments, error compensation processing may include identifying error hotspot regions corresponding to piecewise fitting results where the numerical error exceeds a preset threshold, and performing compensation operations on these error hotspot regions. Error hotspot regions are typically areas where the function changes drastically, has a complex shape, or is difficult to fit using low-order polynomials. The fitting error in these regions is significantly higher than in other regions, becoming a bottleneck for overall fitting accuracy. By identifying and specifically processing these regions, overall fitting accuracy can be significantly improved without significantly increasing global hardware resources. This solves the local accuracy bottleneck and achieves efficient allocation of accuracy and resources.

[0084] In some implementations, lookup tables can be introduced to compensate for areas with large errors. Specifically, error hotspots with errors exceeding a preset threshold can be identified, and lookup tables can be used to replace polynomials in these hotspots, or a combination of lookup tables and polynomials can be used.

[0085] In some embodiments, the compensation operation can employ at least one of the following methods: fitting the error hotspot region using a lookup table alone, or fitting a combination of a lookup table and a local approximation function. Fitting the lookup table alone directly stores the true value or a high-precision approximation of the function within the error hotspot region, suitable for scenarios with small error hotspot regions. Fitting a combination of a lookup table and a local approximation function uses a local approximation function to obtain a basic approximation value, then stores the residual error using a lookup table, and finally adds the basic approximation value and the residual error to obtain the final result, suitable for scenarios with large error hotspot regions. Therefore, based on the size of the error hotspot region and the accuracy requirements, an appropriate compensation method can be selected, flexibly balancing storage and computational resources to achieve a dynamic balance between accuracy and hardware cost.

[0086] In some implementations, the lookup table compensation process is as follows: input x, perform interval judgment, execute a lookup table, optionally perform polynomial compensation, and output the result. This method can improve local accuracy, reduce the polynomial order, and enhance fitting stability.

[0087] In some embodiments, mapping the compensated fitting correlation parameters to hardware implementation code that matches the bit-level operations of the custom floating-point numerical model includes: converting the compensated fitting correlation parameters into one or more of a hardware computation structure, interval selection logic, or special value bypass processing logic. As an example, and not a limitation, the hardware computation structure can employ a Horner structure to implement polynomial operations, reducing the number of multipliers and critical path latency; the interval selection logic can determine the segmented interval to which the input value belongs through a comparator chain and select the corresponding fitting parameters; the special value bypass processing logic can directly output the corresponding result when the input is zero, infinite, or a non-number, bypassing the main computation path to improve computational efficiency. Thus, efficient and synthesizable hardware implementation code can be automatically generated, ensuring that hardware behavior is consistent with software simulation without the need for manual operator design.

[0088] It is understandable that mapping piecewise fitting parameters based on a custom floating-point numerical model to a synthesizable hardware structure to ensure consistency with the numerical behavior of the software simulation model can support not only basic polynomial approximation circuit generation, but also error compensation, boundary continuity optimization, and configurable pipeline structures.

[0089] In some implementations, the hardware generation module performs fitting parameter parsing and structure mapping, inputting segmented interval divisions and fitting function parameters for each segment, and outputting the corresponding hardware computation structure; it completes custom floating-point numerical semantic mapping, and all operations use mantissa alignment, rounding rules, and special value handling consistent with the software to ensure that hardware behavior is completely consistent with software simulation; it automatically generates control logic, including interval selection logic, multiplexers, and lookup table index control; and it supports performance and resource configurability, including single-cycle / multi-cycle operation, pipeline depth configuration, and resource sharing.

[0090] In some implementations, for polynomial functions, the Horner structure is used to map to hardware, reducing the number of multipliers and lowering latency paths. Each operator corresponds to a custom floating-point adder and a custom floating-point multiplier, with rounding and normalization embedded within the operator. The hardware does not use standard IEEE floating-point; instead, it fully replicates the custom floating-point behavior using arithmetic logic units.

[0091] In some implementations, the range to which the input value belongs is determined through a comparator chain. For regions with large fitting errors, a local lookup table compensation module is introduced, which is only activated in error hotspots. The lookup table stores the residual error or the corrected value of the true value, and the output is the sum of the polynomial calculated value and the residual error, or the output value of the function is directly replaced by the true value in the lookup table.

[0092] In some implementations, custom floating-point parameters are directly mapped to the exponent bit width, mantissa bit width, and rounding logic in the hardware; the fitted coefficients are quantized into a custom floating-point format and stored or hard-coded as hardware constants.

[0093] In some implementations, automatic pipeline insertion is supported, with optional strategies including full combination, hierarchical pipeline, and deep pipeline. The pipeline split point can be set after multiplication, addition, or interval selection.

[0094] In some implementations, special value processing logic consistent with the custom floating-point numerical model is implemented, outputting a non-number when the input is non-numerical, outputting infinity when the input is infinity, and outputting zero when the input is zero. This is implemented in hardware as a pre-detection module that bypasses the main calculation path.

[0095] In some embodiments, the verification process may further include model-level accuracy verification. Model-level accuracy verification may include embedding the fitted function into the target application system for accuracy verification. The verification results are used to correct the weights and parameter search space of the iterative optimization. Specifically, model-level accuracy verification may replace the corresponding mathematical operators in the target application system, such as activation function operators in deep learning models, with the generated fitted function to evaluate the impact of function approximation on the overall output accuracy of the system. The verification results can be fed back to the iterative optimization stage to adjust the weights of accuracy indicators and hardware cost indicators, or to narrow the parameter search space, further improving optimization efficiency and effectiveness. This ensures that the performance of the fitted function meets the requirements in real-world application scenarios, achieving unified verification of the algorithm, model, and hardware.

[0096] In some implementations, embedding fitted functions into deep learning models is supported. This includes encapsulating the function and providing an interface to replace mathematical operators in the model, performing computations using a custom floating-point numerical model, and validating the overall model output. This approach can verify the impact of function approximation on the model and supports inference-level testing and system-level validation.

[0097] In some embodiments, the above method may further include providing the verification results as input to the iterative optimization process for the next round of iterative optimization of the fitting-related parameters. It can be understood that the accuracy and smoothness data obtained in each round of verification can be used as the basis for the next round of iterative optimization to adjust the fitting-related parameters, thereby continuously improving the fitting effect. Thus, automated optimization of the fitting process can be achieved, reducing manual intervention and improving development efficiency and fitting quality.

[0098] In some implementations, the overall processing flow is as follows: input function, perform custom floating-point numerical modeling, initialize fitting control parameters, perform piecewise fitting, perform interval accuracy analysis and boundary point smoothness verification, perform gain evaluation, perform multi-function joint optimization, detect error hotspots and perform lookup table compensation, determine whether convergence has occurred, generate hardware implementation code, and perform model verification.

[0099] In some implementations, once the hardware is generated, it can be directly used for bit-by-bit comparison with the simulation results of a custom floating-point numerical model, embedded model inference verification, and error statistics feedback optimization modules, thereby forming a hardware-simulation-fitting and optimization-hardware update system.

[0100] Figure 2This is a schematic diagram of the Register Transfer Level (RTL) generation system 200 in some embodiments of this disclosure. It corresponds to a hardware architecture in which the aforementioned hardware implementation code mapping can be implemented, used to convert compensated fitting parameters into directly synthesizable hardware circuitry. It can be understood that this system architecture starts with input data in a custom floating-point format (DwFloat), sequentially undergoes interval judgment, coefficient selection, polynomial calculation, error compensation, and special value processing, ultimately outputting a function fitting result in the custom floating-point format.

[0101] In some implementations, the system architecture includes an input unit 210, an interval judgment module 220, a polynomial coefficient selection module 230, an optional look-up table (LUT) compensation selection module 240, a polynomial calculation module 250, an LUT error compensation adder 260, a special value processing module 270, and an output unit 280.

[0102] Input unit 210 is used to receive an input value x in a custom floating-point format. As used herein, when referring to a custom floating-point format, it can refer to the numerical format described above, which includes a 1-bit sign bit, a configurable exponent bit, and a configurable mantissa bit, and whose numerical behavior is completely consistent with the target hardware.

[0103] The interval determination module 220, connected to the input unit 210, is used to determine the segment interval to which the input value x belongs. In some embodiments, the interval determination module 220 can be implemented using a comparator chain, which determines the corresponding segment number by sequentially comparing the input value x with the boundary values ​​of each segment interval. This module corresponds to the interval selection logic included in the hardware implementation code mapping described above.

[0104] The polynomial coefficient selection module 230, connected to the interval judgment module 220, is used to select the corresponding polynomial fitting coefficients based on the segmented interval to which the input value x belongs. In some embodiments, the polynomial fitting coefficients can be pre-quantized into a custom floating-point format and integrated into the hardware circuit in a hard-coded or register-stored manner.

[0105] An optional LUT compensation selection module 240 (as depicted by the dashed line), connected to the interval judgment module 220, is used to select the corresponding LUT compensation value when the input value x is located in an error hotspot region. In some embodiments, the LUT compensation selection module 240 is only active when the error compensation function is enabled, and the compensation value stored therein can be a residual error or a true value correction value, corresponding to the specific hardware implementation of the error compensation processing described above.

[0106] The polynomial calculation module 250, connected to the polynomial coefficient selection module 230, is used to perform polynomial operations based on the selected polynomial coefficients and the input value x. In some implementations, the polynomial calculation module 250 is implemented using a Horner architecture, which reduces the number of multipliers and critical path latency through nested multiplication and addition operations; its internal multipliers and adders are dedicated arithmetic logic units that reproduce custom floating-point operation behavior and include built-in normalization and rounding logic.

[0107] The LUT error-compensated adder 260 is connected to both the polynomial calculation module 250 and the LUT compensation selection module 240. It is used to add the polynomial calculation result to the LUT compensation value to obtain the final approximate function value. In some embodiments, when the LUT compensation function is not enabled, the LUT error-compensated adder 260 can directly output the result from the polynomial calculation module 250.

[0108] The special value processing module 270 is connected to the input unit 210 and the LUT error compensation adder 260, respectively, and is used to handle special cases where the input value is zero, infinity, or a non-number. In some embodiments, the special value processing module 270 includes pre-detection logic. When a special value is detected in the input, the corresponding special value result is directly output, bypassing the main calculation path and improving computational efficiency. This module corresponds to the special value bypass processing logic included in the hardware implementation code mapping described above.

[0109] Output unit 280, connected to special value processing module 270, is used to output the final function fitting result in a custom floating-point format.

[0110] Understandably, the aforementioned system architecture supports configurable pipeline depth. For example, pipelined registers can be inserted after multiplication, addition, or interval checks to adapt to different clock frequencies and latency requirements. This system architecture strictly adheres to the operational semantics of the custom floating-point numerical model, ensuring complete consistency between the hardware implementation's numerical behavior and the software simulation results, achieving a WYSIWYG (What You See Is What You Get) effect.

[0111] Figure 3 This is a schematic diagram of the structure of a data fitting device 300 for implementation using an application-specific integrated circuit (ASIC) according to some embodiments of this disclosure. It will be understood that the device 300 includes a numerical modeling module 310, a piecewise fitting module 320, a verification module 330, an optimization module 340, an error compensation module 350, and a code generation module 360.

[0112] The numerical modeling module 310 is used to construct a custom floating-point numerical model that matches the bit-level operations of the target hardware.

[0113] The piecewise fitting module 320 is used to initialize fitting control parameters, which include the segmentation interval division method and smoothness constraint weights. Based on the custom floating-point numerical model and the fitting control parameters, it performs piecewise fitting processing on the target continuous function to obtain piecewise fitting results. The piecewise fitting results include segmentation interval division information and / or local approximation function parameters. The piecewise fitting results and the fitting control parameters together constitute fitting-related parameters.

[0114] Verification module 330 is configured to, in response to obtaining the piecewise fitting result, perform verification processing on the piecewise fitting result based on the custom floating-point numerical model and the fitting-related parameters. The verification processing includes a first verification unit 3301 and a second verification unit 3302. The first verification unit 3301 is configured to evaluate the numerical fitting accuracy within each segment interval to obtain accuracy evaluation data. The second verification unit 3302 is configured to verify the continuity of the multi-order derivatives at the boundaries of adjacent segment intervals based on the smoothness constraint weights in the fitting correlation parameters to obtain continuity verification data. The verification module 330 is further configured to integrate the accuracy assessment data with the continuity verification data to obtain the verification result.

[0115] The optimization module 340 is used to perform iterative optimization processing on the fitting correlation parameters in response to obtaining the verification result, so as to obtain the optimized fitting correlation parameters.

[0116] The error compensation module 350 is used to update the segmented fitting result based on the optimized fitting correlation parameters, and to perform error compensation processing on the segmented fitting result to obtain the compensated fitting correlation parameters.

[0117] The code generation module 360 ​​is used to map the compensated fitting parameters into hardware implementation code that matches the bit-level operations of the custom floating-point numerical model, so that the target hardware can implement the fitting of the target continuous function.

[0118] The beneficial effects of the device 300 disclosed herein are as follows: by constructing a custom floating-point numerical model that matches the bit-level operations of the target hardware, the numerical semantic differences between software simulation and hardware implementation in traditional methods are eliminated, ensuring that algorithm results can be directly mapped to hardware; by adopting a process of initializing fitting control parameters, piecewise fitting combined with dual-dimensional verification and iterative optimization, the resource consumption and latency of hardware implementation can be effectively controlled while ensuring fitting accuracy and function continuity; and the automated processing from function input to hardware implementation code is realized, solving the problem of the separation between algorithm, verification and hardware implementation in traditional processes, and significantly improving the development efficiency of continuous function hardware implementation.

[0119] In some implementations, the custom floating-point numerical model achieves bit-level arithmetic matching with the target hardware through one or more of the following: configurable numerical precision, target hardware floating-point arithmetic logic, target hardware rounding rules, and target hardware special value handling rules. This ensures that the numerical behavior at each stage of the entire process is completely consistent with the target hardware, eliminating the numerical semantic differences between software simulation and hardware implementation.

[0120] In some implementations, the piecewise fitting module can be used to perform uniform or non-uniform segmentation of the domain of the target continuous function to obtain multiple non-overlapping segmented intervals, and to construct a local approximation function for each segmented interval; the verification module is used to perform numerical fitting accuracy evaluation within the segmented intervals (such as pointwise absolute or relative error evaluation), and to verify the continuity of multiple derivatives at the boundaries of adjacent segmented intervals (such as first and second derivative continuity verification). Thus, while ensuring fitting accuracy, the computational complexity of the hardware implementation can be reduced, while improving the smoothness of the function.

[0121] In some implementations, the piecewise fitting module can support combinations of multiple piecewise strategies and multiple approximation function strategies; the piecewise strategies may include at least one of equal-width piecewise segments, adaptive piecewise segments, or error-driven piecewise segments; the approximation function strategies may include at least one of polynomial approximation, lookup tables, or a hybrid of lookup tables and polynomial approximation, as described above. Therefore, it can flexibly adapt to target continuous functions of different forms, achieving an optimal match between fitting performance and hardware cost.

[0122] In some implementations, the verification module can support configurable accuracy thresholds and smoothness constraint thresholds, and output error distribution and boundary continuity analysis reports. The first verification includes statistical analysis of errors at sampling points within each segment interval; the second verification includes verifying at least one of the following: function value continuity, first derivative continuity, or second derivative continuity at the boundaries of adjacent segment intervals. This allows for a quantitative evaluation of the fitting results and precise location of problem areas in the fitting process.

[0123] In some implementations, the optimization module can be used to perform parameter optimization by combining accuracy metrics with hardware cost metrics during iterative optimization. This avoids both the waste of hardware resources due to excessive pursuit of accuracy and insufficient accuracy due to excessive resource conservation, thus achieving a globally optimal design.

[0124] In some implementations, the accuracy metric may encompass the numerical fitting accuracy within the segmented intervals and the smoothness accuracy of the segmented boundaries; the hardware cost metric may encompass at least one of hardware area, latency, or storage resources; and the fitting-related parameters may include at least one of the number of segments, the interval division method, the parameters of the local approximation function, or the weights of the smoothness constraints. Thus, the optimization objective and parameters can be quantified, enabling a configurable and traceable multi-objective optimization process.

[0125] In some implementations, the optimization module can terminate the iteration when any of the following conditions are met: the preset number of iterations is reached, the numerical fitting accuracy reaches a preset threshold, or the change in the fitted parameters is less than a preset threshold. This allows for flexible control over the termination timing of iterative optimization, balancing optimization effectiveness with time cost.

[0126] In some implementations, there can be multiple target continuous functions. The piecewise fitting module and the verification module can perform piecewise fitting and verification processes on the multiple target continuous functions, respectively, to obtain multiple piecewise fitting results and multiple verification results. The optimization module can support a multi-function joint optimization mode, including iterative optimization of the fitting-related parameters of the multiple target continuous functions based on the multiple verification results. This enables hardware resource sharing among multiple functions, improving the overall system resource utilization and performance.

[0127] In some implementations, the error compensation module can be used to identify error hotspots in multiple updated piecewise fitting results where the numerical error exceeds a preset threshold, and to perform compensation operations on these error hotspots. This can precisely address local accuracy bottlenecks and achieve efficient allocation of accuracy and resources.

[0128] In some implementations, the error compensation module can adopt a hybrid architecture that combines lookup tables and function approximation, enabling lookup table resources only in error hotspot regions. The compensation operation can employ at least one method: fitting the error hotspot region using the lookup table alone, or fitting a combination of the lookup table and a local approximation function. Therefore, an appropriate compensation method can be selected based on the size of the error hotspot region and the accuracy requirements, flexibly balancing storage and computational resources.

[0129] In some implementations, the code generation module can generate hardware implementation code that includes hardware computational structures, interval selection logic, and special value bypassing logic. This automatically generates efficient, synthesizable hardware implementation code, ensuring that hardware behavior is completely consistent with software simulation.

[0130] In some implementations, the verification module can also be used to perform model-level accuracy verification. Model-level accuracy verification may include embedding the fitted function into the target application system for accuracy verification. The verification results can be used to correct the weights and parameter search space of the iterative optimization. This ensures that the performance of the fitted function meets requirements in real-world application scenarios, achieving unified verification of the algorithm, model, and hardware.

[0131] In some embodiments, the apparatus 300 may further include a feedback module, which can be used to provide the verification result as input to the optimization module for iterative optimization of the relevant fitting parameters in the next round. This enables automated optimization of the fitting process, reduces manual intervention, and improves development efficiency and fitting quality.

[0132] The operations of the numerical modeling module 310, piecewise fitting module 320, verification module 330, optimization module 340, error compensation module 350, and code generation module 360 ​​described above can be combined. Figure 1 The operations of steps S110, S115, S120, S130, S140, S150 and S160 are similar, so the details of each aspect will not be repeated here.

[0133] According to one aspect of this disclosure, a computer device is also provided, including a memory, a processor, and a computer program stored in the memory. The processor is configured to execute the computer program to implement the steps of any of the method embodiments described above.

[0134] According to one aspect of this disclosure, a non-transitory computer-readable storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the steps of any of the method embodiments described above.

[0135] According to one aspect of this disclosure, a computer program product is also provided, which includes a computer program that, when executed by a processor, implements the steps of any of the method embodiments described above.

[0136] Figure 4 An example computer device 400 is shown in which any of the embodiments described herein may be implemented. Computer device 400 may be used to implement one or more components of the systems and methods described above. Computer device 400 may include a bus 402 or other communication mechanism for communicating information, and one or more processors 404 coupled to the bus 402 for processing information. Processor 404 may be, for example, one or more general-purpose microprocessors.

[0137] Computer device 400 may also include main memory 406, such as random access memory (RAM), cache, and / or other dynamic storage devices, coupled to bus 402, for storing information and instructions to be executed by processor 404. Main memory 406 may also be used to store temporary variables or other intermediate information during the execution of instructions to be executed by processor 404. Such instructions, when stored in a storage medium accessible to processor 404, can make computer device 400 a special-purpose machine customized to perform the operations specified in the instructions. Main memory 406 may include non-volatile media and / or volatile media. Non-volatile media may include, for example, optical discs or magnetic disks. Volatile media may include dynamic memory. Common media formats may include, for example, floppy disks, collapsible disks, hard disks, solid-state drives, magnetic tapes or any other magnetic data storage media, CD-ROMs (read-only optical disc drives), any other optical data storage media, any physical media with a perforated arrangement, RAM (random access memory), DRAM (dynamic random access memory), PROM (programmable read-only memory) and EPROM (erasable programmable read-only memory), FLASH-EPROM (fast erase programmable read-only memory), NVRAM (non-volatile random access memory), any other memory chips or tape cartridges, or network versions of the above.

[0138] Computer device 400 may implement the techniques described herein using custom hardwired logic, one or more ASICs (Application-Specific Integrated Circuits) or FPGAs (Field-Programmable Gate Arrays), firmware, and / or program logic, which, when combined with computer device 400, enable computer device 400 to become a special-purpose machine or to be programmed therein. According to one embodiment, the techniques described herein are executed by computer device 400 in response to processor 404 executing one or more sequences of one or more instructions contained in main memory 406. Such instructions may be read into main memory 406 from another storage medium, such as storage device 408. Executing the sequence of instructions contained in main memory 406 causes processor 404 to perform the processing steps described herein. For example, the processes / methods disclosed herein may be implemented by computer program instructions stored in main memory 406. When these instructions are executed by processor 404, they may perform the steps shown in the corresponding figures and as described above. In alternative embodiments, hardwired circuitry may be used in place of or in combination with software instructions.

[0139] Computer device 400 also includes a network interface 410 coupled to bus 402. Network interface 410 can provide bidirectional data communication coupled to one or more network links connected to one or more networks. As another example, network interface 410 can be a local area network (LAN) card to provide data communication connectivity with a compatible LAN (or a WAN component communicating with a WAN (wide area network)). Wireless links can also be implemented.

[0140] The performance of certain operations can be distributed across processors, not just residing within a single machine, but deployed across many machines. In some exemplary embodiments, the processor or the processor-implemented engine may reside in a single geographic location (e.g., in a home environment, office environment, or server farm). In other exemplary embodiments, the processor or the processor-implemented engine may be distributed across many geographic locations.

[0141] Each process, method, and algorithm described in the preceding sections can be embodied in a code module executed by one or more computer systems or computer processors including computer hardware, and can be fully or partially automated by them. These processes and algorithms can be implemented, in part or in whole, in a specific application circuit.

[0142] When the functions disclosed herein are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Specific technical solutions (all or part) disclosed herein, or aspects contributing to the prior art, can be embodied in the form of a software product. This software product can be stored in a storage medium and includes instructions to cause a computer device (which may be a personal computer, server, network device, etc.) to perform all or part of the steps of the methods of the embodiments of this application. The storage medium may include a flash drive, a portable hard drive, ROM, RAM, a magnetic disk, an optical disk, another medium suitable for storing program code, or any combination thereof.

[0143] The embodiments disclosed herein can be implemented via a cloud platform, server, or group of servers that interact with a client. The client can be a terminal device or a client registered by a user on the platform, wherein the terminal device can be a mobile terminal, a personal computer (PC), or any device that can install platform applications.

[0144] The various features and processes described above can be used independently or combined in various ways. All possible combinations and sub-combinations are intended to fall within the scope of this disclosure. Furthermore, certain method or process blocks may be omitted in some embodiments. The methods and processes described herein are not limited to any particular order, and associated blocks or states may be executed in other suitable orders. For example, described blocks or states may be executed in a non-specifically disclosed order, or multiple blocks or states may be combined in a single block or state. Exemplary blocks or states may be executed serially, in parallel, or otherwise. Blocks or states may be added to or removed from the disclosed exemplary embodiments. The exemplary systems and components described herein may be configured differently from those described. For example, elements may be added, removed, or rearranged compared to the disclosed exemplary embodiments.

[0145] The various operations of the exemplary methods described herein can be performed at least in part by an algorithm. An algorithm may consist of program code or instructions stored in memory (such as the non-transitory computer-readable storage medium described above). Such an algorithm may include a machine learning algorithm. In some embodiments, the machine learning algorithm may not be explicitly programmed into the computer to perform the function, but may learn from training data to obtain a predictive model for performing that function.

[0146] The various operations of the exemplary methods described herein can be performed at least in part by one or more processors, which are temporarily configured (e.g., by software) or permanently configured to perform the relevant operations. Whether temporarily or permanently configured, such processors can constitute the engine of a processor implementation whose operation is to perform one or more of the operations or functions described herein.

[0147] Similarly, the methods described herein can be implemented at least partially by a processor, where a specific processor or one or more processors are examples of hardware. For example, at least some operations of the methods can be performed by one or more processors or an engine implemented by a processor. Furthermore, one or more processors can also run in a “cloud computing” environment or as “Software as a Service” (SaaS) to support the execution of the relevant operations. For example, at least some operations can be performed by a group of computers (as an example of a machine including processors), which can be accessed via a network (e.g., the Internet) and through one or more appropriate interfaces (e.g., application programming interfaces (APIs)).

[0148] The performance of certain operations can be distributed across processors, not just residing within a single machine, but deployed across many machines. In some exemplary embodiments, the processor or the processor-implemented engine may reside in a single geographic location (e.g., in a home environment, office environment, or server farm). In other exemplary embodiments, the processor or the processor-implemented engine may be distributed across many geographic locations.

[0149] In this specification, multiple instances may implement components, operations, or structures described as a single instance. Although individual operations of one or more methods are described and illustrated as independent operations, one or more individual operations may be performed concurrently, and these operations are not required to be performed in the order shown. Structures and functionalities presented as independent components in the example configuration may be implemented as combined structures or components. Similarly, structures and functionalities presented as individual components may be implemented as independent components. These and other variations, modifications, additions, and improvements are all within the scope of this document.

[0150] As used herein, “or” is inclusive rather than exclusive unless explicitly stated or indicated by context. Furthermore, “and” is both common and individual unless explicitly stated or indicated by context. Moreover, multiple instances may be provided for the resources, operations, or structures described herein as a single example. Furthermore, the boundaries between various resources, operations, engines, and data stores are somewhat arbitrary, and specific operations are illustrated within the context of a particular illustrative configuration. The allocation of other functionalities is conceivable and may fall within the scope of various embodiments of this disclosure. Generally, structures and functionalities presented as independent resources in example configurations may be implemented as combined structures or resources. Similarly, structures and functionalities presented as individual resources may be implemented as independent resources. These and other variations, modifications, additions, and improvements are all within the scope of embodiments of this disclosure. Therefore, this specification and accompanying drawings should be viewed in an illustrative rather than restrictive sense.

[0151] The terms “comprising” or “including” are used to indicate the presence of a subsequently stated feature, but do not preclude the addition of other features. Conditional language, in particular, such as “may,” “can,” or “may,” unless specifically stated or otherwise understood in the context of use, is generally intended to express that certain embodiments include certain features, elements, and / or steps, while other embodiments do not. Therefore, such conditional language generally does not imply that a feature, element, and / or step is necessary in any way for one or more embodiments, or that one or more embodiments must include logic that, with or without user input or prompting, determines whether such features, elements, and / or steps are included in any particular embodiment, or whether they are to be performed in any particular embodiment.

Claims

1. A data fitting method for application-specific integrated circuit (ASIC) implementation, characterized in that, The method includes: Construct a custom floating-point numerical model that matches the bit-level operations of the target hardware; Initialize the fitting control parameters, which include the segmentation interval division method and smoothness constraint weights; Based on the custom floating-point numerical model and the fitting control parameters, a piecewise fitting process is performed on the target continuous function to obtain a piecewise fitting result, wherein the piecewise fitting result includes segment interval division information and / or local approximation function parameters, and wherein the piecewise fitting result and the fitting control parameters constitute fitting related parameters. In response to obtaining the piecewise fitting result, a verification process is performed on the piecewise fitting result based on the custom floating-point numerical model and the fitting-related parameters. The verification process includes a first verification and a second verification, wherein: The first verification is used to evaluate the accuracy of numerical fitting within each segment interval in order to obtain accuracy evaluation data; The second verification is used to verify the continuity of the multi-order derivatives at the boundaries of adjacent segment intervals based on the smoothness constraint weights in the fitting correlation parameters, so as to obtain continuity verification data; The accuracy assessment data is integrated with the continuity verification data to obtain the verification result of the verification process; In response to obtaining the verification result, an iterative optimization process is performed on the fitting correlation parameters to obtain optimized fitting correlation parameters; The piecewise fitting results are updated based on the optimized fitting parameters, and error compensation processing is performed on the piecewise fitting results to obtain the compensated fitting parameters. The compensated fitting parameters are mapped to hardware implementation code that matches the bit-level operations of the custom floating-point numerical model, so that the target hardware can implement the fitting of the target continuous function.

2. The method according to claim 1, characterized in that, The custom floating-point numerical model achieves bit-level operation matching with the target hardware through one or more of the following: It can configure numerical precision, target hardware floating-point operation logic, target hardware rounding rules, and target hardware special value handling rules.

3. The method according to claim 1, characterized in that, The piecewise fitting process includes: The domain of the objective continuous function is divided into uniform or non-uniform segments to obtain multiple non-overlapping intervals. Construct a local approximation function for each segmented interval; The numerical fitting accuracy is evaluated by point-by-point absolute error or relative error, and the continuity of the multi-order derivatives is verified by the continuity of the first and second derivatives.

4. The method according to claim 1, characterized in that, The iterative optimization process terminates when any of the following conditions are met: The preset number of iterations is reached, the numerical fitting accuracy reaches a preset threshold, and the change in the fitting-related parameters is less than a preset threshold.

5. The method according to claim 1, characterized in that, The target continuous function is multiple, and piecewise fitting and verification processes are performed on the multiple target continuous functions respectively to obtain multiple piecewise fitting results and multiple verification results; The iterative optimization process is a multi-function joint optimization, which includes jointly performing iterative optimization on the fitting parameters of multiple target continuous functions based on the multiple verification results; The error compensation process includes identifying error hotspot regions in multiple updated piecewise fitting results where the numerical error exceeds a preset threshold, and performing compensation operations on the error hotspot regions.

6. The method according to claim 1, characterized in that, The hardware implementation code that maps the compensated fitting correlation parameters to bit-level operations matching the custom floating-point numerical model includes: converting the compensated fitting correlation parameters into one or more of the following: hardware computing structure, interval selection logic, or special value bypass processing logic. The method further includes: The verification results are provided as input to the iterative optimization process for the next round of iterative optimization of the relevant parameters.

7. A data fitting device for implementation using an application-specific integrated circuit (ASIC), characterized in that, include: The numerical modeling module is configured to build custom floating-point numerical models that match the bit-level operations of the target hardware. The piecewise fitting module is configured to initialize fitting control parameters, which include the segmentation interval division method and smoothness constraint weights. Based on the custom floating-point numerical model and the fitting control parameters, it performs piecewise fitting processing on the target continuous function to obtain piecewise fitting results. The piecewise fitting results include segmentation interval division information and / or local approximation function parameters. The piecewise fitting results and the fitting control parameters together constitute fitting-related parameters. The verification module is configured to, in response to obtaining the piecewise fitting result, perform verification processing on the piecewise fitting result based on the custom floating-point numerical model and the fitting-related parameters. The verification processing includes a first verification unit and a second verification unit. The first verification unit is configured to evaluate the numerical fitting accuracy within each segment interval to obtain accuracy evaluation data. The second verification unit is configured to verify the continuity of the multi-order derivatives at the boundaries of adjacent segment intervals based on the smoothness constraint weights in the fitting correlation parameters to obtain continuity verification data. The verification module is further configured to integrate the accuracy assessment data with the continuity verification data to obtain the verification result; The optimization module is configured to perform iterative optimization processing on the fitting correlation parameters in response to obtaining the verification result, so as to obtain the optimized fitting correlation parameters; The error compensation module is configured to update the piecewise fitting result based on the optimized fitting correlation parameters, and perform error compensation processing on the piecewise fitting result to obtain the compensated fitting correlation parameters. The code generation module is configured to map the compensated fitting parameters to hardware implementation code that matches the bit-level operations of the custom floating-point numerical model, so that the target hardware can implement the fitting of the target continuous function.

8. A computer device, characterized in that, The computer device includes: processor; A memory having a computer program stored thereon, wherein, when executed by the processor, the computer program causes the processor to perform the method of any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, causes the processor to perform the method of any one of claims 1-6.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, causes the processor to perform the method of any one of claims 1-6.

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