SoC forced into burning mode circuit controlled by USB debugging serial port

Abstract

This invention belongs to the field of electronic circuit technology and relates to a circuit for forcibly entering the programming mode of a SoC controlled by a USB debugging serial port. The method includes: a USB-to-TTL serial port circuit for converting the input signal from the host computer into a TTL serial port signal and outputting a control level to a level trigger circuit; a level trigger circuit for generating a trigger signal based on the control level; a timing control circuit electrically connected to the output of the level trigger circuit for adjusting the timing of the trigger signal, generating a download mode trigger signal and a reset signal that meet the requirements of the SoC programming mode and outputting them to the SoC; and an anti-false triggering auxiliary circuit. This invention eliminates the need for physical buttons, jumpers, and dedicated debuggers, enabling physical operation-free triggering of the SoC programming mode. It effectively solves the risks of disassembling sealed devices and the difficulties of on-site maintenance, while also supporting remote USB redirection for off-site programming, significantly improving debugging efficiency and system maintainability.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit technology, specifically relating to a circuit for forcing a SoC into programming mode via USB debug serial port control. Background Technology

[0002] Firmware programming and debugging of SoC chips are essential steps in the development, production, and maintenance of embedded systems. Currently, mainstream SoC programming methods primarily rely on physical operations, including manually pressing the reset and boot buttons, shorting specific pins with jumper caps, or using a dedicated JTAG / SWD debugger to connect to the chip's debugging interface. These traditional methods have many insurmountable drawbacks in practical applications.

[0003] First, physical buttons and jumpers require operators to directly access the internal circuitry of the device. For pre-packaged products, especially SoC systems installed in enclosed chassis, outdoor terminals, or portable devices, disassembly is necessary to trigger the firmware flashing mode. This is not only cumbersome and inefficient, but also introduces the risk of physical damage, compromising the device's original waterproof and dustproof structure and reducing product reliability. In mass production, firmware flashing for a large number of products requires significant manpower and time, severely impacting production efficiency.

[0004] Secondly, while some existing SoC chips support entering programming mode by sending specific commands via serial port, this method has significant limitations. Serial command triggering relies on the early initialization of the serial port receiving module after the chip powers on. If the firmware is faulty or the bootloader is corrupted, the serial command will not be responded to correctly by the chip, requiring a return to physical button forced mode. This renders the method ineffective when the device experiences firmware failure, and thus unsuitable as a reliable emergency maintenance method.

[0005] Furthermore, traditional methods are completely incapable of supporting remote maintenance scenarios. When devices deployed in remote areas or hard-to-reach locations experience firmware issues, technicians must physically go to the site to perform button presses or jumper operations, resulting in high on-site maintenance costs and delayed firmware upgrade responses. For large-scale deployments of IoT terminal devices, the cost and efficiency issues of this maintenance method are particularly prominent.

[0006] To address the aforementioned issues, some improved solutions have emerged in the existing technology. These solutions input a detection signal to an external circuit, which triggers the SoC and controls the BOOT mode to enter the programming mode. However, this solution still has the following shortcomings: First, it requires a dedicated external detection signal, making it impossible to utilize the device's existing USB debug serial port as a control channel. Second, it lacks effective anti-interference and protection mechanisms, making it prone to false triggering when there are cable plugging / unplugging, external environmental interference, or abnormal software instructions, leading to abnormal circuit reset or accidental entry into programming mode. Third, the timing control is inflexible and difficult to adapt to the programming mode entry conditions of various SoC models. Fourth, it still requires a dedicated external triggering device and cannot be directly controlled by the host computer software.

[0007] Therefore, there is an urgent need for a circuit solution that requires no physical buttons, no disassembly, and can automatically force entry into the burning mode, thereby fundamentally solving the problems existing in the current technology. Summary of the Invention

[0008] To address the aforementioned technical problems, the present invention provides a solution. The present invention provides a circuit for forcibly entering programming mode for a SoC controlled by a USB debug serial port, comprising: The USB to TTL serial port circuit is used to convert the input signals of the host computer into TTL serial port signals and output the control level to the level trigger circuit. The level-triggered circuit is connected to the output electrical signal of the USB to TTL serial port circuit and is used to generate a trigger signal according to the control level. The timing control circuit is electrically connected to the output of the level trigger circuit. It is used to adjust the delay time of the download mode trigger signal and the reset signal by adjusting the RC circuit parameters, thereby adjusting the timing of the trigger signal, generating download mode trigger signals and reset signals that meet the requirements of the SoC programming mode, and outputting them to the SoC. The anti-false triggering auxiliary circuit is connected to the output terminal of the level triggering circuit and then to the input terminal of the timing control circuit. It is used to control the output signal of the level triggering circuit according to the access status of the external device.

[0009] In some optional embodiments, a power bus is also included; the power bus is electrically connected to the power input terminals of the USB to TTL serial port circuit, the level triggering circuit, the timing control circuit, and the anti-false triggering auxiliary circuit, respectively.

[0010] In some optional embodiments, the USB to TTL serial port circuit includes a USB to TTL serial port chip and a USB interface; the USB to TTL serial port chip and the USB interface are electrically connected.

[0011] In some alternative embodiments, the USB interface is a Type-C interface or a Type-B interface.

[0012] In some optional embodiments, the level-triggered circuit includes a D flip-flop; the CLK pin of the D flip-flop is electrically connected to the first output terminal of the USB-to-TTL serial port circuit; the D pin of the D flip-flop is electrically connected to the second output terminal of the USB-to-TTL serial port circuit; the clear terminal of the D flip-flop is electrically connected to the second output terminal of the USB-to-TTL serial port circuit; and the Q pin of the D flip-flop, as the output terminal of the level-triggered circuit, is electrically connected to the input terminal of the timing control circuit and the output terminal of the anti-false triggering auxiliary circuit.

[0013] In some optional embodiments, the level-triggered circuit further includes a first power interface, a first resistor, a second power interface, a second resistor, a first capacitor, and a third resistor; the first power interface is electrically connected to the CLK pin of the D flip-flop through the first resistor; the first power interface is electrically connected to the power input terminal of the D flip-flop and the first terminal of the first capacitor; the second terminal of the first capacitor is grounded; the D pin of the D flip-flop is grounded through the second resistor; and the Q pin of the D flip-flop is electrically connected to the output terminal of the level-triggered circuit through the third resistor.

[0014] In some optional embodiments, the timing control circuit includes a first RC delay circuit and a second RC delay circuit; The first RC delay circuit includes a first diode, a fourth resistor, a second capacitor, and a first transistor; the output terminal of the level trigger circuit is electrically connected to the first terminal of the first diode, the first terminal of the fourth resistor, and the first terminal of the second capacitor; the second terminal of the fourth resistor is electrically connected to the base of the first transistor; the collector of the first transistor is electrically connected to the first output terminal of the timing control circuit; the second terminal of the second capacitor and the emitter of the first transistor are grounded. The second RC delay circuit includes a second diode, a fifth resistor, a third capacitor, and a second transistor; the output of the level trigger circuit is electrically connected to the first end of the fifth resistor and the first end of the third capacitor through the second diode; the second end of the fifth resistor is electrically connected to the base of the second transistor; the collector of the second transistor is electrically connected to the second output of the timing control circuit; the second end of the third capacitor and the emitter of the second transistor are grounded.

[0015] In some optional embodiments, the delay time constant of the first RC delay unit is changed by adjusting the parameter values ​​of the fourth resistor and the second capacitor; the delay time constant of the second RC delay unit is changed by adjusting the parameter values ​​of the fifth resistor and the third capacitor.

[0016] In some optional embodiments, the anti-false triggering auxiliary circuit includes a USB OTG interface, a sixth resistor, a third transistor, a seventh resistor, a third power interface, and a fourth transistor; the ID detection interface pin of the USB OTG interface is connected to the base electrical signal of the third transistor through the sixth resistor; the third power interface is connected to the collector of the third transistor and the base electrical signal of the fourth transistor through the seventh resistor; the collector of the fourth transistor is connected to the output electrical signal of the level trigger circuit; the emitter of the fourth transistor is grounded.

[0017] In some alternative embodiments, the third and fourth transistors are NPN transistors.

[0018] The beneficial effects of this invention are: (1) The present invention uses a USB to TTL serial port circuit as the control channel. The host computer can trigger the SoC to enter the burning mode by controlling the level trigger circuit, which completely replaces the traditional physical buttons, jumpers and manual adjustment of BOOT level. It avoids physical damage and failure of waterproof and dustproof structure caused by disassembling sealed equipment. It is especially suitable for outdoor terminals, portable devices and systems that have been installed. (2) This invention does not require a dedicated debugger. It only requires a standard data cable to complete the burning and debugging, which not only reduces the hardware cost of debugging, but also simplifies the operation process. Operators do not need to have professional hardware debugging knowledge. They can complete all operations through the host computer software. (3) The timing control circuit can flexibly change the delay time of the download mode trigger signal and the reset signal by adjusting the RC circuit parameters, thereby adapting to the timing requirements of the programming mode of different SoC chips. It can be applied to a variety of SoC chips with different architectures and has strong versatility. (4) By adding an auxiliary circuit based on preventing false triggering, the output level is forcibly locked when no external host is connected, which effectively avoids abnormal circuit reset or false entry into the burning mode caused by false triggering, cable plugging and unplugging interference or abnormal software instructions, thus ensuring the stability of timing control. (5) This invention relies on the debugging serial port as the control channel, which enables remote engineers to remotely burn firmware and debug equipment, and is especially suitable for large-scale deployment of IoT terminal equipment. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the circuit for forcibly entering the programming mode of a SoC controlled by a USB debugging serial port, provided in Embodiment 1 of the present invention. Figure 2 This is a circuit diagram of the USB to TTL serial port circuit provided in Embodiment 1 of the present invention; Figure 3This is a circuit diagram of the level triggering circuit provided in Embodiment 1 of the present invention; Figure 4 This is a circuit diagram of the timing control circuit provided in Embodiment 1 of the present invention; Figure 5 This is a circuit diagram of the anti-false triggering auxiliary circuit provided in Embodiment 1 of the present invention.

[0020] In the diagram: U1 - USB to TTL serial port chip; U2 - D flip-flop; J1 - USB interface; V1 - first power interface; R1 - first resistor; V2 - second power interface; R2 - second resistor; C1 - first capacitor; R3 - third resistor; D1 - first diode; R4 - fourth resistor; C2 - second capacitor; Q1 - first transistor; U3 - USB OTG interface; D2 - second diode; R5 - fifth resistor; C3 - third capacitor; Q2 - second transistor; R6 - sixth resistor; R7 - seventh resistor; V3 - third power interface; Q3 - third transistor; Q4 - fourth transistor. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0022] Example 1 As an example, to address the problems existing in the prior art, this embodiment provides a circuit for forcing a SoC into programming mode via USB debug serial port control.

[0023] The implementation details of the circuit in this embodiment are described below. The following content is only for the convenience of understanding and is not necessary for implementing this solution.

[0024] As attached Figure 1 As shown, the circuit for forcing the SoC to enter programming mode via USB debug serial port control includes: The USB to TTL serial port circuit is used to convert the input signals of the host computer into TTL serial port signals and output the control level to the level trigger circuit. The level-triggered circuit is connected to the output electrical signal of the USB to TTL serial port circuit and is used to generate a trigger signal according to the control level. The timing control circuit is electrically connected to the output of the level trigger circuit. It is used to adjust the timing of the trigger signal by changing the delay time of the download mode trigger signal and the reset signal by adjusting the RC circuit parameters, so as to generate the download mode trigger signal and reset signal that meet the requirements of the SoC programming mode and output them to the SoC. The anti-false triggering auxiliary circuit is connected to the output terminal of the level triggering circuit and then to the input terminal of the timing control circuit. It is used to control the output signal of the level triggering circuit according to the access status of the external device.

[0025] In some optional embodiments, the circuit further includes a power bus; the power bus is electrically connected to the power input terminals of the USB-to-TTL serial port circuit, the level triggering circuit, the timing control circuit, and the anti-false triggering auxiliary circuit, respectively.

[0026] Specifically, such as Figure 2 As shown, the USB-to-TTL serial port circuit includes a USB-to-TTL serial port chip U1 and a USB interface J1; the USB-to-TTL serial port chip U1 and the USB interface J1 are electrically connected. For example, the USB-to-TTL serial port circuit uses a CH340X chip to convert the USB signal from the host computer into a TTL serial port signal, realizing communication between the host computer and the SoC. Simultaneously, the host computer can send commands to control the RTS and DTR pins of the CH340X chip to output different level states, serving as control signals for subsequent circuits. The UD+ pin of the CH340X chip is electrically connected to the D+ pin of the USB interface, the UD- pin of the CH340X chip is electrically connected to the D- pin of the USB interface, the TXD pin of the CH340X chip is electrically connected to the serial port receive pin of the SoC, the RXD pin is electrically connected to the serial port transmit pin of the SoC, the RTS pin of the CH340X chip is electrically connected to the clock input of the level trigger circuit, and the DTR pin is electrically connected to the data input of the level trigger circuit.

[0027] In some alternative embodiments, the USB interface is a Type-C interface or a Type-B interface.

[0028] This invention uses a USB-to-TTL serial port circuit as the control channel. The host computer can trigger the SoC to enter the programming mode by controlling the level trigger circuit, completely replacing the traditional physical buttons, jumpers, and manual adjustment of the BOOT level. This avoids physical damage and failure of the waterproof and dustproof structure caused by disassembling sealed devices, making it particularly suitable for outdoor terminals, portable devices, and pre-installed systems. This invention does not require a dedicated debugger; only a standard data cable is needed to complete programming and debugging. This not only reduces the hardware cost of debugging but also simplifies the operation process. Operators do not need professional hardware debugging knowledge; all operations can be completed through the host computer software.

[0029] Specifically, the level-triggered circuit includes a D flip-flop; the CLK pin of the D flip-flop is connected to the first output terminal of the USB-to-TTL serial port circuit; the D pin of the D flip-flop is connected to the second output terminal of the USB-to-TTL serial port circuit; the clear terminal of the D flip-flop is connected to the second output terminal of the USB-to-TTL serial port circuit; and the Q pin of the D flip-flop, as the output terminal of the level-triggered circuit, is connected to the input terminal of the timing control circuit and the output signal of the anti-false triggering auxiliary circuit.

[0030] The host computer outputs different level states through the DTR signal line to control the clear terminal and data input terminal of the D flip-flop respectively, and controls the triggering function of the D flip-flop through the RTS signal line, thereby realizing the regulation of the logic level of the Q output terminal of the D flip-flop.

[0031] In some alternative embodiments, as shown in the appendix Figure 3 As shown, the level-triggered circuit also includes a first power interface V1, a first resistor R1, a second power interface V2, a second resistor R2, a first capacitor C1, and a third resistor R3; the first power interface V1 is electrically connected to the CLK pin of the D flip-flop U2 through the first resistor R1; the first power interface V1 is electrically connected to the VCC input terminal of the D flip-flop and the first terminal of the first capacitor C1; the second terminal of the first capacitor C1 is grounded; the D pin of the D flip-flop U2 is grounded through the second resistor R2; the Q pin of the D flip-flop U2 is electrically connected to the output terminal of the level-triggered circuit through the third resistor R3.

[0032] In some alternative embodiments, the timing control circuit includes a first RC delay circuit and a second RC delay circuit.

[0033] As attached Figure 4 As shown, the first RC delay circuit includes a first diode D1, a fourth resistor R4, a second capacitor C2, and a first transistor Q1; the output terminal of the level trigger circuit is electrically connected to the first terminal of the fourth resistor R4 and the first terminal of the second capacitor C2 through the first diode D1; the second terminal of the fourth resistor R4 is electrically connected to the base of the first transistor Q1; the collector of the first transistor Q1 is electrically connected to the first output terminal of the timing control circuit; the second terminal of the second capacitor C2 and the emitter of the first transistor Q1 are grounded.

[0034] The second RC delay circuit includes a second diode D2, a fifth resistor R5, a third capacitor C3, and a second transistor Q2; the output of the level trigger circuit is electrically connected to the first terminal of the fifth resistor R5 and the first terminal of the third capacitor C3 through the second diode D2; the second terminal of the fifth resistor R5 is electrically connected to the base of the second transistor Q2; the collector of the second transistor Q2 is electrically connected to the second output of the timing control circuit; the second terminal of the third capacitor C3 and the emitter of the second transistor D2 are grounded.

[0035] The collector of the first transistor Q1 outputs a download mode trigger signal, and the collector of the second transistor Q1 outputs a reset signal.

[0036] The timing control principle of the timing control circuit is as follows: When the output of the D flip-flop goes high, the first diode D1 charges the first capacitor C3 through the fourth resistor R4, and the second diode D2 charges the second capacitor C2 through the fifth resistor R5. Since the voltage across the capacitor cannot change abruptly, the base voltages of the first transistor Q1 and the second transistor Q2 quickly rise above the conduction threshold. The first transistor Q1 and the second transistor Q2 pull the download mode trigger signal and the reset signal low. When the host computer sets the RTS pin to low, generating a falling edge signal, the state of the D flip-flop remains unchanged, and the Q pin still outputs a high level. When the host computer sets the DTR pin to low again, the CLR pin goes low, the D flip-flop is cleared, the Q pin outputs a low level, and the output of the D flip-flop becomes low. At this time, the first diode D1 and the second diode D2 are cut off, the second capacitor C2 discharges through the fifth resistor R5 and the base-emitter junction of the first transistor Q1, and the third capacitor C3 discharges through the sixth resistor R6 and the base-emitter junction of the second transistor Q2. Because the time constant of the discharge circuit is large, the voltage across the capacitor gradually decreases. When the voltage across the second capacitor C2 drops below the conduction threshold of the first transistor Q1, the first transistor Q1 is turned off, and the download mode trigger signal returns to a high level. When the voltage across the third capacitor C3 drops below the conduction threshold of the second transistor Q2, the second transistor Q2 is turned off, and the reset signal returns to a high level.

[0037] Specifically, the delay time constant of the first RC delay unit is changed by adjusting the parameter values ​​of the fourth resistor and the second capacitor; the delay time constant of the second RC delay unit is changed by adjusting the parameter values ​​of the fifth resistor and the third capacitor.

[0038] By adjusting the parameters of the fifth resistor R5 and the second capacitor C2, the low-level duration of the download mode trigger signal can be changed. By adjusting the parameters of the sixth resistor R6 and the third capacitor C3, the low-level duration of the reset signal and the timing relationship between the download mode trigger signal and the reset signal can be changed. This allows the generation of trigger signals that meet the programming mode requirements of different SoC models. For example, for Allwinner series SoCs, it is usually necessary to first pull the download mode trigger signal low, then pull the reset signal low, and then release both signals simultaneously to enter the programming mode. By properly setting the RC parameters, the timing of these two signals can be precisely controlled, ensuring that the SoC can reliably enter the programming mode. By adjusting the resistor and capacitor parameters, the transistor turn-off delay can be controlled. Let the resistor be R, the capacitor be C, and the theoretical delay time be τ. Then the theoretical delay time constant satisfies the relationship: τ = R C. By adjusting the resistor and capacitor parameters, the delay times of the download mode trigger signal and reset signal can be flexibly changed, thereby adapting to the programming mode entry timing requirements of different SoC models. This makes the invention applicable to a variety of SoC chips with different architectures, exhibiting strong versatility.

[0039] In some alternative embodiments, as shown in the appendix Figure 5 As shown, the anti-false triggering auxiliary circuit includes a USB OTG interface U3, a sixth resistor R6, a third transistor Q3, a seventh resistor R7, a third power interface V3, and a fourth transistor Q4. The ID detection interface pin of the USB OTG interface U3 is connected to the base signal of the third transistor Q3 through the sixth resistor R6. The third power interface V3 is connected to the collector of the third transistor D3 and the base signal of the fourth transistor Q4 through the seventh resistor R7. The collector of the fourth transistor Q4 is connected to the output signal of the level trigger circuit. The emitter of the fourth transistor Q4 is grounded.

[0040] By adding an auxiliary circuit to prevent false triggering, the output level is forcibly locked when no external host is connected, which effectively avoids abnormal circuit reset or false entry into the burning mode caused by false triggering, cable plugging and unplugging interference or abnormal software instructions. At the same time, the diode setting prevents capacitor reverse discharge and ensures the stability of timing control.

[0041] When the device is not connected to the host computer, i.e., when the USB OTG interface does not detect an external host device, the ID pin outputs a low level. At this time, the base voltage of the third transistor Q3 is low, and the third transistor Q3 is cut off. The base of the fourth transistor Q4 is pulled up to the power supply voltage through the seventh resistor R7, and the fourth transistor Q4 conducts, forcibly pulling down the output of the level trigger circuit to a low level. In this state, regardless of the output level of the Q pin of the D flip-flop U2, the output of the D flip-flop always remains low, the first transistor Q1 and the second transistor Q2 are both cut off, the download mode trigger signal and the reset signal remain high, and the SoC works normally. This design effectively prevents abnormal circuit reset or accidental entry into the programming mode due to false triggering, electromagnetic interference, or other abnormal conditions.

[0042] When the device is connected to the host computer, that is, when the USB OTG interface detects an external host device, the ID pin outputs a high level. At this time, the base voltage of the third transistor Q3 is high, the third transistor Q3 is turned on, and pulls the base of the fourth transistor Q4 down to a low level, and the fourth transistor Q4 is turned off. At this time, the output level of the D flip-flop is completely determined by the output of the Q pin of the D flip-flop U2.

[0043] During the programming mode triggering process, the host computer sends commands to the USB-to-TTL serial port chip via the USB interface, controlling the RTS and DTR pins of the USB-to-TTL serial port chip to output a specific level sequence. The specific steps are as follows: First, the host computer sets the DTR pin to a low level. Since the CLR pin of the D flip-flop is electrically connected to the DTR pin, the CLR pin becomes low, the D flip-flop is cleared, and the Q pin outputs a low level. Then, the host computer sets the DTR pin to a high level. At this time, the CLR pin becomes high, the D flip-flop is cleared, and the D pin inputs a high level. Next, the host computer sets the RTS pin to a high level, generating a rising edge signal. Since the D flip-flop is triggered by a positive edge, under the action of the rising edge of the RTS pin, the high level of the D pin is latched to the Q pin, the Q pin outputs a high level, and the output of the D flip-flop becomes high.

[0044] During the timing control process, when the output of the D flip-flop goes high, the first diode D1 and the second diode D2 conduct, charging the second capacitor C2 and the third capacitor C3 through the fourth resistor R4 and the fifth resistor R5, respectively. Since the voltage across the capacitors cannot change abruptly, the base voltages of the first transistor Q1 and the second transistor Q2 quickly rise above the conduction threshold, turning on Q1 and Q2 and pulling the download mode trigger signal and reset signal low. When the host computer sets the RTS pin low, generating a falling edge signal, the state of the D flip-flop remains unchanged, and the Q pin still outputs a high level. When the host computer sets the DTR pin low again, the reset input of the D flip-flop goes low, the D flip-flop is reset, the Q pin outputs a low level, and the output of the D flip-flop becomes low.

[0045] At this time, the first diode D1 and the second diode D2 are off. The first capacitor C1 discharges through the fourth resistor R4 and the base-emitter junction of the first transistor Q1, while the second capacitor C2 discharges through the fifth resistor R5 and the base-emitter junction of the second transistor Q2. Due to the large time constant of the discharge circuit, the voltage across the capacitors gradually decreases. When the voltage across the second capacitor C2 drops below the conduction threshold of the first transistor Q1, Q1 is turned off, and the download mode trigger signal returns to a high level. When the voltage across the second capacitor C2 drops below the conduction threshold of the second transistor Q2, the second transistor Q2 is turned off, and the reset signal returns to a high level.

[0046] In some alternative embodiments, the third and fourth transistors are NPN transistors.

[0047] Furthermore, this invention relies on the debugging serial port as a control channel, and can be combined with remote USB redirection technology or network pass-through technology to enable remote engineers to remotely burn firmware and debug equipment without the need for technicians to be on-site, which greatly reduces the later maintenance costs of the equipment and shortens the firmware upgrade response time. It is especially suitable for large-scale deployment of IoT terminal devices.

[0048] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A circuit for forcing a USB debug serial port-controlled SoC into programming mode, characterized in that: include: The USB to TTL serial port circuit is used to convert the input signals of the host computer into TTL serial port signals and output the control level to the level trigger circuit. The level-triggered circuit is connected to the output electrical signal of the USB to TTL serial port circuit and is used to generate a trigger signal according to the control level. The timing control circuit is electrically connected to the output of the level trigger circuit. It is used to adjust the timing of the trigger signal by adjusting the delay time of the RC circuit parameter signal, thereby generating a download mode trigger signal and a reset signal that meet the requirements of the SoC programming mode and outputting them to the SoC. The anti-false triggering auxiliary circuit is connected to the output terminal of the level triggering circuit and then to the input terminal of the timing control circuit. It is used to control the output signal of the level triggering circuit according to the access status of the external device.

2. The circuit for forcing a SoC into programming mode via USB debug serial port control according to claim 1, characterized in that, It also includes a power bus; the power bus is electrically connected to the power input terminals of the USB to TTL serial port circuit, the level triggering circuit, the timing control circuit, and the anti-false triggering auxiliary circuit.

3. The circuit for forcing a SoC into programming mode via USB debug serial port control according to claim 1, characterized in that, The USB to TTL serial port circuit includes a USB to TTL serial port chip and a USB interface. The USB to TTL serial port chip is electrically connected to the USB interface.

4. The circuit for forcing a SoC into programming mode via USB debug serial port control according to claim 3, characterized in that, The USB interface is either a Type-C interface or a Type-B interface.

5. The circuit for forcing a SoC into programming mode via USB debug serial port control according to claim 1, characterized in that, The level-triggered circuit includes a D flip-flop; the CLK pin of the D flip-flop is electrically connected to the first output terminal of the USB to TTL serial port circuit. The D pin of the D flip-flop is connected to the second output terminal of the USB to TTL serial port circuit. The reset terminal of the D flip-flop is connected to the second output terminal of the USB to TTL serial port circuit. The Q pin of the D flip-flop is connected as the output of the level triggering circuit, the input of the timing control circuit, and the output electrical signal of the anti-false triggering auxiliary circuit.

6. The circuit for forcing a SoC into programming mode via USB debug serial port control according to claim 5, characterized in that, The level-triggered circuit also includes a first power interface, a first resistor, a second power interface, a second resistor, a first capacitor, and a third resistor; the first power interface is electrically connected to the CLK pin of the D flip-flop through the first resistor; the first power interface is electrically connected to the power input pin of the D flip-flop and the first end of the first capacitor; the second end of the first capacitor is grounded; the D pin of the D flip-flop is grounded through the second resistor; the Q pin of the D flip-flop is electrically connected to the output of the level-triggered circuit through the third resistor.

7. The circuit for forcing a SoC into programming mode via USB debug serial port control according to claim 1, characterized in that, The timing control circuit includes a first RC delay circuit and a second RC delay circuit; The first RC delay circuit includes a first diode, a fourth resistor, a second capacitor, and a first transistor; the output terminal of the level trigger circuit is electrically connected to the first terminal of the first diode, the first terminal of the fourth resistor, and the first terminal of the second capacitor; the second terminal of the fourth resistor is electrically connected to the base of the first transistor; the collector of the first transistor is electrically connected to the first output terminal of the timing control circuit; the second terminal of the second capacitor and the emitter of the first transistor are grounded. The second RC delay circuit includes a second diode, a fifth resistor, a third capacitor, and a second transistor; the output of the level trigger circuit is electrically connected to the first end of the fifth resistor and the first end of the third capacitor through the second diode; the second end of the fifth resistor is electrically connected to the base of the second transistor; the collector of the second transistor is electrically connected to the second output of the timing control circuit; the second end of the third capacitor and the emitter of the second transistor are grounded.

8. The circuit for forcing a SoC into programming mode via USB debug serial port control according to claim 7, characterized in that, The delay time constant of the first RC delay unit is changed by adjusting the parameter values ​​of the fourth resistor and the second capacitor; the delay time constant of the second RC delay unit is changed by adjusting the parameter values ​​of the fifth resistor and the third capacitor.

9. The circuit for forcing a SoC into programming mode via USB debug serial port control according to claim 1, characterized in that, The anti-false triggering auxiliary circuit includes a USB OTG interface, a sixth resistor, a third transistor, a seventh resistor, a third power interface, and a fourth transistor. The ID detection pin of the USB OTG interface is connected to the base signal of the third transistor through the sixth resistor. The third power interface is connected to the collector of the third transistor and the base signal of the fourth transistor through the seventh resistor. The collector of the fourth transistor is connected to the output signal of the level trigger circuit. The emitter of the fourth transistor is grounded.

10. The circuit for forcing a SoC into programming mode via USB debug serial port control according to claim 9, characterized in that, The third and fourth transistors are NPN transistors.

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