A three-phase four-wire inverter half-bus voltage balancing method, medium and equipment

Abstract

This application discloses a method, medium, and device for half-bus voltage balancing in a three-phase four-wire inverter, relating to the field of inverter technology. The method includes the following steps: when the half-bus voltage difference is higher than a preset voltage difference threshold, a compensation loop is activated to obtain the amplitude of a preset compensation gain; the sign of the set compensation gain is determined based on the inverter's instantaneous active power; based on the compensation gain and the half-bus voltage difference, a zero-sequence compensation amount is calculated and superimposed on the zero-axis voltage loop of the dq0 control frame; when the half-bus voltage difference falls below the preset voltage difference threshold and remains for a preset time period, the compensation loop is exited. The medium and device are used to implement the above method. The beneficial effects of this application are: by adjusting the common-mode bias of the three-phase modulation wave with the zero-sequence compensation amount, the dynamic adjustment of the upper and lower capacitor connection time ratio is achieved. Its response speed is determined by the PWM switching cycle, effectively suppressing rapidly accumulated charge imbalance within milliseconds.

Description

Technical Field

[0001] This application relates to the field of inverter technology, and in particular to a method, medium and device for half-bus voltage balancing of a three-phase four-wire inverter. Background Technology

[0002] Off-grid photovoltaic-storage power supply systems typically employ a three-phase four-wire inverter structure to directly adapt to single-phase / three-phase mixed loads. In medium-to-high power industrial and commercial applications, an inverter topology using a split capacitor on the DC bus and a neutral line drawn from the midpoint has become one of the preferred solutions. Its advantages include: the neutral line can be naturally drawn using the split capacitor, eliminating the need for an additional transformer, and it has the ability to handle unbalanced loads.

[0003] In off-grid operation, the inverter needs to function as an independent voltage source, requiring good waveform quality in its output voltage under balanced and unbalanced, linear and nonlinear loads. Total harmonic distortion (THD) is typically used as the core performance indicator. Precise control of the voltage loop is crucial to achieving this goal, and currently, there are two main control frameworks: One approach is phase-by-phase control based on a three-phase ABC stationary coordinate system. Each phase voltage loop is independently equipped with a proportional-resonant or quasi-resonant controller, and multiple resonant controllers for specific harmonics are connected in parallel to suppress voltage distortion. This approach is intuitive in structure, but the dynamic performance of the fundamental frequency control is limited by AC regulation, and under unbalanced loads, the three-phase controllers need to coordinate to handle the zero-sequence component, which easily leads to coupling and a heavy computational burden.

[0004] Another approach is control based on the dq0 rotating coordinate system, which transforms the positive-sequence fundamental wave into a DC component using proportional-integral (PI) regulation, while the zero-sequence component is independently controlled by the 0-axis channel. This framework offers significant advantages such as good fundamental-sequence control performance, active and reactive power decoupling, and independent controllability of the zero-sequence component, making it particularly suitable for high-power applications with high requirements for voltage accuracy and protection performance.

[0005] However, in the aforementioned topology employing split capacitors, balancing the voltages of the upper and lower bus capacitors presents an inherent engineering challenge. Under steady-state unbalanced loads, the symmetry of the neutral current's power frequency cycle ensures that the voltage difference between the upper and lower bus capacitors exhibits only controlled periodic ripple. However, under certain transient conditions, such as delayed turn-off of a phase current due to asynchronous load unloading, asymmetry in the positive and negative half-cycles caused by overmodulation, or unidirectional extension of the neutral current due to sudden load changes, the neutral current may lose its symmetry between the positive and negative half-waves for a specific period, generating an equivalent DC component or prolonged unidirectional charging and discharging. This directly leads to a significant difference in charge accumulation between the upper and lower bus capacitors, causing the voltage difference between the upper and lower bus capacitors to expand rapidly in a short time, far exceeding the steady-state ripple amplitude. This transient half-bus overvoltage not only threatens the safe operation of power devices but also degrades the output voltage waveform quality and may even trigger protection shutdown. Summary of the Invention

[0006] One objective of this application is to provide a method for equalizing the half-bus voltage of a three-phase four-wire inverter that can solve at least one of the defects in the aforementioned background art.

[0007] Another object of this application is to provide a computer-readable storage medium for implementing the above-described method for balancing the half-bus voltage of a three-phase four-wire inverter.

[0008] Another object of this application is to provide an electronic device for implementing the above-described method for equalizing the half-bus voltage of a three-phase four-wire inverter.

[0009] To achieve at least one of the above objectives, one aspect of this application provides a method for equalizing the half-bus voltage of a three-phase four-wire inverter, comprising the following steps: when the half-bus voltage difference is higher than a preset voltage difference threshold, a compensation loop is started to obtain a preset compensation gain amplitude; the sign of the compensation gain is determined based on the instantaneous active power of the inverter; based on the compensation gain with both amplitude and sign determined, combined with the half-bus voltage difference, a zero-sequence compensation amount is calculated and superimposed on the 0-axis voltage loop of the dq0 control frame to adjust the common-mode bias of the three-phase modulation wave; when the half-bus voltage difference falls back to below the preset voltage difference threshold and remains for a preset time period, the compensation loop is exited.

[0010] Preferably, the determination of the sign of the compensation gain includes the following process: when the instantaneous active power of the inverter is greater than a preset positive power threshold, the inverter is determined to be in an instantaneous discharge state, and the compensation gain is positive; when the instantaneous active power of the inverter is less than a preset negative power threshold, the inverter is determined to be in an instantaneous charging state, and the compensation gain is negative; when the instantaneous active power of the inverter is greater than or equal to the negative power threshold and less than or equal to the positive power threshold, the sign of the current compensation gain remains unchanged.

[0011] Preferably, the compensation gain is the proportional gain of the proportional regulator; the zero-sequence compensation amount for proportional regulation compensation is obtained by multiplying the compensation gain determined by the positive and negative signs with the half-bus voltage difference.

[0012] Preferably, the magnitude of the compensation gain is obtained by tuning the inverter parameters, and the optimal value of the compensation gain magnitude is determined by performing a step response test on the inverter through simulation or experiment.

[0013] Preferably, the amplitude of the compensation gain is preset to be greater than the stability boundary value; after the zero-sequence compensation amount is calculated based on the compensation gain, the zero-sequence compensation amount is limited so that the amplitude of the three-phase modulation wave does not exceed the amplitude limit of the pulse width modulation carrier.

[0014] Preferably, the obtained zero-sequence compensation is used as a reference for the 0-axis voltage loop and superimposed on the input or output of the 0-axis voltage loop.

[0015] Preferably, when exiting the compensation loop, the zero-sequence compensation amount decays at a preset rate.

[0016] Preferably, the differential pressure threshold is greater than the steady-state power frequency ripple amplitude of the inverter under normal unbalanced load.

[0017] Another aspect of this application provides a computer-readable storage medium storing a computer program; when the computer program is executed by a processor, it implements the above-described method for balancing the half-bus voltage of a three-phase four-wire inverter.

[0018] Another aspect of this application provides an electronic device including a processor and a memory; the memory is used to store a computer program, and the processor is used to execute the computer program to implement the above-described method for balancing the half-bus voltage of a three-phase four-wire inverter.

[0019] Compared with the prior art, the beneficial effects of this application are as follows: (1) This application uses real-time detection of the half-bus voltage difference and a preset threshold to determine whether to activate the compensation loop, so that the compensation loop remains in a standby state under normal operating conditions and is activated only when the voltage difference exceeds the steady-state power frequency ripple amplitude. This avoids excessive interference of the compensation loop with the power frequency ripple under normal unbalanced load and prevents damage to the three-phase output voltage symmetry due to frequent switching; at the same time, it ensures that the compensation loop can respond quickly when transient danger occurs and intervene in time while the voltage difference is still within a controllable range, taking into account both steady-state waveform quality and transient suppression requirements.

[0020] (2) This application uses the instantaneous active power of the inverter to determine the polarity of the compensation gain, so that the compensation direction can follow the instantaneous relationship between voltage and current to change dynamically; ensuring that the compensation direction is correct at every moment under various loads, and achieving the best suppression effect at all times.

[0021] (3) This application achieves dynamic adjustment of the ratio of upper and lower capacitor connection time by superimposing the zero-sequence compensation amount on the 0-axis voltage loop of the dq0 control frame and adjusting the common-mode bias of the three-phase modulation wave. Since this adjustment directly acts on the pulse width modulation link, its response speed is determined by the PWM switching period, which is much faster than the bandwidth limitation of the 0-axis PI regulator, and can effectively suppress the rapidly accumulated charge imbalance within a few milliseconds. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the traditional dq0 control framework for a three-phase four-wire inverter.

[0023] Figure 2This is a schematic diagram of the working steps of this application.

[0024] Figure 3 This is a schematic diagram of the dq0 control framework of this application. Detailed Implementation

[0025] The present application will now be further described in conjunction with specific embodiments. It should be noted that, in the description of this specification, the use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicates that the specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0026] In the description of this application, it should be noted that the terms "center", "lateral", "longitudinal", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., which indicate the orientation and positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and should not be construed as limiting the specific protection scope of this application.

[0027] It should be noted that the terms "first," "second," etc., in the specification and claims of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0028] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0029] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0030] The terms “comprising” and “having”, and any variations thereof, in the specification and claims of this application are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or device.

[0031] To facilitate understanding of the technical solution of this application, the specific control process of the traditional dq0 control framework of a three-phase four-wire inverter will be described in detail below.

[0032] like Figure 1 As shown, the traditional dq0 control framework employs a three-channel independent control structure in the dq0 rotating coordinate system, independently regulating the positive-sequence fundamental component (d-axis and q-axis) and zero-sequence component (0-axis) of the three-phase voltage. The control outputs of the three channels are converted into three-phase modulated waves after dq0 / ABC inverse transformation, which are then fed into the pulse width modulation module to generate drive signals. The overall control architecture can be divided into three parallel voltage loop channels: a d-axis voltage loop, a q-axis voltage loop, and a 0-axis voltage loop. The d-axis voltage loop controls the active component of the output voltage, achieving amplitude regulation; the q-axis voltage loop controls the reactive component of the output voltage, achieving phase regulation; and the 0-axis voltage loop controls the zero-sequence component of the output voltage, responsible for neutral point potential balance and zero-sequence voltage suppression.

[0033] For the d-axis voltage loop, the given voltage reference value V ref-d The d-axis component V extracted from the three-phase output voltage after ABC / dq0 transformation inv-dError calculation is performed to obtain an error signal. This error signal is then sent to the d-axis voltage controller, where it undergoes PI calculation to generate the initial adjustment amount for the d-axis voltage command. Simultaneously, a cascaded d-axis resonant module composed of multiple parallel resonant controllers can compensate for specific harmonics in the error signal to suppress periodic harmonic distortion in the output voltage and reduce total harmonic distortion. Based on the compensated error signal, the initial adjustment amount of the d-axis voltage command is superimposed and corrected to obtain the corrected d-axis voltage command. To prevent excessive output from the d-axis voltage controller from causing the modulation wave to exceed limits or the system to malfunction, the corrected d-axis voltage command is amplitude-limited to keep it within a safe range.

[0034] For the q-axis voltage loop, the given voltage reference value V ref-q The q-axis component V extracted from the three-phase output voltage after ABC / dq0 transformation inv-q Error calculation is performed to obtain an error signal. This error signal is then sent to the q-axis voltage controller, where it undergoes PI calculation to generate a preliminary adjustment amount for the q-axis voltage command. Simultaneously, a cascaded q-axis resonant module composed of multiple parallel resonant controllers can compensate for specific harmonics in the error signal to suppress periodic harmonic distortion in the output voltage and reduce total harmonic distortion. Based on the compensated error signal, the preliminary adjustment amount of the q-axis voltage command is superimposed and corrected to obtain the corrected q-axis voltage command. To prevent excessive output from the q-axis voltage controller from causing the modulation wave to exceed limits or the system to malfunction, the corrected q-axis voltage command is amplitude-limited to keep it within a safe range.

[0035] For the 0-axis voltage loop, the given voltage reference value V ref-0 The zero-axis component V extracted from the three-phase output voltage after ABC / dq0 transformation inv-0 Error calculation is performed to obtain an error signal. This error signal is then sent to the zero-axis voltage controller, where it undergoes PI calculation to generate the initial adjustment amount for the zero-axis voltage command. Simultaneously, a cascaded zero-axis resonant module composed of multiple parallel resonant controllers can compensate for specific harmonics in the error signal to suppress periodic harmonic distortion in the output voltage and reduce total harmonic distortion. Based on the compensated error signal, the initial adjustment amount of the zero-axis voltage command is superimposed and corrected to obtain the corrected zero-axis voltage command. To prevent excessive output from the zero-axis voltage controller, which could lead to modulation exceeding limits or system malfunction, the corrected zero-axis voltage command is amplitude-limited to keep it within a safe range.

[0036] In some high-performance control scenarios, a current loop is added to the output of each voltage loop in the dq0 control framework. The output of the voltage loop is used as the reference value of the current loop, and the current loop achieves a faster dynamic response.

[0037] It should be understood that the technical solution of this application is applied to a three-phase four-wire inverter using a DC bus split capacitor topology. The DC bus of this inverter consists of an upper half-bus capacitor and a lower half-bus capacitor, with a neutral line drawn from their midpoint for direct adaptation to mixed single-phase and three-phase loads. The three-phase bridge arms of this inverter output phase a, phase b, and phase c voltages respectively, and the three-phase voltages are regulated through the aforementioned dq0 control framework. During the operation of the three-phase four-wire inverter, the steady-state balance of the zero-sequence voltage is mainly maintained by the PI regulator and resonant controller of the 0-axis voltage loop. However, the bandwidth of the PI regulator is limited, and the resonant controller is mainly designed for periodic harmonics; neither can effectively cope with the rapid imbalance of the half-bus voltage under transient conditions. When the load undergoes asynchronous unloading, sudden heavy load application, or the system enters an overmodulation state, a significant charge accumulation difference may occur between the upper and lower half-bus capacitors within milliseconds. Once this difference forms, if it is not quickly suppressed, it will lead to the following serious consequences: (1) The voltage difference between the upper and lower half of the busbars will continue to widen, causing the voltage of the upper or lower half of the busbars to quickly exceed the rated withstand voltage of the power switching transistors and DC bus capacitors. Taking an 800V busbar system as an example, if the withstand voltage of the upper transistor is 600V, the overvoltage of the upper half of the busbars may cause it to be subjected to voltage stress exceeding the withstand voltage limit. At best, it will trigger the overvoltage protection and cause the machine to shut down; at worst, it will cause the switching transistors to avalanche breakdown and permanent damage.

[0038] (2) The withstand voltage of a single capacitor in a split capacitor is usually designed based on half of the rated voltage of the busbar, with limited margin. Continuous half-busbar overvoltage will cause a single capacitor to withstand a voltage exceeding its rated value, accelerating capacitor aging. In severe cases, it can lead to capacitor breakdown, electrolyte leakage, or even explosion, causing irreversible damage to the entire inverter module.

[0039] (3) Severe imbalance of half bus voltage will deteriorate the output voltage waveform, generate a large number of low-order harmonics, and further aggravate the THD exceeding the standard under unbalanced load. More seriously, overvoltage may trigger hardware overvoltage protection, causing the inverter to shut down unexpectedly, resulting in load power failure in off-grid power supply scenarios, and causing unacceptable production or life losses.

[0040] (4) Conventional PI regulators with a zero-axis voltage loop are limited by bandwidth and cannot respond effectively to transient voltage drops within milliseconds. Increasing the capacitance can slow down the rate of voltage drop rise, but it will significantly increase the size and cost and cannot solve the problem.

[0041] Based on the aforementioned technical problems, one aspect of this application provides a method for balancing the half-bus voltage of a three-phase four-wire inverter, such as... Figure 2 and Figure 3 As shown, one preferred embodiment includes the following steps: S100: When the voltage difference of the half bus is higher than the preset voltage difference threshold, the compensation loop is started to obtain the preset compensation gain amplitude.

[0042] It should be understood that the half-bus voltage difference is calculated by subtracting the upper half-bus voltage and the lower half-bus voltage of the inverter, and serves as the basis for subsequent judgment on whether to activate the compensation loop. The upper half-bus voltage refers to the voltage at the upper capacitor terminal connected between the DC positive bus and the neutral point in the DC bus split capacitor, and the lower half-bus voltage refers to the voltage at the lower capacitor terminal connected between the DC negative bus and the neutral point in the DC bus split capacitor. The voltage difference threshold is a preset voltage value used to distinguish between normal steady-state power frequency ripple and transient overvoltage events requiring intervention. The compensation loop is a zero-sequence compensation control loop added in this application to suppress the half-bus voltage difference. This compensation loop is set in the 0-axis channel of the dq0 control frame; when the compensation loop is not activated, it does not participate in the adjustment of the 0-axis voltage loop; when the compensation loop is activated, its output zero-sequence compensation amount will be superimposed on the 0-axis voltage loop to actively suppress the half-bus voltage difference.

[0043] S200: Determine the sign of the compensation gain based on the instantaneous active power of the inverter.

[0044] It should be understood that the instantaneous active power of an inverter refers to the instantaneous power P(t) output by the inverter at a certain time t, which is defined as the sum of the products of the three-phase voltage and the corresponding instantaneous phase current, i.e., P(t) = v a ×i a + v b ×i b + v c ×i c ; where v a v b and v c These are the instantaneous values ​​of the three-phase voltages of the inverter, i. a i b and i c These are the instantaneous values ​​of the three-phase currents of the inverter. The compensation gain is a coefficient used to suppress and compensate for the voltage difference between the half-buses. Its amplitude determines the compensation strength, and its sign determines the compensation direction. Different signs will result in different directions of the zero-sequence compensation, which in turn affects the offset direction of the three-phase modulation wave.

[0045] S300: Based on the compensation gain with both amplitude and sign determined, combined with the half-bus voltage difference, the zero-sequence compensation is calculated and superimposed on the 0-axis voltage loop of the dq0 control frame to adjust the common-mode bias of the three-phase modulated wave.

[0046] It should be noted that the zero-sequence compensation is a correction signal superimposed on the 0-axis voltage loop, used to change the common-mode bias of the three-phase modulation wave; the ratio of the access time of the upper and lower capacitors in each phase in the pulse width modulation refers to the proportion of the time that the upper or lower capacitor participates in energy exchange in each PWM switching cycle, which is determined by the positive half-cycle width and the negative half-cycle width of the modulation wave.

[0047] S400: When the half-bus voltage difference drops below the preset voltage difference threshold and remains for a preset time period, exit the compensation loop.

[0048] It should be noted that, to avoid frequent switching of the compensation loop due to instantaneous fluctuations, this step employs an exit judgment mechanism combining amplitude and time conditions to ensure system stability. The specific value of the preset time period can be selected according to the actual needs of those skilled in the art, for example, it can be 2~5 seconds.

[0049] Understandably, this application uses real-time detection of the half-bus voltage difference and a preset threshold to determine whether to activate the compensation loop. This keeps the compensation loop in a standby state under normal operating conditions, activating only when the voltage difference exceeds the steady-state power frequency ripple amplitude. This avoids excessive interference of the compensation loop with the power frequency ripple under normal unbalanced loads, preventing damage to the three-phase output voltage symmetry due to frequent switching. Simultaneously, it ensures that the compensation loop can respond quickly in the event of transient hazards, intervening promptly while the voltage difference remains within a controllable range, thus balancing steady-state waveform quality with transient suppression requirements.

[0050] This application uses the instantaneous active power of the inverter to determine the polarity of the compensation gain, so that the compensation direction can dynamically change with the instantaneous relationship between voltage and current; ensuring that the compensation direction is correct at every moment under various loads, and achieving the optimal suppression effect throughout the entire time period.

[0051] This application achieves dynamic adjustment of the upper and lower capacitor connection time ratio by superimposing zero-sequence compensation on the 0-axis voltage loop of the dq0 control framework and adjusting the common-mode bias of the three-phase modulation wave. Since this adjustment directly acts on the pulse width modulation stage, its response speed is determined by the PWM switching period and is much faster than the bandwidth limitation of the 0-axis PI regulator, effectively suppressing rapidly accumulated charge imbalance within milliseconds.

[0052] This application directly adjusts the connection time of the upper and lower capacitors through common-mode bias, which is independent of the direction of the neutral current and has strong robustness. Furthermore, it only requires superimposing zero-sequence compensation on the existing 0-axis voltage loop, resulting in minimal computational overhead and easy engineering deployment. It is applicable to all three-phase four-wire topologies with N-line drawn from the midpoint of the split capacitor.

[0053] In one specific embodiment, when performing step S100, a resistor divider network can be used in conjunction with an isolated voltage sensor, such as a Hall effect voltage sensor or a linear optocoupler, to perform real-time detection of the half-bus voltage. The voltage sampling signal is converted into a digital quantity by an analog-to-digital converter and then sent to a digital signal processor or microcontroller for calculation; the sampling frequency is usually set to be the same as or an integer multiple of the pulse width modulation switching frequency. For example, when the pulse width modulation switching frequency is 10kHz, the voltage sampling frequency can be set to 10kHz to ensure that the latest half-bus voltage information can be obtained in each switching cycle.

[0054] Understandably, by acquiring the voltage of the upper and lower busbars in real time and calculating the voltage difference, it is possible to promptly capture voltage imbalance signals under transient operating conditions, providing accurate input basis for the rapid activation of subsequent compensation loops. For ease of understanding, a specific example will be used below for detailed explanation.

[0055] In a specific example, taking an 800V DC bus system, the rated voltage of both the upper and lower capacitors is 450V, meaning there is a certain margin. Under normal operating conditions, the upper half of the bus voltage corresponding to the upper capacitor is V. bus-1 The lower half bus voltage V corresponding to the lower capacitor bus-2 If both are approximately 400V, then the half-bus voltage difference ΔV is close to 0V. When a transient imbalance event occurs, such as asynchronous unloading of a phase load causing a unidirectional extension of the neutral current, assuming the upper capacitor is over-discharged and the lower capacitor is over-charged, the upper half-bus voltage V... bus-1 The voltage drops to 380V, and the lower half bus voltage V bus-2 If the voltage rises to 420V, the voltage difference between the half busbars will be ΔV = -40V, indicating that the voltage between the half busbars has become significantly unbalanced.

[0056] In a specific embodiment, when executing step S100, the specific value of the differential voltage threshold can be set to be greater than the steady-state power frequency ripple amplitude of the inverter under normal unbalanced load. Thus, the differential voltage threshold can distinguish between steady-state power frequency ripple and actual transient overvoltage events, keeping the compensation loop in a ready-to-use state under normal operating conditions, avoiding excessive intervention in steady-state power frequency ripple; at the same time, it ensures that the compensation loop can be quickly activated when a transient danger occurs, intervening in a timely manner while the half-bus voltage difference is still within a controllable range.

[0057] It is understandable that if the differential voltage threshold is too low, the compensation loop will frequently intervene and disrupt the symmetry of the three-phase output voltage; if the differential voltage threshold is too high, it may not be able to suppress the truly dangerous transient overvoltage in time. Therefore, the specific value of the differential voltage threshold needs to be selected in combination with the actual unbalanced load conditions of the inverter.

[0058] It should be known that the steady-state power frequency ripple amplitude is related to the load imbalance, capacitor value, and power frequency, and can be approximately calculated using the following formula: V m =I N / (2×π×f×C).

[0059] In the formula, V m I represents the steady-state power frequency ripple amplitude. N This represents the effective value of the neutral current under maximum unbalanced load, f represents the power frequency, i.e., the grid frequency; C represents the capacitance value of a single split capacitor.

[0060] In a specific example, assuming the capacitance of a single split capacitor is C = 2000μF, and the effective value of the neutral current I under the maximum unbalanced load... N =10A, power frequency f=50Hz, then the steady-state power frequency ripple amplitude V m =10 / (2×3.14×50×0.002)≈15.9V. Therefore, the voltage difference threshold can be taken as 20V; thus, when the half-bus voltage difference is greater than 20V, the compensation loop can be activated.

[0061] In one specific embodiment, when performing step S100, the amplitude of the compensation gain needs to be balanced between response speed and system stability; if the amplitude of the compensation gain is too large, it may cause overmodulation of the three-phase modulated wave or induce system oscillation, while if the amplitude of the compensation gain is too small, the suppression effect will be insufficient. Therefore, in this embodiment, there are multiple ways to adjust the amplitude of the compensation gain, which will be described in detail below through two specific examples.

[0062] In a specific example, the magnitude of the compensation gain is obtained by tuning the inverter parameters, and the optimal value of the compensation gain magnitude is determined by performing a step response test on the inverter through simulation or experiment.

[0063] Specifically, the theoretical initial value of the compensation gain can be calculated based on the inverter's DC bus voltage, the capacitance of the split capacitor, the PWM switching frequency, and the expected maximum unbalanced load current. The specific calculation method is well-known to those skilled in the art and will not be elaborated upon here. A step response test is performed: When the inverter is operating in steady state with an unbalanced load, a known unbalanced load is suddenly applied or removed, such as a sudden single-phase full load. The response waveform of the half-bus voltage difference is recorded. The peak value, settling time, and presence of oscillations in the half-bus voltage difference waveform are observed. The settling time can be the time from the start of the step to the half-bus voltage difference entering the steady-state error band ±5%. If the response speed is too slow, i.e., the settling time is too long, the amplitude of the compensation gain can be appropriately increased. If excessive overshoot or oscillation occurs, the amplitude of the compensation gain can be appropriately decreased. Repeated testing is conducted until the optimal amplitude of the compensation gain that meets both the response speed requirements and stability requirements is obtained.

[0064] In another specific example, the amplitude of the compensation gain is directly preset to be greater than the stability boundary value. The stability boundary value refers to the compensation gain amplitude that brings the control system to a critical stable state; exceeding this value will cause the system to oscillate or even diverge. After calculating the zero-sequence compensation amount based on the compensation gain, the zero-sequence compensation amount is limited so that the amplitude of the three-phase modulated wave does not exceed the amplitude limit of the pulse width modulation carrier. The amplitude limit of the pulse width modulation carrier refers to the peak value of the triangular carrier in pulse width modulation, usually normalized to ±1. Exceeding this limit will lead to overmodulation and generate severe low-order harmonics.

[0065] Understandably, by setting the amplitude of the compensation gain to a large value and combining it with output limiting, sufficient suppression capability is ensured under most operating conditions, i.e., the gain is large and the response is sensitive when the half-bus voltage difference is small. At the same time, it prevents the zero-sequence compensation from being too large when the half-bus voltage difference is large, which would lead to over-modulation of the modulated wave or system oscillation.

[0066] In a specific embodiment, when performing step S200, positive and negative power threshold values ​​can be preset for determining the sign of the compensation gain. The specific values ​​of the positive and negative power threshold values ​​can be selected according to the actual needs of those skilled in the art; for example, the range of the positive power threshold value can be 2% to 5% of the rated power, and the range of the negative power threshold value can be -5% to -2% of the rated power. The specific process of determining the sign of the compensation gain based on the preset positive and negative power threshold values ​​is as follows: When the inverter's instantaneous active power exceeds a preset positive power threshold, the inverter is determined to be in an instantaneous discharge state, meaning that the inverter's energy flows from the DC side to the AC load side, and the compensation gain is positive at this time. It should be noted that in this scenario, if the upper bus voltage is higher than the lower bus voltage, the positive zero-sequence compensation calculated based on the compensation gain widens the positive half-cycle of each phase's modulation wave. At this time, most of the current flows out, i.e., it is in a discharge state. Therefore, the upper bus capacitor participates more in the discharge, thus pulling down the upper bus voltage.

[0067] When the inverter's instantaneous active power is less than the preset negative power threshold, the inverter is determined to be in an instantaneous charging state, meaning that the inverter's energy flows from the AC side to the DC side. In this case, the compensation gain takes a negative value. It should be noted that in this scenario, the current and voltage directions are opposite. The negative zero-sequence compensation amount calculated based on the compensation gain shortens the positive half-cycle of each phase modulation wave, preventing the upper half-bus capacitor from being additionally charged.

[0068] When the instantaneous active power of the inverter is greater than or equal to the negative power threshold and less than or equal to the positive power threshold, the sign of the current compensation gain remains unchanged to avoid frequent switching of the sign of the compensation gain due to signal noise near the power zero crossing point.

[0069] To better understand the specific effects of the above process for determining the sign of the compensation gain under actual load conditions, a detailed explanation will be given below using an RL inductive load as an example.

[0070] In a specific example, taking an RL inductive load with a power factor of 0.6 as an example, in one power frequency cycle, the instantaneous active power is positive for most of the time, that is, the voltage and current are in the same direction. At this time, the instantaneous active power is greater than the positive power threshold value, the compensation gain is positive, and the positive zero-sequence compensation widens the positive half-cycle of each phase modulation wave, which can effectively suppress the excessively high trend of the upper bus voltage.

[0071] In the brief interval of approximately 53° where the voltage has just entered the positive half-cycle and the current is still negative, the instantaneous active power is less than the negative power threshold. The compensation gain automatically switches to a negative value, and the negative zero-sequence compensation shortens the positive half-cycle of each phase modulation wave, thus avoiding a reverse aggravation of the half-bus voltage difference in this interval.

[0072] Within the extremely low power range near the current zero-crossing point, the absolute value of the instantaneous active power does not exceed the positive power threshold, and the sign of the compensation gain remains unchanged to avoid sign jitter caused by noise.

[0073] It should be noted that the above example of an RL inductive load demonstrates that the sign of the compensation gain can dynamically switch within one power frequency cycle as instantaneous active power changes. To further illustrate the applicability of this sign criterion to other types of loads, the following explanations will focus on different load types.

[0074] For resistive loads, the voltage and current are in phase, and the power factor is 1. Under this condition, the instantaneous active power is always positive and never crosses zero throughout the entire power frequency cycle. Therefore, the instantaneous active power is always greater than the positive power threshold, and the compensation gain is always positive. The positive compensation gain generates a positive zero-sequence compensation, causing the three-phase modulation wave to shift upwards, widening the positive half-cycle and narrowing the negative half-cycle, reducing the voltage difference between the half-buses, ensuring the compensation direction is completely correct and the effect is ideal.

[0075] For a regenerative resistive load, the voltage and current are in opposite directions, and the power factor is -1. Under this condition, the instantaneous active power is always negative and never crosses zero throughout the entire power frequency cycle. Therefore, the instantaneous active power is always less than the negative power threshold, and the compensation gain is always negative. The negative compensation gain generates a negative zero-sequence compensation, causing the three-phase modulation wave to shift downwards, narrowing the positive half-cycle and widening the lower half-cycle, reducing the voltage difference between the half-buses, ensuring the compensation direction is completely correct and the effect is ideal.

[0076] For purely inductive or capacitive loads, the total active power is zero, and the instantaneous active power alternates symmetrically between positive and negative values ​​within the power frequency cycle. During the half-cycle when the instantaneous active power is positive, the compensation gain is positive, and the positive zero-sequence compensation shifts the modulation wave upwards; during the half-cycle when the instantaneous power is negative, the compensation gain is negative, and the negative zero-sequence compensation shifts the modulation wave downwards. Since the total active power of a purely inductive or capacitive load is zero, theoretically, the half-bus voltage difference will not have a net cumulative effect without compensation. Through alternating positive and negative half-cycle compensation in the compensation loop, the net effect will not exacerbate the voltage difference. Furthermore, in actual systems with a small amount of active power loss, the compensation direction still follows the direction of the instantaneous active power, effectively suppressing the accumulation of small voltage differences caused by losses.

[0077] For RC capacitive loads, the process of suppressing the half-bus voltage difference is the same as that for RL inductive loads, so it will not be repeated here.

[0078] Understandably, based on the analysis of the various load types described above, the reason why this embodiment uses instantaneous active power instead of average power when determining the sign of the compensation gain is as follows: Under loads with a power factor not equal to 1, the instantaneous active power will experience a brief negative range within one power frequency cycle, during which the voltage and current directions are opposite. If the sign of the compensation gain remains unchanged in the direction corresponding to the average power during this range, the duty cycle bias will briefly produce a reverse effect, exacerbating the half-bus voltage difference. Although the current is small and the time is short during this range, in order to pursue the optimal suppression effect, the sign of the compensation gain should follow the sign of the instantaneous active power in real time.

[0079] Specifically, the method for determining the sign of the compensation gain using instantaneous active power in this application has the following general characteristics: it does not rely on prior judgments about the load type; that is, regardless of whether the load is resistive, inductive, capacitive, regenerative, or purely reactive, the instantaneous active power is calculated based on the real-time detected instantaneous values ​​of voltage and current, automatically adapting to different load characteristics. It has adaptive capability to power factor changes; that is, under loads with a power factor not equal to 1, it can dynamically switch the sign of the compensation gain within one power frequency cycle, solving the problem of incorrect compensation direction in the reverse interval of instantaneous active power. This is a significant improvement of the technical solution in this application compared to traditional methods based on average power criteria or fixed direction criteria, avoiding the reverse aggravation effect generated in the reverse interval of instantaneous active power, thereby improving the accuracy and robustness of compensation.

[0080] In a specific embodiment, when performing step S300, there are multiple ways to set the compensation gain, such as using proportional gain and proportional-integral composite gain. The calculation method for the zero-sequence compensation amount differs depending on the different compensation gain setting methods; for ease of understanding, the calculation process of the zero-sequence compensation amount based on various gain setting methods will be briefly described below.

[0081] In a specific example, the compensation gain uses the proportional gain K of the proportional regulator. p Then, by multiplying the compensation gain determined by the positive or negative sign by the half-bus voltage difference, we obtain the zero-sequence compensation amount m for proportional adjustment compensation, i.e., m = K. p × V; where, V represents the voltage difference between the half busbars.

[0082] Understandably, when calculating the zero-sequence compensation based on proportional gain, the zero-sequence compensation is directly proportional to the current half-bus voltage difference, with no delay, and can respond immediately within the current switching cycle, achieving rapid suppression of transient voltage differences. Since only one multiplication operation is required, there is no need to store historical data, resulting in extremely low computational requirements for the processor; moreover, the system transfer function is a typical first-order proportional element, which is not prone to nonlinear oscillations.

[0083] In another specific example, the compensation gain uses the proportional-integral composite gain of a proportional-integral controller. The expression for calculating the zero-sequence compensation amount m is: .

[0084] In the formula, Indicates proportional gain. Indicates integral gain. V represents the voltage difference between the half busbars.

[0085] Understandably, after introducing an integral term into the compensation gain, as long as the half-bus voltage difference exists, the integral regulator will continuously accumulate until it outputs a sufficient zero-sequence compensation to completely reduce the half-bus voltage difference to zero, which is suitable for high-precision scenarios with zero steady-state error. At the same time, for unbalanced current injections that last for a long time, the integral term can continuously increase the compensation intensity until the half-bus voltage difference is completely eliminated.

[0086] It should be understood that both of the above-mentioned methods for setting the compensation gain can meet the actual needs of this application, and those skilled in the art can choose according to their actual needs; in this embodiment, the method for setting the compensation gain is preferably the proportional gain form, and the following content will also be described using the proportional gain as an example.

[0087] In a specific embodiment, when executing step S300, the obtained zero-sequence compensation amount is used as a reference for the 0-axis voltage loop. When superimposed onto the 0-axis voltage loop, it can be superimposed on either the input or output of the 0-axis voltage loop. Superimposing it on the input of the 0-axis voltage loop allows for smooth execution using existing 0-axis PI regulators and resonant controllers, minimizing modifications to the original control structure. Superimposing it on the output of the 0-axis voltage loop provides a more direct and faster response. Both methods can achieve the objectives of this application and adapt to application scenarios with different control platforms and performance requirements. For ease of understanding, the two superimposition methods will be described in detail below.

[0088] In a specific example, the zero-sequence compensation amount m is superimposed on the input of the 0-axis voltage loop, that is, the zero-sequence compensation amount m is superimposed on the voltage reference value of the 0-axis voltage loop, so that the given voltage reference value is changed from the initial value V. ref-0 Revised to V ref-0 +m. The corrected voltage reference value and the zero-axis component V extracted after the three-phase output voltage undergoes ABC / dq0 transformation. inv-0 After error calculation, the data is fed into the 0-axis PI controller. In this method, the corrected voltage reference value is output after processing by the PI controller and the resonant controller, resulting in good smoothness.

[0089] In a specific example, such as Figure 3As shown, the zero-sequence compensation is superimposed on the output of the 0-axis voltage loop, that is, the zero-sequence compensation m is superimposed on the 0-axis voltage command output by the 0-axis voltage loop. The superimposed 0-axis voltage command is then limited and directly participates in the generation of the modulated wave. In this method, the superimposed 0-axis voltage command bypasses the bandwidth limitation of the 0-axis PI controller, resulting in a more direct response.

[0090] In one specific embodiment, when executing step S400, the zero-sequence compensation amount can exit immediately or attenuate based on a preset rate when the compensation loop is closed. Considering that the sudden exit of the zero-sequence compensation amount may cause an impact on the inverter's output voltage, in order to ensure the smoothness of the compensation loop exit process, this embodiment preferably adopts attenuation based on a preset rate for the exit of the zero-sequence compensation amount.

[0091] It is important to know that the rate at which the zero-sequence compensation quantity decays can be linear or nonlinear. For ease of understanding, the following will use linear decay and nonlinear exponential decay as examples to briefly describe the exit process of the zero-sequence compensation quantity.

[0092] In a specific example, the zero-sequence compensation is linearly decayed, and the specific decay expression is as follows: m(k+1)=m(k)- m.

[0093] In the formula, m(k+1) and m(k) represent the zero-sequence compensation amounts for the (k+1)th and kth decay cycles, respectively. m represents a fixed attenuation step size, and the specific value can be set according to the actual needs of those skilled in the art. For example, the value can be 1% to 10% of the zero-sequence compensation amount m(0) of the 0th attenuation cycle.

[0094] In another specific example, the zero-sequence compensation decays exponentially, and the specific decay expression is as follows: m(k+1)=λ×m(k).

[0095] In the formula, m(k+1) and m(k) represent the zero-sequence compensation amount of the (k+1)th and kth decay cycles, respectively, and λ represents the decay coefficient, which takes a value of (0, 1). The specific value can be determined by those skilled in the art based on their actual needs, for example, 0.8 or 0.9.

[0096] Another aspect of this application provides a computer-readable storage medium, in a preferred embodiment of which a computer program is stored on the storage medium; when the computer program is executed by a processor, the above-described method for equalizing the half-bus voltage of a three-phase four-wire inverter is implemented.

[0097] Another aspect of this application provides an electronic device, in one preferred embodiment of which includes a processor and a memory; the memory is used to store a computer program, and the processor is used to execute the computer program to implement the above-described method for equalizing the half-bus voltage of a three-phase four-wire inverter.

[0098] The basic principles, main features, and advantages of this application have been described above. Those skilled in the art should understand that this application is not limited to the above embodiments. The embodiments and descriptions in the specification are merely the principles of this application. Various changes and modifications can be made to this application without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claims. The scope of protection claimed by this application is defined by the appended claims and their equivalents.

Claims

1. A method for equalizing the half-bus voltage of a three-phase four-wire inverter, characterized in that, Includes the following steps: When the voltage difference between the half busbars is higher than the preset voltage difference threshold, the compensation loop is activated to obtain the preset compensation gain amplitude. The sign of the compensation gain is determined based on the instantaneous active power of the inverter; Based on the compensation gain with both amplitude and sign determined, and combined with the half-bus voltage difference, the zero-sequence compensation is calculated and superimposed on the 0-axis voltage loop of the dq0 control frame to adjust the common-mode bias of the three-phase modulation wave. When the voltage difference of the half bus drops below the preset voltage difference threshold and remains so for a preset period of time, the compensation loop is exited.

2. The method for equalizing the half-bus voltage of a three-phase four-wire inverter as described in claim 1, characterized in that, The determination of the sign of the compensation gain includes the following process: When the instantaneous active power of the inverter is greater than the preset positive power threshold, the inverter is determined to be in an instantaneous discharge state, and the compensation gain is positive at this time. When the instantaneous active power of the inverter is less than the preset negative power threshold, the inverter is determined to be in an instantaneous charging state, and the compensation gain is negative at this time. When the instantaneous active power of the inverter is greater than or equal to the negative power threshold and less than or equal to the positive power threshold, the sign of the current compensation gain remains unchanged.

3. The method for equalizing the half-bus voltage of a three-phase four-wire inverter as described in claim 1, characterized in that, The compensation gain uses the proportional gain of a proportional regulator; The zero-sequence compensation amount for proportional adjustment compensation is obtained by multiplying the compensation gain determined by the positive and negative signs of the compensation gain with the half-bus voltage difference.

4. The method for equalizing the half-bus voltage of a three-phase four-wire inverter as described in claim 3, characterized in that, The magnitude of the compensation gain is obtained by tuning the inverter parameters, and the optimal value of the compensation gain magnitude is determined by conducting step response tests on the inverter through simulation or experiment.

5. The method for equalizing the half-bus voltage of a three-phase four-wire inverter as described in claim 3, characterized in that, The amplitude of the compensation gain is preset to be greater than the stability boundary value; after the zero-sequence compensation amount is calculated based on the compensation gain, the zero-sequence compensation amount is limited so that the amplitude of the three-phase modulated wave does not exceed the amplitude limit of the pulse width modulation carrier.

6. The method for equalizing the half-bus voltage of a three-phase four-wire inverter as described in any one of claims 1-5, characterized in that, The obtained zero-sequence compensation is used as a reference for the 0-axis voltage loop and superimposed on the input or output of the 0-axis voltage loop.

7. The method for equalizing the half-bus voltage of a three-phase four-wire inverter as described in claim 1, characterized in that, When exiting the compensation loop, the zero-sequence compensation amount decays at a preset rate.

8. The method for equalizing the half-bus voltage of a three-phase four-wire inverter as described in claim 1, characterized in that, The differential pressure threshold value is greater than the steady-state power frequency ripple amplitude of the inverter under normal unbalanced load.

9. An electronic device, characterized in that, It includes a processor and a memory; the memory is used to store a computer program, and the processor is used to execute the computer program to implement the half-bus voltage balancing method for a three-phase four-wire inverter as described in any one of claims 1-8.

10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program; when the computer program is executed by a processor, it implements the three-phase four-wire inverter half-bus voltage balancing method as described in any one of claims 1-8.

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