Filter circuit and its tunable inductor

Abstract

A filter circuit and an adjustable inductor thereof, which relates to a filter circuit, includes a power supply end, an output end, a power supply line and an adjustable inductor. The power supply end is used to receive an operating power supply. The output end is used to output the operating power supply. The power supply line is coupled between the power supply end and the output end. The adjustable inductor is electrically connected between the power supply end and a ground end and used to eliminate noise on the power supply line. The adjustable inductor includes a first transducer and a second transducer. The first transducer and the second transducer have opposite transconductance phases, and the second transducer is electrically connected between two ends of the first transducer.

Description

Technical Field

[0001] This disclosure relates to filters and inductors thereof, and particularly to a filter circuit and an adjustable inductor thereof. Background Technology

[0002] In various types of circuit systems (e.g., but not limited to analog, digital, and radio frequency systems), power supply lines are often subject to interference from other paths, generating noise that affects the operation of the circuit system. To overcome the various noises that may exist in the circuit system, filters are applied to adjust the frequency response. Generally, traditional filters consist of inductors and capacitors connected in series or parallel. However, traditional filters have a large area, resulting in high cost. Furthermore, the inductance value of the inductors in traditional filters cannot be adjusted, leading to a low quality factor. Summary of the Invention

[0003] In view of this, the inventors proposed a filter circuit and its adjustable inductor, which can effectively adjust its inductance value and also solve problems such as excessive layout area and insufficient quality factor (also known as "Q value").

[0004] In some embodiments, a filter circuit includes a power supply terminal, an output terminal, a power line, and an adjustable inductor. The power supply terminal is used to receive a working power supply. The output terminal is used to output the working power supply. The power line is coupled between the power supply terminal and the output terminal. The adjustable inductor is electrically connected between the power line and a ground terminal to eliminate noise on the power line.

[0005] In some embodiments, the adjustable inductor includes a first transducer and a second transducer. The input terminal of the first transducer is electrically connected to a power supply terminal. The output terminal of the second transducer is electrically connected to the input terminal of the first transducer, and the input terminal of the second transducer is electrically connected to the output terminal of the first transducer.

[0006] In some embodiments, the first transducer includes a first transistor and a first current source, the first current source being electrically connected between a first power source and a node, the input terminal of the first transistor being electrically connected to the node, the control terminal of the first transistor being electrically connected to the power source, and the output terminal of the first transistor being electrically connected to ground. The second transducer includes a second transistor and a second current source, the input terminal of the second transistor being electrically connected to a second power source, the control terminal of the second transistor being electrically connected to the node, the output terminal of the second transistor being electrically connected to the power source, and the second current source being electrically connected between the power source and ground.

[0007] In some embodiments, at least one of the first transistor and the second transistor is an adjustable transistor.

[0008] In some embodiments, at least one of the first transistor and the second transistor is a single transistor element.

[0009] In some embodiments, the voltage values ​​of both the first power supply and the second power supply are lower than the voltage value of the operating power supply.

[0010] In some embodiments, the first transducer further includes a resistor and a third transistor. The resistor is electrically connected between the node and the control terminal of the second transistor. The input terminal of the third transistor is electrically connected to the node, the control terminal of the third transistor is electrically connected to a bias voltage, and the output terminal of the third transistor is electrically connected to the input terminal of the first transistor.

[0011] In some embodiments, the third transistor is an adjustable transistor.

[0012] In some embodiments, the third transistor is a single transistor element.

[0013] In some embodiments, the filter circuit further includes an impedance element. The impedance element is connected in parallel with the adjustable inductor.

[0014] In some embodiments, the filter circuit further includes an impedance element. One end of the impedance element is electrically connected to a power supply line, and the other end of the impedance element is electrically connected to an adjustable inductor.

[0015] In some embodiments, the filter circuit further includes an impedance element. One end of the impedance element is electrically connected to the power supply terminal, and the other end of the impedance element is electrically connected to the adjustable inductor and the output terminal.

[0016] In other embodiments, an adjustable inductor includes a first transconductor and a second transconductor. The first transconductor and the second transconductor have opposite transconductance phases. The second transconductor is electrically connected between the two ends of the first transconductor.

[0017] In summary, any embodiment of the filter circuit or adjustable inductor implements an inductor with adjustable inductance value (i.e., an adjustable inductor) using a small number of hardware components. Thus, the filter circuit can effectively eliminate noise from an external power supply received by a circuit system through the adjustable inductor, thereby improving the stability of the circuit system. Furthermore, by changing the parameters of each hardware component in the adjustable inductor, the cost, size, and power consumption of the adjustable inductor can be effectively reduced, thereby improving the quality factor of the adjustable inductor. Moreover, users can incorporate an impedance element into the filter circuit to form different circuit combinations with the adjustable inductor, thereby realizing various types of filters. Attached Figure Description

[0018] Figure 1A This is a schematic diagram of one embodiment of an adjustable inductor.

[0019] Figure 1B This is a schematic diagram of a first exemplary embodiment of an adjustable inductor.

[0020] Figure 2 yes Figure 1A and Figure 1B A circuit diagram of a second exemplary embodiment of a medium-adjustable inductor.

[0021] Figure 3 yes Figure 1A and Figure 1B A circuit diagram of a third exemplary embodiment of a medium-adjustable inductor.

[0022] Figure 4 yes Figure 1A and Figure 1B A circuit diagram of a fourth exemplary embodiment of a medium-adjustable inductor.

[0023] Figure 5 yes Figure 1A and Figure 1B A circuit diagram of the fifth exemplary embodiment of the adjustable inductor.

[0024] Figure 6 This is a schematic diagram of the first embodiment of the filter circuit.

[0025] Figure 7 This is a schematic diagram of a second embodiment of the filter circuit.

[0026] Figure 8 This is a schematic diagram of the third embodiment of the filter circuit.

[0027] Figure 9 This is a schematic diagram of the fourth embodiment of the filter circuit.

[0028] Figure 10 This is a schematic diagram of one embodiment of an adjustable transistor.

[0029] Symbol Explanation

[0030] 1: Filtering circuit

[0031] 10: Adjustable inductor

[0032] 11,12: Transducers

[0033] 20: Impedance element

[0034] 30: Power supply line

[0035] 40: Circuit System

[0036] 41: Functional Circuit

[0037] 50: Selection Circuit

[0038] C1: Capacitor element

[0039] Cgs1, Cgs2, Cgs3, Cgs4: Parasitic capacitance

[0040] G1: Grounding terminal

[0041] I1, I2: Current sources

[0042] M1~Mn: Transistor elements

[0043] N1, N2, N3: Nodes

[0044] Q1, Q2, Q3: Transistors

[0045] Qi: Adjustable transistor

[0046] P1: First connection point

[0047] P2: Second connection point

[0048] P3: Third connection point

[0049] R1: Resistor

[0050] Sc1~Scn: Control signals

[0051] SW1~SWn: Switches

[0052] T1: Power supply terminal

[0053] T2: Output terminal

[0054] V1, V2: Power supply

[0055] Vb1, Vb2, Vb2', Vb3: Bias voltages

[0056] VDD,VDD': Power supply

[0057] Zc: Capacitive impedance

[0058] Zin1: Input impedance Detailed Implementation

[0059] With regard to the terminology used herein, it should be clear that: the term "comprising" is an open-ended term and should therefore be interpreted as "comprising but not limited to"; terms such as "coupled" and "electrically connected to" refer to two or more elements making physical or electrical contact with each other "directly" or "indirectly"; and terms such as "a," "another," "first," and "second" are used to distinguish the elements referred to, and unless otherwise specified, are not used to order or limit the differences between the elements referred to, nor are they used to limit the scope of this disclosure.

[0060] Please refer to Figure 1A An adjustable inductor 10 includes two transconductors 11 and 12 (hereinafter referred to as first transconductor 11 and second transconductor 12, respectively). First transconductor 11 and second transconductor 12 have opposite transconductance phases. In one example, first transconductor 11 has positive transconductance, and second transconductor 12 has negative transconductance. In another example, first transconductor 11 has negative transconductance, and second transconductor 12 has positive transconductance.

[0061] Herein, the second transducer 12 is electrically connected between the two ends of the first transducer 11. In some embodiments, the output terminal of the second transducer 12 is electrically connected to the input terminal of the first transducer 11, and the input terminal of the second transducer 12 is electrically connected to the output terminal of the first transducer 11.

[0062] Specifically, the input terminal of the first transducer 11 and the output terminal of the second transducer 12 are coupled to node N1 (hereinafter referred to as the first node N1), and the output terminal of the first transducer 11 and the input terminal of the second transducer 12 are coupled to another node N2 (hereinafter referred to as the second node N2). In other words, the first node N1, the input terminal of the first transducer 11, and the output terminal of the second transducer 12 have the same voltage value (i.e., equivalent potential), and the second node N2, the output terminal of the first transducer 11, and the input terminal of the second transducer 12 have the same voltage value.

[0063] Furthermore, the output terminal of the adjustable inductor 10 (i.e., the second node N2) has a capacitive impedance Zc (i.e., the output impedance of the adjustable inductor 10). This capacitive impedance Zc is located between the second node N2 and the ground terminal G1. Here, the opposite transconductance phases of the first transducer 11 and the second transducer 12 can convert the capacitive impedance Zc at the output terminal into an inductive impedance at the input terminal (i.e., the input impedance Zin1 of the adjustable inductor 10). In other words, the input impedance Zin1 at the input terminal (i.e., the first node N1) of the adjustable inductor 10 is inductive.

[0064] Zin1=jωL (Equation 1)

[0065] Where L is the inductance value of the adjustable inductor 10, and its unit is Henry (H). j is a complex number unit. ω is the angular frequency of the electrical signal passing through the adjustable inductor 10 (i.e., 2π times the frequency of the electrical signal), and its unit is radians per second.

[0066] In some embodiments, the impedance element providing this capacitive impedance Zc can be an actively added capacitor element C1, that is, this capacitor element C1 is a component other than transducers 11 / 12 and is coupled between the second node N2 and the ground terminal G1, such as Figure 1B As shown. In other embodiments, the impedance element providing this capacitive impedance Zc may also be a parasitic capacitance of at least one component of the transducer 11 (e.g., Figure 2 Parasitic capacitances Cgs1 and Cgs2 within transducers 11 / 12, or Figure 4 Parasitic capacitances Cgs3 and Cgs4 within transducers 11 / 12.

[0067] Please refer to Figure 1A and Figure 2 In some embodiments, each transducer 11 / 12 includes a transistor Q1 / Q2 and a current source I1 / I2. Specifically, the first transducer 11 includes a transistor Q1 (hereinafter referred to as the first transistor Q1) and a current source I1 (hereinafter referred to as the first current source I1), and the second transducer 12 includes another transistor Q2 (hereinafter referred to as the second transistor Q2) and another current source I2 (hereinafter referred to as the second current source I2). The first current source I1 and the second current source I2 can be constant current sources with fixed current values ​​or variable current sources with current value adjustment functions.

[0068] like Figure 2 As shown, in some embodiments, a first current source I1 is electrically connected between a power supply V1 (hereinafter referred to as the first power supply V1) and a second node N2. In other words, one end of the first current source I1 is electrically connected to the first power supply V1, and the other end of the first current source I1 is electrically connected to the second node N2. Furthermore, in some embodiments, the input terminal of the first transistor Q1 is electrically connected to the second node N2, the control terminal of the first transistor Q1 is electrically connected to the first node N1, and the output terminal of the first transistor Q1 is electrically connected to a ground terminal G1. In other words, the input terminal of the first transistor Q1 is electrically connected to the other end of the first current source I1.

[0069] like Figure 2As shown, in some embodiments, the input terminal of the second transistor Q2 is electrically connected to another power supply V2 (hereinafter referred to as the second power supply V2), the control terminal of the second transistor Q2 is electrically connected to the second node N2, and the output terminal of the second transistor Q2 is electrically connected to the first node N1. In other words, the control terminal of the second transistor Q2 is electrically connected to the input terminal of the first transistor Q1 and the other end of the first current source I1, and the output terminal of the second transistor Q2 is electrically connected to the control terminal of the first transistor Q1. Furthermore, in some embodiments, the second current source I2 is electrically connected between the first node N1 and a ground terminal G1. In other words, one end of the second current source I2 is electrically connected to the control terminal of the first transistor Q1 and the output terminal of the second transistor Q2, and the other end of the second current source I2 is electrically connected to the ground terminal G1. Here, the control terminal of the first transistor Q1 receives a bias voltage Vb1 (i.e., the terminal voltage of the first node N1), and the operating region of the first transistor Q1 is controlled by the bias voltage Vb1. The control terminal of the second transistor Q2 receives the bias voltage Vb2 (i.e., the terminal voltage of the second node N2), and the operating region of the second transistor Q2 is controlled by the bias voltage Vb2.

[0070] It should be noted that, here Figure 1A The capacitive impedance Zc shown can be obtained from Figure 2 The parasitic capacitance Cgs1 of the first transistor Q1 and the parasitic capacitance Cgs2 of the second transistor Q2 are provided by the variable inductor 10. In other words, the output of the variable inductor 10 has a capacitive impedance Zc due to the parasitic capacitances Cgs1 and Cgs2. Furthermore, this capacitive impedance Zc can be converted into an inductive input impedance Zin1 at the input of the variable inductor 10 by the positive and negative transconductances of the first transducer 11 and the second transducer 12. That is, the first transistor Q1, the second transistor Q2, the first current source I1, and the second current source I2 relate to the value of the input impedance Zin1. Specifically, the value of the input impedance Zin1 changes with any of the following: the operating region of the first transistor Q1, the operating region of the second transistor Q2, the magnitude of the current in the first current source I1, and the magnitude of the current in the second current source I2. In other words, the user can effectively adjust the inductance value of the adjustable inductor 10 by changing at least one of the bias voltage of the first transistor Q1, the bias voltage of the second transistor Q2, the current value of the first current source I1, and the current value of the second current source I2.

[0071] In some embodiments, the first transistor Q1 and / or the second transistor Q2 may be a single transistor element, such as Figure 2 As shown. In other embodiments, the first transistor Q1 and / or the second transistor Q2 may be tunable transistors. Figure 3For example, in this embodiment, the first transistor Q1 and / or the second transistor Q2 can be adjustable transistors implemented with n transistor elements M1 to Mn. Here, n is a positive integer greater than 1. The value of the input impedance Zin1 is also related to the size of the first transistor Q1 and / or the second transistor Q2. In this case, the user can also change the value of the input impedance Zin1 of the adjustable inductor 10 by adjusting the number of transistor elements used in the first transistor Q1 and / or the second transistor Q2. In some embodiments, when the first transistor Q1 and the second transistor Q2 are adjustable transistors, these adjustable transistors can be implemented with the same number of transistor elements M1 to Mn (i.e., K1 = K2) or with different numbers of transistor elements M1 to Mn (i.e., K1 ≠ K2). Here, the total number (n) of transistor elements M1 to Mn of the first transistor Q1 is K1, and the total number (n) of transistor elements M1 to Mn of the first transistor Q1 is K2. Both K1 and K2 are positive integers.

[0072] It should be clear that, although Figure 2 Therefore, both the first transistor Q1 and the second transistor Q2 are shown as single transistor elements, and Figure 3 The first transistor Q1 and the second transistor Q2 are both shown as adjustable transistors; however, the present invention is not limited thereto. That is, depending on actual needs, the adjustable inductor 10 can also be designed such that one of the first transistor Q1 and the second transistor Q2 is a single transistor element, while the other is an adjustable transistor.

[0073] Please refer to Figure 1A and Figure 4 In some embodiments, in addition to the aforementioned first transistor Q1 and first current source I1, the first transducer 11 may further include a resistor R1 and another transistor Q3 (hereinafter referred to as the third transistor Q3). Resistor R1 is electrically connected between the second node N2 and the control terminal of the second transistor Q2. In other words, the first end of resistor R1 is electrically connected to the first current source I1, and the second end of resistor R1 is electrically connected to the control terminal of the second transistor Q2. That is, one end of resistor R1 is coupled to the first current source I1 at the second node N2, and the other end of resistor R1 is coupled to the control terminal of the second transistor Q2 at another node N3. Here, the control terminal of the second transistor Q2 receives a bias voltage Vb2 (i.e., the terminal voltage of the second node N2) via resistor R1. In other words, the bias voltage Vb2 is stepped down by resistor R1 to form a bias voltage Vb2', and this bias voltage Vb2' controls the operating region of the second transistor Q2.

[0074] The input terminal of the third transistor Q3 is electrically connected to the second node N2, the control terminal of the third transistor Q3 is electrically connected to (receives) a bias voltage Vb3, and the output terminal of the third transistor Q3 is electrically connected to the input terminal of the first transistor Q1. In other words, the input terminal of the third transistor Q3 is electrically connected to the first current source I1 and the first terminal of the resistor R1. Here, the bias voltage Vb3 is used to control the operating region of the third transistor Q3.

[0075] Therefore, the operating region of the third transistor Q3 and the resistance value of resistor R1 are also related to the input impedance Zin1 of the adjustable inductor 10. Furthermore, the user can also change the input impedance Zin1 of the adjustable inductor 10 by adjusting the bias voltage Vb3 of the third transistor Q3.

[0076] In some embodiments, resistor R1 can be a fixed resistor with a fixed resistance value. In other embodiments, resistor R1 can also be a variable resistor with resistance value adjustment function. In this case, the user can also change the input impedance Zin1 of the adjustable inductor 10 by adjusting the resistance value of resistor R1.

[0077] It should be noted that, Figure 1A The capacitive impedance Zc shown can be obtained from Figure 4 The parasitic capacitance Cgs3 of the second transistor Q2 and the parasitic capacitance Cgs4 of the third transistor Q3 are provided to give the output of the adjustable inductor 10 a capacitive impedance Zc.

[0078] In some embodiments, the third transistor Q3 may be a single transistor element, such as Figure 4 As shown. In other embodiments, the third transistor Q3 may also be an adjustable transistor. Figure 5 For example, in this embodiment, the third transistor Q3 can be an adjustable transistor implemented with n transistor elements M1 to Mn, where n is a positive integer greater than 1. The value of the input impedance Zin1 is also related to the size of the third transistor Q3. Furthermore, the user can change the value of the input impedance Zin1 of the adjustable inductor 10 by adjusting the number of transistor elements M1 to Mn used in the third transistor Q3.

[0079] It should be clear that, although Figure 4 Therefore, the first transistor Q1, the second transistor Q2, and the third transistor Q3 are all shown as single transistor elements, and Figure 5The first transistor Q1, the second transistor Q2, and the third transistor Q3 are all tunable transistors, but the present invention is not limited thereto. That is, depending on actual needs, the tunable inductor 10 can also be designed such that at least one of the first transistor Q1, the second transistor Q2, and the third transistor Q3 is a single transistor element, while the others are tunable transistors.

[0080] In some embodiments, when at least two of the first transistor Q1, the second transistor Q2, and the third transistor Q3 are adjustable transistors, these adjustable transistors can be implemented with the same number of transistor elements M1 to Mn, or with different numbers of transistor elements M1 to Mn. When all three transistors are adjustable transistors, two of these adjustable transistors can be implemented with the same number of transistor elements M1 to Mn, while the remaining transistor is implemented with a different number of transistor elements M1 to Mn.

[0081] Please refer to Figures 6 to 9 In some embodiments, the adjustable inductor 10 of any of the foregoing embodiments can be applied to a filter circuit 1. In other words, the filter circuit 1 includes at least the adjustable inductor 10 of any of the foregoing embodiments. For example, Figures 6 to 9 The filter circuit 1 shown in any of the figures contains at least one of the following: Figure 1A , Figure 1B and Figures 2 to 5 One of the figures shows the adjustable inductor 10.

[0082] Please refer to Figures 6 to 9 In some embodiments, the filter circuit 1 includes a power supply terminal T1, an adjustable inductor 10, and an output terminal T2. The adjustable inductor 10 is electrically connected between the power supply terminal T1 and the ground terminal G1, and the output terminal T2 is electrically connected to both the power supply terminal T1 and the adjustable inductor 10. The power supply terminal T1 and the output terminal T2 are electrically connected to the first node N1. In other words, the power supply terminal T1 and the output terminal T2 are electrically connected to the control terminal of the first transistor Q1, the output terminal of the second transistor Q2, and one end of the second current source I2 in the adjustable inductor 10.

[0083] Here, power supply terminal T1 is used to receive a working power supply VDD. Adjustable inductor 10 is used to eliminate noise on the power line 30 between power supply terminal T1 and output terminal T2 to generate working power supply VDD'. Output terminal T2 is used to output the noise-eliminated working power supply VDD'.

[0084] Please refer to Figures 2 to 9In some embodiments, the voltage values ​​of the first power supply V1 and the second power supply V2 are both lower than the voltage value of the operating power supply VDD. The voltage values ​​of the first power supply V1 and the second power supply V2 are, for example, 1 volt or 3 volts, but are not limited thereto. Furthermore, the voltage value of the operating power supply VDD is, for example, 5 volts, 10 volts, or 12 volts, but is not limited thereto. Since the filter circuit 1 can be driven without requiring a high-voltage power supply (e.g., but not limited to 12 volts), setting the voltage values ​​of the first power supply V1 and the second power supply V2 driving the filter circuit 1 to be lower than the voltage value of the operating power supply VDD can effectively reduce the power consumption of the filter circuit 1. Thus, the user can eliminate noise in the circuit system using the low-power filter circuit 1.

[0085] Please refer to Figures 7 to 9 In some embodiments, the filter circuit 1 further includes an impedance element 20. The impedance element 20 can be disposed at different positions in the filter circuit 1 according to actual needs to form different types of filters with the adjustable inductor 10.

[0086] by Figure 7 For example, in this embodiment, the impedance element 20 is connected in parallel with the adjustable inductor 10. In other words, one end of the impedance element 20 is electrically connected to the first node N1, and the other end of the impedance element 20 is electrically connected to the ground terminal G1. Here, the circuit combination formed by the adjustable inductor 10 and the impedance element 20 can be regarded as a band-pass filter.

[0087] And with Figure 8 For example, in this embodiment, one end of the impedance element 20 is electrically connected to the power supply terminal T1 and the output terminal T2, and the other end of the impedance element 20 is electrically connected to the adjustable inductor 10. In other words, the other end of the impedance element 20 is electrically connected to the first node N1. Here, the circuit combination formed by the adjustable inductor 10 and the impedance element 20 can be regarded as a band-stop filter.

[0088] Again Figure 9 For example, in this embodiment, one end of the impedance element 20 is electrically connected to the power supply terminal T1, and the other end of the impedance element 20 is electrically connected to the adjustable inductor 10 and the output terminal T2. In other words, the other end of the impedance element 20 is electrically connected to the first node N1 and the output terminal T2. Here, the circuit combination formed by the adjustable inductor 10 and the impedance element 20 can be regarded as a high-pass filter.

[0089] In some embodiments, the impedance element 20 can be a single hardware component with an impedance value, or a circuit composed of multiple hardware components with impedance values. For example, the impedance element 20 can be, but is not limited to, a resistor, a capacitor, or a circuit composed of a resistor and a capacitor (hereinafter referred to as an RC circuit). In one example, in response to the impedance element 20 being a resistor, the impedance element 20 forms an RL circuit with the adjustable inductor 10. In another example, in response to the impedance element 20 being a capacitor, the impedance element 20 forms an LC circuit with the adjustable inductor 10. In yet another example, in response to the impedance element 20 being an RC circuit, the impedance element 20 forms an RLC circuit with the adjustable inductor 10. Furthermore, in some embodiments, the user can also change the frequency filtered by the filter circuit 1 by adjusting the inductance value of the adjustable inductor 10.

[0090] Please refer to Figures 6 to 9 In some embodiments, the filter circuit 1 of any of the foregoing embodiments can be applied to any type of circuit system 40 to eliminate noise on the power supply line 30 of the circuit system 40, thereby improving the stability of the circuit system 40. Specifically, the power supply terminal T1 of the filter circuit 1 serves as the power supply terminal of the circuit system 40, while its output terminal T2 serves as the power supply terminal of the functional circuit 41 of the circuit system 40. That is, the power supply line 30 of the filter circuit 1 replaces the wiring between the power supply terminal of the circuit system 40 and the power supply terminal of the functional circuit 41, so that the filter composed of the adjustable inductor 10 of any embodiment is connected in parallel on the power supply line 30 of the circuit system 40. Here, the filter can eliminate noise coupled from unknown paths (e.g., noise of unknown frequency transmitted to the power supply line 30 via coupling between metals in the circuit), and the frequency filtered by the filter can be adjusted by adjusting the inductance value of the adjustable inductor 10.

[0091] Please refer to Figures 6 to 9 In some embodiments, the filter circuit 1 is provided in a radio frequency system (i.e., circuit system 40) as an example. In this case, the power supply terminal T1 of the filter circuit 1 is electrically connected to the power supply terminal of the radio frequency system, and the output terminal T2 of the filter circuit 1 is electrically connected to the power supply terminal of a radio frequency chip (i.e., functional circuit 41) in the radio frequency system. In response to the start of operation of the radio frequency system, that is, the external power supply circuit (not shown) applies the operating power supply VDD to the power supply terminal of the radio frequency system, the radio frequency system receives the operating power supply VDD from the external power supply circuit (not shown) through the power supply terminal T1 in the filter circuit 1, and the radio frequency chip receives the noise-canceling operating power supply VDD' through the output terminal T2 in the filter circuit 1 as the power required for its operation (e.g., performing wireless communication functions).

[0092] Please refer to Figure 10In some embodiments, the adjustable transistor Qi includes a plurality of transistor elements M1 to Mn, a plurality of switches SW1 to SWn, and a selection circuit 50. These transistor elements M1 to Mn are connected in parallel between a first connection point P1 and a second connection point P2, and the control terminals of the transistor elements M1 to Mn are respectively coupled to a third connection point P3 via switches SW1 to SWn. The control terminals of switches SW1 to SWn are coupled to and controlled by the selection circuit 50. In other words, the input terminals of each transistor element M1 / M2 / ... / Mn are coupled to the first connection point P1, and the output terminals of each transistor element M1 / M2 / ... / Mn are coupled to the second connection point P2. Transistor elements M1 to Mn correspond one-to-one with switches SW1 to SWn. The first terminal of each switch SW1 / SW2 / ... / SWn is coupled to the control terminal of the corresponding transistor element M1 / M2 / ... / Mn. The second terminal of each switch SW1 / SW2 / ... / SWn is coupled to the third connection point P3, and the control terminal of each switch SW1 / SW2 / ... / SWn is coupled to the selection circuit 50. The selection circuit 50 generates a set of control signals Sc1~Scn to control whether the switches SW1~SWn are working, thereby adjusting the input impedance Zin1 of the adjustable inductor 10. When the adjustable transistors Q1 / Q2 / Q3 are applied to the adjustable inductor 10, the first connection point P1 is coupled to the preceding stage circuit (e.g., the second node N2, the power supply V2, or the transistor Q3), the second connection point P2 is coupled to the following stage circuit (e.g., the ground terminal G1, the first node N1, or the transistor Q1), and the third connection point P3 is electrically connected to the bias voltage Vb1 / Vb2 / Vb2' / Vb3. Here, i is 1, 2, or 3.

[0093] Specifically, when the adjustable transistor Qi is Figure 3 When the first transistor Q1 is shown, the first connection point P1 is the input terminal of the first transistor Q1, the second connection point P2 is the output terminal of the first transistor Q1, and the third connection point P3 is the control terminal of the first transistor Q1. (Refer to...) Figure 3 and Figure 10 The first connection point P1, the first current source I1, and the control terminal of the second transistor Q2 are all coupled to the second node N2. The second connection point P2 is coupled to the ground terminal G1. The third connection point P3, the second current source I2, and the output terminal of the second transistor Q2 are all coupled to the first node N1. Here, the third connection point P3 is used to receive the bias voltage Vb1, which is the terminal voltage of the first node N1.

[0094] When the adjustable transistor Qi is Figure 3 When the second transistor Q2 is shown, the first connection point P1 is the input terminal of the second transistor Q2, the second connection point P2 is the output terminal of the second transistor Q2, and the third connection point P3 is the control terminal of the second transistor Q2. (Refer to...) Figure 3 and Figure 10 The first connection point P1 is coupled to the power supply circuit (not shown) and is used to receive power supply V2. The second connection point P2, the second current source I2, and the control terminal of the first transistor Q1 are all coupled to the first node N1. The third connection point P3, the first current source I1, and the input terminal of the first transistor Q1 are all coupled to the second node N2. Here, the third connection point P3 is used to receive the bias voltage Vb2, that is, the terminal voltage of the second node N2.

[0095] When the adjustable transistor Qi is Figure 5 When the first transistor Q1 is shown, the first connection point P1 is the input terminal of the first transistor Q1, the second connection point P2 is the output terminal of the first transistor Q1, and the third connection point P3 is the control terminal of the first transistor Q1. (Refer to...) Figure 5 and Figure 10 The first connection point P1 is coupled to the output terminal of the third transistor Q3. The second connection point P2 is coupled to the ground terminal G1. The third connection point P3, the second current source I2, and the output terminal of the second transistor Q2 are all coupled to the first node N1. Here, the third connection point P3 is used to receive the bias voltage Vb1, that is, the terminal voltage of the first node N1.

[0096] When the adjustable transistor Qi is Figure 5 When the second transistor Q2 is shown, the first connection point P1 is the input terminal of the first transistor Q1, the second connection point P2 is the output terminal of the first transistor Q1, and the third connection point P3 is the control terminal of the first transistor Q1. (Refer to...) Figure 5 and Figure 10 The first connection point P1 is coupled to the power supply circuit (not shown) and is used to receive power supply V2. The second connection point P2, the second current source I2, and the control terminal of the first transistor Q1 are all coupled to the first node N1. The third connection point P3 is coupled to the resistor R1. Here, the third connection point P3 is used to receive the bias voltage Vb2', that is, the terminal voltage of the second end of the resistor R1.

[0097] When the adjustable transistor Qi is Figure 5 When the third transistor Q3 is shown, the first connection point P1 is the input terminal of the third transistor Q3, the second connection point P2 is the output terminal of the third transistor Q3, and the third connection point P3 is the control terminal of the third transistor Q3. (Refer to...) Figure 5 and Figure 10 The first connection point P1, the first current source I1, and the first end of the resistor R1 are all coupled to the second node N2. The second connection point P2 is coupled to the input terminal of the first transistor Q1. The third connection point P3 is coupled to the bias voltage generating circuit (not shown in the figure) and is used to receive the bias voltage Vb3.

[0098] Please refer to Figure 3 , Figure 5 and Figure 10 When the adjustable transistor Qi is applied to the adjustable inductor 10, during the operation of the adjustable inductor 10, the control signals Sc1 to Scn generated by the selection circuit 50 are input one-to-one to the control terminals of the corresponding switches SW1 to SWn, causing the switches SW1 to SWn to turn on or off in response to the corresponding control signals Sc1 to Scn. In other words, a predetermined number (for example, j) of the switches SW1 to SWn turn on in response to the corresponding control signals Sc1 to Scj, causing the corresponding transistor elements M1 to Mj to receive bias voltages Vb1 / Vb2 / Vb2' / Vb3 through the switches SW1 to SWn and generate corresponding actions. The remaining switches SWk to SWn turn off in response to the corresponding control signals Sck to Scn, causing the corresponding transistor elements Mk to Mn to be unable to receive bias voltages Vb1 / Vb2 / Vb2' / Vb3 through the corresponding switches SWk to SWn, and thus are disabled. In this way, the input impedance Zin1 of the adjustable inductor 10 can be controlled. Here, j is any positive integer from 1 to n, and k is j+1.

[0099] In some embodiments, the aforementioned transistor elements (e.g., transistors Q1-Q3 implemented as a single transistor element or transistor elements M1-Mn in an adjustable transistor Qi) can be any type of transistor, such as, but not limited to, bipolar junction transistors (BJTs) and metal-oxide-semiconductor field-effect transistors (MOSFETs). In one example, using a MOSFET, the input terminal of the transistor element is the drain, its output terminal is the source, and its control terminal is the gate. In another example, using a BJT, the input terminal of the transistor element is the collector, its output terminal is the emitter, and its control terminal is the base. In some embodiments, the transistor elements M1-Mn corresponding to the implementation of transistors Q1 / Q2 / Q3 are bipolar junction transistors, and the operating region of transistors Q1 / Q2 / Q3 includes a cutoff region, a saturation region, and an amplification region. In other embodiments, the transistor elements M1-Mn corresponding to the implementation of transistors Q1 / Q2 / Q3 are metal-oxide-semiconductor field-effect transistors, and the operating region of transistors Q1 / Q2 / Q3 includes a cutoff region, a linear region, and a saturation region.

[0100] In summary, the filter circuit 1 or adjustable inductor 10 of any embodiment implements an inductor (i.e., adjustable inductor 10) with inductance value adjustment function using a small number of hardware components. This allows for effective adjustment of the inductance value while avoiding and solving problems such as excessive layout area and insufficient quality factor (Q value). Thus, the filter circuit 1 implemented with the adjustable inductor 10 can effectively eliminate noise on the power line 30 of the circuit system to which it is applied by adjusting the inductance value of the adjustable inductor 10, thereby improving the stability of the circuit system. Furthermore, by changing the parameters of each hardware component (e.g., transistors Q1 / Q2 / Q3) in the adjustable inductor 10, the cost, size, and power consumption of the adjustable inductor 10 can be effectively reduced, thereby improving the quality factor of the adjustable inductor 10. Moreover, the user can incorporate an impedance element 20 into the filter circuit 1 to form different circuit combinations with the adjustable inductor 10, thereby realizing various types of filters.

[0101] Although this disclosure has been presented above with reference to embodiments, it is not intended to limit the invention of this disclosure. Any person skilled in the art may make some modifications and variations without departing from the concept and scope of this disclosure, and such modifications and variations shall still be within the scope of the claims of this disclosure.

Claims

1. A filter circuit, comprising: One power supply terminal is used to receive a working power supply; One output terminal is used to output the operating power supply; A power supply line is coupled between the power supply terminal and the output terminal; and An adjustable inductor is electrically connected between the power line and a ground terminal to eliminate noise on the power line.

2. The filter circuit of claim 1, wherein the adjustable inductor comprises: A first transducer, the input terminal of which is electrically connected to the power supply terminal; and A second transducer, the output of which is electrically connected to the input of the first transducer, and the input of which is electrically connected to the output of the first transducer.

3. The filter circuit of claim 2, wherein the first transducer comprises: A first current source is electrically connected between a first power source and a node; and A first transistor, the input terminal of which is electrically connected to the node, the control terminal of which is electrically connected to the power supply terminal, and the output terminal of which is electrically connected to the ground terminal; and The second transducer includes: A second transistor, the input terminal of which is electrically connected to a second power supply, the control terminal of which is electrically connected to the node, and the output terminal of which is electrically connected to the power supply terminal; and A second current source is electrically connected between the power supply terminal and the ground terminal.

4. The filter circuit of claim 3, wherein the first transistor is an adjustable transistor or a single transistor element, and the second transistor is an adjustable transistor or a single transistor element.

5. The filter circuit of claim 3, wherein the first transducer further comprises: A resistor is electrically connected between the node and the control terminal of the second transistor; and A third transistor, the input terminal of which is electrically connected to the node, the control terminal of which is electrically connected to a bias voltage, and the output terminal of which is electrically connected to the input terminal of the first transistor.

6. The filter circuit of claim 5, wherein the third transistor is an adjustable transistor or a single transistor element.

7. The filter circuit of claim 1 further includes an impedance element electrically connected to the adjustable inductor.

8. An adjustable inductor, comprising: A first transducer; and A second transconductor is electrically connected between the two ends of the first transconductor, wherein the first transconductor and the second transconductor have opposite transconductance phases.

9. The adjustable inductor of claim 8, wherein the first transducer comprises a first transistor and a first current source, the first current source being electrically connected between a first power source and a node, the input terminal of the first transistor being electrically connected to the node, the control terminal of the first transistor being electrically connected to another node, and the output terminal of the first transistor being electrically connected to a ground terminal; and The second transducer includes a second transistor and a second current source. The input terminal of the second transistor is electrically connected to a second power supply, the control terminal of the second transistor is electrically connected to the node, the output terminal of the second transistor is electrically connected to the other node, and the second current source is electrically connected between the other node and the ground terminal.

10. The adjustable inductor of claim 9, wherein the first transducer further comprises: A resistor electrically connected between the node and the control terminal of the second transistor; and A third transistor, the input terminal of which is electrically connected to the node, the control terminal of which is electrically connected to a bias voltage, and the output terminal of which is electrically connected to the input terminal of the first transistor.

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