A hierarchical calibration method for lightweight crystal oscillator frequency offset estimation and adaptive compensation

Abstract

The present disclosure relates to a hierarchical calibration lightweight crystal frequency offset estimation and adaptive compensation method, aiming to solve the problems of precision limitation, slow convergence of frequency offset estimation, lack of long-term stability guarantee and high computational complexity of pure software scheme in existing technology when dealing with crystal frequency offset. The scheme designs a "short time + long time" hierarchical calibration lightweight crystal frequency offset estimation and adaptive compensation scheme with the help of the system clock and hardware interrupt mechanism of the chip, and considers the frequency offset estimation of the offline situation. Based on CH585 chip, the scheme can control the equivalent frequency offset to below 0.02ppm within 10 seconds, and the 10-second cumulative error is less than 200ns, which can meet the requirements of nanosecond-level long-term synchronization of distributed wireless system. Without additional DPLL circuit or high-precision temperature compensation crystal oscillator, the hardware cost can be reduced by more than 80%, the power consumption can be reduced by more than 50%, and it is especially suitable for large-scale sensor networks and device deployment with limited resources.

Description

Technical Field

[0001] This disclosure relates to the interdisciplinary fields of communication and electronic systems, signal processing, and instrument science and technology, and in particular to a lightweight crystal oscillator frequency offset estimation and adaptive compensation method with graded calibration. Background Technology

[0002] In distributed wireless sensor networks, each node is typically equipped with an independent local clock source to maintain system operation. Quartz crystal oscillators (crystals) are the most commonly used clock source in embedded systems due to their low cost, low power consumption, and small size. However, the frequency stability of crystals is affected by various factors, including: (1) Manufacturing tolerance: The initial frequency deviation of the crystal oscillator is ±20ppm or even higher when it leaves the factory; (2) Temperature change: Fluctuations in ambient temperature can cause the crystal oscillator frequency to drift, with a typical value of ±10-20ppm / ℃; (3) Aging effect: During long-term use, the crystal oscillator frequency will change slowly over time, and the aging rate is about 1-5 ppm / year; (4) Voltage fluctuations: Changes in the supply voltage can also cause frequency shifts.

[0003] For applications such as distributed wireless signal acquisition and industrial IoT monitoring, distributed systems requiring high-precision clock synchronization will experience gradual clock drift between nodes due to crystal oscillator frequency offset. For example, with a 32MHz crystal oscillator and a frequency offset of ±20ppm, the clock deviation between two nodes will accumulate at a rate of approximately 20μs / second. If the synchronization period is 10 seconds, the accumulated error can reach 200μs, far exceeding the requirements for nanosecond-level synchronization accuracy.

[0004] Therefore, it is necessary to design an effective frequency offset estimation and compensation mechanism to suppress clock drift during the synchronization interval and maintain the long-term synchronization stability of the distributed system.

[0005] Currently, the following technical solutions are mainly used to address the crystal oscillator frequency offset problem: (1) Hardware DPLL phase-locked loop scheme A digital phase-locked loop (DPLL) is a hardware circuit that achieves clock synchronization through feedback control. This scheme uses a phase detector to detect the phase difference between the local clock and a reference clock, generates a control voltage through a loop filter, and adjusts the output frequency of a voltage-controlled oscillator (VCO) to make the local clock track the reference clock. The main drawbacks of this scheme are: first, it requires additional hardware circuitry, increasing system cost and power consumption; second, the DPLL's lockout time is relatively long, typically on the order of milliseconds to seconds, making it difficult to meet the requirements of fast synchronization; and third, the loop parameters (bandwidth, damping coefficient) need to be finely adjusted according to the application scenario, resulting in poor versatility.

[0006] (2) High-precision temperature-compensated crystal oscillator (TCXO) solution Temperature-compensated crystal oscillators (TCXOs) automatically adjust their oscillation frequency to counteract the effects of temperature drift through a built-in temperature sensor and compensation circuit. High-end TCXOs can achieve frequency stability of ±0.5-2ppm. The main drawbacks of this approach are: firstly, the cost is significantly higher than ordinary crystal oscillators (5-10 times), making it unsuitable for large-scale sensor network deployments; secondly, it can only compensate for temperature-induced drift and cannot address other factors such as aging and voltage fluctuations; and thirdly, it has high power consumption, which is detrimental to battery-powered wearable devices.

[0007] (3) Software NTP / PTP time synchronization scheme Network Time Protocol (NTP) and Precision Time Protocol (PTP) adjust the local clock by periodically exchanging timestamp messages, measuring network round-trip delay, and calculating clock skew. The main shortcomings of this approach are: first, it relies on frequent network communication for time calibration, increasing channel occupancy and power consumption; second, synchronization accuracy is affected by network jitter, typically only reaching millisecond to microsecond levels in wireless environments; and third, it does not actively compensate for crystal oscillator frequency offset, resulting in continuous clock drift during the synchronization interval. Summary of the Invention

[0008] The shortcomings of the existing technologies mentioned in the background technology include: (1) High cost and high power consumption of hardware solutions: Hardware compensation solutions such as DPLL and TCXO require additional dedicated circuits, which significantly increases system cost and power consumption, and is not suitable for large-scale sensor networks with limited resources. (2) Limited accuracy of software solutions: Software synchronization solutions such as NTP rely on network communication, and the synchronization accuracy is affected by protocol stack jitter and channel quality, making it difficult to reach the nanosecond level, and the clock drift problem during the synchronization interval is not solved. (3) Slow convergence of frequency offset estimation: Existing frequency locking mechanisms require multiple iterations to converge, which is difficult to meet the need for rapid synchronization. (4) Lack of long-term stability guarantee: Existing solutions do not fully consider the impact of long-term factors such as temperature drift and aging on synchronization accuracy, making it difficult to maintain the long-term synchronization stability of the system. (5) High computational complexity: Some frequency offset estimation algorithms involve complex floating-point operations or matrix inversion, which have poor real-time performance on resource-constrained embedded platforms.

[0009] Based on this, the purpose of this disclosure is to provide a lightweight crystal oscillator frequency offset estimation and adaptive compensation method with graded calibration. By utilizing the chip's system clock and hardware interrupt mechanism, a lightweight crystal oscillator frequency offset estimation and adaptive compensation scheme with "short-time + long-time" graded calibration is designed, eliminating the need for additional hardware DPLL or high-precision crystal oscillators. Using the graded calibration strategy of this application on the CH585 chip, the equivalent frequency offset voltage is reduced to below 0.02ppm within 10 seconds, and the cumulative error over 10 seconds is less than 200ns, meeting the nanosecond-level long-term synchronization requirements of distributed wireless systems. Furthermore, this scheme considers offline scenarios.

[0010] The first aspect of this disclosure proposes a lightweight crystal oscillator frequency offset estimation and adaptive compensation method with hierarchical calibration. In a distributed wireless system where a host and slave are connected, the steps include: when the number of short-time calibration executions is less than a preset number, or when the number of short-time calibration executions is greater than or equal to a preset number and two consecutive frequency offset estimates are greater than or equal to a preset frequency offset threshold, frequency offset estimation is performed based on two synchronization signals sent by the master node to all slave nodes, with the interval between the two synchronization signals being a preset short-time calibration period; when the number of short-time calibration executions is greater than or equal to a preset number and two frequency offset estimates are less than a preset threshold, frequency offset estimation is performed based on two synchronization signals sent by the master node to all slave nodes, with the interval between the two synchronization signals being a preset long-time calibration period.

[0011] A second aspect of this disclosure provides a computer-readable storage medium storing a computer program that can be loaded by a processor and execute any of the methods described in this disclosure.

[0012] A third aspect of this disclosure proposes a distributed wireless system including a master node and slave nodes, wherein the slave nodes perform crystal oscillator frequency offset estimation and compensation using any of the methods described in this disclosure.

[0013] Compared with existing crystal oscillator frequency offset compensation technologies, this invention offers significant advantages in cost, power consumption, accuracy, and adaptability. First, the pure software frequency offset compensation scheme proposed in this invention is implemented entirely based on the existing resources of the CH585 chip, requiring no additional DPLL circuits or high-precision temperature-compensated crystal oscillators. This reduces hardware costs by over 80% and power consumption by over 50%, making it particularly suitable for resource-constrained large-scale sensor networks and device deployments. Second, the dual-point synchronization frequency offset estimation algorithm of this invention requires only two synchronizations to accurately estimate the frequency offset. Combined with short-time calibration, it can converge the frequency offset estimation error to less than 0.01ppm within 30–90 seconds, a convergence speed 3–5 times faster than traditional progressive frequency locking mechanisms. The background compensation execution mechanism reduces the equivalent frequency offset from ±20ppm to less than 0.02ppm, with a cumulative error of less than 200ns over 10 seconds, meeting the long-term maintenance requirements for nanosecond-level synchronization accuracy. The lightweight design allows all compensation calculations to be completed within an interrupt, without affecting the main business thread, with a memory overhead of less than 10 bytes, providing excellent real-time performance on resource-constrained embedded platforms. When the system is stable, long-term calibration reduces resource consumption. Offline calibration based on temperature ensures system operation and improves system stability. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a flowchart of a hierarchical overall calibration process in one implementation method. Detailed Implementation

[0016] In response to the problems mentioned in the background art, the present invention provides a low-cost, low-power, high-precision, and adaptive crystal oscillator frequency offset compensation solution for distributed wireless systems.

[0017] The following will describe clearly and completely how the technical solution of this application is implemented, with reference to the accompanying drawings. Obviously, the described implementation methods are only a part of the implementation methods of this application, and not all of them. Based on the implementation methods in this application, all other implementation methods obtained by those skilled in the art without inventive effort are within the scope of protection of this application. The distributed wireless system in this application includes a host and slave devices, with the host acting as the master node and the slave devices as slave nodes.

[0018] In one implementation, a lightweight crystal oscillator frequency offset estimation and adaptive compensation scheme with "short-time + long-time" graded calibration is designed based on the System Tick timer of the CH585 chip, utilizing its 78MHz system clock (resolution of approximately 12.82ns) and hardware interrupt mechanism.

[0019] The lightweight crystal oscillator frequency offset estimation and adaptive compensation scheme with graded calibration is applied to a distributed wireless system, which includes a master node and slave nodes. The master node, acting as a reference clock source, is responsible for sending synchronization broadcast packets, collecting timestamps from each node, calculating frequency offset parameters, and issuing compensation commands. The slave nodes perform frequency offset estimation and compensation tasks, maintain local compensation counters, and complete the compensation operation in timer interrupts.

[0020] The introduction of the lightweight crystal oscillator frequency offset estimation and adaptive compensation scheme with graded calibration includes the following parts.

[0021] (1) Two-point synchronization frequency offset estimation algorithm See Figure 1 During the initialization phase, the dual-point synchronization frequency offset estimation initialization is performed to trigger the master node and the slave node to be synchronized to enter the synchronization mode.

[0022] The dual-point synchronous frequency offset estimation algorithm is a method for accurately estimating the crystal oscillator frequency offset based on two synchronous samplings. It accurately calculates the crystal oscillator frequency offset by measuring the cumulative clock error within the time interval.

[0023] Specifically, the first synchronization involves the master node sending a synchronization signal to all slave nodes, and each slave node n recording its local System Tick value during a PHY (Physical Layer) interrupt. The synchronization signal can be a wired connection pulse or a wireless synchronization radio frequency.

[0024] Wait N seconds: During this period, each node operates freely, and the crystal oscillator frequency deviation causes the clock to gradually drift.

[0025] Second synchronization: The master node sends a synchronization signal to all slave nodes again, and each slave node n records its local System Tick value. .

[0026] Master node waiting time T Using the formula Calculate the frequency offset value, where is the frequency offset value of the nth slave node (dimensionless, positive indicates clock speed is too fast, negative indicates clock speed is too slow), N is the number of seconds between two synchronizations, and 78MHz is the CH585 system clock frequency.

[0027] The above-mentioned two-point synchronization frequency offset estimation algorithm only requires two synchronizations to estimate the frequency offset, without the need for complex statistical averaging or filtering processing, and has low computational load and fast convergence speed.

[0028] (2) Calculation of compensation parameters Each slave node will display its own system clock value. and The data is sent to the host, which calculates the clock frequency offset for each slave node. T is the master node's waiting period.

[0029] The master node calculates the compensation period for each slave node: ,For example =20ppm =50,000. Compensation direction: = sign(δ), for example, +1 indicates the clock is too fast and needs to be subtracted, -1 indicates the clock is too slow and needs to be added. For the calculated compensation parameters... The master node distributes the information to each slave node, and each slave node performs the compensation in the background.

[0030] (3) Back-end compensation execution mechanism The background compensation execution mechanism is a lightweight background compensation method based on a compensation counter. This mechanism integrates frequency offset compensation into the existing timer interrupt without adding extra interrupt overhead, achieving true background compensation without affecting the execution of the main business thread.

[0031] Specifically, each slave node maintains a compensation counter in the timer interrupt, which increments every tick: when the counter is greater than or equal to P, the compensation cycle is reached, System Tick += D is executed, and then the counter is cleared to zero.

[0032] This background compensation mechanism reduces the equivalent frequency offset from ±20ppm to less than 0.02ppm, with a cumulative error of less than 200ns over 10 seconds. Since the compensation operation is completed during a timer interrupt, it does not affect the main business thread, thus achieving true background compensation.

[0033] (4) Short-time calibration phase To achieve rapid convergence of the frequency offset estimation error, a short-time iterative calibration process is designed in one implementation. The short-time calibration period is denoted as... Set the calibration interval to 10-30 seconds, and perform a preset number of short calibrations. Specific calibration interval values ​​are, for example, 10 seconds, 20 seconds, and 30 seconds. The preset number of calibrations is, for example, 2-3 times.

[0034] The master node calculates the clock frequency offset of each slave node. . Short-time calibration is an iterative process: after each calibration, the compensation parameters are updated to gradually reduce the residual frequency offset.

[0035] The convergence criterion is: when the frequency deviation value calculated from two consecutive calibrations is less than a preset threshold, the convergence state is determined to be reached. The preset threshold is, for example, 0.01 ppm.

[0036] This mechanism can bring the frequency offset estimation error to the theoretical limit within 30-90 seconds. For example, at a 78MHz clock frequency, one clock cycle is 12.83ns, which is approximately 13-39ns. Specifically for the CH585 platform and a 78MHz clock frequency, the theoretical limit is an error of 1-3 clock cycles. (5) Long-term calibration phase and internal frequency offset table update After a short period of convergence, the system enters a long-term calibration phase to address the impact of long-term factors such as temperature drift.

[0037] Specifically, frequency offset estimation is performed based on two synchronization signals sent from the master node to all slave nodes, with the interval between the two synchronization signal transmissions being a preset long-term calibration period. The steps include: The master node sends a synchronization signal to all slave nodes, and the slave nodes record their own System Tick time value. ; The master node waits for a preset long calibration period. ; The master node sends a synchronization signal to all slave nodes again, and the slave nodes record their own System Tick time value. ; All slave nodes will update their own system clock values. and The data is sent to the host, which calculates the clock frequency offset for each slave node. ; The master node calculates the compensation period for each slave node. Compensation direction Packaging parameters It is then distributed to each slave node.

[0038] (6) Offline frequency offset estimation If the device is constantly under the control of the host (central node), the temperature compensation coefficient can be ignored, and the frequency correction mainly relies on the frequency stability of the central node. Based on this, this disclosure designs a temperature-based offline frequency offset estimation, so that when the slave device is no longer under the control of the host, it can perform crystal oscillator polarization compensation and updates based on its built-in temperature sensor.

[0039] When a master and slave node connect in a distributed wireless system: the slave node n receives parameters. Then, obtain the current temperature. According to parameters The System Tick has been modified, including: maintaining a compensation counter in the timer interrupt for slave node n. Incrementing with each tick, when Greater than or equal to When using System Tick+ Update System Tick and its built-in frequency offset table. For example, a temperature-frequency offset compensation table is built within a temperature range of 0-40℃ to achieve more precise temperature compensation.

[0040] In a distributed wireless system, when the master and slave nodes disconnect, the slave node obtains the current temperature. Based on its built-in frequency offset table, it obtains parameters for automatic frequency offset correction in offline mode.

[0041] When the host and slave devices in a distributed wireless system reconnect, it is preferable to perform a re-initialization.

[0042] In summary, the lightweight crystal oscillator frequency offset estimation and adaptive compensation method with hierarchical calibration proposed in this application adopts a hierarchical calibration strategy when the master and slave nodes are connected. This strategy comprises three stages: the first stage initializes the compensation parameters by performing dual-point synchronous frequency offset estimation; the second stage achieves rapid convergence of compensation accuracy through iterative optimization of the accuracy using 2-3 consecutive short-term calibrations (10-30 second cycles); and the third stage utilizes periodic calibration to achieve long-term maintenance. Furthermore, during the calibration process, a temperature-frequency offset parameter table is recorded so that calibration can still be performed when the master and slave nodes are disconnected.

[0043] This solution is a lightweight design optimization scheme. Firstly, since all compensation calculations use integer operations, floating-point operation overhead is avoided. Secondly, interrupt optimization is implemented: timer interrupt handling is controlled within 5 clock cycles (@78MHz ≈ 64ns). Thirdly, this solution requires only 4 bytes to store the compensation counter, 2 bytes to store the compensation period, and 1 byte to store the direction, with a total memory overhead of <10 bytes. Finally, the compensation operation is completed within the existing timer interrupt, without increasing additional power consumption.

[0044] Based on the above, those skilled in the art will understand that the above method can be applied to a distributed wireless system. Specifically, the distributed wireless system includes a master node and slave nodes, and the slave nodes use the above-described lightweight crystal oscillator frequency offset estimation and adaptive compensation method with hierarchical calibration to estimate and compensate for the crystal oscillator frequency offset.

[0045] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein. The scope of the invention is defined by the appended claims.

Claims

1. A lightweight crystal oscillator frequency offset estimation and adaptive compensation method with graded calibration, characterized in that, When a host and slave device connect in a distributed wireless system, the steps include: When the number of short-time calibration executions is less than the preset number, or when the number of short-time calibration executions is greater than or equal to the preset number and the frequency offset estimates of two consecutive times are greater than or equal to the preset frequency offset threshold, frequency offset estimation is performed based on the master node sending synchronization signals to all slave nodes twice. The interval between the two synchronization signal transmissions is the preset short-time calibration period. When the number of short-time calibration executions is greater than or equal to the preset number and the frequency offset estimates of the two times are less than the preset threshold, frequency offset estimation is performed based on the master node sending synchronization signals to all slave nodes twice. The interval between the two synchronization signal transmissions is the preset long-time calibration period.

2. The method according to claim 1, characterized in that: The preset short-time calibration cycle is 10 to 30 seconds.

3. The method according to claim 1, characterized in that: The preset long-term calibration cycle is 5 to 10 minutes.

4. The method according to claim 1, characterized in that, Frequency offset estimation is performed based on two synchronization signals sent from the master node to all slave nodes, with the interval between the two synchronization signal transmissions being a preset short-time calibration period. The steps include: The master node sends a synchronization signal to all slave nodes, and the slave nodes record their own System Tick time value. ; The master node waits for a preset short calibration period. ; The master node sends a synchronization signal to all slave nodes again, and the slave nodes record their own System Tick time value. ; All slave nodes will update their own system clock values. and The data is sent to the host, which calculates the clock frequency offset for each slave node. ; The master node calculates the compensation period for each slave node. Compensation direction Packaging parameters It is then distributed to each slave node.

5. The method according to claim 1, characterized in that, Frequency offset estimation is performed based on two synchronization signals sent from the master node to all slave nodes, with the interval between the two synchronization signal transmissions being a preset long-time calibration period. The steps include: The master node sends a synchronization signal to all slave nodes, and the slave nodes record their own System Tick time value. ; The master node waits for a preset long calibration period. ; The master node sends a synchronization signal to all slave nodes again, and the slave nodes record their own System Tick time value. ; All slave nodes will update their own system clock values. and The data is sent to the host, which calculates the clock frequency offset for each slave node. ; The master node calculates the compensation period for each slave node. Compensation direction Packaging parameters It is then distributed to each slave node.

6. The method according to claim 1, characterized in that, The method also includes updating the frequency offset table built into the slave node to perform temperature-based offline frequency offset estimation when the master and slave nodes are disconnected in a distributed wireless system, including: Receive parameters from node n Then, obtain the current temperature. According to parameters The System Tick has been modified, including: maintaining a compensation counter in the timer interrupt for slave node n. Incrementing with each tick, when Greater than or equal to When using System Tick+ Update System Tick and its built-in frequency offset table. ; In a distributed wireless system, when the master and slave nodes disconnect, the slave node obtains the current temperature. Frequency offset estimation is performed based on its built-in frequency offset table.

7. The method according to claim 1, characterized in that: The preset frequency offset threshold is preferably 0.01ppm.

8. A computer-readable storage medium, characterized in that: The computer program is stored that can be loaded by a processor and executed as described in any one of claims 1 to 7.

9. A distributed wireless system, comprising a master node and slave nodes, characterized in that, Crystal oscillator frequency offset estimation and compensation are performed at the node using any one of the methods described in claims 1 to 7.

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