Vertical channel transistor structure and method of manufacturing the same

Abstract

A vertical channel transistor structure and a method of manufacturing the same are provided. The vertical channel transistor structure includes a plurality of oxide semiconductor pillars, a first electrode, a second electrode, a plurality of word lines, and a gate oxide layer. Each of the oxide semiconductor pillars has a top end and a bottom end. The first electrode is disposed below and connected to the top end of each of the oxide semiconductor pillars, and the second electrode is disposed above and connected to the bottom end of each of the oxide semiconductor pillars. The plurality of word lines is disposed at different heights of the plurality of oxide semiconductor pillars. The gate oxide layer is disposed between each of the oxide semiconductor pillars and each of the word lines.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more particularly to a vertical channel transistor structure and a method for manufacturing the same. Background Technology

[0002] To continue the development path of DRAM below 10 nm, a 4F DRAM using a vertical channel / pillar transistor structure (VCT / VPT) is proposed. 2 Unit cell structure replaces 6F 2 Unit cell structure to meet the requirements of high density and low cost.

[0003] However, interference from the adjacent word line (WL) is 4F. 2 The VCT / VPT transistors in DRAM are weak points, and can cause RETH problems after frequent operation of adjacent WLs. Therefore, the small WL-WL spacing (poor coupling effect) leads to a reduction in the next generation of 4F transistors. 2 The size of DRAM cells is difficult to determine. Summary of the Invention

[0004] This invention relates to a vertical channel transistor structure and its fabrication method, which reduces the WL-WL coupling effect and increases 4F. 2 Feasibility of reducing the unit cell size in DRAM.

[0005] According to an embodiment of the present invention, a vertical channel transistor structure includes a plurality of oxide semiconductor pillars, a first electrode, a second electrode, a plurality of word lines, and a gate oxide layer. Each of the plurality of oxide semiconductor pillars has a top end and a bottom end. The first electrode is disposed below and connected to the bottom end of the plurality of oxide semiconductor pillars. The second electrode is disposed above and connected to the top end of the plurality of oxide semiconductor pillars. The plurality of word lines are disposed at different heights of the plurality of oxide semiconductor pillars. The gate oxide layer is disposed between each of the plurality of oxide semiconductor pillars and each of the plurality of word lines.

[0006] In a vertical channel transistor structure according to an embodiment of the present invention, one word line and another word line adjacent to it are disposed at different heights of an oxide semiconductor pillar.

[0007] In the vertical channel transistor structure according to an embodiment of the present invention, the minimum distance between one of the word lines and the adjacent word line is greater than the horizontal distance between one of the word lines and the adjacent word line.

[0008] In the vertical channel transistor structure according to an embodiment of the present invention, in a cross-sectional view, the shape of each word line is trapezoidal.

[0009] In the vertical channel transistor structure according to an embodiment of the present invention, in the cross-sectional view, each oxide semiconductor pillar is inverted trapezoidal in shape.

[0010] In a vertical channel transistor structure according to an embodiment of the present invention, one of the plurality of word lines surrounds a set of oxide semiconductor pillars along a direction parallel to the plane, and the oxide semiconductor pillars are arranged perpendicular to the plane.

[0011] According to another embodiment of the present invention, a method for manufacturing a vertical channel transistor structure includes the following steps: A plurality of first electrodes are formed on a substrate. A first word line is formed at a first height above the first electrodes. A second word line is formed at a second height above the first electrodes, wherein the first height and the second height are different. A plurality of channel openings are formed, respectively penetrating the first word line and the second word line. A gate oxide layer is formed on the sidewall of each channel opening. A plurality of oxide semiconductor pillars are formed in the plurality of channel openings. A plurality of second electrodes are formed on the plurality of oxide semiconductor pillars.

[0012] In a manufacturing method according to another embodiment of the present invention, the first height is higher than the second height, or the first height is lower than the second height.

[0013] In a manufacturing method according to another embodiment of the present invention, the method of forming a first word line includes forming a first insulating layer on a plurality of first electrodes, depositing a conductive material layer on the first insulating layer, forming a first patterned mask on the conductive material layer, and using the first patterned mask as an etching mask to etch back the conductive material layer.

[0014] In a manufacturing method according to another embodiment of the present invention, the method of forming a second word line includes forming a second insulating layer above the first word line, depositing a conductive material layer on the second insulating layer, forming a second patterned mask on the conductive material layer, and using the second patterned mask as an etching mask to etch back the conductive material layer.

[0015] In a manufacturing method according to another embodiment of the present invention, the method of forming a plurality of channel openings includes forming a third insulating layer on a second word line, forming a third patterned mask on the third insulating layer, and using the third patterned mask as an etching mask to etch the third insulating layer, the second word line and the first word line until the plurality of first electrodes are exposed.

[0016] In a manufacturing method according to another embodiment of the present invention, a third patterned mask has a first opening aligned with a first letter line.

[0017] In a manufacturing method according to another embodiment of the present invention, the third patterned mask has a second opening aligned with the second letter line.

[0018] Based on the above, the vertical channel transistor structure according to the present invention reduces the WL-WL coupling effect by placing multiple word lines at different heights. Simultaneously, the present invention also increases the 4F... 2 Feasibility of reducing the unit cell size in DRAM. Attached Figure Description

[0019] Figure 1 This is a top view of a plurality of vertical channel transistor structures according to some embodiments of the present invention;

[0020] Figure 2 yes Figure 1 A cross-sectional view of the vertical channel transistor structure;

[0021] Figure 3 This is a cross-sectional view of a vertical channel transistor structure according to some embodiments of the present invention;

[0022] Figures 4A to 4H This is a cross-sectional view of the manufacturing process of a vertical channel transistor structure according to some embodiments of the present invention. Detailed Implementation

[0023] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. However, the invention can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, for clarity and explicitness, the dimensions of layers and regions and their relative dimensions may not be shown to exact scale.

[0024] Figure 1 This is a top view of a plurality of vertical channel transistor structures according to some embodiments of the present invention. Figure 2 It is along Figure 1 A cross-sectional view of XX. For clarity, it is not shown. Figure 1 Some components, such as Figure 2 The second electrode 102 and the upper part of the insulating layer 108.

[0025] Now refer to Figure 1 and Figure 2Each vertical channel transistor structure 100 includes a plurality of oxide semiconductor pillars OS, a first electrode 104, a second electrode 102, a plurality of word lines WL1-WL2, and a gate oxide layer 106. Each oxide semiconductor pillar OS has a top OSt and a bottom OSb. The first electrode 104 is disposed below and connected to the bottom OSb of each oxide semiconductor pillar OS. The second electrode 102 is disposed on and connected to the top OSt of each oxide semiconductor pillar OS. In some embodiments, the oxide semiconductor pillars OS are vertically disposed above the substrate 110. In some embodiments, the material of the oxide semiconductor pillars OS can be at least one of indium gallium zinc oxide (IGZO), manganese oxide (MnO2), zinc oxide (ZnO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), etc., and the present invention does not impose any limitations.

[0026] Word lines WL1-WL2 are positioned at different heights from the oxide semiconductor pillar OS. The term "height" in this embodiment may also refer to the vertical distance from the same object, such as substrate 110 or first electrode 104. In other words, word lines WL1-WL2 can be considered as a double-layer WL. In some embodiments, one of the word lines (e.g., word line WL1) and the adjacent other (e.g., word line WL2) are positioned at different heights from the oxide semiconductor pillar OS. In some embodiments, the minimum distance s1 between word lines WL1 and WL2 is longer than the horizontal distance s2 between word lines WL1 and WL2. The horizontal distance s2 is the spacing between word lines WL1 and WL2 along the XX line. By positioning word lines WL1 and WL2 at different heights, the present invention can increase the distance between word lines WL1 and WL2 to reduce WL-WL coupling (neighboring WL interference) effects, or increase 4F. 2 The feasibility of reducing the unit cell size in DRAM. Figure 2 In the cross-sectional view, each character line WL1-WL2 is a rectangle with vertical edges.

[0027] exist Figure 1 In the middle, one of the character lines WL1 or WL2 is parallel to the plane ( Figure 2 The substrate 110 is oriented around a set of oxide semiconductor pillars OS, and the oxide semiconductor pillars OS are disposed perpendicular to the plane. A gate oxide layer 106 is disposed between each oxide semiconductor pillar OS and each word line WL1-WL2. In some embodiments, the vertical channel transistor structure 100 further includes an insulating layer 108, the material of which may include oxide or other suitable insulating material. The oxide semiconductor pillars OS, the gate oxide layer 106, and the word lines WL1-WL2 may be disposed within the insulating layer 108. In some embodiments, the gate oxide layer 106 is also disposed between each oxide semiconductor pillar OS and the insulating layer 108.

[0028] Figure 3 This is a cross-sectional view of a vertical channel transistor structure according to some embodiments of the present invention, wherein the same reference numerals as in the previous embodiment are used to denote the same or similar parts and components, and the relevant content of the same or similar parts and components can also refer to the content of the previous embodiment, and will not be repeated here.

[0029] exist Figure 3 In the vertical channel transistor structure 300, there are word lines WL1' and WL2', and both word lines WL1' and WL2' are trapezoidal in shape. This trapezoidal structure is obtained through natural etching characteristics, and the minimum distance s3 between word lines WL1' and WL2' can be greater than the minimum distance in the above embodiment (e.g., ...). Figure 2 (Minimum distance s1 in the WL). In other words, the vertical channel transistor structure 300 may be superior to the previous embodiment in reducing WL-WL coupling effects.

[0030] Figures 4A to 4H This is a cross-sectional view of the manufacturing process of a vertical channel transistor structure according to some embodiments of the present invention.

[0031] Reference Figure 4A A plurality of first electrodes 402 are formed on a substrate 400. A first insulating layer 404 may be formed on the first electrodes 402, and then a conductive material layer 406 may be deposited on the first insulating layer 404. In some embodiments, the first insulating layer 404 may be an oxide or other suitable material. A first patterned mask PM1 is formed on the conductive material layer 406 to expose a portion of the conductive material layer 406. In some embodiments, the first patterned mask PM1 may be a patterned photoresist formed by a photolithography process.

[0032] Reference Figure 4B ,use Figure 4A The first patterned mask PM1 in the process is used as an etching mask for... Figure 4A The conductive material layer 406 in the middle is etched back to form a first word line WL1 at a first height h1 above the first electrode 402. Due to the etching characteristics, the outlines of the two adjacent first word lines WL1 and the first insulating layer 404 between them present an inverted trapezoidal shape. Figure 4A The first patterned mask PM1 will be removed later.

[0033] Reference Figure 4CA second insulating layer 408 is formed on the first word line WL1, and then another conductive material layer 410 is deposited on the second insulating layer 408 above the first word line WL1. In some embodiments, the method of forming the second insulating layer 408 includes depositing oxide to fill the gaps and cover the first word line WL1, followed by CMP (chemical mechanical polishing). A second patterned mask PM2 is formed on the conductive material layer 410 to expose a portion of the conductive material layer 410. In some embodiments, the second patterned mask PM2 may be a patterned photoresist formed by a photolithography process.

[0034] Reference Figure 4D ,use Figure 4C The second patterned mask PM2 in the process is used as an etching mask for... Figure 4C The conductive material layer 410 is etched back to form a second word line WL2 at a second height h2 above the first electrode 402, wherein the first height h1 is different from the second height h2. In this embodiment, the first height h1 is shorter than the second height h2. Due to the etching characteristics, the outlines of the two adjacent second word lines WL2 and the second insulating layer 408 between them form an inverted trapezoidal shape. Figure 4C The second patterned mask PM2 will be removed later.

[0035] Reference Figure 4E A third insulating layer 412 is formed on the second word line WL2. In some embodiments, the method of forming the third insulating layer 412 includes depositing oxide to fill the gaps and cover the second word line WL2, followed by CMP.

[0036] Reference Figure 4F A third patterned mask PM3 is formed on the third insulating layer 412. In some embodiments, the third patterned mask PM3 may be a patterned photoresist formed via a photolithography process. The third patterned mask PM3 has a first opening O1 aligned with the first word line WL1. The third patterned mask PM3 has a second opening O2 aligned with the second word line WL2.

[0037] Reference Figure 4G ,use Figure 4F The third patterned mask PM3 is used as an etching mask to etch the third insulating layer 412, the second word line WL2, the second insulating layer 408, and the first word line WL1 until the first electrode 402 is exposed, thereby forming multiple channel openings HO that respectively penetrate the first word line WL1 and the second word line WL2. (The text abruptly ends here, likely due to an incomplete sentence or missing information.) Figure 4FAfter the third patterned mask PM3, a gate oxide layer 414 is formed on the sidewall of the channel opening HO, and then a plurality of oxide semiconductor pillars OS are formed in the channel opening HO. The oxide semiconductor pillars OS can be in direct contact with the first electrode 402. In some embodiments, each oxide semiconductor pillar OS is inverted trapezoidal in shape.

[0038] Reference Figure 4H Multiple second electrodes 416 are formed on the oxide semiconductor pillar OS.

[0039] In conclusion, from a process perspective, the feasibility of a two-layer WLs process is achievable. Furthermore, from an electrical perspective, WL-WL coupling can be further reduced.

[0040] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A vertical channel transistor structure, characterized in that, include: A plurality of oxide semiconductor pillars, wherein each of the oxide semiconductor pillars has a top end and a bottom end; A first electrode is disposed below and connected to the bottom end of each of the oxide semiconductor pillars; A second electrode is disposed above and connected to the top of each of the oxide semiconductor pillars; Multiple word lines are positioned at different heights of the multiple oxide semiconductor pillars; as well as A gate oxide layer is disposed between each of the oxide semiconductor pillars and each of the word lines.

2. The vertical channel transistor structure according to claim 1, characterized in that, One of the plurality of word lines and another of the plurality of word lines adjacent to it are disposed at different heights of the plurality of oxide semiconductor pillars.

3. The vertical channel transistor structure according to claim 2, characterized in that, The minimum distance between one of the plurality of character lines and another of the plurality of character lines adjacent to it is greater than the horizontal distance between one of the plurality of character lines and another of the plurality of character lines adjacent to it.

4. The vertical channel transistor structure according to claim 1, characterized in that, In the cross-sectional view, each of the character lines is trapezoidal in shape.

5. The vertical channel transistor structure according to claim 1, characterized in that, In the cross-sectional view, each of the oxide semiconductor pillars is inverted trapezoidal in shape.

6. The vertical channel transistor structure according to claim 1, characterized in that, One of the plurality of word lines surrounds a set of the plurality of oxide semiconductor pillars along a direction parallel to the plane, and the plurality of oxide semiconductor pillars are arranged perpendicular to the plane.

7. A method for manufacturing a vertical channel transistor structure, characterized in that, include: Multiple first electrodes are formed on the substrate; A first word line is formed at a first height above the first electrode; A second letter line is formed at a second height above the first electrode, wherein the first height is different from the second height; Multiple channel openings are formed, which respectively penetrate the first word line and the second word line; A gate oxide layer is formed on the sidewall of each of the channel openings; Multiple oxide semiconductor pillars are formed in the plurality of channel openings; as well as Multiple second electrodes are formed on the plurality of oxide semiconductor pillars respectively.

8. The method for manufacturing a vertical channel transistor structure according to claim 7, characterized in that, The first height is higher than the second height.

9. The method for manufacturing a vertical channel transistor structure according to claim 7, characterized in that, The method for forming the first character line includes: A first insulating layer is formed on the plurality of first electrodes; A conductive material layer is deposited on the first insulating layer; A first patterned mask is formed on the conductive material layer; and The conductive material layer is etched back using the first patterned mask as an etching mask.

10. The method for manufacturing a vertical channel transistor structure according to claim 7, characterized in that, The methods for forming the second letter line include: A second insulating layer is formed on the first letter line; A conductive material layer is deposited on the second insulating layer; A second patterned mask is formed on the conductive material layer; and The conductive material layer is etched back using the second patterned mask as an etching mask.

11. The method for manufacturing a vertical channel transistor structure according to claim 7, characterized in that, The method for forming the plurality of channel openings includes: A third insulating layer is formed on the second letter line; A third patterned mask is formed on the third insulating layer; and Using the third patterned mask as an etching mask, the third insulating layer, the second word line, and the first word line are etched until the plurality of first electrodes are exposed.

12. The method for manufacturing a vertical channel transistor structure according to claim 11, characterized in that, The third patterned mask has a first opening aligned with the first letter line.

13. The method for manufacturing a vertical channel transistor structure according to claim 11, characterized in that, The third patterned mask has a second opening aligned with the second letter line.

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