Light emitting diode and light emitting device

Abstract

The application provides a light emitting diode and a light emitting device. The light emitting diode comprises a substrate, a semiconductor stack with a first mesa exposing a first semiconductor layer and a second mesa exposing a second semiconductor layer, an insulating structure comprising a first insulating layer and a second insulating layer stacked in sequence, and an electrode hole comprising a first through hole above the first mesa and a second through hole above the second mesa. The first through hole has opposite top and bottom openings and a sidewall connecting the two. The sidewall is a multi-section structure with at least two different inclination angles. By designing the first through hole as a multi-section structure with an angle greater near the bottom opening than near the top opening, i.e. optimizing the sidewall of the N-hole, the coverage of the electrode metal material can be improved while ensuring the contact area of the electrode and the epitaxial layer, reducing stress concentration and the risk of metal layer cracking, thereby significantly improving the reliability and service life of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a light-emitting diode and a light-emitting device. Background Technology

[0002] A light-emitting diode (LED) is a semiconductor device whose basic structure consists of a PN junction between a P-type semiconductor and an N-type semiconductor. When a forward voltage is applied to the LED, electrons and holes recombine at the junction of the PN junction, releasing energy. This energy is emitted in the form of photons, forming light radiation.

[0003] In Micro LED chips, the opening structure of the insulating layer directly affects the subsequent electrode structure and the chip's electrical performance, especially for N-type electrode holes. Because N-type electrode holes are located at the bottom of MESA holes, the height difference is more pronounced compared to P-type electrode holes, making them more prone to stress cracking. Traditional through-hole structures typically employ a single-angled sidewall design. If the sidewall angle is too small, while it facilitates subsequent metal electrode material deposition and reduces the risk of cracking, it results in an excessively small bottom opening, limiting the contact area between the electrode and the semiconductor layer. This leads to problems such as high contact resistance, uneven current distribution, and overheating. Conversely, if the sidewall angle is too large, although a larger bottom contact area can be achieved, the metal film will experience poor coverage and stress concentration during stepped deposition, making it highly susceptible to cracking or peeling at the step corners, resulting in open circuits and reduced product reliability. Therefore, it is necessary to rationally optimize the electrode hole structure in existing Micro LED chips to solve these problems. Summary of the Invention

[0004] In view of the defects and deficiencies in the prior art, this application provides a light-emitting diode and a light-emitting device that can improve the problem of poor metal coverage, reduce metal electrode cracking and peeling, and at the same time maintain light reflection capability, thereby improving the chip light efficiency.

[0005] In a first aspect, this application provides a light-emitting diode, comprising:

[0006] Substrate;

[0007] A semiconductor stack is disposed on the substrate and includes a first semiconductor layer, an active layer and a second semiconductor layer stacked sequentially. The semiconductor stack has a first mesa exposing the first semiconductor layer and a second mesa exposing the second semiconductor layer.

[0008] An insulating structure is disposed above the semiconductor stack, comprising a first insulating layer and a second insulating layer stacked sequentially.

[0009] An electrode hole, penetrating the insulating structure, includes a first through hole located on the first platform and a second through hole located on the second platform; the first through hole has opposing top and bottom openings and a sidewall connecting the two; wherein,

[0010] The sidewall is a multi-segment structure with at least two different tilt angles, and the angle between the sidewall near the bottom opening and the horizontal direction is greater than the angle between the sidewall near the top opening and the horizontal direction.

[0011] Secondly, this application provides a light-emitting device, the light-emitting device comprising:

[0012] Packaging substrate;

[0013] At least one light-emitting diode is disposed on the surface of the packaging substrate, and the packaging substrate and the electrode structure of the light-emitting diode are electrically connected; the light-emitting diode is the light-emitting diode provided by the above technical solution.

[0014] Compared with the prior art, the technical solution provided in this application has at least the following beneficial effects:

[0015] The light-emitting diode provided in this application features electrode vias with a multi-segment sidewall structure. By optimizing the structural design of the N-side electrode vias, the coverage of the electrode metal material can be optimized while ensuring the contact area between the electrode and the epitaxial layer. This reduces stress concentration and the risk of metal layer cracking, thereby significantly improving the reliability and lifespan of the device. Furthermore, by defining the structural synergy between the multi-segment sidewalls and the insulating layer, the light extraction area is maximized while maintaining electrical performance and mechanical reliability, achieving higher luminous efficiency. This is of great significance for improving the performance of small-sized chips such as Micro LEDs. Attached Figure Description

[0016] Figure 1 A schematic diagram of the planar structure of the light-emitting diode provided in Embodiment 1;

[0017] Figure 2 A schematic diagram of the cross-sectional structure of the light-emitting diode provided in Embodiment 1;

[0018] Figure 3a and Figure 3b Two partially enlarged structural diagrams of the first through hole provided in Embodiment 1;

[0019] Figure 4a and Figure 4b This is a schematic diagram of two partially enlarged structures of the first through hole provided in Embodiment 2;

[0020] Figure 5This is a schematic diagram of the light-emitting device provided in Embodiment 3.

[0021] List of reference numerals in the attached diagram:

[0022] 100, Substrate; 200, Semiconductor stack; 201, First mesa; 202, Second mesa; 210, First semiconductor layer; 220, Active layer; 230, Second semiconductor layer; 300, Transparent conductive layer; 400, First insulating layer; 500, Second insulating layer; 610, First via; 620, Second via; 710, First electrode; 720, Second electrode;

[0023] 10. Light-emitting device; 101. Packaging substrate; 102. Light-emitting element. Detailed Implementation

[0024] This application provides a light-emitting diode, including:

[0025] Substrate;

[0026] A semiconductor stack is disposed on the substrate and includes a first semiconductor layer, an active layer and a second semiconductor layer stacked sequentially. The semiconductor stack has a first mesa exposing the first semiconductor layer and a second mesa exposing the second semiconductor layer.

[0027] An insulating structure is disposed above the semiconductor stack, comprising a first insulating layer and a second insulating layer stacked sequentially.

[0028] An electrode hole, penetrating the insulating structure, includes a first through hole located on the first platform and a second through hole located on the second platform; the first through hole has opposing top and bottom openings and a sidewall connecting the two; wherein,

[0029] The sidewall is a multi-segment structure with at least two different tilt angles, and the angle between the sidewall near the bottom opening and the horizontal direction is greater than the angle between the sidewall near the top opening and the horizontal direction. By adopting a multi-segment angle design with a gentler upper section and a steeper lower section for the sidewall of the first through hole, the contradiction between contact area and metal coverage in traditional single-angle sidewalls is overcome. The multi-segment sidewall can effectively disperse the internal stress caused by abrupt step changes during metal deposition, significantly improve the step coverage of the metal film in the hole, and avoid metal cracking or peeling off from the sidewall due to stress concentration, thereby greatly improving the long-term reliability of the electrode structure.

[0030] In some embodiments, the first insulating layer is a SiO2 material layer. The etching characteristics of this material layer have a good selectivity ratio with the underlying semiconductor layer and the upper DBR material, which is beneficial for precise control of the sidewall morphology of the first inclined segment.

[0031] In some embodiments, the second insulating layer is a distributed Bragg reflector structure. Covering the second mesa with a DBR as part of the insulating structure can efficiently reflect light emitted from inside the chip, reduce light absorption loss, and improve the light extraction efficiency of the Micro LED.

[0032] In some embodiments, the multi-segment structure includes a first inclined segment and a second inclined segment, the first inclined segment being closer to the bottom opening than the second inclined segment; the angle between the first inclined segment and the horizontal direction is α, 45°≤α≤75°, and the angle between the second inclined segment and the horizontal direction is β, 30°≤β≤55°. The steeper angle of the bottom first inclined segment ensures sufficient bottom contact area, while the upper second inclined segment provides a sufficiently gentle transition, ensuring uninterrupted continuous metal coverage without excessively sacrificing the reflective area of ​​the DBR.

[0033] In some embodiments, the electrode hole further includes a first blind hole on the first semiconductor layer; the first blind hole is located below the first through hole; the multi-segment structure further includes a fourth inclined segment located in the first blind hole, the fourth inclined segment being connected to the first inclined segment, and the depth of the fourth inclined segment being 30 nm to 50 nm.

[0034] In some embodiments, the slope of the fourth inclined segment is less than the slope of the first inclined segment, thereby increasing the contact area between the first electrode and the N semiconductor layer while ensuring the width of the opening at the bottom of the first inclined segment.

[0035] In some embodiments, the height of the first inclined segment is D1, the height of the second inclined segment is D2, and D1 < D2. The larger height of the upper second inclined segment provides a more gentle electrode deposition base, while preserving as much of the effective reflective area of ​​the insulation structure as possible.

[0036] In some implementations, 3 ≤ D2 / D1 ≤ 8 to achieve the optimal balance between increased contact area and stress relief effect.

[0037] In some embodiments, the total thickness of the insulating structure is between 4000 Å and 15000 Å. This thickness ensures the insulating structure's dielectric withstand capability and the optical thickness required for use as a DBR.

[0038] In some embodiments, the thickness of the first insulating layer is 500 Å to 4000 Å; and the thickness of the second insulating layer is 2000 Å to 10000 Å.

[0039] In some embodiments, the second inclined segment includes a sidewall of the second insulating layer and a portion of the sidewall of the first insulating layer that connects to the edge of the second insulating layer. That is, the second inclined segment is mainly composed of DBR material, the first inclined segment includes DBR material and SiO2 material, and the junction of the first inclined segment and the second inclined segment is located in the DBR material layer.

[0040] In some embodiments, the first inclined segment includes a sidewall of the first insulating layer and a portion of the sidewall of the second insulating layer that is in contact with the edge of the first insulating layer.

[0041] In some embodiments, the bottom opening width of the first through hole is W1, where W1 ≤ 8 μm; the top opening width of the first through hole is W2, where W2 ≤ 10 μm. Controlling the bottom opening W1 ≤ 8 μm to match the area of ​​the first platform, and controlling the top opening W2 ≤ 10 μm, can prevent the opening from being too large and thus losing the DBR reflective area, affecting the light extraction efficiency.

[0042] In some embodiments, in the top view of the light-emitting diode, the distance between the top opening edge of the first through hole and the edge of the first mesa is between 2 μm and 8 μm, and the distance between the bottom opening edge and the edge of the first mesa is between 3 μm and 10 μm.

[0043] In some embodiments, the number of the first through holes is one to three, and they are symmetrically distributed at the center or both sides of the first platform. The symmetrically distributed first through holes can optimize current spreading capability and antistatic capability.

[0044] In some embodiments, the angle between the sidewall of the second through hole and the horizontal direction is between 30° and 70°. The second through hole is located in a flat area with no significant height difference, resulting in a lower risk of metal cracking. The above-mentioned suitable angle design can effectively balance the contact area and the manufacturing difficulty.

[0045] This application also provides a light-emitting device, the light-emitting device comprising:

[0046] Packaging substrate;

[0047] At least one light-emitting diode (LED) is disposed on the surface of the encapsulation substrate, and the encapsulation substrate and the electrode structure of the LED are electrically connected; the LED is any of the LEDs provided in the above-described technical solutions. Light-emitting devices configured with the aforementioned LEDs have higher light output brightness, significantly improved product performance and lifespan, and can better meet the needs of Micro LED products.

[0048] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0049] The composition and dopants of each layer of the light-emitting diode in this application can be analyzed by any suitable method, such as secondary ion mass spectrometry (SIMS). The thickness of each layer of the light-emitting diode in this application can be analyzed by any suitable method, such as transmission electron microscopy (TEM) or scanning electron microscopy (SEM), in conjunction with, for example, the depth positions of each layer on a SIMS spectrum.

[0050] Example 1:

[0051] This embodiment provides a light-emitting diode (LED), see [link]. Figure 1 and Figure 2 The light-emitting diode includes a substrate 100, a semiconductor stack 200, a transparent conductive layer 300, a first insulating layer 400, a second insulating layer 500, and an electrode structure, etc. The projection of the light-emitting diode along its top view direction is a horizontal projection. The specific structure and technical solution of the light-emitting diode provided in this embodiment will be described in detail below.

[0052] See Figure 1 and Figure 2 The substrate 100 serves as the epitaxial growth substrate and can be made of a conductive, insulating, or light-transmitting material with excellent thermal conductivity, such as a sapphire substrate, silicon carbide substrate, gallium nitride substrate, zinc oxide substrate, gallium arsenide substrate, or silicon substrate, to meet different epitaxial growth requirements. In this embodiment, the substrate 100 is a surface-patterned sapphire substrate (PSS) to improve the epitaxial quality of the semiconductor stack 200 and facilitate efficient light emission from the semiconductor stack 200.

[0053] See also Figure 1 and Figure 2A semiconductor stack 200 is disposed on a substrate 100. The semiconductor stack 200 includes a first semiconductor layer 210, an active layer 220, and a second semiconductor layer 230 stacked sequentially. The first semiconductor layer 210 is composed of a III-V or II-VI compound semiconductor and is doped with N-type dopants such as Si, Ge, Sn, Se, or Te, and is an N-type semiconductor layer used to provide electrons for recombination light emission. The second semiconductor layer 230 is composed of a III-V or II-VI compound semiconductor and is doped with P-type dopants such as Mg, Zn, Ca, Sr, or Ba, and is a P-type semiconductor layer used to provide holes for recombination light emission. The active layer 220 can have any of the following structures, including but not limited to a single-well structure, a multi-well structure, a single quantum well structure, or a multi-quantum well structure, for electron and hole recombination light emission, such as at least one of InGaN / GaN, InGaN / InGaN, GaN / AlGaN, InAlGaN / GaN, GaAs(InGaAs) / AlGaAs, or GaP(InGaP) / AlGaP. The specific process includes etching the semiconductor stack 200 to obtain a first mesa 201 exposing the upper surface of the first semiconductor layer 210 and a second mesa 202 exposing the upper surface of the second semiconductor layer 230. The first mesa 201 provides a contactable area for the N-type electrode, and the top surface of the second mesa 202 is the surface of the second semiconductor layer 230, which is the main light-emitting surface of the LED chip. In the horizontal projection direction of the LED, the first platform 201 is located inside the second platform 202 or is partially surrounded by the second platform 202 and is lower than the second platform 202. Therefore, a stepped structure with a significant height difference is formed between the first platform 201 and the second platform 202. This height difference is the root cause of the difficulty in covering the metal of the subsequent N-type electrode hole. Therefore, this embodiment improves the problem of covering the metal material of the electrode hole by optimizing the sidewall structure of the electrode hole of the insulating structure.

[0054] See also Figure 1 and Figure 2 A transparent conductive layer 300 is disposed on the semiconductor stack 200, and the transparent conductive layer 300 is formed above the second mesa 202 to achieve higher current injection efficiency of the second semiconductor layer 230 and reduce light loss. The material of the transparent conductive layer 300 can be one or a combination of ITO (indium tin oxide), ZnO (zinc oxide), AZO (aluminum-doped zinc oxide), or IZO (indium zinc oxide). Further, the thickness of the transparent conductive layer 300 is between 5 nm and 50 nm.

[0055] See also Figure 1 and Figure 2A first insulating layer 400 is disposed above and on the sidewalls of the transparent conductive layer 300 and the semiconductor stack 200. The first insulating layer 400 includes SiO2, SiN, and SiO2. x N y The material is selected from at least one of TiO2, Si3N4, Al2O3, TiN, AlN, ZrO2, TiAlN, TiSiN, HfO, TaO2, and MgF2. Precision control of the etching process of the first insulating layer 400 is fundamental to achieving multi-segment sidewalls. As an example, the first insulating layer 400 is made of SiO2 with a thickness of 500 Å to 4000 Å. SiO2 has excellent step coverage capabilities, enabling the formation of a continuous, dense film on mesa sidewalls with varying elevations. It also effectively blocks moisture and oxygen penetration, ensuring the integrity of the insulating layer and the reliability of the chip quality. Furthermore, during subsequent dry etching to form electrode holes, the etching gas exhibits differentiated etching selectivity towards SiO2, the underlying GaN, and the upper DBR material. Therefore, a SiO2 layer of appropriate thickness allows for more precise control of the surface morphology and etching depth of the first inclined segment S1. Further, the thickness of the first insulating layer 400 is between 1000 Å and 2000 Å.

[0056] See also Figure 1 and Figure 2A second insulating layer 500 is disposed above the first insulating layer 400. The second insulating layer 500 is a distributed Bragg reflector structure, also known as a DBR layer. The DBR disposed above the second mesa 202 can efficiently reflect light emitted from inside the chip, reduce light absorption loss, and improve the light extraction efficiency of the Micro LED. The DBR structure includes several alternately stacked first material layers 501 and second material layers 502. The first material layer 501 or the second material layer 502 is one or more of SiO2, TiO2, NbO2, ZrO2, or Ta2O5. As an example, the first material layer 501 is a SiO2 layer, and the second material layer 502 is a TiO2 layer. In some embodiments, the second insulating layer 500 includes 4 to 15 pairs of alternately stacked material layer pairs, for example, 6, 8, 10, or 12 pairs of alternately stacked material layer pairs. In some embodiments, the thickness of a single layer of the first material layer 501 is between 10 nm and 100 nm; the thickness of a single layer of the second material layer 502 is between 10 nm and 100 nm; and the total thickness of the second insulating layer 500 is between 2000 Å and 10000 Å. A second insulating layer 500 of suitable thickness can achieve a reflectivity of over 98% for light emitted from the active layer 220, significantly improving light extraction efficiency. Furthermore, the second insulating layer 500, together with the first insulating layer 400, forms a complete insulating structure, preventing short circuits between electrodes. Further, the thickness of the second insulating layer 500 is between 4000 Å and 8000 Å. It is understood that the thickness of the insulating structure is positively correlated with its reflectivity, and a minimum thickness of 4000 Å for the second insulating layer 500 ensures that its minimum reflectivity meets the preset requirements. Further, the thickness of a single layer of both the first material layer 501 and the second material layer 502 is between 10 nm and 80 nm. The total thickness of the insulation structure ranges from 5000 Å to 10000 Å.

[0057] See Figure 1As shown in Figure 3, the first insulating layer 400 and the second insulating layer 500, stacked sequentially, together constitute an insulating structure. This insulating structure, as a whole, can be etched using photolithography and dry etching processes to form electrode holes that penetrate the entire structure, for subsequent deposition of electrode metal material. The electrode holes include a first through-hole 610 located on the first mesa 201 and a second through-hole 620 located on the second mesa 202, which are respectively an N-hole and a P-hole. This embodiment optimizes the sidewall structure of the first through hole 610, differentiating it from the sidewall design of the second through hole 620. Specifically, the first through hole 610 has a top opening and a bottom opening, as well as a sidewall connecting the two. The sidewall of the first through hole 610 can be regarded as a multi-segment structure with at least two different inclination angles. The angle between the sidewall near the bottom opening and the horizontal direction is greater than the angle between the sidewall near the top opening and the horizontal direction. That is, the sidewall near the bottom opening is steeper, and the sidewall near the top opening is gentler. By adopting a multi-segment angle design with a gentler top and a steeper bottom for the sidewall of the first through hole 610, the contradiction between contact area and metal coverage in the traditional single-angle sidewall is overcome.

[0058] See details Figure 3a Taking the two-segment sidewall structure with the inflection point of the sidewall slope in the second insulating layer 500 as an example, the two-segment sidewall with different slopes can effectively disperse the internal stress caused by the step change during metal deposition, improve the step coverage of the metal film in the hole, avoid the phenomenon of metal cracking or peeling off from the sidewall caused by stress concentration, and thus greatly improve the long-term reliability of the electrode structure.

[0059] See also Figure 3a The two-segment structure includes a first inclined segment S1 and a second inclined segment S2 that are connected. The first inclined segment S1 is closer to the bottom opening than the second inclined segment S2. The angle between the first inclined segment S1 and the horizontal direction is α, where 45°≤α≤75°, and the angle between the second inclined segment S2 and the horizontal direction is β, where 30°≤β≤55°.

[0060] The first inclined segment S1 is typically not less than 45° to ensure sufficient steepness. It is understandable that for Micro LEDs, their small size limits the area of ​​the first mesa 201. If the sidewall of the first inclined segment S1 is too gentle, the bottom opening width W1 of the through hole will be reduced at the bottom of the limited mesa, affecting the effective contact area of ​​the electrode material and causing an increase in contact resistance. The sidewall of the first inclined segment S1 should also not be too vertical, and its inclination is typically not higher than 75° to prevent the metal material from being difficult to effectively deposit at the bottom corner of the sidewall when the electrode structure is formed in the first through hole 610, resulting in discontinuous metal coverage. At the same time, steep sidewalls may also increase stress concentration and increase the risk of metal layer cracking.

[0061] The second inclined section S2 is typically no less than 30°. While ensuring a relatively gentle slope, it's crucial to avoid excessive expansion of the top opening width W2 of the first via 610. An excessively large top opening would result in a loss of effective reflective area in the upper distributed Bragg reflector layer, reducing the chip's light extraction efficiency. Simultaneously, as a stress buffer for metal deposition, the second inclined section S2 must provide a sufficiently gentle deposition surface; therefore, its inclination should not exceed 55°. A gentler sidewall enhances the step coverage of the metal material, achieving a smooth transition from the upper surface of the insulating structure to the first inclined section S1, effectively dispersing internal stress in the metal layer and preventing cracks from forming at the abrupt angle change at the junction of the two sections.

[0062] See details Figure 3b Taking a two-segment sidewall structure with the sidewall slope inflection point in the first insulating layer 400 as an example, this two-segment structure also includes a first inclined segment S1 and a second inclined segment S2 that are connected. The first inclined segment S1 is closer to the bottom opening than the second inclined segment S2. The angle between the first inclined segment S1 and the horizontal direction is α, 45°≤α≤75°, and the angle between the second inclined segment S2 and the horizontal direction is β, 30°≤β≤55°. By controlling the slope of the two inclined segments and the thickness ratio of the two inclined segments, the deposition quality of the metal electrode can be further improved.

[0063] Both of the aforementioned segmented sidewall structures can be achieved by adjusting parameters step-by-step during the dry etching process. Etching begins on the upper surface of the insulating structure. Appropriate process parameters are set for the SiO2 / TiO2 DBR structure. When the etching depth reaches the preset second tilted segment height D2, the etching parameters are adjusted in real time. For example, the power is increased or the gas ratio is adjusted to improve selectivity for SiO2, thereby creating a relatively steep sidewall angle until the first insulating layer 400 is completely penetrated and the etching stops at the upper surface of the first semiconductor layer 210, forming the first tilted segment S1. Precise process control ensures that α > β and that both have appropriate tilt angles. The steeper angle of the bottom first tilted segment S1 ensures sufficient bottom contact area, while the upper second tilted segment S2 provides a sufficiently smooth transition, ensuring continuous, unbroken metal coverage without excessively sacrificing the reflective area of ​​the DBR.

[0064] See Figure 3a and Figure 3b The first inclined segment S1 in the above two-segment structure also includes a fourth inclined segment S0 located below the first inclined segment S1. The fourth inclined segment is also part of the electrode hole. Its manufacturing process is similar to that of the two-segment structure. The difference is that when etching reaches the surface of the first semiconductor layer 210, the first semiconductor layer 210 is over-etched to a depth range of 30nm~50nm.

[0065] In some embodiments, the slope of the fourth inclined segment S0 may be the same as or different from that of the first inclined segment S1. That is, the angle between the sidewall of the fourth inclined segment S0 and the horizontal plane is equal to the angle α between the first inclined segment S1 and the horizontal plane. Alternatively, the angle between the sidewall of the fourth inclined segment S0 and the horizontal plane may be smaller than the angle α between the first inclined segment S1 and the horizontal plane. By setting the slope of the fourth inclined segment S0 to be smaller than the slope of the first inclined segment S1, the contact area between the first electrode and the N semiconductor layer is increased while maintaining the bottom opening width of the first inclined segment S1.

[0066] See also Figure 3a and Figure 3b The height of the first inclined segment S1 is D1, and the height of the second inclined segment S2 is D2, where D1 < D2. The height D1 of the first inclined segment is defined as the vertical distance from the lower surface of the first insulating layer 400 along the vertical direction to the junction of the first inclined segment S1 and the second inclined segment S2; the height D2 of the second inclined segment is defined as the vertical distance from the junction along the vertical direction to the upper surface of the second insulating layer 500. The larger height of the upper second inclined segment S2 provides a more gentle electrode deposition base, which helps to disperse the stress transmitted from the steeper section below, eliminating the risk of cracking or peeling of the metal material at the step transition due to stress concentration. The structure of the first inclined segment S1 is a key factor in determining the bottom opening width W1. Even though the height D1 of the first inclined segment is relatively small, its angle α is relatively large, thus allowing for a sufficiently large bottom opening to meet the low contact resistance requirement even with a relatively small D1. Meanwhile, the second inclined section S2 is a key area for relieving stress during metal deposition. The second inclined section has a larger height D2, which can provide a longer stress buffer section and stress release area. D2>D1 means that the electrode hole has a longer and gentler slope, providing a more sufficient adhesion area for the metal material, so that the metal material layer can cover the entire sidewall more evenly and stably.

[0067] In some embodiments, the height D0 of the fourth inclined segment S0 is D0 > D1 and D2 > D1. The purpose of the first inclined segment S1 is to minimize the ohmic contact resistance while ensuring good coverage of the electrode material. Due to its relatively steep sidewalls, a lower thickness can improve the ohmic contact area. The appropriate height D0 of the fourth inclined segment S0 can further enhance the bonding force between the electrode layer and the insulating structure and semiconductor stack 200.

[0068] See Figure 1As shown in Figure 3, the thickness of the second insulating layer 500 is between 4000 Å and 8000 Å, and the thickness of the first insulating layer 400 is between 1000 Å and 2000 Å. The sidewalls of the second insulating layer 500 form a second inclined segment S2 and extend downward to form the first inclined segment S1. That is, the second inclined segment S2 is mainly composed of DBR material, the first inclined segment S1 includes DBR material and SiO2 material, and the junction of the first inclined segment S1 and the second inclined segment S2 is located in the DBR material layer.

[0069] Furthermore, the ratio of the height D2 of the second inclined segment S2 to the height D1 of the first inclined segment S1 is between 3 and 8. This height ratio achieves a better balance between contact area and stress release. For products of different sizes or with multiple through holes, due to structural limitations, the relative dimensions of D1 and D2 can be flexibly designed by adjusting them according to actual needs and process capabilities. D2 / D1≥3 ensures that the gentle section has sufficient height, while D2 / D1≤8 prevents the steep section from being too short, making it difficult to form a bottom opening with a good sidewall morphology. Furthermore, the ratio of the height D2 of the second inclined segment S2 to the height D1 of the first inclined segment S1 can be designed in conjunction with its inclination angle. For example, when the angle α between the first inclined segment S1 and the horizontal plane is large, a higher D2 / D1 ratio can be used to compensate for the stress that the steep section may cause; when the angle α is small, a lower D2 / D1 ratio can be used.

[0070] In some embodiments, the total thickness of the insulation structure is 4000 Å to 15000 Å, which ensures the insulation withstand voltage capability of the insulation structure and the optical thickness required as a DBR. Further, the total thickness of the insulation structure is 5000 Å to 10000 Å. An insulation structure with a thickness of 8000 Å to 10000 Å will be used as an example below.

[0071] As an example, to ensure the quality and reliability of the metal layer, D2 / D1 can be designed to be relatively high, for example, D2 / D1≈7, where D1 is between 1100Å and 1150Å and D2 is between 7500Å and 8000Å. The control of the top opening in the aforementioned sidewall structure depends on a small β angle; gentler sections dominate to provide good metal coverage reliability and stress relief, while steeper sections are shorter but still form an effective ohmic contact area.

[0072] As an example, to achieve a balance between metallic coverage and bottom ohmic contact area, D2 / D1 can be designed with moderate parameters, such as D2 / D1≈5, where D1 is between 1300Å and 1350Å and D2 is between 6650Å and 6700Å. The aforementioned sidewall structure achieves a performance balance between good contact area and luminous efficacy.

[0073] As an example, to further optimize contact resistance, D2 / D1 can be designed with a lower ratio, such as D2 / D1≈3.2, where D1 is between 1800Å and 2200Å, and D2 is between 6000Å and 7000Å. This design allows for a moderate increase in the proportion of the steep bottom section to further optimize contact resistance while ensuring good deposition of the metal material, whereas the gentler section remains long enough to guarantee stress relief.

[0074] See Figure 3a and Figure 3b The bottom opening width of the first through-hole 610 is W1, where W1 ≤ 8 μm. Controlling the bottom opening width W1 ≤ 8 μm ensures it matches the area of ​​the first mesa. The top opening width of the first through-hole 610 is W2, where W2 ≤ 10 μm. Controlling the top aperture W2 ≤ 10 μm prevents excessively large openings that could reduce the DBR reflective area and affect light extraction efficiency. This proportional structure can be achieved by controlling the depth ratio of the two-step dry etching process. It is understood that for a circular hole, W1 is defined as the diameter; for other shapes, W1 can be defined as the equivalent diameter or minimum width. The values ​​of W1 and W2 directly affect the difficulty of controlling the sidewall morphology; therefore, the above size range is a prerequisite for ensuring a high aspect ratio through-hole sidewall angle. The size of Micro LED chips is typically in the tens of micrometers range, and the size of the first mesa 201 region where the first through-hole 610 is located is even more limited. An excessively small aperture limits the ohmic contact area and increases the processing difficulty, potentially leading to uncontrolled sidewall morphology. Limiting W1 to 8μm and W2 to 10μm ensures that the electrode aperture structure can be well positioned within the limited area of ​​the first mesa 201. For the bottom opening, increasing W1 to increase the bottom contact area is a direct way to reduce contact resistance. A bottom opening of close to 8μm already provides sufficient contact area, and further increasing it not only has limited marginal benefits in reducing contact resistance but also encroaches on the space of other structures. For the top opening, W2 directly determines the area of ​​the aperture in the insulating structure, especially in the DBR structure that serves as a reflective layer. An excessively large aperture will weaken the light reflection efficiency, resulting in a decrease in the emitted light brightness.

[0075] As an example, the first through hole 610 is a circular hole with a bottom opening W1≈3μm and a top opening W2≈5μm. This through hole structure can achieve a good balance between contact performance, optical loss and manufacturing difficulty.

[0076] As an example, the first via 610 is a circular hole with bottom openings W1≈8μm and W2≈10μm. This via structure is suitable for relatively large Micro LED chips.

[0077] As an example, the first through hole 610 is a circular hole with a bottom opening W1≈1.5μm and a top opening W2≈3μm. Although this through hole structure relatively ignores the increase in contact resistance, it greatly saves the area of ​​the first platform 201.

[0078] See Figure 1 As shown in Figure 3, in the top view of the LED, the distance d1 between the top opening edge of the first via 610 and the edge of the first mesa 201 is between 1 μm and 8 μm, and the distance d2 between the bottom opening edge and the edge of the first mesa 201 is between 2 μm and 10 μm. This appropriate spacing range ensures that a continuous and sufficiently wide insulating structure is maintained at the edge of the first mesa 201, effectively preventing short circuits caused by subsequently deposited electrode metal, which could lead to device failure. Furthermore, while ensuring structural quality, this spacing does not need to be excessive, leaving sufficient space for other structures such as vias within the mesa.

[0079] See Figure 1 As shown in Figure 3, the number of first vias 610 is 1 to 3, and they are symmetrically distributed at the center or both sides of the first mesa 201. The symmetrical distribution of the first vias 610 optimizes current spread capability and anti-static capability. The electrode hole sidewall scheme provided in this embodiment is adaptable to various hole shapes to meet the needs of different chip specifications. The bottom opening of the first via 610 is a combination of one or more of the following shapes: circular, elliptical, elongated, or polygonal with curved chamfers. The shape of its top opening is usually adapted to the bottom opening to form a good transition of the two-section sidewall structure, and can effectively avoid the electric field concentration at sharp corners, further improving the ESD capability of the device. When only one first via 610 is provided, the center of the hole is located at the center point or center line of the first mesa 201. When two or three first vias 610 are provided, the multiple holes are symmetrically distributed with respect to the axis of symmetry of the first mesa 201. For extremely small chips, such as those with a side length ≤ 15μm, the area of ​​the first mesa 201 is extremely limited, and the number of the first via 610 is preferably one. The current radiates from the center to the surrounding area, which can reduce the difficulty of the process to the greatest extent while satisfying the basic electrical contact.

[0080] See Figure 1 As shown in Figure 3, the angle between the sidewall of the second through-hole 620 and the horizontal direction provided in this embodiment is between 30° and 70°. The second through-hole 620 is located in a flat area above the second mesa 202, for example, above the transparent conductive layer, with no significant height difference, resulting in a lower risk of metal cracking. Therefore, its sidewall angle can focus more on ensuring sufficient contact area to reduce contact resistance. This appropriate angle design can effectively balance contact area and process difficulty. The sidewall morphology of the second through-hole 620 can be formed by selecting appropriate etching process parameters and performing a single dry etching process, directly etching a sidewall with an angle in the range of 30° to 70°.

[0081] See Figure 1 As shown in Figure 3, an electrode layer is formed on the upper surface of the insulating layer 400 and at the electrode holes. The electrode layer includes a first electrode 710 located at the first through hole 610 and a second electrode 720 located at the second through hole 620. The first electrode 710 is electrically connected to the first semiconductor layer 210, and the second electrode 720 is electrically connected to the second semiconductor layer 230 through the transparent conductive layer 300. The electrode layer material includes gold, germanium, beryllium, nickel, palladium, zinc, or alloys thereof. The first electrode 710 and the second electrode 720 can be metal layers or multilayer metal stacks with the same material and structure.

[0082] Example 2:

[0083] See Figure 1 Similar to Figure 4, this embodiment also provides a light-emitting diode (LED), which includes at least a substrate 100, a semiconductor stack 200, a transparent conductive layer 300, a first insulating layer 400, a second insulating layer 500, and an electrode structure. The similarities to Embodiment 1 will not be repeated here. Based on Embodiment 1, this embodiment further optimizes the first through-hole 610 into a three-segment structure to achieve better electrode coverage. The differences between the LED provided in this embodiment and Embodiment 1 will be described in detail below.

[0084] See Figure 4a and Figure 4b The insulating structure includes a first insulating layer 400 and a second insulating layer 500 stacked sequentially. As a whole, the insulating structure can be etched using photolithography and dry etching processes to form electrode holes that penetrate the entire structure for subsequent deposition of electrode metal material. The electrode holes include a first through-hole 610 located on the first mesa 201 and a second through-hole 620 located on the second mesa 203, i.e., an N-hole and a P-hole, respectively. This embodiment optimizes the sidewall structure of the first through hole 610, differentiating it from the sidewall design of the second through hole 620. Specifically, the first through hole 610 has a top opening and a bottom opening, as well as a sidewall connecting the two. The sidewall of the first through hole 610 can be regarded as a multi-segment structure with three different inclination angles. From the bottom opening to the top opening, the angle between the sidewall and the horizontal direction decreases sequentially. That is, the sidewall near the bottom opening is steeper, the inclination angle of the middle section is moderate, and the sidewall near the top opening is gentler. By adopting a three-segment angle design for the sidewall of the first through hole 610, the contradiction between contact area and metal coverage in the traditional single-angle sidewall is further overcome.

[0085] See details Figure 4aThe three-segment structure includes three connected inclined segments: a first inclined segment S1, a second inclined segment S2, and a third inclined segment S3. The first inclined segment S1 is closer to the bottom opening than the third inclined segment S3. The angle between the first inclined segment S1 and the horizontal direction is α, where 45°≤α≤75°; the angle between the second inclined segment S2 and the horizontal direction is β, where 35°≤β≤65°; and the angle between the third inclined segment S3 and the horizontal direction is γ, where 30°≤γ≤55°.

[0086] See details Figure 4b Taking a three-segment sidewall structure with the sidewall slope inflection point in the first insulating layer 400 as an example, this three-segment structure also includes a first inclined segment S1, a second inclined segment S2, and a third inclined segment S3 that are connected. The first inclined segment S1 is closer to the bottom opening than the third inclined segment S3. The angle between the first inclined segment S1 and the horizontal direction is α, 45°≤α≤75°; the angle between the second inclined segment S2 and the horizontal direction is β, 35°≤β≤65°; and the angle between the third inclined segment S3 and the horizontal direction is γ, 30°≤γ≤55°. By controlling the slope of the three inclined segments and the thickness ratio of the three inclined segments, the deposition quality of the metal electrode can be further improved.

[0087] The two segmented sidewall structures provided in this embodiment can also be achieved by controlling the etching selectivity under a single photomask, which will not be elaborated here.

[0088] See also Figure 4a and Figure 4b The first inclined segment S1 in the aforementioned three-segment structure also includes a fourth inclined segment S0 located below the first inclined segment S1. The fourth inclined segment S0 is also part of the electrode hole. Specifically, the electrode hole also includes a first blind hole on the first semiconductor layer 210, which is located below the first through hole. The three-segment structure also includes a fourth inclined segment S0 located in the first blind hole, which is connected to the first inclined segment S1. Its fabrication process is similar to that of the three-segment structure, except that when etching reaches the surface of the first semiconductor layer 210, the first semiconductor layer 210 is over-etched to a depth of 30nm to 50nm. The slope of the fourth inclined segment S0 may be the same as or different from that of the first inclined segment S1. For example, the slope of the fourth inclined segment S0 may be less than that of the first inclined segment S1, thereby increasing the contact area between the first electrode and the N semiconductor layer while ensuring the opening width at the bottom of the first inclined segment S1.

[0089] See also Figure 4a and Figure 4bThe thickness of the second insulating layer 500 is between 4000 Å and 8000 Å, and the thickness of the first insulating layer 400 is between 1000 Å and 2000 Å. The height of the first inclined segment S1 is D1, the height of the second inclined segment S2 is D2, and the height of the third inclined segment S3 is D3, wherein D2 + D3 > D1. The electrode hole has a longer, gentler slope, providing a more sufficient adhesion area for the metal material, allowing the metal material layer to cover the entire sidewall more uniformly and stably.

[0090] Example 3:

[0091] See Figure 5 This embodiment provides a light-emitting device 10, which is a flip-chip LED product, including a packaging substrate 101; at least one light-emitting element 102 disposed on the surface of the packaging substrate 101, and the packaging substrate 101 is electrically connected to the electrode structure of the light-emitting diode. The light-emitting element 102 is the light-emitting diode provided in Embodiment 1 or Embodiment 2. The light-emitting device configured with the above-mentioned light-emitting diode has good quality reliability and long service life, and can better meet the needs of Micro LED products.

[0092] In summary, the light-emitting diode and light-emitting device provided in this application have high industrial application value because they effectively overcome the various shortcomings of the prior art.

[0093] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A light emitting diode, characterized by, include: Substrate; A semiconductor stack is disposed on the substrate and includes a first semiconductor layer, an active layer and a second semiconductor layer stacked sequentially. The semiconductor stack has a first mesa exposing the first semiconductor layer and a second mesa exposing the second semiconductor layer. An insulating structure is disposed above the semiconductor stack, comprising a first insulating layer and a second insulating layer stacked sequentially. An electrode hole, penetrating the insulating structure, includes a first through hole located on the first platform and a second through hole located on the second platform; the first through hole has opposing top and bottom openings and a sidewall connecting the two; wherein, The sidewall is a multi-segment structure with at least two different tilt angles, and the angle between the sidewall near the bottom opening and the horizontal direction is greater than the angle between the sidewall near the top opening and the horizontal direction.

2. The light-emitting diode according to claim 1, characterized in that, The first insulating layer is a SiO2 material layer.

3. The light-emitting diode according to claim 1, characterized in that, The second insulating layer is a distributed Bragg reflection structure.

4. The light-emitting diode according to claim 1, characterized in that, The multi-segment structure includes a first inclined segment and a second inclined segment connected together. The first inclined segment is closer to the bottom opening than the second inclined segment. The angle between the first inclined segment and the horizontal direction is α, 45°≤α≤75°, and the angle between the second inclined segment and the horizontal direction is β, 30°≤β≤55°.

5. The light-emitting diode according to claim 4, characterized in that, The electrode hole also includes a first blind hole on the first semiconductor layer; the first blind hole is located below the first through hole; the multi-segment structure also includes a fourth inclined segment located in the first blind hole, the fourth inclined segment being connected to the first inclined segment, and the depth of the fourth inclined segment being 30nm to 50nm.

6. The light-emitting diode according to claim 5, characterized in that, The slope of the fourth inclined segment is less than the slope of the first inclined segment.

7. The light-emitting diode according to claim 4, characterized in that, The height of the first inclined segment is D1, the height of the second inclined segment is D2, and D1 < D2.

8. The light-emitting diode according to claim 7, characterized in that, 3≤D2 / D1≤8.

9. The light-emitting diode according to claim 1, characterized in that, The total thickness of the insulating structure is between 4000 Å and 15000 Å.

10. The light-emitting diode according to claim 1, characterized in that, The thickness of the first insulating layer is 500 Å to 4000 Å; the thickness of the second insulating layer is 2000 Å to 10000 Å.

11. The light-emitting diode according to claim 1, characterized in that, The second inclined segment includes the sidewall of the second insulating layer and the portion of the sidewall of the first insulating layer that is connected to the edge of the second insulating layer.

12. The light-emitting diode according to claim 1, characterized in that, The first inclined segment includes the sidewall of the first insulating layer and the portion of the sidewall of the second insulating layer that is connected to the edge of the first insulating layer.

13. The light-emitting diode according to claim 1, characterized in that, The bottom opening width of the first through hole is W1, where W1 ≤ 8 μm; the top opening width of the first through hole is W2, where W2 ≤ 10 μm.

14. The light-emitting diode according to claim 1, characterized in that, In the top view of the light-emitting diode, the distance between the top opening edge of the first through hole and the edge of the first mesa is between 1 μm and 8 μm, and the distance between the bottom opening edge and the edge of the first mesa is between 2 μm and 10 μm.

15. The light-emitting diode according to claim 1, characterized in that, The angle between the sidewall of the second through hole and the horizontal direction is between 30° and 70°.

16. A light-emitting device, characterized in that, The light-emitting device includes: Packaging substrate; At least one light-emitting diode is disposed on the surface of the packaging substrate, and the packaging substrate and the electrode structure of the light-emitting diode are electrically connected; the light-emitting diode is the light-emitting diode according to any one of claims 1 to 15.

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