Deep trench isolation structure, method of manufacturing the same, and semiconductor device

Abstract

This invention provides a deep trench isolation structure, its fabrication method, and a semiconductor device. After forming a shallow trench in a substrate, a stress compensation structure is filled within the shallow trench. A deep trench is then formed within the stress compensation structure and the substrate. Finally, an isolation layer is filled within the deep trench. The substrate and isolation layer are then thermally annealed to form the deep trench isolation structure. Because the stress compensation structure has opposite thermal expansion characteristics to the substrate, during the thermal annealing process, when the substrate contracts and tears the isolation layer due to temperature changes, the stress compensation structure expands. Since the stress compensation structure is located within the shallow trench, the stress compensation structure and the substrate form a complementary thermal expansion structure in the region near the isolation layer surface, reducing the thermal stress on the isolation layer surface and effectively suppressing cracks on the isolation layer surface.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a deep trench isolation structure, its fabrication method, and a semiconductor device. Background Technology

[0002] Deep trench isolation (DTI) is widely used in high-voltage SOI BCD (Bipolar-CMOS-DMOS) technology due to its excellent isolation capabilities. By introducing DTI, high-voltage devices in BCD can be physically separated from low-voltage devices, preventing high-voltage breakdown or leakage. At the same time, the synergistic effect of DTI and SOI can block substrate current and parasitic transistor effects.

[0003] However, during the fabrication of deep trench isolation structures using existing processes, cracks can easily form in the filler material within the deep trenches, and these cracks may extend to the surface of the filler material, thereby affecting the electrical performance of the fabricated device. Summary of the Invention

[0004] The technical problem solved by this invention is how to effectively suppress cracking on the surface of the filler material in the deep trench isolation structure during the preparation of the deep trench isolation structure.

[0005] To solve the above technical problems, the present invention provides a method for preparing a deep trench isolation structure, the method comprising: Provide a base; The substrate is etched to form shallow trenches; The shallow trench is filled with stress-compensating material to form a stress-compensating structure, wherein the thermal expansion characteristics of the stress-compensating material are opposite to those of the substrate. A deep trench is formed within the stress compensation structure, the deep trench penetrating the stress compensation structure and extending into the substrate; An insulating layer is filled into the deep trench; The substrate having the stress compensation structure and the isolation layer is subjected to rapid thermal annealing to form a deep trench isolation structure.

[0006] Optionally, forming shallow trenches on the substrate surface includes: A buffer layer and a hard mask layer are sequentially formed on the surface of the substrate; A patterned first photomask layer is formed on the surface of the hard mask layer. The first photomask layer includes a shallow trench etching region and a blocking region. Using the patterned first photolithographic mask layer as a mask, the hard mask layer, the buffer layer, and the substrate within the shallow trench etching area are etched sequentially to form a shallow trench.

[0007] Optionally, the stress-compensating material fills the shallow trench before the deep trench is formed.

[0008] Optionally, before forming the deep trench, the stress compensation material is partially filled into the shallow trench, the surface of the stress compensation structure is lower than the surface of the substrate, and a portion of the sidewalls of the shallow trench are exposed, and the deep trench communicates with the shallow trench.

[0009] Optionally, the thickness of the stress compensation structure is at least 20% of the shallow trench depth.

[0010] Optionally, an insulating layer is filled within the deep trench, specifically including: An isolation layer is filled in the shallow trench and the deep trench in which the stress compensation structure is formed, and the upper surface of the isolation layer is flush with the opening of the shallow trench.

[0011] Optionally, the stress compensation material includes ZrW 2-x Mo x O8, x equals 0~2.

[0012] Optionally, the projection of the deep trench is located in the central region of the projection of the shallow trench, the depth of the deep trench is greater than the depth of the shallow trench, and the cross-sectional diameter of the deep trench is smaller than the cross-sectional diameter of the shallow trench.

[0013] The technical solution of the present invention also provides a deep trench isolation structure, which is prepared by the above-described method for preparing a deep trench isolation structure.

[0014] The present invention also provides a semiconductor device, including a substrate and at least two semiconductor elements spaced apart on the substrate and the aforementioned deep trench isolation structure, wherein the deep trench isolation structure is used to isolate the semiconductor elements.

[0015] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: The method for preparing a deep trench isolation structure provided by the present invention involves forming a shallow trench in a substrate, filling the shallow trench with a stress compensation structure, forming a deep trench within the stress compensation structure and the substrate, and finally filling the deep trench with an isolation layer. The substrate and the isolation layer are then thermally annealed to form the deep trench isolation structure. Because the portion of the isolation layer near the substrate surface within the deep trench is formed within the stress compensation structure, and the stress compensation structure has thermal expansion characteristics opposite to those of the substrate, during the thermal annealing process, when the substrate contracts and tears the isolation layer due to temperature changes, the stress compensation structure expands instead. Therefore, the stress compensation structure and the substrate form a complementary thermal expansion structure in the region near the isolation layer surface, reducing the thermal stress on the isolation layer surface and effectively suppressing cracks on the isolation layer surface. Attached Figure Description

[0016] Figure 1 A cross-sectional schematic diagram of a deep trench isolation structure; Figure 2 A photograph of a deep trench isolation structure with cracks. Figures 3 to 8 These are schematic cross-sectional views of the preparation method of the deep trench isolation structure provided in an embodiment of the present invention, corresponding to each step. Figures 9 to 12 These are schematic cross-sectional views of the preparation method of the deep trench isolation structure provided in another embodiment of the present invention, corresponding to each step.

[0017] Figure label: 200, 300 - bottom silicon layer; 201, 301 - Buried Oxygen Layer; 202, 302 - Top silicon layer; 203, 303 - Buffer layer; 204, 304 - hard mask layer; 205, 305 - Shallow groove; 206, 306 - Stress compensation structure; 207, 307 - Deep trench; 208, 308 - Isolation layer. Detailed Implementation

[0018] As described in the background art, during the process of fabricating a deep trench isolation structure using existing processes, cracks can easily form in the isolation layer within the deep trench, and these cracks may penetrate to the surface of the filler, thereby affecting the electrical performance of the fabricated device.

[0019] Please refer to Figure 1Since the material of the isolation layer 108 filling the deep trenches 107 and shallow trenches 106 is usually silicon dioxide, while the material of the top silicon layer 103 is usually silicon, during the thermal annealing process of the isolation layer 108 and the top silicon layer 103, the isolation layer 108 may be subjected to tensile stress caused by the shrinkage of the top silicon layer 103, which may result in cracks penetrating to the surface of the isolation layer 108. Figure 2 As shown.

[0020] In addition, it may be due to unavoidable non-uniform internal stress caused by the excessively large wafer size, which tore the isolation layer 108 during the hot annealing process.

[0021] The crack may store chemicals used in subsequent processes, such as wet etching solutions. When the crack fills and these chemicals overflow, they can spread to the surfaces of other functional structures in the semiconductor device, causing damage to those structures. This can affect the electrical performance of the final device and even contaminate the production line, resulting in significant losses.

[0022] In view of this, the technical solution of the present invention provides a novel method for preparing a deep trench isolation structure. After forming a shallow trench in a substrate, a stress compensation structure is filled within the shallow trench. A deep trench is then formed within the stress compensation structure and the substrate. Finally, an isolation layer is filled within the deep trench, and the substrate and the isolation layer are thermally annealed to form the deep trench isolation structure. Since the portion of the isolation layer near the substrate surface within the deep trench is formed within the stress compensation structure, and the stress compensation structure has thermal expansion characteristics opposite to those of the substrate, during the thermal annealing process, when the substrate contracts and tears the isolation layer due to temperature changes, the stress compensation structure expands instead. Therefore, the stress compensation structure and the substrate form a thermal expansion complementary structure in the region of the isolation layer near the substrate surface, reducing the thermal stress on the isolation layer surface and effectively suppressing cracks on the isolation layer surface. Furthermore, because the substrate material is relatively fixed, selecting the appropriate material for the stress compensation structure based on the substrate material is sufficient to effectively suppress cracks on the isolation layer surface, thereby significantly reducing the R&D and design costs for crack suppression and achieving a good suppression effect.

[0023] To make the above-mentioned objectives, features, and beneficial effects of the present invention more apparent and understandable, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus. Additionally, directional terms such as above, below, up, down, upward, downward, left, right, etc., are used relative to exemplary embodiments as they are shown in the figures, with upward or upper directions pointing towards the top of the corresponding figure and downward or lower directions pointing towards the bottom of the corresponding figure.

[0025] Please refer to Figures 3 to 12 This embodiment provides a method for fabricating a deep trench isolation structure, which specifically includes the following steps: S110: Provides a substrate, such as Figure 3 As shown.

[0026] The specific structure of the substrate is not limited in this application; examples include silicon substrates commonly used in semiconductors, and other substrates such as... Figure 3 The SOI substrate shown in this embodiment of the application uses an SOI substrate, comprising a bottom silicon layer 200, a buried oxide layer 201, and a top silicon layer 202 stacked sequentially. Electrical isolation between the bottom silicon layer 200 and the top silicon layer 202 is achieved by introducing the buried oxide layer 201 between them. The bottom silicon layer 200 serves as a support layer, while various semiconductor devices are fabricated on the top silicon layer 202. Due to the isolation provided by the buried oxide layer 201, the parasitic capacitance between semiconductor devices can be significantly reduced, dynamic power consumption and leakage current can be lowered, and the signal transmission efficiency of the semiconductor device can be improved. Furthermore, in subsequent processes, shallow trenches 205 are fabricated within the top silicon layer 202, and deep trenches 207 penetrate the top silicon layer 202 and communicate with the buried oxide layer 201.

[0027] S120: Etching the substrate to form shallow trenches 205, such as Figure 4 As shown.

[0028] In some specific embodiments, the step of etching the substrate to form shallow trenches 205 specifically includes S121 to S122: S121: Provide a substrate, and sequentially form a buffer layer 203 and a hard mask layer 204 on the surface of the substrate, continuing as follows Figure 3 As shown.

[0029] In some specific embodiments, the buffer layer 203 is used to alleviate thermal stress in subsequent layer stacking and protect the surface of the substrate. The buffer layer 203 may be made of silicon dioxide and has a thickness typically between a few nanometers and tens of nanometers. This layer is located between the substrate and the hard mask layer 204, serving as a stress buffer and adhesion layer between the substrate and the hard mask layer 204. The hard mask layer 204 serves as a hard mask for the shallow trench 205 etching and provides a polishing stop reference for subsequent polishing processes. The hard mask layer 204 may be made of silicon nitride or polysilicon and has a thickness typically between tens and hundreds of nanometers, exhibiting good etching resistance. Patterns are subsequently defined on the hard mask layer 204 through photolithography and etching.

[0030] S122: A patterned first photomask layer is formed on the surface of the hard mask layer 204. The first photomask layer includes a shallow trench etching region and a blocking region. Using the patterned first photomask layer as a mask, the hard mask layer 204, the buffer layer 203, and the top silicon layer 202 within the shallow trench etching region are sequentially etched to form a shallow trench 205. After forming the shallow trench 205, the first photomask layer is removed. If the substrate is an SOI substrate, the shallow trench 205 is formed within the top silicon layer 202, and the depth of the shallow trench 205 is less than the thickness of the top silicon layer 202 of the SOI substrate.

[0031] In some specific embodiments, the shallow trench 205 may be in the shape of an inverted trapezoid or a square, and no limitation is made here. The depth of the shallow trench 205 can be adjusted according to the actual situation to work with the material of the stress compensation structure subsequently prepared to adjust the stress, and no limitation is made here.

[0032] Optionally, the depth of the shallow trench 205 is between 0.2 and 0.5 micrometers. If the substrate is an SOI substrate, the shallow trench 205 is formed within the top silicon layer 202, and the depth of the shallow trench 205 is less than the thickness of the top silicon layer 202 of the SOI substrate. Due to the different stresses caused by different wafers and processes, the depth of the shallow trench can be adjusted according to the actual situation, and the stress can be adjusted together with the filler composition and the retained thickness. No limitation is made here.

[0033] S130: Stress-compensating material is filled into the shallow trench 205 to form a stress-compensating structure 206. The thermal expansion characteristics of the stress-compensating material are opposite to those of the substrate. Figure 5 As shown.

[0034] In some specific embodiments, the material of the stress compensation structure 206 includes ZrW. 2-x Mo x O8, x equals 0~2.

[0035] Furthermore, if x equals 0, the material of the stress compensation structure 206 is ZrW₂O₈. If x equals 1, the material of the stress compensation structure 206 is ZrWMoO₈. If x equals 2, the material of the stress compensation structure 206 is ZrMo₂O₈. This can be understood as controlling the coefficient of thermal expansion by adjusting the content of Mo and W. See Table 1 for details.

[0036] Table 1. Characterization of the basis and ZrW at different x values 2-x Mo x The coefficient of thermal expansion of O8.

[0037]

[0038] Of course, the material of the stress compensation structure 206 can also be other materials with thermal expansion characteristics opposite to those of the substrate, and this is not limited here. If the substrate is an SOI substrate, the thermal expansion characteristics of the material of the stress compensation structure 206 are opposite to those of the top silicon layer 202.

[0039] In this embodiment, in some specific implementations, before forming the deep trench, the shallow trench 205 is filled with stress compensation structure 206. Specifically, stress compensation material is deposited in the shallow trench 205 and on the surface of the hard mask layer 204, and then... Figure 5 As shown. After depositing the stress compensation material, the stress compensation material is ground to make its surface flush with the surface of the hard mask layer 204, thereby forming the stress compensation structure 206. Further, the grinding process of the stress compensation material may include chemical mechanical polishing.

[0040] Please refer to Figure 9 In another specific embodiment, the shallow trench 305 is partially filled with the stress compensation material, the surface of the stress compensation structure 306 is lower than the surface of the substrate and exposes part of the sidewall of the shallow trench 305, and the deep trench 307 communicates with the shallow trench 305.

[0041] Specifically, the shallow trench 205 is filled with stress compensation material, and the stress compensation material is etched to expose part of the sidewalls of the shallow trench 305, thereby forming the stress compensation structure 306. This allows for adjustment of the layer thickness of the stress compensation structure 306 to meet the stress compensation requirements of different applications. In some specific embodiments, a patterned second photomask layer is formed on the surface of the hard mask layer 304. Using the patterned second photomask layer as a mask, the stress compensation material is etched to expose part of the sidewalls of the shallow trench 305, thereby forming the stress compensation structure 306. The photomask used for the second photomask layer is the same as that used for the first photomask layer. Alternatively, a photomask and a second photomask layer can be omitted, and the hard mask layer 304 can be used as a barrier layer to etch the stress compensation material to adjust the layer thickness of the stress compensation structure 306. The etching parameters are not limited here, and those skilled in the art can select them according to specific circumstances. In another specific embodiment, a wet etching process can be used to etch the stress compensation structure to adjust the layer thickness of the stress compensation structure 306. The etching solution is selected to have a high selectivity for the stress compensation material and the hard mask layer 304 to ensure that the hard mask layer is not damaged when etching the stress compensation material. Those skilled in the art can make the selection according to the specific actual situation, and no limitation is made here.

[0042] Preferably, the thickness of the stress compensation structure 306 is at least 20% of the depth of the shallow groove 305. The depth of the shallow groove 305 can be adjusted according to the actual situation to work together with the material of the stress compensation structure 306 and the reserved thickness to adjust the stress. No limitation is made here.

[0043] S140: A deep trench 207 is formed within the stress compensation structure 206, the deep trench 207 penetrating the stress compensation structure 206 and extending into the substrate, such as... Figure 6 As shown.

[0044] In some specific embodiments, the process of forming a deep trench within the stress compensation structure specifically includes: forming a patterned photomask layer (not shown) with an opening on the stress compensation structure and a hard mask layer. In the vertical projection direction, the projection of the patterned opening is located within the projection of the stress compensation structure 206. The patterned photomask layer serves as a hard mask, and the stress compensation structure 206 and the substrate are sequentially etched to form a deep trench 207. The deep trench 207 penetrates the stress compensation structure 206 and extends into the substrate below the stress compensation structure 206. If the substrate is an SOI substrate, the deep trench 207 penetrates the stress compensation structure 206 and the top silicon layer 202 of the SOI substrate, and the bottom of the deep trench 207 exposes the buried oxide layer 201 of the SOI substrate.

[0045] In this embodiment, reactive ion etching or deep reactive ion etching technology is used to etch the stress compensation structure and the substrate downward through patterned openings located on the surface of the stress compensation structure.

[0046] Specifically, deep reactive ion etching (DRIE) processes achieve high aspect ratio vertical deep trenches 207 by alternating etching and passivation steps. The depth of the deep trenches 207 can reach several micrometers or even tens of micrometers.

[0047] In this embodiment, the projection of the deep trench is located in the central region of the projection of the shallow trench. The depth of the deep trench is greater than the depth of the shallow trench, and the cross-sectional diameter of the deep trench is smaller than the cross-sectional diameter of the shallow trench. In this embodiment, the projection of the deep trench 207 is located in the central region of the projection of the shallow trench 205 to improve isolation performance and filling effect, ensuring that all parts of the deep trench isolation structure can receive equal thermal expansion compensation from the stress compensation structure 206 during the subsequent rapid hot annealing process, thereby avoiding cracks in the deep trench isolation structure. Simultaneously, having the projection of the deep trench 207 within the projection of the shallow trench 205 also reduces process development difficulty and fully utilizes the shallow trench process.

[0048] Preferably, the ratio of the outer diameter of the shallow trench to the diameter of the deep trench is greater than 2, which ensures the degree of thermal expansion compensation of the deep trench isolation structure by the stress compensation structure 206. Since the expansion / contraction of the stress compensation structure 206 is closely related to its volume, a smaller ratio of the outer diameter of the shallow trench 205 to the diameter of the deep trench 207 results in a smaller volume of the stress compensation structure 206. During subsequent rapid thermal annealing, when the substrate shrinks and stretches the deep trench isolation structure, the expansion compensation generated by the stress compensation structure 206 may not be sufficient to effectively offset the stress generated during the thermal annealing process, potentially leading to the formation and propagation of cracks in the deep trench isolation structure. Conversely, a larger ratio of the outer diameter of the shallow trench 205 to the diameter of the deep trench 207 increases the chip size and reduces the chip's integration density. It should be noted that this application does not impose any restrictions on the ratio of the outer diameter of the shallow trench 205 to the diameter of the deep trench 207; adjustments can be made according to actual needs to effectively suppress crack formation caused by thermal stress in the deep trench isolation structure during subsequent processes.

[0049] S150: Fill the deep trench with an isolation layer.

[0050] In this design, the upper surface of the isolation layer 208 is flush with the opening of the shallow trench 205. The isolation layer 208, filling the deep trench 207, serves as the primary isolation component for the isolated semiconductor element. Figure 7 As shown.

[0051] Please refer to Figure 10-11 ,exist Figure 9 In the corresponding embodiment, with Figure 7 Corresponding to the preparation method shown, an isolation layer 308 is filled in the shallow trench 305 and deep trench 307 where the stress compensation structure 306 is formed. The upper surface of the isolation layer 308 is flush with the opening of the shallow trench 305 to improve the flatness of the wafer and ensure the accuracy of subsequent processes.

[0052] In this embodiment, the isolation layer is made of an insulating material. The isolation layer in this embodiment is made of silicon dioxide. Silicon dioxide has good insulation, thermal stability and good interface characteristics with silicon substrate, and is easy to form by chemical vapor deposition, etc., which makes the deep trench isolation structure have good isolation effect and good stability, and is also relatively easy to form.

[0053] Furthermore, since the isolation layer and the buried oxide layer 201 are made of the same material, the isolation layer and the buried oxide layer 201 are connected to form a full-dielectric isolation.

[0054] In this embodiment, the process of filling the isolation layer in the deep trench specifically includes: depositing an isolation layer material on the surface of the top silicon layer 202 and in the deep trench. After depositing the isolation layer material, the isolation layer material is chemically and mechanically polished to make the surface of the isolation layer material flush with the surface of the hard mask layer, thereby forming the isolation layer.

[0055] S160: The substrate on which the stress compensation structure and the isolation layer are formed is subjected to rapid thermal annealing to form a deep trench isolation structure.

[0056] In this embodiment, the stress compensation structure 206 is made of ZrW2O8 or ZrMo2O8, which has thermal expansion characteristics opposite to those of the top silicon layer 202. Therefore, during the thermal annealing process of the top silicon layer 202 and the isolation layer 208, when the top silicon layer 202 contracts due to temperature changes and stretches the isolation layer 208, the stress compensation structure 206 will instead expand. Furthermore, since the stress compensation structure is located within the shallow trench 205, the stress compensation structure 206 and the top silicon layer 202 form a thermal expansion complementary structure in the region adjacent to the surface of the isolation layer 208. This reduces the thermal stress on the surface of the isolation layer 208, effectively suppressing cracks on the surface of the isolation layer 208. This avoids a series of problems caused by cracks on the surface of the isolation layer 208, such as electrical performance deviation and production line contamination, ultimately ensuring the yield and reliability of the device.

[0057] Since the material of the top silicon layer 202 is relatively fixed, the cracks on the surface of the isolation layer 208 can be effectively suppressed simply by selecting the material of the corresponding stress compensation structure 206 based on the material of the top silicon layer 202. This greatly reduces the R&D and design costs of crack suppression and provides a good suppression effect. Furthermore, the stress magnitude can be adjusted by regulating the material composition ratio, offering excellent flexibility.

[0058] Please refer to Figure 8 After thermal annealing the top silicon layer 202 and the isolation layer 208, the hard mask layer 204 and the buffer layer 203 are etched away so that the upper surface of the isolation layer 208 and the upper surface of the stress compensation structure 206 are both higher than the upper surface of the top silicon layer 202, thereby minimizing the risk of short circuits caused by residual polysilicon at the edge of the active region during subsequent polysilicon gate etching steps.

[0059] Please refer to Figure 12 ,exist Figure 9 In the corresponding embodiment, with Figure 8 Corresponding to the fabrication method shown, after thermal annealing the top silicon layer 302 and the isolation layer 308, the hard mask layer 304 and the buffer layer 303 are etched away so that the upper surface of the isolation layer 308 is higher than the upper surface of the top silicon layer 302, thereby minimizing the possibility of short circuits caused by residual polysilicon at the edge of the active region during subsequent polysilicon gate etching steps.

[0060] Please continue to refer to this. Figure 8 This embodiment also provides a deep trench isolation structure, which is prepared by the above-described method for preparing a deep trench isolation structure. It further includes: a substrate, a shallow trench formed on the top of the substrate, a stress compensation structure 206 completely filled in the shallow trench, a deep trench penetrating through the stress compensation structure 206 and extending into the substrate below the stress compensation structure 206, and an isolation layer 208 filled in the deep trench 207.

[0061] Please refer to Figure 12 In another specific embodiment, when the stress compensation structure 306 is partially filled in the shallow trench, both the deep trench and the shallow trench without the stress compensation structure are filled with an isolation layer. Since the structure and beneficial effects of the deep trench isolation structure have been described in detail in the foregoing embodiments, they will not be repeated here.

[0062] This application also provides a semiconductor device, including a substrate, at least two semiconductor elements spaced apart on the substrate, and the aforementioned deep trench isolation structure, which is used to isolate the semiconductor elements. Since the structure and beneficial effects of the deep trench isolation structure have been described in detail in the foregoing embodiments, they will not be repeated here.

[0063] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for preparing a deep trench isolation structure, characterized in that, The method includes: Provide a base; The substrate is etched to form shallow trenches; The shallow trench is filled with stress-compensating material to form a stress-compensating structure, wherein the thermal expansion characteristics of the stress-compensating material are opposite to those of the substrate. A deep trench is formed within the stress compensation structure, the deep trench penetrating the stress compensation structure and extending into the substrate; An insulating layer is filled into the deep trench; The substrate on which the stress compensation structure and the isolation layer are formed is subjected to rapid thermal annealing to form a deep trench isolation structure.

2. The method for preparing the deep trench isolation structure according to claim 1, characterized in that, Etching the substrate to form shallow trenches includes: A buffer layer and a hard mask layer are sequentially formed on the surface of the substrate; A patterned first photomask layer is formed on the surface of the hard mask layer. The first photomask layer includes a shallow trench etching region and a blocking region. Using the patterned first photolithographic mask layer as a mask, the hard mask layer, the buffer layer, and the substrate within the shallow trench etching area are etched sequentially to form a shallow trench.

3. The method for preparing the deep trench isolation structure according to claim 1, characterized in that, Before the deep trench is formed, the stress-compensating material fills the shallow trench.

4. The method for preparing the deep trench isolation structure according to claim 1, characterized in that, Before forming the deep trench, the stress compensation material is partially filled into the shallow trench. The surface of the stress compensation structure is lower than the surface of the substrate and exposes part of the sidewalls of the shallow trench. The deep trench communicates with the shallow trench.

5. The method for preparing the deep trench isolation structure according to claim 4, characterized in that, The thickness of the stress compensation structure is at least 20% of the depth of the shallow trench.

6. The method for preparing the deep trench isolation structure according to claim 4, characterized in that, The filling of the isolation layer within the deep trench specifically includes: An isolation layer is filled in the shallow trench and the deep trench in which the stress compensation structure is formed, and the upper surface of the isolation layer is flush with the opening of the shallow trench.

7. The method for preparing the deep trench isolation structure according to any one of claims 1 to 6, characterized in that, The stress compensation material includes ZrW 2-x Mo x O8, x equals 0~2.

8. The method for preparing the deep trench isolation structure according to claim 1, characterized in that, The projection of the deep trench is located in the central region of the projection of the shallow trench, the depth of the deep trench is greater than the depth of the shallow trench, and the cross-sectional diameter of the deep trench is smaller than the cross-sectional diameter of the shallow trench.

9. A deep trench isolation structure, characterized in that, The deep trench isolation structure is prepared by the method described in any one of claims 1 to 8.

10. A semiconductor device, characterized in that, The invention includes a substrate and at least two semiconductor elements spaced apart on the substrate, and the deep trench isolation structure of claim 9, wherein the deep trench isolation structure is used to isolate the semiconductor elements.

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