Method for manufacturing small capacity embedded flash memory of 90 nm or more

Abstract

The present invention relates to a method for manufacturing a small capacity embedded flash memory of 90nm or above, which comprises a memory array region and a peripheral logic region on a substrate, wherein the memory array region comprises at least one memory cell, which comprises a stacked gate, the stacked gate comprising a floating gate and a control gate vertically stacked above the floating gate, and a floating gate gate oxide layer between the floating gate and the substrate; the logic region comprises at least one 5V high voltage logic transistor, which comprises a high voltage logic gate and a high voltage logic gate oxide layer below the high voltage logic gate; the method for manufacturing the small capacity embedded flash memory of 90nm or above comprises the following steps: forming the floating gate gate oxide layer and the high voltage logic gate oxide layer simultaneously in the same process, and the thicknesses of the two layers are equal. The method has less manufacturing processes, can reduce the cost and improve the efficiency, and the flash memory manufactured by the method has excellent performance.

Description

Technical Field

[0001] This invention relates to a method for fabricating embedded flash memory with a wavelength of 90nm or larger, and more particularly to a method for fabricating small-capacity embedded flash memory with a wavelength of 90nm or larger. Background Technology

[0002] Embedded flash memory (eFlash) is used in widely applied electronic products such as microcontrollers (MCUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), and programmable logic devices (PLDs). Compared with traditional EEPROM solutions, embedded flash memory has advantages such as fast read and write speeds, small size, and low power consumption, and is widely used in current Internet of Things (IoT) and automotive electronics. Small-capacity embedded flash memory (8KB to 4MB storage capacity) has the most applications, mainly in read-heavy, write-light, miniaturized, and high-reliability scenarios. Its largest application markets are IoT and wireless sensing, consumer portable wearable electronics, home appliance main control MCUs, automotive small controllers, industrial control & instrumentation, security identification and payment chips, and small medical devices.

[0003] In embedded flash memory solutions, floating gate-based structures are predominantly used. A common embedded flash memory structure includes a stacked gate, where a control gate is vertically stacked on top of the floating gate and surrounds its side surface. The floating gate is coupled to a potential from the control gate for programming and erasing operations. This structure is simple and easy to fabricate. For example, NXP Semiconductors in the Netherlands produces a dual-transistor (2T) structure with two select gates (SG) and two stacked gates in the memory cell. The two select gates are positioned on either side of the stacked gates, and the memory cell structure is left-right mirror symmetrical. In the stacked gate, the control gate (CG) is stacked on top of the floating gate (FG). Its structure is even simpler and more compact. Programming uses the Fowler-Nordheim method, where electrons are injected into the floating gate from the channel or source in the substrate below the stacked gate. During erasing, electrons tunnel through the gate oxide layer back to the channel or source below the floating gate.

[0004] Small-capacity embedded flash memory often adopts this structure. However, the fabrication process of small-capacity embedded flash memory still has some problems. One prominent issue is the large number of masks used, making it impossible to reduce the cost of fixed masks. Traditional floating-gate embedded flash memory requires 5 to 13 dedicated masks on top of the standard CMOS logic process for tunneling dielectric lithography, floating gate patterning, high-voltage injection of memory, and memory area isolation. However, the memory array occupies a very small portion of the die surface in small-capacity flash memory chips, and the fixed cost of the entire mask-related process can only be allocated to a very small number of memory bits, resulting in a contradiction that the smaller the capacity, the higher the mask cost per bit. Large-capacity embedded flash memory can rely on a large-area array to reduce costs, but small-capacity chips do not have a high cost-performance ratio. Secondly, each mask corresponds to a set of deposition, illumination, and etching processes. The more masks there are, the more processes there are, and the longer the wafer processing cycle. Moreover, multi-layer overlay has accumulated alignment deviations. The compact arrangement of small-capacity array cells makes it easy for alignment deviations to cause problems such as gate short circuits, dielectric breakdown, and reduced yield, further increasing the cost per wafer.

[0005] To address these issues, existing technologies employ simplified masking schemes to reduce costs, but this results in decreased flash memory erase / write lifespan and high-temperature retention, failing to meet automotive and industrial-grade requirements. Other approaches use standard multi-mask methods to achieve reliability and meet automotive and industrial-grade requirements, but the high cost of masks and manufacturing makes them uncompetitive with low-priced consumer IoT products. Furthermore, current industry optimization solutions for reducing mask counts and simplifying processes are mostly designed for large-capacity storage arrays, lacking dedicated cell and process designs for storage arrays ranging from tens of KB to 4MB and even smaller capacities.

[0006] Therefore, the industry urgently needs a new method for fabricating small-capacity embedded flash memory that is simple and low-cost. Summary of the Invention

[0007] This invention provides a novel method for fabricating small-capacity embedded flash memory with a wavelength of 90nm or larger. This method involves fewer fabrication steps, reduces costs, and improves efficiency. At the same time, the fabricated small-capacity embedded flash memory exhibits excellent performance.

[0008] In the fabrication method of small-capacity embedded flash memory above 90nm described in this invention, the embedded flash memory includes: a substrate, and a memory array region and a peripheral logic region on the substrate. The memory array region includes at least one memory cell, which includes: a stacked gate on the substrate, the stacked gate including a floating gate and a control gate vertically stacked above it, and a floating gate gate oxide layer between the floating gate and the substrate; the peripheral logic region includes at least one 5V high-voltage logic transistor, the high-voltage logic transistor including a high-voltage logic gate on the substrate and a high-voltage logic gate oxide layer below it; wherein the method includes the following steps: simultaneously forming a floating gate gate oxide layer and a high-voltage logic gate oxide layer in the same process, and the two layers have equal thickness.

[0009] In a preferred embodiment, the potential coupling rate of the floating gate from the control gate is 85-90%. More preferably, the width of the floating gate is 0.90-1.30 micrometers.

[0010] In another preferred embodiment, the method further includes the following steps: after forming the floating gate oxide layer and the high-voltage logic gate oxide layer, simultaneously depositing a lower gate material layer on both surfaces; the lower gate material layer deposited on the floating gate oxide layer constitutes the floating gate, and the lower gate material layer deposited on the high-voltage logic gate oxide layer constitutes the lower portion of the high-voltage logic gate. More preferably, the upper portions of the control gate and the high-voltage logic gate are formed in such a way that, in the same deposition step, an upper gate material layer is simultaneously deposited on the memory array region and the peripheral logic region, and then the deposited upper gate material layer is etched on the memory array region and the peripheral logic region, respectively.

[0011] In another preferred embodiment, the memory cell further includes: a select gate on the substrate and a select gate oxide layer below it, the select gate being located next to the stacked gate; the select gate oxide layer and the floating gate oxide layer are formed simultaneously in the same fabrication process, and both have the same thickness.

[0012] In another preferred embodiment, the small-capacity embedded flash memory of 90nm or above is an embedded flash memory of 90nm or above with a storage capacity of less than or equal to 16KB.

[0013] In another preferred embodiment, the small-capacity embedded flash memory of 90nm or above is a small-capacity embedded flash memory of 180nm or 153nm.

[0014] In another preferred embodiment, the high-voltage logic transistor is a standard high-voltage logic transistor.

[0015] In the method of this invention, the floating gate oxide layer is formed together with the gate oxide layer of the peripheral 5V high-voltage logic transistor in the same process, eliminating the need for a separate process to form the floating gate oxide layer, and reducing the need for a dedicated mask and related processes. This simplifies the process flow, reduces manufacturing costs, and improves fabrication efficiency.

[0016] Meanwhile, in the method of the present invention, although the thickness of the floating gate oxide layer is increased to be equal to that of the peripheral 5V high-voltage logic transistor, the coupling rate obtained by the floating gate from the control gate is 85-90%, which is much higher than the 65-70% of similar products made by similar preparation methods in the prior art (i.e., the floating gate oxide layer is formed separately and the thickness is smaller than that of the logic transistor). This can provide the higher programming and erasing voltage required due to the increased thickness of the floating gate oxide layer, thus ensuring the excellent operating performance of the flash memory. Attached Figure Description

[0017] The same numbers in the accompanying drawings indicate the same or similar elements.

[0018] Figure 1 This is a partial top view of a specific embodiment of an embedded flash memory with a storage capacity of 16KB and a 153nm process manufactured by the method of the present invention.

[0019] Figure 2 yes Figure 1 The diagram shown is a schematic diagram along the BB section line after the active region (AA) and the isolation region (STI) are formed on the substrate surface.

[0020] Figure 3 Is Figure 2 The diagram shows an N-well forming the memory array region and the N-well and P-well forming the high-voltage (HV) and low-voltage (LV) logic regions in the substrate of the structure shown.

[0021] Figure 4a Is Figure 3 A schematic diagram of the first formation of a gate oxide layer on the substrate surface of the structure shown.

[0022] Figure 4b From Figure 4a A schematic diagram showing the removal of the initially formed gate oxide layer on the substrate surface of the low-voltage logic region of the structure shown.

[0023] Figure 4c Is Figure 4b A schematic diagram of a secondary gate oxide layer formed on the substrate surface of the structure shown.

[0024] Figure 5 Is Figure 4c A schematic diagram showing the deposition of a lower gate material on the secondary gate oxide layer of the structure shown.

[0025] Figure 6a Is Figure 5This diagram illustrates the preparation of photomask etching to form the gaps (PCs) between the floating gates of adjacent cells in each row of memory cells on the lower gate material layer deposited in the memory array region of the structure shown.

[0026] Figure 6b yes Figure 6a The diagram shows a memory array region that has been etched to form the partition (PC) between the floating gates of adjacent cells in each row of memory cells.

[0027] Figure 6c Is with Figure 6a The top view of the corresponding storage array area of ​​the structure shown.

[0028] Figure 6d Is with Figure 6b The top view of the corresponding storage array area of ​​the structure shown.

[0029] Figure 7 Is Figure 6b A schematic diagram showing the deposition of a dielectric layer on the surface of the structure shown.

[0030] Figure 8a Is Figure 7 A schematic diagram showing the removal of the deposited dielectric layer on the high-voltage and low-voltage logic regions of the structure shown.

[0031] Figure 8b Is with Figure 7 The top view of the via VH formed by etching in the dielectric layer deposited on the surface of the selected gate portion of the memory cell in the memory array region corresponding to the structure shown.

[0032] Figure 9 Is Figure 8a A schematic diagram showing the deposition of an upper gate material on the surface of the structure shown.

[0033] Figure 10a yes Figure 1 The diagram shows the structure of a memory cell in a flash memory along the CC section before etching to form the stacked gate and select gate.

[0034] Figure 10b yes Figure 1 The diagram shows the structure of a memory cell in a flash memory along the CC section line after etching to form a stacked gate and a select gate.

[0035] Figure 10c yes Figure 1 The diagram shows the structure of the high-voltage logic device in the flash memory along the EE section line before etching to form the high-voltage logic gate.

[0036] Figure 10d yes Figure 1The diagram shows the structure of the high-voltage logic device in the flash memory along the EE section line after etching to form the high-voltage logic gate.

[0037] Figure 10e yes Figure 1 The diagram shows the structure of the low-voltage logic device in the flash memory along the DD section line before the low-voltage logic gate is etched.

[0038] Figure 10f yes Figure 1 The diagram shows the structure of the low-voltage logic device in the flash memory along the DD section line after etching to form the low-voltage logic gate.

[0039] Figure 11a yes Figure 1 The diagram shows a memory cell structure along the CC section line in a flash memory, illustrating the steps of sequentially forming an outer gate isolation wall and ion implantation to form the source and drain.

[0040] Figure 11b yes Figure 11a The diagram illustrates the steps of removing the floating gate oxide layer above the source and drain electrodes and connecting the bit line (BL), common line (COM), and word line (WL). Detailed Implementation

[0041] The relevant definitions in this application are described below.

[0042] The width of the floating gate as described in this article refers to the size of the floating gate along the direction perpendicular to its length, within the top surface of the floating gate that is parallel to the substrate surface of the flash memory. The length direction of the floating gate is a known concept in the industry, referring to the direction of the line connecting the source and drain of the memory device in the memory cell of the flash memory storage area.

[0043] In this invention, the stacked gate is also referred to as a memory device, and the logic transistor is also referred to as a logic device. The logic gate is also referred to as a logic gate, the select gate is also referred to as a select gate, and the floating gate is also referred to as a floating gate.

[0044] The embedded flash memory of this invention includes a substrate, a memory array region on the substrate, and a high-voltage logic region on the periphery, typically also including a low-voltage logic region on the periphery. The memory array region and the logic region each have a well located within the substrate, respectively accommodating memory cells in the memory array and logic devices in each logic region. Both the memory cells and logic devices are located within active regions on the substrate surface. The logic transistors are preferably standard logic transistors.

[0045] The peripheral logic region includes a high-voltage region and a low-voltage region. The high-voltage region can contain multiple high-voltage logic transistors of different types, depending on the application, and the type of wells they occupy also varies. Similarly, the low-voltage region can contain multiple low-voltage logic transistors of different types, depending on the application, and the type of wells they occupy also varies. Typically, both N-wells and P-wells coexist in the low-voltage logic region and the high-voltage logic region.

[0046] A memory array region contains multiple memory cells, each typically identical. There is usually only one well within the memory array region, located in the substrate, accommodating all the memory cells. The type of this well depends on the electrical type of the device or transistor in the memory cell; it can be an N-well or a P-well. If the device is PMOS, the well is an N-well; if the device is NMOS, the well is a P-well. The device in the memory cell includes a stacked gate, and preferably also includes a select transistor, which can also be called a select tube or select device.

[0047] Preferably, the memory cell is a dual-transistor (2T) structure, namely, it includes two select gates (SG) and two stacked gates, with the overall structure being mirror-symmetrical from left to right. Specifically, each memory cell includes: a common source located in the substrate; a common line (COM) located on the substrate, directly above and connected to the common source; a pair of stacked gates located on the substrate, arranged mirror-symmetrically on both sides of the common line, wherein each stacked gate includes a vertically stacked control gate (CG) and a floating gate (FG), and a dielectric layer in between, the control gate extending downward to wrap part of the side surface of the floating gate, so that the floating gate obtains a large coupling potential from the control gate for programming and erasing; a pair of select gates (SG), located on the non-common line side of the two stacked gates respectively, and aligned with the stacked gates, and arranged mirror-symmetrically from left to right along the common line. The select gate is divided into upper and lower parts, with a dielectric layer sandwiched in between, and a via (VH) in the dielectric layer to make the upper and lower parts electrically conductive. On the side of each of the two select gates that is not adjacent to the stacked gates, there is a drain in the substrate below. The drains are connected to the bit line (BL), and the select gates are connected to the word line (WL).

[0048] In the flash memory array of the present invention, preferably, the direction of the floating gate length in the memory cell is the column direction, and the direction of the floating gate width is the row direction. The bit lines (BL) of each memory cell in each column are connected, and the word lines (WL), common lines (COM), and control lines (CG') of each memory cell in each row are connected respectively.

[0049] The embedded flash memory described in this invention has a programming channel from the channel region near the common source of the memory cell to the floating gate, and an erasing channel from the floating gate to the channel region in the underlying substrate. These are simple channels conventional in the industry, requiring no additional components to form new channels, such as erase gates or floating gate side bumps. In the memory array of this invention, all memory cells can be erased simultaneously, while programming is bit-selectable.

[0050] In the fabrication method of this invention, the floating gate oxide layer in the memory device is formed together with the gate oxide layer of the 5V high-voltage logic transistor in the peripheral logic region. This eliminates the need for a separate mask and related processes for forming the floating gate oxide layer, reducing the need for a dedicated mask and its associated processes, simplifying the process flow, lowering costs, and improving efficiency. The thickness of the floating gate oxide layer formed in this way is equal to that of the 5V high-voltage logic transistor.

[0051] In the case where the memory cell includes a select gate, it is preferable that the select gate oxide layer and the floating gate oxide layer are formed together in the same process, both formed in the same step as the gate oxide layer of the 5V high voltage logic transistor, and with equal thickness.

[0052] In small-capacity embedded flash memory of 90nm or above prepared by the method of the present invention, it is preferable to achieve a potential coupling rate of 85-90% obtained by the floating gate self-controlling gate. This value is much higher than the coupling rate of 65-70% of similar products prepared by prior art similar methods. This can provide higher programming voltage and erase voltage required due to the increased thickness of the floating gate oxide layer, ensuring that the flash memory has excellent working performance.

[0053] To achieve a high potential coupling rate of 85-90% for the floating gate self-controlled gate, the width of the formed floating gate is preferably increased in the method described in this invention. The floating gate width of similar products (153nm node process) manufactured by similar methods in the prior art is approximately 0.60 micrometers. In the small-capacity embedded flash memory of 90nm and above of this invention, the floating gate width is preferably increased to 0.90-1.30 micrometers, more preferably to 1.00-1.21 micrometers. This increases the area of ​​the floating gate and its contact area with the control gate, thereby improving the potential coupling rate of the floating gate. Additionally, the width of the active region below the floating gate can be narrowed, further improving the potential coupling rate obtained by the floating gate self-controlled gate. The width of the active region is the dimension of the active region along the direction perpendicular to the length of the floating gate.

[0054] The aforementioned prior art similar methods refer to methods that include the step of separately forming a floating gate oxide layer without increasing the floating gate width, and whose other process steps are the same as those of the present invention. Similar products made by prior art similar methods refer to small-capacity embedded flash memory with a floating gate oxide layer and floating gate width of 90nm or larger, manufactured by this method, while maintaining conventional dimensions.

[0055] Increasing the floating gate width will increase the size of the memory cell. However, this has minimal impact on the overall size of the small-capacity embedded flash memory described in this invention, and will hardly increase the overall size of the small-capacity embedded flash memory. The reason is as follows.

[0056] The high-voltage charge pumps, isolation traps, and high-voltage MOSFETs required for embedded flash memory erase and write operations occupy a significant amount of die area. The logic area of ​​the flash memory chip is high, amplifying the area occupied by peripheral high-voltage circuitry, while the memory array area is small. In small-capacity embedded flash memory, the memory array area is already small, and it still requires these charge pumps, sensitive amplifiers, and other peripheral circuits, resulting in an even smaller area proportion within the overall flash memory chip. Therefore, slightly increasing the size of the memory cells has almost no impact on the overall chip size. From a manufacturing perspective, reducing the number of photomasks significantly lowers costs, which is of great importance. In the context of intense cost competition in the embedded flash memory field, the fabrication method of this invention is highly advantageous for enhancing competitiveness and reducing costs while increasing efficiency.

[0057] The small-capacity embedded flash memory described in this invention preferably has a storage capacity of 16KB or less, and more preferably 8KB or less. The smaller the storage capacity, the smaller the area ratio of the storage region within the entire flash memory chip, making it easier to increase the potential coupling rate of the floating gate by increasing the floating gate width, and minimizing the impact on chip size. The small-capacity embedded flash memory of 90nm or more described in this invention is preferably 110nm or more, more preferably 153nm or more, and even more preferably 180nm or more. Larger process nodes typically lead to longer floating gates, which is more conducive to improving the potential coupling rate obtained by the floating gate from the self-controlled gate.

[0058] In the fabrication method of this invention, the fabrication process of the small-capacity embedded flash memory adopts the existing technology and includes the following steps in sequence: a. forming active regions (AA) and isolation regions (STI) on the substrate surface → b. forming the traps of the memory array region and the peripheral logic region → c. forming the gate oxide layer → d. depositing the lower gate material layer and etching to form the separation between the floating gates of adjacent cells → e. depositing the dielectric layer and etching away the dielectric layer from the logic region → f. depositing the upper gate material layer → g. etching to form each gate. Each step can adopt conventional techniques in the industry and can be adjusted in detail according to the requirements of the technical solution of this invention.

[0059] When forming the active region in step a, it is preferable to slightly narrow the width of the active region, which can further improve the potential coupling rate obtained by the floating gate self-controlling gate.

[0060] In step b, since memory devices are generally high-voltage devices, and in this invention, the thickness of the floating gate oxide layer of the memory device is equal to that of the high-voltage logic gate oxide layer, it is preferable that the high-voltage logic region and the memory array region form a trap of the same electrical charge together. The traps in the low-voltage logic region are formed at a shallower depth.

[0061] In step c, when forming the gate oxide layer, since the low-voltage logic gate oxide layer is the thinnest, it is preferable to first form a gate oxide layer on the entire substrate surface, with a thickness equal to the difference between the thicknesses of the high-voltage logic gate oxide layer and the low-voltage logic gate oxide layer. Then, the first gate oxide layer is removed from the substrate surface of the low-voltage logic region using HF acid, and a second gate oxide layer is formed on the entire substrate surface, with a thickness equal to that of the low-voltage logic gate oxide layer. Preferably, the gate oxide layer and the floating gate oxide layer are formed simultaneously with the high-voltage logic gate oxide layer, and all three have equal thicknesses.

[0062] In step d, after forming the gate oxide layer, a lower gate material layer is simultaneously deposited on the entire gate oxide layer surface. The lower gate material layer deposited on the floating gate oxide layer constitutes the floating gate; the lower gate material layer deposited on the select gate oxide layer constitutes the lower portion of the select gate; and the lower gate material layers deposited on the high-voltage and low-voltage logic gate oxide layers constitute the lower portions of the high-voltage and low-voltage logic gates, respectively. Then, in the memory array region, using a photomask, the deposited lower gate material layer is etched away at predetermined positions of the partitions (PCs) between the floating gates of adjacent memory cells in each row, forming the partitions (PCs) between the floating gates. The spacing between two adjacent partitions in each row is the width (WD) of the floating gate. Simultaneously, partitions (PCs) can also be etched between the select gates of adjacent memory cells in each row, or no partitions may be formed between the select gates of adjacent cells.

[0063] In step e, a dielectric layer is deposited on the surface of the structure formed above, and then the deposited dielectric layer is etched away from the peripheral logic region. Furthermore, in the memory array region, a via VH is etched into the dielectric layer above a predetermined location of the lower portion of the select gate of each memory cell. Especially when a partition (PC) is formed between the select gates of adjacent memory cells in each row, a via (VH) needs to be formed in the dielectric layer above the predetermined location of the lower portion of each select gate so that the lower portion and upper portion of each select gate are electrically connected. When there is no partition (PC) between the select gates of adjacent cells in each row, the lower portions of the select gates of the memory cells in each row are connected into a strip, and only a few vias need to be etched into the dielectric layer above this strip location. A via can be formed in the dielectric layer every 8-64 memory cells, preferably every 16-32 memory cells in each row.

[0064] In steps f and g, an upper gate material layer is first deposited on the surface of the structure formed above. Then, using the same photomask, the stacked gate and select gate in the memory cell and the high voltage logic gate and low voltage logic gate in the logic region are etched to form the memory array region and the peripheral logic region, respectively.

[0065] The method for fabricating small-capacity embedded flash memory of 90nm or larger according to the present invention will now be described in detail with reference to the accompanying drawings. However, the scope of the present invention is not limited to the specific embodiments shown in the drawings.

[0066] Figure 1 This is a partial top view of a specific embodiment of an embedded flash memory with a storage capacity of 16KB and a 153nm process fabricated by the method of this invention. The figure only shows a portion of the flash memory's storage array consisting of eight memory cells, as well as the surrounding high-voltage and low-voltage logic regions. The storage array and the surrounding low-voltage and high-voltage logic regions share a single substrate.

[0067] Figure 1 All memory cells in the flash memory array shown are identical. The memory devices within each cell are PMOS type, and the common source is P-type. All memory cells share a single N-well, constructed within the substrate. Figure 1 The logic transistors in the low-voltage and high-voltage logic regions shown are of different types; those located in the N-well are PMOS type, and those located in the P-well are NMOS type. The P-wells and N-wells of the logic devices in the logic region are also constructed in the substrate.

[0068] Figure 1 In this design, both the memory cells and peripheral logic transistors are constructed within active regions (AA) on the substrate surface. On the substrate surface, the active regions and shallow channel isolation regions (STIs) are arranged alternately and parallel to each other. High-voltage logic transistors are 5V devices, and low-voltage logic transistors are 1.5V devices, with gate oxide thicknesses of 125 angstroms (A) and 30 angstroms, respectively.

[0069] Figure 1 In the illustrated memory array, all memory cells are arranged and oriented in the same way. The column direction is defined by the length of the floating gate or the line connecting the same parts of two select gates within a memory cell. Odd and even columns are separated by shallow channel isolation regions (STIs). The array shown has four memory cells per row and two memory cells per column.

[0070] The structure of the storage unit is as follows: Figure 11b As shown. Figure 11b yes Figure 1The diagram shows the structure of a memory cell in a flash memory along a CC section. It includes: a P common source located in the substrate; a common line (COM) located directly above the common source and connected to it at the bottom; a pair of stacked gates located on the substrate, arranged in a mirror-symmetrical configuration on both sides of the common line, each stacked gate including a vertically stacked control gate (CG) and a floating gate (FG), and a dielectric layer between them; a pair of select gates (SG), located on the side of the stacked gates opposite to the common line, aligned with the stacked gates, and arranged in a mirror-symmetrical configuration along the common line. On the side of each select gate not adjacent to the stacked gates, there is a drain in the substrate below. Each select gate includes upper and lower parts, with a dielectric layer between the two parts containing vias (VH). The common source of the memory cell is connected to the common line (COM), and the control gate is connected to the control line (CG'). Figure 11b (Not shown in the image), select the gate drain connectivity bit line (BL), select the gate connectivity word line (WL).

[0071] In the illustrated memory array, the select gate upper portion and control gate of all memory cells in each row are connected along the row across the isolation region (STI) to form a stripe, and these stripes are parallel to each other. However, the floating gate and select gate lower portion of each memory cell in each row are not connected. Between the floating gates or select gate lower portions of adjacent cells in each row, there is an etched partition (PC), and the floating gates or select gate lower portions of adjacent cells are disconnected by the PC, as shown below. Figure 1 and Figures 6c-6d As shown. The spacing between two adjacent partitions is the width of the floating gate (WD), which is 1.0 micrometers. The potential coupling rate of the floating gate to the control gate in the memory cell is 86%. As a comparison, a similar product prepared by a similar method in the prior art has a floating gate width of 0.6 micrometers and a floating gate coupling rate of 68% to the control gate.

[0072] The bit lines (BL) of each memory cell in each column are connected, and the word lines (WL), common lines (COM), and control lines (CG') of each memory cell in each row are connected respectively.

[0073] Figure 2 , Figure 3 , Figure 4a , Figure 4b , Figure 4c , Figure 5 , Figure 6a , Figure 6b , Figure 7 , Figure 8a , Figure 9 They are respectively Figure 1 The diagram shows a portion of the memory cells and logic devices in the flash memory along the BB cross-section during the fabrication process (the steps before the cutoff etching to form each gate). Figures 10a-10f and Figures 11a-11b The etching and formation steps of each gate in the memory cell and logic device, as well as the formation steps of the source and drain, are shown respectively. The following is a detailed description in sequence with reference to these figures. Figure 1 The flash memory fabrication process is shown.

[0074] Figure 2 yes Figure 1 The diagram shows a schematic of the substrate in a flash memory along the bottom border (BB) before device fabrication begins. First, adjacent and alternating active regions (AA) and shallow channel isolation regions (STI) are formed on the substrate surface. Memory cells and logic devices are subsequently formed within the active regions. The width of the active regions (AA) is conventional and not narrowed. Then, as... Figure 3 As shown, below the predetermined regions of the memory array region and the two logic regions in the substrate, the N-wells of the memory array region and the N-wells and P-wells of each logic region are formed. The N-wells in the high-voltage logic region are formed together with the N-wells of the memory array region. The N-wells and P-wells of the low-voltage logic region are shallower.

[0075] like Figures 4a-4c As shown, a gate oxide layer is formed on the substrate surface. Specifically, as... Figure 4a As shown, a gate oxide layer is first formed on the entire substrate surface, with a thickness equal to the difference between the thicknesses of the high-voltage logic gate oxide layer and the low-voltage logic gate oxide layer. Then, as... Figure 4b As shown, the gate oxide layer initially formed is removed from the substrate surface of the low-voltage logic region using HF acid, and then as follows... Figure 4c The diagram shows a secondary gate oxide layer formed on the entire substrate surface, with a thickness equal to that of the low-voltage logic gate oxide layer. The gate oxide layers for the select gate and floating gate regions are formed simultaneously with the high-voltage logic gate oxide layer, and all three have an equal thickness of 125 angstroms. For comparison, the floating gate oxide layer of a similar product prepared using a similar method in the prior art has a thickness of 90 angstroms.

[0076] Next, as Figure 5 As shown, a lower gate material is deposited on the entire gate oxide layer surface.

[0077] Then, as Figures 6a-6d As shown, in the memory array region, a photomask is used to etch away the deposited lower gate material layer at predetermined positions of the partitions (PCs) between the floating gates of adjacent memory cells in each row, forming the partitions (PCs) between the floating gates. The spacing between two adjacent partitions in each row is the width (WD) of the floating gate, which is 1.0 micrometers. Simultaneously, partitions (PCs) are also etched between the select gates of adjacent memory cells in each row. Figures 6a-6b These are schematic diagrams showing how photomask etching is used to form the spacing (PC) between corresponding floating gates of adjacent cells in each row. Figures 6c-6d They are respectively the corresponding Figures 6a-6bThe top view of the memory array region shown in the diagram shows that partitions (PCs) are also etched between the corresponding select gates of adjacent memory cells in each row.

[0078] Subsequently, as Figure 7 As shown, a dielectric layer is deposited on the surface of the structure formed above, and then as follows: Figure 8a As shown, the deposited dielectric layer is etched away from the outer logic region. Furthermore, as... Figure 8b As shown, in the memory array region, a via VH is etched into the dielectric layer above a predetermined location below each select gate portion of each memory cell.

[0079] Then, as Figure 9 As shown, an upper gate material layer is deposited on the surface of the structure formed above.

[0080] Subsequently, as Figures 10a-10f As shown, the same photomask is used in the memory array area and the peripheral logic area to etch the stacked gate and select gate in the memory cell, and the high voltage logic gate and low voltage logic gate in the logic area, respectively.

[0081] Specifically, in the memory array region, in the area of ​​each row of memory cells, a photomask is used to block the predetermined selection gate and stacked gate portions. In the areas outside these portions, etching is performed down to the floating gate oxide layer to remove the upper gate material layer, dielectric layer, and lower gate material layer from these portions, thereby forming the stripe of the upper portion of the selection gate and the stripe of the control gate in each row (see...). Figure 1 The text describes a series of elements, including the lower portion of the select gate and the floating gate of each cell separated by partitions (PCs). Each row contains two stripes for the upper portion of the select gate and two stripes for the control gate, arranged parallel to each other along the row direction. Figure 1 The storage array is shown in the figure.

[0082] Figures 10a-10b They are Figure 1 The diagram shows a memory cell in a flash memory, with its structure along the CC cross-section in the column direction, before and after the etching process to form the stacked gate and select gate. Figure 10a The image shows the portion of the memory cell that is covered by a photomask, which is the portion where the select gate and the stacked gate are to be formed. Figure 10b The image shows the upper and lower portions of the select gate (SG) formed after etching in the memory cell, and the control gate (CG) and floating gate (FG) in the stacked gates.

[0083] In the logic region, the same photomask used to etch the gate in the memory cell is used to block the predetermined parts of the logic gate, and in the areas outside these parts, the upper gate material layer and the lower gate material are etched away to form the logic gate. Figures 10c-10d They are shown respectively Figure 1The diagram shows the steps before and after etching to form the high-voltage logic gate in the high-voltage logic device along the EE cross-section of the flash memory. Figure 10e-10f They are shown respectively Figure 1 The structure of the low-voltage logic device in the flash memory shown is along the DD section line, and the steps before and after etching to form the low-voltage logic gate. Figure 10c and Figure 10e The photomask blocking areas are the locations where high-voltage logic gates and low-voltage logic gates are to be formed.

[0084] Next, isolation walls for each gate and source / drain electrodes for the memory device are formed. For example... Figure 11a As shown, an isolation wall is formed on both sides of each gate formed by etching, which serves as insulation; and ions are implanted into the active region on the substrate surface outside the isolation wall of each gate to form the P-type source and drain on both sides of the selection gate and the stacked gate in the memory cell, and the source and drain of the logic transistor.

[0085] In the memory cell, ions are implanted in the substrate below the two stacked gates to form a common source; ions are implanted in the substrate below the outer side of the select gate (the side not adjacent to the stacked gates) to form the drain of the select transistor.

[0086] Subsequently, the gate oxide layer remaining above each ion implantation region is removed using HF acid; and a self-aligned polysilicide is formed between the two stacked gates above the common source of the memory cell, forming a common line (COM) that connects to the common source in the substrate below; the drain below the outer side of the select gate of the memory cell (the side not adjacent to the stacked gates) is connected to the bit line (BL). The select gate is connected to the word line (WL).

[0087] Those skilled in the art will know that the method for fabricating small-capacity embedded flash memory of 90nm or above in this invention is not limited to the specific examples described above.

Claims

A method for fabricating small-capacity embedded flash memory with a wavelength of 1.90 nm or more, wherein the embedded flash memory comprises: A substrate, and a memory array region and a peripheral logic region on the substrate, the memory array region including at least one memory cell, the memory cell including: a stacked gate on the substrate, the stacked gate including a floating gate and a control gate vertically stacked above it, and a floating gate gate oxide layer between the floating gate and the substrate; the peripheral logic region including at least one 5V high-voltage logic transistor, the high-voltage logic transistor including a high-voltage logic gate on the substrate and a high-voltage logic gate oxide layer below it; The method is characterized by the following steps: simultaneously forming a floating gate oxide layer and a high-voltage logic gate oxide layer in the same process, with both having equal thicknesses; The potential coupling rate obtained by the floating gate from the self-controlled gate is 85-90%. The width of the floating gate is 0.90-1.30 micrometers.

2. The method for fabricating small-capacity embedded flash memory of 90nm or larger as described in claim 1, characterized in that, It also includes the following steps: after forming the floating gate oxide layer and the high-voltage logic gate oxide layer, a lower gate material is deposited on both surfaces simultaneously; the lower gate material layer deposited on the floating gate oxide layer constitutes the floating gate, and the lower gate material layer deposited on the high-voltage logic gate oxide layer constitutes the lower part of the high-voltage logic gate.

3. The method for fabricating small-capacity embedded flash memory of 90nm or larger as described in claim 2, characterized in that, It also includes the following steps: the upper portion of the control gate and the high voltage logic gate is formed in such a way that, in the same deposition step, an upper gate material layer is deposited simultaneously on the memory array region and the peripheral logic region, and then the deposited upper gate material layer is etched on the memory array region and the peripheral logic region, respectively.

4. The method for fabricating small-capacity embedded flash memory of 90nm or larger as described in claim 1, characterized in that, The memory cell further includes: a select gate on the substrate and a select gate oxide layer below it, the select gate being located next to the stacked gate; the select gate oxide layer and the floating gate oxide layer are formed simultaneously in the same fabrication process, and both have the same thickness.

5. The method for fabricating small-capacity embedded flash memory of 90nm or larger as described in claim 1, characterized in that, The aforementioned small-capacity embedded flash memory with a wavelength of 90nm or above refers to embedded flash memory with a storage capacity of less than or equal to 16KB and a wavelength of 90nm or above.

6. The method for fabricating small-capacity embedded flash memory of 90nm or larger as described in claim 1, characterized in that, The small-capacity embedded flash memory with a wavelength of 90nm or above refers to a small-capacity embedded flash memory with a wavelength of 180nm or 153nm.

7. The method for fabricating small-capacity embedded flash memory of 90nm or larger as described in claim 1, characterized in that, The high-voltage logic transistor mentioned is a standard high-voltage logic transistor.

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