Test circuit, test method and chip product

Abstract

The embodiment of the application discloses a test circuit, a test method and a chip product. The test circuit comprises a test bus and a plurality of analog boundary sub-modules; each of the analog boundary sub-modules is connected with a corresponding functional module; each of the analog boundary sub-modules is used for controlling a connection state between the connected functional module and the test bus; an input end of the test bus is used for accessing a test signal of an external test source; an output end of the test bus is used for accessing a test analysis device; and the test analysis device is used for testing and analyzing at least one functional module accessed to the test bus, or testing and analyzing the functional module accessed to the test bus to obtain a test result.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of integrated circuit technology, and in particular to a test circuit, a test method, and a chip product. Background Technology

[0002] Mixed-signal transceiver circuits, as core functional units of modern communication systems, integrate multiple functional modules. Due to the complex structure of mixed-signal transceiver circuits and the fact that their signal links consist of both digital and analog signals, they are prone to various types of faults during practical use.

[0003] In related technologies, it is usually based on the IEEE 1149.4 standard, which is officially called the Mixed Signal Test Bus Standard. The Signal Test Bus (SBT) is used to perform signal testing on mixed-signal transceiver circuits. Specifically, it can test the input / output pins of the mixed-signal transceiver circuit using analog boundary modules defined in the standard, and obtain test results. However, this method yields test results for the complete transmit / receive link in the mixed-signal transceiver circuit, and cannot accurately locate the fault to a specific, single functional module, resulting in low accuracy and efficiency in fault diagnosis. Summary of the Invention

[0004] This application provides at least one test circuit, test method, and chip product.

[0005] The technical solution of this application embodiment is implemented as follows: On one hand, embodiments of this application provide a test circuit, which includes a test bus and multiple simulated boundary sub-modules; each simulated boundary sub-module is connected to a corresponding functional module; each simulated boundary sub-module is used to control the connection state between the connected functional module and the test bus; the input terminal of the test bus is used to receive test signals from an external test source; the output terminal of the test bus is used to receive test analysis equipment; the test analysis equipment is used to perform test analysis on at least one functional module connected to the test bus to obtain test results.

[0006] Secondly, embodiments of this application provide a testing method applied to a test circuit used to test functional modules in an integrated circuit. The method includes: responding to a target test command, controlling the connection state between the connected functional modules and the test bus through each simulated boundary submodule in the test circuit; and performing test analysis on at least one functional module connected to the test bus based on test signals from an external test source through the test bus to obtain test results.

[0007] Thirdly, embodiments of this application provide a chip product, the chip product including the test circuit provided in the first aspect of embodiments of this application.

[0008] In this embodiment, a test circuit is provided, comprising a test bus and multiple simulated boundary submodules. Each simulated boundary submodule is connected to a corresponding functional module. Each simulated boundary submodule controls the connection state between the connected functional module and the test bus. The input terminal of the test bus is used to receive test signals from an external test source. The output terminal of the test bus is used to connect to a test analysis device. The test analysis device performs test analysis on at least one functional module connected to the test bus to obtain test results. Thus, by independently configuring simulated boundary submodules for each functional module within the integrated circuit, each simulated boundary submodule can control the connection state between the connected functional module and the test bus, enabling more detailed internal testing of the functional modules in the integrated circuit. This improves the accuracy and efficiency of integrated circuit fault diagnosis.

[0009] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of this application. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a test circuit provided in an embodiment of this application. Figure 1 ; Figure 2 This is a schematic diagram of a test circuit provided in an embodiment of this application. Figure 2 ; Figure 3 This is a schematic diagram of a test circuit provided in an embodiment of this application. Figure 3 ; Figure 4 This is a schematic diagram of a test circuit provided in an embodiment of this application. Figure 4 ; Figure 5 This is a schematic diagram of a test circuit provided in an embodiment of this application. Figure 5 ; Figure 6 This is a flowchart illustrating a testing method for an integrated circuit provided in an embodiment of this application; Figure 7 This is a schematic diagram of a transceiver circuit provided in an embodiment of this application; Figure 8 This is a flowchart of a fault diagnosis method provided in an embodiment of this application. Detailed Implementation

[0011] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0012] In the following description, references to "some embodiments" refer to a subset of all possible embodiments. It is understood that "some embodiments" may be the same or different subsets of all possible embodiments and may be combined with each other without conflict. The terms "first / second / third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0013] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of this application.

[0014] Currently, mixed-signal transceiver circuits, as core functional units of modern communication systems, are themselves highly integrated system-on-a-chip. They are not simply single-function circuits, but integrate multiple functional modules from the digital, analog, and radio frequency (RF) domains. Each domain has distinct operating principles, signal characteristics, performance indicators, and failure mechanisms. For example, digital modules focus on logic levels and timing, analog modules on the amplitude and linearity of continuous signals, and RF modules on impedance matching, noise, and nonlinearity at high frequencies. This mixed-signal structure means that a single physical failure can lead to completely different manifestations of faults in different domains.

[0015] Furthermore, the signal path of the transceiver circuit is a continuous link containing multiple processing stages, from baseband to radio frequency, with each stage module operating in series. The impact of any single-point failure will propagate along the link to subsequent stages and be amplified or transformed by subsequent modules. For example, a small nonlinear distortion in the pre-stage mixer can lead to spectrum regeneration in subsequent stages, ultimately manifesting as severe adjacent channel interference and increased bit error rate at the overall level. This cascading effect results in a many-to-one fuzzy mapping relationship between terminal performance degradation and specific fault sources, greatly increasing the difficulty of fault tracing.

[0016] In related technologies, transceiver circuits are typically tested based on the IEEE 1149.4 standard. Existing test schemes based on the IEEE 1149.4 standard can specifically test the input / output pins of mixed-signal transceiver circuits using analog boundary modules defined in the standard to obtain test results. However, since the analog boundary modules are only located on the outer pins of the chip, the test signal can only be injected from an external pin and the response can only be acquired from another external pin. This means that the test path must traverse all internal functional modules of the entire transceiver link (such as digital-to-analog converters, mixers, filters, low-noise amplifiers, analog-to-digital converters, etc.). In other words, the test system essentially always deals with a black box with the transceiver circuit chip as its boundary, and cannot directly access or control the input or output nodes of any independent functional module within it. Therefore, the test stimulus cannot be customized for a specific module, and the test response is a mixed result of crosstalk, noise and distortion accumulated from all functional modules. This results in the loss of module-level characteristic information of the fault. The test result obtained is the test result of the complete transmit and receive link in the mixed-signal transceiver circuit, which cannot accurately locate the fault to a specific, single functional module, resulting in low accuracy and efficiency of fault diagnosis.

[0017] To address the aforementioned issues, this application proposes a test circuit, a test method, and a chip product. By independently configuring a simulated boundary submodule for each functional module within the integrated circuit, each simulated boundary submodule can control the connection status between the connected functional module and the test bus. This enables more detailed internal testing of the functional modules within the integrated circuit, thereby improving the accuracy and efficiency of integrated circuit fault diagnosis.

[0018] Figure 1 This is a schematic diagram of a test circuit provided in an embodiment of this application. Figure 1 ,like Figure 1 As shown, the test circuit 100 includes a test bus 101 and multiple analog boundary submodules 102.

[0019] Each simulation boundary submodule 102 is connected to a different functional module 11. Thus, each simulation boundary submodule 102 can perform different test control operations for the connected functional module 11; specifically, each simulation boundary submodule 102 can independently control its connected functional module 11 to switch between normal operation and test isolation states according to external target test commands. When the functional module 11 is in normal operation, it can be controlled by the corresponding simulation boundary submodule 102 to access the test bus 101; when the functional module 11 switches to test isolation state, it can be controlled by the corresponding simulation boundary submodule 102 to disconnect the connected functional module 11 from the test bus 101.

[0020] In this embodiment, each simulated boundary submodule 102 is used to control the connection status between the connected functional module 11 and the test bus 101.

[0021] The connection status between functional module 11 and test bus 101 may include access to test bus 101.

[0022] In practical applications, each analog boundary submodule 102 can be connected to a designated functional module 11, and each analog boundary submodule 102 can be used to connect the connected functional module 11 to the test bus 101.

[0023] Specifically, each analog boundary submodule 102 can connect the input / output ports of the connected functional modules 11 to the internal network of the test bus 101. In this case, the pin signals of the functional module 11 can be directed from the main signal path during normal operation to the test bus 101. At this time, the input / output of the functional module 11 no longer interacts directly with other functional modules 11 before and after it, but instead interacts with the test bus 101. When multiple analog boundary submodules 102 perform this access operation, the functional modules 11 connected to each of the multiple analog boundary submodules 102 can be connected in series through the test bus 101. Each accessed functional module 11 can act as a node on the test bus 101, and the test bus 101 is the common transmission backbone running through these nodes. External test equipment can sequentially apply test stimulus signals to the functional module 11 at the beginning of the link by accessing the endpoints of the test bus 101. For example, by accessing the AT1 and AT2 ports of the ATAP (Analog Test Access Port) ports in the test bus 101, test stimulus signals can be sequentially applied to the functional module 11 at the beginning of the link. The equipment can also collect the response signals output from the functional module 11 at the end of the link, thereby realizing the performance test of the entire serial link.

[0024] For example, in a mixed-signal transceiver circuit, functional module 11 may include, but is not limited to, low-noise amplifiers, filters, analog-to-digital converters, digital processors, etc. When the analog boundary submodules 102 corresponding to these modules are all configured to be connected to the test bus 101, these modules can be connected in series through the test bus 101 to form a virtual link defined by the test architecture. At this time, external test equipment can inject standard test excitation signals from the link start point (e.g., the input of the low-noise amplifier or the output of the digital processor) through the access ports of the test bus 101 (e.g., AT1 and AT2 of the ATAP port). The excitation signal will flow through the connected low-noise amplifier, filter, analog-to-digital converter, etc., sequentially through the test bus 101. After each module processes the signal, the resulting response continues to be transmitted to the next module through the test bus 101, and is finally output from the end of the link and acquired by the external test equipment through the test bus 101.

[0025] In some embodiments, the connection state between the functional module 11 and the test bus 101 may also include bypassing the functional module 11 from the test bus 101. That is, any one of the multiple analog boundary sub-modules 102 can bypass the connected functional module 11 from the test bus 101.

[0026] Specifically, when the simulation boundary submodule 102 receives a control command to bypass the connected functional module 11 from the test bus 101, it can physically disconnect the electrical connection between the input / output pins of the functional module 11 and the internal network of the test bus 101. At this time, the bypassed functional module 11 is electrically equivalent to being skipped from the test link formed by the test bus 101, and the test signal will no longer flow through the bypassed functional module 11.

[0027] The test bus 101 may include a digital test bus and an analog test bus. The digital test bus typically uses a test access port and protocol conforming to the IEEE 1149.1 standard. Its main functions are to transmit test commands, configuration data, and test results in digital form, to control and configure the status of each analog boundary submodule 102, and to read the test response results of the digital modules; the analog test bus can be used to transmit analog signals and analog test results.

[0028] The input terminal of the test bus 101 is used to connect to the test signal of an external test source; the output terminal of the test bus 101 is used to connect to a test analysis device.

[0029] Specifically, the input terminal of the test bus 101 can be connected to the dedicated test pin of the chip containing the transceiver circuit to access external test equipment; the output terminal of the test bus 101 can be connected to the test access port of the chip containing the transceiver circuit.

[0030] The external test source may include, but is not limited to, external test instruments, signal sources, ATE (Automatic Test Equipment), etc., which can be used to send test signals as test excitation signals to the test bus 101, so that the test excitation signals enter the transceiver circuit from the outside, and then flow through the multiple connected functional modules 11 via the test bus 101. The test analysis equipment may include, but is not limited to, signal acquisition and analysis units, spectrum analyzers, bit error rate testers, host computers, etc., which can detect and analyze the test response signals obtained from the test.

[0031] Specifically, the test and analysis equipment can be used to test and analyze multiple functional modules 11 connected to the test bus 101.

[0032] In one possible implementation, when each simulated boundary submodule 102 can be used to connect the connected functional module 11 to the test bus 101, the test analysis device can perform end-to-end overall performance testing on the complete transceiver link.

[0033] Specifically, when all analog boundary submodules 102 are configured to connect their connected functional modules 11 to the test bus 101, the functional modules 11 are connected in series to form a complete working link from signal input to signal output. At this time, test excitation signals generated by external test sources (such as RF or IF signals of a specific modulation format) can be injected from the dedicated test pins of the chip containing the transceiver circuitry and flow through this complete link. The test analysis equipment then captures the final output response from the test access port of the chip containing the transceiver circuitry.

[0034] However, this method can only analyze whether there is a fault in the overall performance of the entire link, and cannot pinpoint the fault to a specific individual functional module 11 in the link. Therefore, in another implementation, after performing end-to-end overall performance testing on the complete transmit and receive link and determining that there is a faulty link, the link consisting of the remaining functional modules 11 can be tested by bypassing any one of the multiple functional modules 11 from the test bus 101.

[0035] Specifically, test commands can be issued through the test bus 101 to control the simulated boundary submodule 102 to bypass one functional module 11 on the link from the test bus 101 in turn. After bypassing one functional module 11 each time, a complete end-to-end performance test can be performed again on the new link formed by reconnecting the remaining functional modules 11.

[0036] The performance of the new link measured after bypassing a specific functional module 11 each time can be compared and analyzed with the performance of the original complete faulty link. If the performance indicators of the new link return to normal or significantly improve after bypassing a certain functional module 11 (denoted as functional module X), it indicates that the bypassed functional module X is the root cause of the original link failure. If the performance indicators of the new link are still abnormal after bypassing functional module X, it indicates that the failure is not caused by functional module X, but exists in other modules in the remaining link. Subsequently, the connection of functional module X is restored, and the next functional module 11 to be tested (such as functional module Y) is bypassed, and the above testing and comparison process is repeated until the faulty module that has a decisive impact on the link performance is found.

[0037] Once the faulty module is identified, it can be subjected to precise independent testing. Specifically, the analog boundary submodule 102 of the faulty module can be configured to test isolation mode, so that the functional module 11 connected to it can be individually connected to the internal analog test bus 101. Subsequently, external test equipment can directly inject test stimuli into the faulty module through the test bus 101 and directly measure its output response, thereby performing test analysis on the faulty module.

[0038] By adopting the above technical solution, by independently configuring an analog boundary submodule for each functional module inside the integrated circuit (i.e., transceiver circuit), each analog boundary submodule can control the connection status between the connected functional module and the test bus, enabling more detailed internal testing of the functional modules in the integrated circuit, thereby improving the accuracy and efficiency of integrated circuit fault diagnosis.

[0039] Considering that in related technologies, the standard 1149.4 instructions only include general basic operations, in order to implement the operation of specific configuration of multiple analog boundary submodules 102 in the embodiments of this application, the controller in the transceiver circuit needs to repeatedly execute multiple standard instructions and combine the operations of multiple registers through the state machine of the TAP (Test Access Port) controller. This will result in a lengthy test process, long test clock cycles, and low test efficiency.

[0040] Therefore, in some embodiments, new dedicated instructions can be constructed to encapsulate the operations of selecting functional module 11 and setting its working state into atomic instructions. By configuring the parameters of the instructions, precise control of the specified module can be directly completed within one instruction cycle, shortening the delay cycle of complex configuration, and improving the execution efficiency and fault location speed of performing specific configuration operations on multiple simulated boundary submodules 102.

[0041] In some embodiments, Figure 2 This is a schematic diagram of a test circuit provided in an embodiment of this application. Figure 2 ,like Figure 2 As shown, the test circuit 100 also includes a path control unit 103, which is connected to the analog boundary submodule 102.

[0042] In this embodiment, after constructing the newly added dedicated target test instruction, the access control unit 103 can receive the target test instruction and send control information to each simulated boundary sub-module 102 based on the target test instruction. The control information is used to instruct the corresponding simulated boundary sub-module 102 to perform an operation matching the target test instruction.

[0043] When each simulation boundary submodule 102 receives the corresponding control information, it can maintain the connection between the connected functional module and the test bus, or bypass the connected functional module from the test bus, according to the control information.

[0044] The target test instruction may include, but is not limited to, the first test instruction, the second test instruction, and the third test instruction.

[0045] The first test command can be represented as the LINK_SCAN command (global command). This command controls each analog boundary submodule 102 to connect its connected functional module 11 to the test bus 101, forming a complete transmit / receive link, and performs an overall test on the link. The high-order bits of its configuration parameters can be used to specify whether to test the transmit link, receive link, or both links; the low-order bits can be used to indicate the test sampling rate.

[0046] The second test command can be represented as the MODULE_ISOLATE command (single module command). This command controls the specified analog boundary submodule 102 to isolate the corresponding functional module 11 from the test bus 101 and activate the internal bypass channel, allowing signals to bypass the functional module 11 for transmission. This enables module-level fault diagnosis while maintaining link connectivity. The high-order bits of its configuration parameters can specify the type of functional module 11, and the low-order bits can specify the identifier of the functional module 11.

[0047] The third test instruction can be represented as the PIN_TEST instruction. This instruction controls a specified analog boundary submodule 102 to connect its connected functional module 11 to the internal test bus 101, thereby exposing the module's input / output pins to external test equipment for direct access. Its configuration parameters specify the identifier of the functional module 11 and the specific pin numbers within that module. The low-order bits of the configuration parameters specify the pin labels, while the high-order bits specify the identifier of the functional module 11.

[0048] In this embodiment, extended test instructions can be constructed based on the TAP state machine of the IEEE 1149.4 standard. The instruction format of the extended test instructions can be represented as "2-bit instruction code + 8-bit configuration parameters + N-bit data". Specifically, test instructions as shown in Table 1 can be constructed.

[0049] Table 1

[0050] By adopting the above technical solution, the complex process of selecting modules and configuring operations can be encapsulated into a single instruction, which can reduce the test clock cycle of configuration latency and speed up test execution. Moreover, multiple functional modules 11 can be configured simultaneously through a single broadcast instruction, which can improve the test efficiency of transceiver circuits.

[0051] Considering that in related technologies, the standard TAP controller and its state machine are general-purpose and simple instruction shift and update hardware sequence generators, which can only recognize and respond to a limited set of predefined standard instructions, and do not have the ability to decode and translate instruction semantics to generate complex cooperative control sequences, the TAP controller cannot parse and execute the newly constructed test instructions in the above embodiments.

[0052] Therefore, in some embodiments, the access control unit 103 can receive the target test command and determine the set of test actions corresponding to the target test command. Then, the access control unit 103 can send control information according to the set of test actions.

[0053] The control information sent to each simulated boundary submodule is matched with the test actions in the test action set; each action in the test action set is used to instruct different simulated boundary submodules 102 to perform a connection state switching operation corresponding to the target test instruction.

[0054] In this embodiment, the access control unit 103 can monitor the instruction code shifted into the instruction register via TAP. When it is identified that the instruction code belongs to a newly added dedicated target test instruction, rather than a standard instruction, the access control unit 103 can parse the test action set corresponding to the test instruction based on the instruction code of the target test instruction and the configuration parameters of the data register shifted in simultaneously. This test action set can include what state (connected, bypassed) each related simulation boundary submodule 102 needs to switch its connected functional module 11 to.

[0055] After obtaining the set of test actions, the path control unit 103 can send the corresponding control information to all the involved analog boundary submodules 102 through a dedicated control bus independent of the 1149.4 test bus 101. This control information can drive each analog boundary submodule 102 to switch connection states, thereby atomically establishing the required test path (such as the overall link or the remaining link of bypassing a certain module) within one instruction cycle.

[0056] In some embodiments, the simulated boundary submodule 102 includes a module isolation switch.

[0057] One end of the module isolation switch is connected to the input / output pin of the connected functional module 11; the other end of the module isolation switch is connected to the test bus 101.

[0058] In this embodiment, the module isolation switch can be implemented using a matrix network composed of multiple physical switches. The multiple physical switches can reconstruct the connection relationship between the pins of the analog functional module 11, the test bus 101, and the signal paths of the preceding and following functional modules, thereby realizing the three states of the functional module 11: connection, bypass (isolation), and pin testing.

[0059] In this implementation, the external test equipment serially shifts the test command and corresponding configuration parameters to the instruction register and boundary scan register chain of the transceiver circuit via the TAP's TDI (Test Data In) pin. When the TAP controller state machine enters the update data register state, the configuration parameters shifted to the boundary scan unit corresponding to each analog boundary submodule 102 can be latched into the update latch of that boundary scan unit. The local control logic inside the analog boundary submodule 102 then decodes the configuration parameters in the update latch and generates a set of corresponding analog switch control levels. These analog switch control levels can simultaneously drive multiple switches in the module isolation switch to change their on or off states, thereby completing the switching of the working state (such as connection, bypass, and pin test) of each functional module 11 in an atomic operation within one instruction cycle.

[0060] In some embodiments, the control information sent by the access control unit 103 to each analog boundary submodule 102 may include first control information and second control information.

[0061] In this embodiment, the target test instructions include link scan instructions and module isolation instructions, and the control information includes first control information corresponding to the link scan instructions and second control information corresponding to the module isolation instructions.

[0062] The first control information can be a logic high level or a specific digital code, used to instruct the target analog boundary submodule 102 to close its internal module isolation switch; the second control information can be a logic low level or another different digital code, used to instruct the target analog boundary submodule 102 to open its internal module isolation switch.

[0063] In one possible implementation, the module isolation switch can, according to the first control information, close the connection between the input / output pins of the functional module 11 and the test bus 101 to maintain the connection between the connected functional module 11 and the test bus 101; and, according to the second control information, disconnect the connection between the input / output pins of the functional module 11 and the test bus 101 to bypass the functional module 11 from the test bus 101.

[0064] Using the above technical solution, the access and isolation states of functional module 11 in the link can be switched by the module isolation switch according to specific test instructions.

[0065] In some embodiments, the simulated boundary submodule 102 includes a pin test interface. The pin test interface can be connected to the pins of the connected functional module 11.

[0066] In this embodiment, the target test instruction also includes a pin test instruction, and the control information also includes third control information corresponding to the pin test instruction.

[0067] The third control information can be a specific digital code or a set of configuration signals that are different from the first and second control information, used to indicate that the analog boundary submodule 102 is switched to pin test mode so that the pin to be tested of the functional module 11 connected to it is connected to the test bus 101.

[0068] In this embodiment, when the simulated boundary submodule 102 switches to the pin test mode according to the third control information, the pin to be tested of the functional module 11 can be connected to the test bus 101 through the internal pin test interface, so as to switch the functional module 11 to the test bus 101.

[0069] Using the above technical solution, the electrical characteristics of any pin of the connected functional module 11 can be thoroughly tested and verified through the pin test interface.

[0070] Considering that in existing tests based on 1149.4, the test control logic of test setups such as TAP state machines and instruction shifting runs on independent test clocks, while the normal operation of transceiver circuits (such as baseband processing and data conversion) is driven by their system clock, for example, when testing the entire initial link, if the clock domains used for acquiring analog signals and reading digital data are not synchronized, the digital data read from the digital module will not accurately correspond to the analog signal acquisition results at a specific moment, making fault analysis unreliable.

[0071] In one possible implementation, the access control unit 103 can also acquire the test clock of the test interface of the test circuit 100 and the system operating clock of the functional module 11; and perform timing synchronization operation based on the test clock and the system operating clock.

[0072] The timing synchronization operation includes binding the test clock with the system operating clock to achieve timing alignment between digital test control signals and analog acquisition signals.

[0073] In this implementation, the system clock of functional module 11 can be the clock signal used when the transceiver circuit (i.e., the TXRX mixed-signal circuit) where functional module 11 is located is working normally; the test clock of the test interface of test circuit 100 can be the test clock defined by the IEEE 1149.4 standard.

[0074] In its implementation, the access control unit 103 can simultaneously acquire the test clock from the test interface and the system operating clock from the transceiver circuit via a dedicated clock network. The system clock includes, but is not limited to, the baseband processing clock, the data converter's sampling clock, and the derived clock of the RF local oscillator.

[0075] When binding the test clock to the system operating clock, the test clock, which serves as the test control reference, can be synchronized with the system operating clock of the functional module 11 in terms of phase and frequency through the clock management circuit, thereby binding the test clock to the system operating clock.

[0076] After binding is completed, the effective edges of all test control signals issued by the access control unit 103 and analog signal acquisition via the test bus 101 can be aligned with the system operating clock of the functional module 11. In this way, it can be ensured that the waveforms acquired from the analog port and the data read from the digital module have a unified time stamp during end-to-end testing.

[0077] In one possible implementation, the access control unit 103 can determine the first action set corresponding to the link scan command, and send first control information to each analog boundary submodule 102 according to the first action set, so as to control the connection between the input and output pins of the isolation switch of each module and the test bus 101 to construct the first test link.

[0078] Each action in the first action set is used to indicate the connection between the input / output pins of the functional module 11 connected by the closed isolation switch of each module and the test bus 101.

[0079] In this implementation, the link scan command can be represented by the LINK_SCAN command in the above embodiments. The command code of this link scan command is 01. When the access control unit 103 receives the command code encoded as 01 through the test access port, it can identify it as a link scan command. Then, the access control unit 103 can read the configuration parameters of the link scan command, wherein the configuration parameters of the link scan command can be used to characterize the target link to be tested (transmit link, receive link, or dual link) and the test sampling rate.

[0080] After the access control unit 103 obtains the configuration parameters of the link scan command, it can generate a corresponding first action set based on the configuration parameters. This first action set can be a list containing several micro-instructions, each micro-instruction in the list uniquely pointing to a specific analog boundary submodule 102, and the instruction content of each micro-instruction can be to command the module isolation switch inside the corresponding analog boundary submodule 102 to perform a connection operation.

[0081] The access control unit 103 distributes the microinstructions from the first set of actions to all relevant analog boundary submodules 102 via its dedicated control bus. Upon receiving its specific microinstruction, each analog boundary submodule 102 immediately decodes its internal local control logic and drives the corresponding switch in its module isolation switch to close. Specifically, each module isolation switch closes the connection between the input terminal of its connected functional module 11 and the preceding circuit, and between its output terminal and the following circuit.

[0082] In this case, the input and output pins of all functional modules 11 complete the construction of the first test link through their respective closed module isolation switches.

[0083] In this way, by translating and executing a single link scan instruction as a global, synchronous hardware reconfiguration action, the cumbersome process of programming each boundary module separately multiple times in related technologies can be avoided. This allows the instruction to be converted into a usable test path within a single instruction cycle, thus improving testing efficiency.

[0084] In some embodiments, a first test signal from an external test source can be received through the test bus 101 and applied to the first test link. Then, a first test response signal generated when testing the first test link can be obtained from the test bus 101 through a test analysis device, and the link test result of the first test link can be determined based on the first test response signal.

[0085] The first test link is a transmit link or receive link composed of multiple functional modules 11 connected in series; the first test signal is applied to the input end of the first test link via the test bus 101; the first test response signal is the analog domain performance parameters and digital domain operating parameters output by the first test link; the test analysis equipment completes the fault screening of the first test link by comparing the first test response signal with the preset benchmark parameters.

[0086] In this embodiment, after the first test link is constructed, the external test equipment initiates the IEEE 1149.4 standard PROBE (Probe Instruction) command to perform real-time signal acquisition on the test link through the simulated test access port to obtain the first test response signal. Specifically, in the analog domain, the error vector amplitude and gain parameters of the output signal of the transmit link, as well as the noise figure and phase noise parameters of the input signal of the receive link, can be acquired; in the digital domain, the modulation timing parameters of the baseband digital module and the bit error rate parameters after sampling by the analog-to-digital converter can be acquired.

[0087] The first test response signal acquired can then be transmitted to the test analysis device via the test bus 101 to compare the acquired test parameters with preset benchmark thresholds. Specifically, if all test parameters are within the preset benchmark threshold range, it is determined that there are no link-level faults in the entire transmission and reception links, and the test diagnosis process ends; if at least one test parameter exceeds the preset benchmark threshold, it is determined that there is a link-level fault in the test link, and the subsequent module-level fault isolation step is initiated.

[0088] For example, taking the transmit link under test as an example, the error vector amplitude reference threshold of the transmit link can be 3%, and the gain reference threshold range can be 10dB±1dB. After the external test equipment completes the construction of the transmit link, it can start the PROBE command to collect signals from the link. If the measured value of the error vector amplitude of the transmit link is 4% and the measured value of the gain is 9.8dB in the first test response signal returned via the test bus 101, since the measured value of the error vector amplitude of 4% exceeds the preset reference threshold of 3%, while the gain parameter is within the normal range, the test analysis equipment determines that there is a link-level fault in the transmit link, and the test process enters the subsequent module-level fault isolation step.

[0089] If the measured value of the transmit link error vector amplitude M is 2.2%, the measured value of the gain is 10.1dB, and the parameters such as the receive link noise figure, phase noise, and digital domain bit error rate are all within the corresponding preset benchmark threshold range, then the test analysis equipment determines that both the transmit and receive links are working normally and there is no link-level fault, and the test and diagnosis process ends.

[0090] The above technical solution, relying on the standard 1149.4 test bus 101 and PROBE command to realize test signal transmission and parameter acquisition, is compatible with existing boundary scan test platforms and test equipment, and does not require the design of complex dedicated test interfaces for RF transceiver links. Moreover, by completing the test signal application and test response feedback through the test bus 101, it is possible to quickly determine whether there is a fault in the entire link, without the need for manual inspection, which greatly improves the efficiency of link-level fault screening.

[0091] Considering that when a fault is determined to exist in the entire link (such as the transmission link) through the link scanning command, the fault may originate from any module on the link. In order to accurately locate the specific failed functional module 11, in some embodiments, the target test command may also include a module isolation command.

[0092] The access control unit 103 can determine the second action set corresponding to the module isolation command, and according to the second action set, send second control information to the target simulation boundary submodule 102 and send first control information to other simulation boundary submodules 102 besides the target simulation boundary submodule 102, so as to control the module isolation switch of the target simulation boundary submodule 102 to disconnect the input and output pins of the target functional module from the test bus 101, so as to construct a second test link other than the target functional module.

[0093] The second set of actions includes a target action for instructing the target module isolation switch to disconnect the input / output pins of the target functional module from the test bus 101, and other actions for instructing the isolation switches other than the target module isolation switch to close and connect the input / output pins of the functional module 11 to the test bus 101; the target functional module is any one of the multiple functional modules 11.

[0094] In this embodiment, the module isolation instruction can be the MODULE_ISOLATE instruction from the above embodiment. The instruction code of this module isolation instruction is 10. When the access control unit 103 receives the instruction code coded as 10 through the test access port, it can identify it as a module isolation instruction. Then, the access control unit 103 can read the configuration parameters of the module isolation instruction, wherein the configuration parameters of the module isolation instruction can be used to characterize the unique identifier of the target functional module. Specifically, its high 4 bits (bits [7:4]) are used to characterize the module type, for example, 0001 represents a low noise amplifier and 0010 represents a bandpass filter; its low 4 bits (bits [3:0]) are used to characterize the specific module instance ID under this type, for example, 0001 represents the first low noise amplifier and 0010 represents the second low noise amplifier.

[0095] After the path reconstruction unit 103 obtains the configuration parameters of the module isolation instruction, the path control unit 103 can generate a corresponding second action set according to the configuration parameters of the module isolation instruction. This second action set can be a list containing several micro-instructions, each micro-instruction uniquely pointing to a specific analog boundary submodule 102. Specifically, for the target functional module, the instruction content of the micro-instruction can be to control the target functional module to switch to a bypass state; for other functional modules 11 besides the target functional module, the micro-instruction can maintain the connection state.

[0096] The path control unit 103 can distribute the micro-instructions in the second action set to all relevant analog boundary sub-modules 102. After receiving its own micro-instruction, each analog boundary sub-module 102 can decode the micro-instruction through its internal local control logic and drive the corresponding switch in its module isolation switch to perform the operation corresponding to the micro-instruction. Specifically, the input / output pins of the target functional module are isolated from the test bus 101, and the bypass path in the analog boundary sub-module 102 corresponding to the target functional module is turned on to ensure that the target functional module is bypassed from the test bus 101, so that the signal flow can still be continuously transmitted to the downstream functional module 11 after bypassing the target functional module; while other functional modules 11, except for the target functional module, continue to work normally in the test bus 101 and are not affected by this isolation operation.

[0097] In this case, the input and output pins of the other functional modules 11, excluding the target functional module, complete the construction of the second test link through their respective closed module isolation switches.

[0098] In one possible implementation, the second set of actions may further include a clock synchronization microinstruction, which can be used to instruct all the aforementioned microinstruction control signals for the analog boundary submodule 102 to be enabled simultaneously at a preset synchronization clock edge. For example, all the aforementioned microinstruction control signals for the analog boundary submodule 102 can be enabled simultaneously at the synchronization edges of the bound test clock and the system operating clock.

[0099] This ensures that the state switching of all simulated boundary submodules 102 is an atomic operation, thereby avoiding signal transient interruptions, race conditions, or glitches caused by asynchronous switching during the reconfiguration process, and thus guaranteeing the electrical integrity of the test link and the accuracy of the test results.

[0100] In some embodiments, a second test signal from an external test source can be received through the test bus 101 and applied to the second test link. Then, a second test response signal generated when testing the second test link can be obtained from the test bus 101 through a test analysis device, and the module test result for the target functional module can be determined based on the second test response signal.

[0101] The second test link is a link consisting of multiple functional modules 11 connected in series, excluding the target functional module. The second test signal is applied to the input of the second test link via the test bus 101. The second test response signal is the analog domain performance parameters and digital domain operating parameters output by the second test link. The test analysis equipment completes the link-level fault screening of the second test link by comparing the second test response signal with the preset benchmark parameters. Then, based on the link-level fault screening of the second test link, it can determine whether the target functional module is a faulty module.

[0102] In this embodiment, after the second test link is constructed, the steps for testing the second test link can refer to the steps for testing the first test link in the above embodiment, and the specific details will not be repeated here.

[0103] If all test parameters of the second test link are determined to have returned to the preset baseline threshold range, it indicates that the performance of the entire link has returned to normal after the target functional module is removed. Therefore, the isolated target functional module can be identified as the faulty module causing the initial link-level failure. If at least one of the test parameters of the second test link is still found to exceed the preset baseline threshold, it indicates that the fault has not been eliminated by isolating the target functional module, and the source of the fault remains within the remaining modules in the link. In this case, it can be determined that the isolated target functional module is not the faulty module, and the diagnostic process will return to selecting another module on the link as the new target functional module for isolation and testing until the true faulty module is located.

[0104] By adopting the above technical solution, the specified target functional module is isolated from the test bus 101, and then the remaining links after isolation are tested one by one. By comparing the link-level test results of each module before and after isolation, the fault range can be gradually narrowed down by elimination. The fault can be accurately located from the entire link to the specific failed functional module 11, thereby improving the accuracy of fault diagnosis.

[0105] In some embodiments, when a faulty module is identified from multiple functional modules 11, the access control unit 103 may also receive a pin test command for the faulty module; and in response to the pin test command, send third control information to the analog boundary submodule 102 corresponding to the faulty module to control the analog boundary submodule 102 corresponding to the faulty module to switch to pin test mode, and when the analog boundary submodule 102 switches to pin test mode, the input and output pins of the faulty module can be connected to the test bus 101 through the pin test interface.

[0106] The pin test instruction can be a predefined pin test instruction, such as the PIN_TEST instruction with a specific opcode.

[0107] In this embodiment, when a pin test command such as PIN_TEST is issued via an external test device, the access control unit 103 can parse the pin test command and generate corresponding third control information based on the configuration parameters it contains. This third control information can be sent to the analog boundary submodule 102 connected to the fault module.

[0108] Upon receiving the third control information, the simulated boundary submodule 102 can be configured to pin test mode. Specifically, the simulated boundary submodule 102 connects all the input / output pins under test of the faulty module to the test bus 101. Thus, external test equipment can access each pin of the faulty module through the test bus 101.

[0109] In this embodiment, a third test signal from an external test source can be received through the test bus 101, and the third test signal can be applied to each pin of the faulty module. Then, the third test response signal generated when testing the faulty module can be obtained from the test bus 101 through the test analysis device, and the pin test result for each pin of the faulty module can be determined based on the third test response signal.

[0110] In practical applications, external testing equipment can send pin test commands and their configuration parameters to the access control unit 103 through the test bus 101. The access control unit 103 parses the command, generates a control signal, and configures the analog boundary submodule 102 corresponding to the fault module into pin test mode, thereby connecting the pins of the fault module to the test bus 101 through the pin test interface of the corresponding analog boundary submodule 102.

[0111] External test equipment can initiate standard test algorithms via internal test bus 101 to apply test stimuli to the pins of the faulty module and collect responses.

[0112] Specifically, external test equipment can follow the impedance measurement procedure defined by the IEEE 1149.4 standard, injecting a known reference current (e.g., 100μA) into the target pin through a simulated test access port as the first test stimulus. Simultaneously, the test analysis equipment can measure the response voltage generated on the pin and calculate the pin's dynamic impedance according to a preset algorithm.

[0113] External test equipment can also execute the EXTEST instruction (ExtestInstruction) from the IEEE 1149.4 standard, applying a preset digital test vector to the target pin via test bus 101 as a second test stimulus. Simultaneously, the actual logic level output by the pin is captured by the corresponding digital boundary module as a response to the stimulus.

[0114] The test analysis equipment can extract the actual impedance value and actual logic state of the pin from the response data, and automatically compare the extracted measured parameters with pre-stored reference parameters. The reference parameters include the pin's nominal impedance tolerance range and the expected logic state. For example, the pin's nominal impedance tolerance range could be 50Ω ± 10%, and the expected logic state could include high level, low level, or high impedance state.

[0115] If the measured impedance of a pin is higher than the open circuit threshold, it can be determined that the pin has an open circuit fault; if the measured impedance is lower than the short circuit threshold, it can be determined that the pin has a short circuit fault; if the measured impedance or logic state is within the reference tolerance, it can be determined that the pin is functioning normally.

[0116] By adopting the above technical solution, the fault location accuracy can be improved to the pin level of functional module 11, which can improve the accuracy of fault detection.

[0117] In some embodiments, Figure 3 This is a schematic diagram of a test circuit provided in an embodiment of this application. Figure 3 ,like Figure 3As shown, the test bus 101 includes a multi-channel bus interface circuit 104; the bus interface circuit 104 includes multiple input terminals and multiple output terminals. The input terminals are used to connect to multiple analog boundary submodules 102, and the output terminals are used to connect to test and analysis equipment.

[0118] The bus interface circuit 104 can configure the connection between the input and output terminals based on the target test command, so as to route the signal from the input terminal to the corresponding test and analysis equipment.

[0119] In this embodiment, the bus interface circuit 104 can be implemented using a switch matrix, specifically, a multi-input multi-output analog crossbar switch network. The bus interface circuit 104 can include multiple independent input and output terminals, with its input terminals connected to various analog boundary submodules 102. When an analog boundary submodule 102 responds to a test command and connects its monitored functional module 11 to the test state, the signal under test of that functional module 11 can be connected to a designated input terminal of the bus interface circuit 104 via test wires. In this way, the bus interface circuit 104 can access observable signal sources of different locations and types within the transceiver circuit.

[0120] Accordingly, the multiple outputs of the bus interface circuit 104 can be connected to the pins of multiple external test interfaces, each of which can be connected to different test and analysis devices. For example, the external test interfaces may include standard-compliant analog test access ports or high-speed digital input / output interfaces. Each output can be independently connected to a test and analysis device, such as a vector signal analyzer, oscilloscope, or logic analyzer. The bus interface circuit 104 can configure the connection relationship between the input and output terminals according to the configuration commands sent by the path control unit 103, thereby establishing an electrical path between any input port and any output port.

[0121] Specifically, the bus interface circuit 104 may include a crosspoint array composed of multiple switch units. Each crosspoint switch is driven by an independent control signal, and the on / off state of each crosspoint switch collectively determines the connection topology between the input and output terminals. After parsing the test commands from the outside, the path control unit 103 generates a corresponding switch matrix configuration word according to the semantics of the command. This configuration word is loaded into the control logic of the switch matrix, and under the drive of a specific synchronous clock edge, updates the state of all relevant crosspoint switches, thereby dynamically establishing one or more signal paths from a selected internal signal source to a specified external test interface.

[0122] For example, after receiving a link test command (such as a LINK_SCAN command), the access control unit 103 can generate two sets of coordinated micro-instructions. One set of micro-instructions is sent to the relevant analog boundary submodule 102, commanding it to connect the target functional node to the internal test bus 101. The other set is issued to the bus interface circuit 104 as a configuration word. After the configuration word is loaded, the cross-switch network inside the bus interface circuit 104 can reconfigure the connection state. For example, the signal of the "transmit channel power amplifier output" node can be routed to port 1 (to connect an external spectrum analyzer to measure spectrum regeneration), the "receive channel low-noise amplifier bias current" reading can be routed to port 2 (to connect an external precision source meter), and the "baseband processor real-time bit error rate status word" can be routed to port 3 (to connect an external logic analyzer).

[0123] By adopting the above technical solution, on the one hand, the test path can be flexibly reconstructed through test commands without changing the physical connection, which improves the flexibility and automation of the test system; on the other hand, it enables the simultaneous acquisition of data from different functional modules or instruments during a single test, realizing the parallel transmission of multiple signals and shortening the overall test time.

[0124] In some embodiments, Figure 4 This is a schematic diagram of a test circuit provided in an embodiment of this application. Figure 4 ,like Figure 4 As shown, the test circuit 100 also includes a digital boundary module 105 connected to the test analysis equipment. The digital boundary module 105 includes a fault status register group and a read interface. The digital boundary module 105 can store the test results in the fault status register group and make the test results available for external access using the read interface.

[0125] The test results include one or more of the following: link test results, module test results, and pin test results.

[0126] In this embodiment, the fault status register group can be a set of dedicated registers that correspond one-to-one with the link test results, module test results, and pin test results.

[0127] Specifically, this register group may include a link fault flag register. Each bit of the link fault flag register can be predefined as a fault flag corresponding to a specific functional link (such as a transmit link or a receive link). For example, when the test analysis device completes the test corresponding to the LINK_SCAN instruction and determines that a link has a performance fault, it can set the flag bit corresponding to that link. For example, bit 0 set to '1' indicates a transmit link fault, and bit 1 set to '1' indicates a receive link fault.

[0128] This register group may also include a module fault ID register. After a specific faulty module is located through the elimination method using instructions such as MODULE_ISOLATE, the test analysis device or the channel control unit 103 will write the unique identification code of the faulty module into the module fault ID register. The code may include the module type and instance number; for example, 0101 represents a low-noise amplifier, and 001 represents the first low-noise amplifier.

[0129] This register set may also include a pin fault code register. After pin-level testing is completed, this register stores the pin-level test results of functional module 11. The pin fault code register can include the faulty pin number, fault type, and measured electrical parameter value. For example, a 32-bit register can store the pin address in the high 16 bits, the fault type code in the middle 4 bits, and the measured electrical parameter value in the low 12 bits.

[0130] In practical applications, the fault status register group can be accessed via an extended boundary scan chain and the TDI (Test Data Input) / TDO (Test Data Output) ports. When test results need to be read from the fault status register group, a test result read command can be sent through the TAP controller, concatenating the data path stored in the fault status register group into the scan chain between TDI and TDO. In data register capture mode, the data in the fault status register group is serially shifted to the TDO pin output; upon completion of the data register update operation, the data in the fault status register group is updated with the new test results.

[0131] By adopting the above technical solution, the test results can be non-volatilely latched, allowing the fault conclusions to be retrieved even after the test process is completed, so as to facilitate problem reproduction. Moreover, the diagnostic results are converted into structured coded output, enabling external hosts or automated testing equipment to quickly obtain clear diagnostic reports through simple and standardized read operations, simplifying the upper-level logic of the test software and improving the efficiency of automated testing.

[0132] In some embodiments, Figure 5 This is a schematic diagram of a test circuit provided in an embodiment of this application. Figure 5 ,like Figure 5 As shown, the test circuit 100 also includes a fault reference fingerprint library unit 106, and the test analysis equipment is connected to the test bus 101 and the fault reference fingerprint library unit 106 respectively.

[0133] In this embodiment, the fault reference fingerprint library unit 106 can store test reference parameters; the test analysis device can obtain the test response signal generated when performing signal testing on at least one functional module 11 from the test bus 101, and compare and analyze the test response signal with the pre-stored reference parameters to obtain the test results of the transceiver circuit.

[0134] The test results include one or more of the following: link test results, module test results, and pin test results.

[0135] The fault baseline fingerprint library unit 106 can be a non-volatile memory module integrated into or connected to the transceiver circuit, which stores multi-dimensional and multi-level standard performance data obtained from design and process angle simulations or actual tests on known good samples. The fault baseline fingerprint library unit 106 can establish a data path with test and analysis equipment.

[0136] The reference parameters stored in the fault reference fingerprint library unit 106 can include key performance characteristics of the transceiver circuit at three levels: link level, module level, and pin level, such as link-level reference fingerprint, module-level reference fingerprint, and pin-level reference fingerprint.

[0137] Specifically, the link-level reference fingerprint may include, but is not limited to, the ideal output waveform data of the complete transmit and receive links under standard modulation signal excitation, the statistical distribution limit of the error vector amplitude, the noise figure and sensitivity threshold of the receive link, and the nominal values ​​and tolerance ranges of the overall gain and power.

[0138] The module-level benchmark fingerprint may include, but is not limited to, the deep parameter models or feature curves such as the input-output transfer function, linearity index, bandwidth, group delay characteristics, and noise spectral density corresponding to each functional module 11.

[0139] Pin-level reference fingerprints may include, but are not limited to, the standard electrical characteristics of each input / output pin of each functional module 11 in DC and AC states, including but not limited to DC input impedance, capacitance to ground, voltage threshold of logic level, output drive capability curve, and standard impedance reference values ​​for interconnect testing.

[0140] In this embodiment, when a test command (such as LINK_SCAN, MODULE_ISOLATE, PIN_TEST) is executed and the corresponding test response signal is acquired through the test bus 101, the test analysis device automatically retrieves the corresponding baseline parameters from the fault baseline fingerprint library unit 106 based on the currently executed test level. For example, when performing a link scan, the link-level fingerprint is retrieved; when performing isolation testing on a specific module, the module-level fingerprint of that module is retrieved. Subsequently, the test analysis device compares and analyzes the measured test response signal with the retrieved baseline parameters to obtain the test results for the corresponding test level.

[0141] In related technologies, pass / fail decisions typically rely on simple parameter thresholds, which struggle to detect correlational anomalies and gradual performance changes. However, the aforementioned technical solution, through a fault benchmark fingerprint library unit storing complete feature models and nominal data for each level of the link, module, and pin, allows for intelligent comparison of real-time test data with corresponding multi-dimensional benchmark fingerprints using test analysis equipment. This not only detects out-of-limit faults but also identifies potential defects and performance degradation trends such as feature deviations and related parameter imbalances. It transforms testing from static threshold checks to dynamic feature matching, improving fault diagnosis accuracy.

[0142] Based on the foregoing embodiments, this application provides an integrated circuit, which includes multiple functional modules and the aforementioned test circuit.

[0143] Figure 6 This is a flowchart illustrating a testing method for an integrated circuit provided in an embodiment of this application, as shown below. Figure 6 As shown, this method is applied to a test circuit used to test functional modules in an integrated circuit. The method includes the following steps.

[0144] Step S201: In response to the target test command, control the connection status between the connected functional modules and the test bus through each analog boundary submodule in the test circuit.

[0145] Step S202: Through the test bus, at least one functional module connected to the test bus is tested and analyzed based on the test signals from an external test source to obtain test results.

[0146] By adopting the above technical solution, by independently configuring a simulation boundary submodule for each functional module inside the integrated circuit, each simulation boundary submodule can control the connection status between the connected functional module and the test bus, enabling more detailed internal testing of the functional modules in the integrated circuit, thereby improving the accuracy and efficiency of integrated circuit fault diagnosis.

[0147] In the embodiments of this application, specific implementation methods can be referred to the description of any of the foregoing test circuits. The descriptions of the above method embodiments are similar to the descriptions of the above test circuit embodiments, and have similar beneficial effects as the test circuit embodiments. For technical details not disclosed in the method embodiments of this application, please refer to the description of the test circuit embodiments of this application for understanding.

[0148] The following describes the application of the test circuit provided in the embodiments of this application in a real-world scenario, mainly involving a fault diagnosis device and method for a transmit-receive mixed-signal circuit based on IEEE 1149.4 extension.

[0149] Currently, mixed-signal transceiver circuits (i.e., transmit / receive circuits) serve as core functional units in modern communication systems. They highly integrate various heterogeneous functional modules, including baseband digital modules, digital-to-analog converters, analog front-ends (containing low-noise amplifiers, bandpass filters, mixers, etc.), analog-to-digital converters, and antenna interfaces. This complex circuit architecture, with its mixed-signal processing link, leads to a wide variety of fault types in practical applications.

[0150] These faults can be mainly categorized into three levels: First, link-level faults, which manifest as abnormal signal transmission caused by coupling distortion and timing mismatch between digital and analog links, such as excessive error vector amplitude in the transmit link or increased bit error rate in the receive link; Second, module-level faults, which refer to parameter drift or complete functional failure of a single functional module, such as gain attenuation of the low-noise amplifier, filter bandwidth shift, or no output of the digital-to-analog converter or sampling distortion of the analog-to-digital converter; Third, pin-level faults, which involve open circuits, short circuits, abnormal logic levels of the module's input / output pins, and interconnection failures between the pins and the printed circuit board.

[0151] Testing of such circuits currently relies primarily on solutions based on the IEEE 1149.4 standard. However, this existing technology has significant technical limitations, failing to meet the urgent need for refined and localized fault diagnosis of transceiver circuits. The primary drawback lies in the limitations of its test architecture: such as... Figure 7As shown, the analog boundary modules defined in the standard are typically configured only at the overall input / output pins of the integrated circuit chip (i.e., the chip containing the transceiver circuit), without designing independent, electrically isolated test access units for each internal core functional module. This makes it impossible to isolate specific internal modules from the complete signal link for accurate testing. When the link performance is abnormal, fault location can only remain at the macroscopic level of the "link level," and cannot further pinpoint the specific functional module causing the fault. Secondly, there are deficiencies in pin testing capabilities: existing solutions mainly use general boundary scan instructions to detect open or short circuits in pin interconnects, failing to combine this with in-depth measurement of analog signal parameters (such as impedance and signal amplitude), thus making it difficult to achieve correlation diagnosis and effective differentiation between pin faults and internal circuit faults within the module. Thirdly, a digital-analog co-testing mechanism is lacking: the existing architecture does not design a synchronous test mechanism for the inherent closed-loop link of "digital control-analog signal processing-digital sampling" in the transmit and receive circuits, making it difficult to diagnose cross-domain coupling faults such as analog parameter abnormalities caused by digital timing deviations. Furthermore, its instruction set is incomplete: it currently relies mainly on several basic instructions specified by the IEEE 1149.4 standard, lacking dedicated instructions for advanced diagnostic scenarios such as module isolation and pin-specific testing. The configuration and execution of the test process often require significant manual intervention, resulting in low automation. Finally, a benchmark comparison system is missing: the solution does not integrate standardized parameter benchmark storage and automated comparison mechanisms. Test data analysis and fault determination rely on human experience, leading to low diagnostic efficiency and limited accuracy.

[0152] In other words, although the IEEE 1149.4 standard itself possesses core capabilities such as analog signal access, boundary scan control, and impedance measurement, related technologies have failed to deeply extend its architecture, instruction set, and data processing logic to suit the characteristics of transmit and receive circuits. It has also failed to fully exploit its potential capabilities in modular isolation and precise parameter acquisition. Consequently, its accuracy, efficiency, and automation in fault diagnosis cannot meet the stringent testing requirements of industrial-grade high-performance transmit and receive circuits. Therefore, an innovative testing architecture and method are urgently needed to overcome these shortcomings and achieve systematic and refined fault diagnosis from the link and module levels to the pin level.

[0153] The embodiments of this application can achieve precise fault location at the module level and pin level by extending the hardware structure and instruction logic of the IEEE 1149.4 standard, so as to solve the problems of low fault location accuracy, difficult module isolation, poor digital-analog coordination and low degree of automation in the existing IEEE 1149.4-based transmitter and receiver circuit test schemes.

[0154] In this embodiment, based on the IEEE 1149.4 standard, refined fault diagnosis can be achieved through architecture extension, instruction addition, and benchmark comparison. Specifically, devices such as TDI / TDO / TCK / TMS (digital test pins), AT1 / AT2 (analog test pins), ABM (analog boundary module), DBM (digital boundary module), and TBIC (bus interface circuit) in existing integrated circuits can be retained.

[0155] In some embodiments, for highly integrated functional modules within the transmit and receive circuits, the design in related technologies that places analog boundary modules only on the input / output pins of the integrated circuit chip can be modified to obtain a design in which a dedicated analog boundary submodule is independently configured at the input and output ports of each core functional module. Each analog boundary submodule includes a module isolation switch and a pin test interface.

[0156] Specifically, the module isolating switch can be implemented using an analog switch array, which can, under command control, atomically and electrically isolate or reconnect the connected functional modules from the main signal path. The pin test interface can be directly coupled to the specific physical pins of the functional modules. The pin test interface can also integrate a programmable attenuation / buffer network and a high-impedance input front end, which not only supports the detection of digital logic states, but also directly performs AC / DC signal amplitude acquisition, impedance spectrum measurement, and timing waveform capture, realizing in-depth electrical characteristic analysis of the pin's own performance and its external interconnection status.

[0157] In some embodiments, the test circuit of this application may also include a dedicated fault status register group for fault information management in the digital boundary module. This fault status register group may include multiple dedicated registers such as link fault status words, module fault identifiers, and detailed pin fault codes. These registers can automatically latch diagnostic results at each level during the test process.

[0158] Specifically, when a link scan detects a performance failure, the corresponding link flag is set; when a module isolation test locates a fault source, the module's hardware ID is written to a designated register; and after a pin test is performed, the specific fault type, pin coordinates, and measured electrical parameters are encoded and stored.

[0159] Furthermore, the fault status register group can be accessed via an extended boundary scan chain and the TDI (Test Data Input) / TDO (Test Data Output) ports. When test results need to be read from the fault status register group, a test result read command can be sent through the TAP controller, concatenating the data path stored in the fault status register group into the scan chain between TDI and TDO.

[0160] In some embodiments, the switch matrix in the bus interface circuit of the related art can be modified into a large-scale programmable cross switch network with 16×16 or higher channels. Its inputs can simultaneously receive internal node signals from multiple analog boundary submodules, as well as outputs from various dedicated measurement instruments integrated on-chip; its outputs can be flexibly configured to connect multiple external high-precision measurement devices. This switch matrix can route multiple internal test signals in parallel to different external analysis instruments, enabling synchronous, multi-dimensional data acquisition and analysis across multiple circuit nodes for a single excitation or under the same operating condition.

[0161] In some embodiments, a path control unit can be added to the test circuit of this application. Traditional TAP controllers can only process standard instructions, while the path control unit can recognize and execute extended instruction sets designed for the characteristics of transmit and receive circuits. When receiving specialized test instructions such as LINK_SCAN, MODULE_ISOLATE, or PIN_TEST via the TAP, these instructions can be translated into micro-operation sequences at the hardware level. These micro-operation sequences can be directly converted into control signals for the switch matrices within each analog boundary submodule, configuration commands for the digital boundary module, and synchronous trigger signals for internal or external test instruments. This compresses complex operations that originally required multiple software interventions and sequential execution into single-instruction-driven, atomic hardware operations, greatly improving the speed of test configuration and execution.

[0162] In one possible implementation, to ensure a strict timing correspondence between digital control, analog signal generation, and acquisition, the path control unit also includes a clock management circuit. This circuit can phase- and frequency-bind the test clock used in the IEEE 1149.4 standard with the critical system operating clock of the transmit / receive circuit. This ensures that all test control signals and data acquisition trigger signals emitted are precisely aligned with the actual operating cycle of the target functional module.

[0163] In practical applications, the path control unit can send configuration commands to the switch matrix of the bus interface circuit and all related analog boundary submodules. For example, when executing the LINK_SCAN command, it can control the module isolation switches of all analog boundary submodules to close and configure the TBIC to connect the main signal path to the test and analysis equipment, thereby constructing the overall link test path. As another example, when executing the MODULE_ISOLATE command, it can control the analog boundary submodules of the target functional module to isolate it and simultaneously configure the analog boundary submodules of adjacent modules to establish bypasses, forming a test path after the specific module is isolated.

[0164] In this embodiment, extended test instructions can be constructed based on the TAP state machine of the IEEE 1149.4 standard. The instruction format of the extended test instructions can be represented as "2-bit instruction code + 8-bit configuration parameters + N-bit data". Specifically, test instructions as shown in Table 1 can be constructed.

[0165] In some embodiments, the test circuit of this application may also integrate a fault reference fingerprint library unit and a signal acquisition and analysis unit.

[0166] The fault reference fingerprint library unit is a non-volatile parameter storage and management system. Its core function is to pre-store multi-level parameter fingerprint references that characterize the transmitting and receiving circuits and their internal components under normal and tolerant operating conditions.

[0167] Specifically, the storage content of the fault baseline fingerprint database unit can be divided into three levels. First, at the link level, it can store the overall performance parameters of the transmit and receive links, including the nominal gain range, the acceptable threshold for error vector amplitude, the upper limit of bit error rate, and the critical timing synchronization deviation limit. Second, at the module level, it stores the detailed performance specifications of each independent functional module, such as the gain value and fluctuation tolerance of the low-noise amplifier, the 3dB bandwidth and offset range of the filter, the upper limit of the conversion delay of the data converter, and the sampling accuracy and linearity indicators of the analog-to-digital converter. Third, at the pin level, it can define the nominal interconnect impedance and tolerance of each input / output pin, and the voltage thresholds for logic high / low levels.

[0168] The signal acquisition and analysis unit (i.e., the test analysis device in the above embodiments) can be directly connected to the test bus, especially the analog test access port. Its front end integrates an on-chip analog signal conditioning module, such as a low-noise amplifier and an anti-aliasing filter, used to amplify, filter, and shape the raw analog signal acquired from the analog test access port to optimize signal quality and improve the signal-to-noise ratio and accuracy of subsequent processing. Its back end can have a dedicated digital signal processing hardware module built in. This processing module receives the conditioned and digitized signal and executes digital signal processing algorithms. It can be used to calculate performance parameters in the acquired signal in real time, such as error vector magnitude, phase noise spectrum, gain deviation, and spectral template margin.

[0169] After calculation, the processing module can call the corresponding hierarchical benchmark parameters in the fault benchmark fingerprint library unit, compare and analyze the real-time calculated parameter values ​​with the pre-stored benchmark values, and generate a structured parameter deviation report based on a preset decision algorithm. This parameter deviation report can not only indicate whether a parameter exceeds the limit, but also quantify its degree and trend of deviation from the benchmark, thereby realizing the transformation from data acquisition to intelligent diagnosis and improving the autonomous decision-making ability and diagnostic efficiency of the testing system.

[0170] Figure 8 This is a flowchart of a fault diagnosis method provided in an embodiment of this application, such as... Figure 8 As shown, the method includes the following steps.

[0171] Step S301, Test initialization and benchmark loading.

[0172] In this step, the external test equipment sends an initialization command to the access control unit via the IEEE 1149.4 standard test access port. In response to this initialization command, the access control unit generates a trigger signal. This trigger signal drives the fault reference fingerprint library unit to load pre-stored link-level, module-level, and pin-level parameter fingerprint reference values ​​corresponding to the current transmit / receive circuit under test from its non-volatile memory, providing a reference for subsequent automated comparison. This trigger signal also enables the signal acquisition and analysis unit to complete a power-on self-test, ensuring that its internal analog conditioning and digital processing modules function normally. At the same time, the connected on-chip and off-chip test instruments are configured and connected to the test bus through the bus interface circuit, and the entire test system then enters a standby ready state, awaiting subsequent test commands.

[0173] Step S302, link-level fault screening.

[0174] In this step, the external test equipment sends a LINK_SCAN command via the test bus. In response to this command, the path control unit parses its encoding and generates the corresponding coordination control signal. This unit controls all relevant analog boundary submodules, configuring their module isolation switches to the connected state, thereby establishing a full-link transmit and full-link receive signal path.

[0175] Subsequently, the test system automatically initiates the PROBE command conforming to the IEEE 1149.4 standard. Through the simulated test access port, real-time signal acquisition and parameter extraction are performed on the constructed complete link. In the analog domain, the error vector magnitude and gain of the transmit link output signal, as well as the noise figure and phase noise of the receive link input signal, are acquired and calculated. In the digital domain, the modulation timing parameters of the baseband digital module and the bit error rate data sampled by the analog-to-digital converter are read and obtained through the digital boundary module. All acquired raw parameters are transmitted to the signal acquisition and analysis unit in real time.

[0176] After receiving data, the signal acquisition and analysis unit immediately calls the loaded corresponding link-level reference fingerprint and automatically compares and judges the real-time acquired parameters with the pre-stored reference thresholds. If all parameters are within their corresponding reference threshold ranges, the unit generates a judgment result indicating no link-level fault, and the diagnostic process ends. If any parameter exceeds the reference threshold, for example, if the measured transmit link error vector amplitude is 4%, exceeding the 3% reference threshold, the unit determines that a link-level fault exists and automatically generates a trigger signal to drive the diagnostic process to the next stage of module-level fault isolation and location operations.

[0177] Step S303: Module-level fault isolation.

[0178] In this step, after determining that a link-level fault exists, the external test equipment sends a module isolation command to the path control unit. In response to this command, the path control unit begins executing a systematic module-level fault location process according to preset module test logic. This unit iteratively isolates and tests each functional module on the link in a predefined order.

[0179] In each iteration, the path control unit generates specific control signals to precisely control the simulated boundary submodule corresponding to the current target module, configuring its module isolation switch to the open state, thereby electrically isolating the target module from the core signal path. Simultaneously, it controls the simulated boundary submodules of the remaining functional modules to remain connected, constructing a functional link excluding the current target module. Subsequently, the path control unit automatically triggers a simplified link test procedure, which reuses the core acquisition function of the link scan command but applies test stimuli to the remaining functional links and acquires their performance parameters.

[0180] The signal acquisition and analysis unit compares the remaining link parameters (such as error vector magnitude) acquired in this instance with the link-level benchmark values ​​in the fault benchmark fingerprint database in real time. If the comparison result shows that the performance parameters of the remaining link recover to within the normal benchmark threshold after isolating the target module, the currently isolated module is determined to be the faulty module, and the localization process terminates. If the parameters still exceed the benchmark threshold, it indicates that the fault point is not in this module. The access control unit will automatically restore the connection of the current module and set the next module as the target module according to a preset order, repeating the above process of isolation, building the remaining link, testing, and comparison until the functional module causing the abnormal link performance is uniquely located.

[0181] After successfully locating the faulty module, the access control unit generates a unique identification code for that module and writes it into a dedicated module fault identification register in the digital boundary module. For example, when the low-noise amplifier is determined to be a faulty module, its corresponding predefined code will be stored in this register, locking the diagnostic conclusion in the form of hardware status, which can then be read by external systems through a standard test interface, thereby completing the automated and accurate location and status reporting of module-level faults.

[0182] Step S304, pin-level fault location.

[0183] In this step, after accurately locating the faulty module, the external test equipment sends a pin test command to the access control unit. In response to this command, the access control unit executes a refined pin diagnostic process. First, the unit controls the analog boundary submodule corresponding to the faulty module to switch to pin test mode, which allows it to establish a direct electrical connection with all input / output pins of the module.

[0184] Subsequently, the access control unit can initiate an impedance measurement process compliant with the IEEE 1149.4 standard. This involves injecting a precisely defined reference current into the target pin through a simulated test access port, simultaneously measuring the pin voltage, and calculating its dynamic impedance according to a preset algorithm. At the same time, a standard boundary scan test command is executed, applying a digital test vector to the pin and capturing its response to verify its logic level state.

[0185] The signal acquisition and analysis unit receives test data and uses the reference parameters of the corresponding pin in the fault reference fingerprint library for real-time, automatic comparison. Based on a preset decision algorithm: if the measured pin impedance approaches infinity and significantly deviates from its nominal impedance reference value, it is determined to be an open-circuit fault; if the measured impedance is far below the nominal value, it is determined to be a short-circuit fault; if the captured logic level state does not match the expected vector, it is determined to be a pin logic fault.

[0186] After completing all pin tests and analyses, the access control unit writes the final determined physical number of the faulty pin, the specific fault type code, and other relevant electrical parameters into a dedicated pin fault code register in the digital boundary module.

[0187] Step S305: Output the fault result and restore the path.

[0188] In this step, after completing the aforementioned layered diagnostic process, the external test equipment can access and read all the diagnostic information latched in the fault status register group of the digital boundary module through the test data output port. This information includes link fault identifiers indicating macroscopic anomalies, module fault identification codes for precise location, and detailed pin fault codes at the finest granularity. Based on this structured data directly obtained from the hardware, the host computer software of the external test equipment can automatically parse and generate a visualized diagnostic report containing fault location paths, fault type descriptions, and key parameter deviations, thereby completing the final conversion from the chip's internal state to user-readable conclusions.

[0189] After the diagnostic report is generated, the external test equipment sends a system recovery command to the path control unit. In response to this command, the path control unit generates a global reset control signal and performs a cleanup operation: controlling all analog boundary submodules and digital boundary modules to switch their internal switch configurations and operating modes back to their initial normal operating state; and simultaneously controlling the bus interface circuit to disconnect all test instruments from the internal bus. Ultimately, the signal path of the entire transmit / receive circuit is completely reconstructed into a standard communication function path, and the integrated circuit fully restores its normal wireless transceiver communication function, ensuring that the test activities do not interfere with the subsequent operation of the system.

[0190] In some embodiments, the hierarchical diagnostic process is driven by extended, dedicated instructions, each adhering to strict clock synchronization timing to ensure determinism and repeatability of operation. The following details the hardware execution timing of three core extended instructions in the test circuit, using them as examples.

[0191] Example 1: Link scanning command.

[0192] The link scan instruction is encoded as 01. This instruction contains 8 bits of configuration parameters, where the high 4 bits are used to select the target link and the low 4 bits are used to configure the test sampling rate. Its execution timing strictly follows the clock edge of the TCK (clock signal) of the test access port.

[0193] Specifically, during the SHIFT-IR (instruction shift state) phase, the external test equipment shifts 8 bits of serial data containing the instruction code into the instruction register via the TDI (data input) pin over 8 consecutive TCK cycles, during which the TMS (control signal) signal remains low. At the end of the 8th TCK cycle, the TMS signal goes high, driving the TAP controller state machine to switch to the EXECUTE-IR (instruction execution state).

[0194] During the EXECUTE-IR (Instruction Execution State) phase, the path control unit completes hardware decoding of the instruction code within the first TCK cycle. Subsequently, it generates a synchronization trigger signal precisely synchronized with the rising edge of the second TCK. This signal simultaneously controls all relevant analog boundary submodules, atomically switching their module isolation switches to the connected state, thereby reconstructing a complete transmit or receive link test path in hardware.

[0195] During the signal acquisition and processing phase, the channel control unit initiates signal acquisition according to the configuration parameters. For example, a preset benchmark test signal is injected through the AT1 (analog signal) port, and the link response is synchronously acquired through the AT2 (analog signal 2) port. This phase lasts for N TCK cycles, where N is determined by the sampling rate in the configuration parameters. After acquisition is completed, the internal flag signal is set high.

[0196] During the CAPTURE-DR (data capture state) phase, one TCK cycle is used to convert the acquired and processed key parameters of the analog and digital domains into digital data in a fixed format and latch them into the data register.

[0197] Finally, during the SHIFT-DR (data shift state) phase, the latched result data is serially shifted out via the TDO pin over multiple consecutive TCK cycles for external devices to read. At the end of the 16th TCK cycle, the TMS signal is set high, the state machine returns to the idle state, and a single link scan is completed.

[0198] Example 2: Module isolation instructions.

[0199] The module isolation instruction is encoded as 10. Its 8-bit configuration parameters have the high 4 bits identifying the module type and the low 4 bits identifying the specific module instance within that type. Its timing control focuses on precise isolation of specific modules.

[0200] During the SHIFT-IR phase, the instruction code is shifted in over 8 TCK cycles.

[0201] Upon entering the EXECUTE-IR phase, the access control unit parses the instructions and configuration parameters in the first TCK cycle to uniquely identify the target module. In the second TCK cycle, it generates a trigger signal, but this signal only controls the analog boundary submodule corresponding to the target module, switching its module isolation switch to the "off" state, while the switches of other modules remain unchanged, thereby achieving electrical isolation of a single module.

[0202] Subsequently, the access control unit automatically embeds a simplified link testing procedure to verify the isolation effect. This process reuses some of the acquisition logic from the aforementioned link scan and outputs result data including the isolation operation status and remaining link performance in the subsequent CAPTURE-DR and SHIFT-DR stages.

[0203] Example 3: Pin test command.

[0204] The pin test instruction is coded as 11, and its configuration parameters specify the faulty module and the specific pins within that module. Its timing design is used to perform pin-level electrical measurements.

[0205] After instruction loading and parsing are completed, the EXECUTE-IR phase begins. In the first TCK cycle, the path control unit activates the target module's pin test interface. In the second TCK cycle, the analog boundary submodule of the module is switched to "pin test mode," connecting its pins to the test bus. In the third TCK cycle, a trigger signal initiates a specific measurement operation, such as injecting a reference current into the target pin via the ATAP port.

[0206] In the subsequent test execution phase, the path control unit performs standard operations such as impedance measurement and logic function testing in a time-sharing manner. For example, impedance measurement and analog-to-digital conversion are completed in the first 5 TCK cycles, and boundary scan testing is performed in the last 5 TCK cycles to obtain the logic state.

[0207] Finally, the composite data containing impedance values, logic states, and fault identifiers is latched in the CAPTURE-DR stage and serially output in the SHIFT-DR stage, thus providing a complete diagnostic report for a single pin.

[0208] By adopting the scheme of the above embodiments, the timing design of the above three extended instructions can ensure that every hardware operation from link construction and module isolation to pin testing is completed under the control of a determined TCK clock, realizing high-precision synchronization and fully automated execution of the test process.

[0209] This application provides a chip product that includes the aforementioned integrated circuit.

[0210] It should be noted that the descriptions of the various embodiments above tend to emphasize the differences between them, while their similarities or commonalities can be referred to interchangeably. The descriptions of the above embodiments of the device, storage medium, computer program, and computer program product are similar to the descriptions of the above method embodiments and have similar beneficial effects. For technical details not disclosed in the embodiments of the device, storage medium, computer program, and computer program product of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0211] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above embodiments of this application are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0212] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0213] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0214] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0215] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A test circuit, characterized in that, The test circuit includes a path control unit, a test bus, and multiple simulated boundary sub-modules; each simulated boundary sub-module is connected to a corresponding functional module, and the path control unit is connected to the simulated boundary sub-module. The path control unit is used to send control information to each of the simulated boundary submodules; wherein the control information includes first control information, second control information generated when a link fault is determined, and third control information generated when a faulty module is determined; Each of the simulated boundary submodules is configured to control the connection status between the connected functional modules and the test bus according to the control information, including: in response to the first control information, connecting each functional module on the link to be tested to the test bus; in response to the second control information, bypassing the target functional module from the test bus while keeping other functional modules connected to the test bus; and in response to the third control information, connecting the pins of the faulty module to the test bus. The input terminal of the test bus is used to connect to the test signal from an external test source; The output terminal of the test bus is used to connect to test and analysis equipment; The test analysis equipment is used to perform test analysis on at least one functional module connected to the test bus and obtain test results.

2. The test circuit according to claim 1, characterized in that, The simulated boundary submodule includes a module isolation switch, one end of which is connected to the input / output pin of the connected functional module; the other end of which is connected to the test bus.

3. The test circuit according to claim 2, characterized in that, The path control unit is used to receive a target test command and send control information to each of the simulated boundary submodules based on the target test command. The control information is used to instruct the corresponding simulated boundary submodule to perform an operation that matches the target test command. Each of the simulated boundary submodules is configured to maintain the connection between the connected functional module and the test bus, or to bypass the connected functional module from the test bus, according to the control information.

4. The test circuit according to claim 3, characterized in that, The pathway control unit is used for: Determine the set of test actions corresponding to the target test instruction; wherein each action in the set of test actions is used to instruct different simulated boundary submodules to perform a connection state switching operation corresponding to the target test instruction; According to the set of test actions, control information is sent to each of the simulated boundary submodules, wherein the control information sent to each of the simulated boundary submodules matches the test actions in the set of test actions.

5. The test circuit according to claim 4, characterized in that, The control information includes first control information and second control information; the module isolation switch is used for: According to the first control information, the connection between the input / output pins of the functional module and the test bus is closed to keep the connected functional module and the test bus connected. According to the second control information, disconnect the input / output pins of the functional module from the test bus to bypass the functional module from the test bus.

6. The test circuit according to claim 5, characterized in that, The simulated boundary submodule also includes a pin test interface, which is connected to the pins of the connected functional module; the control information also includes third control information. The pin test interface is used to connect the pin to be tested of the functional module to the test bus according to the third control information, when a faulty module is determined from among the multiple functional modules based on the first control information and the second control information.

7. The test circuit according to claim 3, characterized in that, The pathway control unit is further configured to: Obtain the test clock of the test interface of the test circuit and the system operating clock of the functional module; A timing synchronization operation is performed based on the test clock and the system operating clock; wherein, the timing synchronization operation includes binding the test clock and the system operating clock to achieve timing alignment between digital test control signals and analog acquisition signals.

8. The test circuit according to claim 6, characterized in that, The pathway control unit is used for: Determine the first set of actions corresponding to the link scan command, whereby each action in the first set of actions is used to indicate the connection between the input / output pins of the functional module connected by the closed isolation switch of each module and the test bus. According to the first set of actions, the first control information is sent to each of the simulated boundary submodules to control the isolation switch of each module to close the connection between the input / output pins of the functional module and the test bus, so as to construct the first test link.

9. The test circuit according to claim 8, characterized in that, The test bus is used to receive a first test signal from the external test source and apply the first test signal to the first test link; The test analysis device is used to acquire a first test response signal generated when testing the first test link from the test bus, and to determine the link test result of the first test link based on the first test response signal.

10. The test circuit according to claim 6, characterized in that, The pathway control unit is used for: A second set of actions corresponding to the module isolation instruction is determined; wherein, the second set of actions includes a target action for instructing the target module isolation switch to disconnect the input / output pins of the target functional module from the test bus, and other actions for instructing isolation switches other than the target module isolation switch to close and connect the input / output pins of the functional modules to the test bus; the target functional module is any one of the plurality of functional modules; According to the second set of actions, the second control information is sent to the target simulated boundary submodule and the first control information is sent to other simulated boundary submodules other than the target simulated boundary submodule, so as to control the target module isolation switch to disconnect the input and output pins of the target functional module from the test bus, so as to construct a second test link other than the target functional module.

11. The test circuit according to claim 10, characterized in that, The test bus is used to receive the second test signal from the external test source and apply the second test signal to the second test link; The test analysis device is used to acquire a second test response signal generated when testing the second test link from the test bus, and to determine the module test result for the target functional module based on the second test response signal.

12. The test circuit according to claim 6, characterized in that, The pathway control unit is further configured to: The system receives a pin test command for the faulty module; and in response to the pin test command, sends the third control information to the analog boundary submodule corresponding to the faulty module to control the analog boundary submodule corresponding to the faulty module to switch to pin test mode, and connects the input and output pins of the faulty module to the test bus through the pin test interface.

13. The test circuit according to claim 12, characterized in that, The test bus is used to receive the third test signal from the external test source and apply the third test signal to each pin of the fault module; The test analysis device is used to acquire a third test response signal generated when testing the faulty module from the test bus, and to determine the pin test result for each pin of the faulty module based on the third test response signal.

14. The test circuit according to any one of claims 3-13, characterized in that, The test bus includes a multi-channel bus interface circuit; the bus interface circuit includes multiple input terminals and multiple output terminals, wherein the input terminals are used to connect to multiple of the analog boundary sub-modules, and the output terminals are used to connect to the test analysis equipment; The bus interface circuit is used to configure the connection relationship between the input terminal and the output terminal based on the target test command, so as to route the signal from the input terminal to the corresponding test analysis device.

15. The test circuit according to any one of claims 1-13, characterized in that, The test circuit also includes a digital boundary module connected to the test analysis equipment, the digital boundary module including a fault status register group and a read interface; The digital boundary module is used to store the test results in the fault status register group and to make the test results accessible to the outside through the read interface. The test results include one or more of the following: link test results, module test results, and pin test results.

16. The test circuit according to any one of claims 1-13, characterized in that, The test circuit also includes a fault reference fingerprint library unit, and the test analysis device is connected to the test bus and the fault reference fingerprint library unit respectively; The fault benchmark fingerprint library unit is used to store test benchmark parameters; The test analysis device is used to acquire test response signals generated when performing signal tests on at least one of the functional modules from the test bus, and compare and analyze the test response signals with the pre-stored reference parameters to obtain the test results; wherein, the test results include one or more of the following: link test results, module test results, and pin test results.

17. A testing method, characterized in that, The method is applied to a test circuit, which is used to test functional modules in an integrated circuit. The method includes: The path control unit in the test circuit sends control information to each simulated boundary submodule in the test circuit. The control information includes first control information, second control information generated when a link fault is determined, and third control information generated when a faulty module is determined. Each simulated boundary submodule in the test circuit controls the connection status between the connected functional modules and the test bus according to the control information, including: in response to the first control information, connecting each functional module on the link to be tested to the test bus; in response to the second control information, bypassing the target functional module from the test bus while keeping other functional modules connected to the test bus; and in response to the third control information, connecting the pins of the faulty module to the test bus. The at least one functional module connected to the test bus is tested and analyzed based on the test signals from an external test source, and the test results are obtained.

18. A chip product, characterized in that, The chip product includes the test circuit as described in any one of claims 1-16.

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