Leakage current test analysis method and platform for low-power-consumption chip

Abstract

The invention discloses a leakage current test analysis method and platform for a low-power-consumption chip, and belongs to the field of semiconductor testing, and the method comprises the steps: collecting the chip feature data of a target low-power-consumption chip, and determining a plurality of environment parameter test ranges and working voltage test ranges of the target low-power-consumption chip; generating an environment test sequence and a voltage test sequence, combining the environment test sequence and the voltage test sequence, and generating an adaptive test scheme; constructing a leakage current data matrix based on the adaptive test scheme; obtaining a first analysis result; obtaining a second analysis result; and obtaining a leakage current characteristic evaluation result of the target low-power-consumption chip based on the first analysis result and the second analysis result. The technical problems that in the prior art, the leakage current testing condition is single, the characteristics of the low-power-consumption chip under the multi-environment parameter and voltage condition are difficult to comprehensively evaluate, and consequently the accuracy and applicability of the testing result are insufficient are solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor testing, and in particular to a leakage current testing and analysis method and platform for low-power chip. Background Art

[0002] With the popularization of electronic devices and the diversification of application scenarios, low-power chips play an important role in the fields of Internet of Things, mobile devices, smart wearables, etc. The application of low-power chips requires devices to maintain low power consumption while working efficiently to extend the battery life of the device or reduce energy consumption.

[0003] At present, the leakage current test of low-power chips mostly relies on standardized test methods, that is, testing in the laboratory with fixed environmental parameters and operating voltage ranges. Although this method can basically meet the needs of product testing, it is difficult to cover the changing environment of the chip in actual application scenarios. Traditional testing schemes are often unable to flexibly adapt to these changes, resulting in limited actual reference value of the test results. Therefore, there is an urgent need for a leakage current test and analysis method and platform for low-power chips to solve the technical problems in the prior art that the leakage current test conditions are single and it is difficult to comprehensively evaluate the characteristics of low-power chips under multiple environmental parameters and voltage conditions, resulting in insufficient accuracy and applicability of the test results. Summary of the invention

[0004] This application provides a leakage current test and analysis method and platform for low-power chips, aiming to solve the technical problems in the prior art that the leakage current test conditions are single and it is difficult to comprehensively evaluate the characteristics of low-power chips under multiple environmental parameters and voltage conditions, resulting in insufficient accuracy and applicability of the test results.

[0005] In view of the above problems, the present application provides a leakage current testing and analysis method and platform for low-power chips.

[0006] The first aspect disclosed in the present application provides a leakage current test and analysis method for a low-power chip, the method comprising collecting chip feature data of a target low-power chip, determining multiple environmental parameter test ranges and operating voltage test ranges of the target low-power chip according to the chip feature data, wherein the multiple environmental parameter test ranges include a temperature test range, a humidity test range, and an electromagnetic interference test range; generating an environmental test sequence according to the multiple environmental parameter test ranges, and generating a voltage test sequence according to the operating voltage test range, combining the environmental test sequence and the voltage test sequence to generate an adaptive test scheme; based on the adaptive test scheme, setting environmental parameters and applying operating voltage, obtaining leakage current test data of the target low-power chip through a current sensor, and constructing a leakage current data matrix with the leakage current test data; extracting row vector data of the leakage current data matrix in sequence, analyzing the voltage-leakage current characteristics under the same environmental parameter conditions, and obtaining a first analysis result; extracting column vector data of the leakage current data matrix in sequence, analyzing the environment-leakage current characteristics under the same operating voltage conditions, and obtaining a second analysis result; performing correlation evaluation on the target low-power chip based on the first analysis result and the second analysis result to obtain a leakage current characteristic evaluation result of the target low-power chip.

[0007] Another aspect disclosed in the present application provides a leakage current test and analysis platform for a low-power chip, the platform comprising a chip feature data acquisition module: used to acquire chip feature data of a target low-power chip, and determine multiple environmental parameter test ranges and operating voltage test ranges of the target low-power chip according to the chip feature data, wherein the multiple environmental parameter test ranges include a temperature test range, a humidity test range, and an electromagnetic interference test range; an environmental test sequence generation module: used to generate an environmental test sequence according to the multiple environmental parameter test ranges, and to generate a voltage test sequence according to the operating voltage test range, and to combine the environmental test sequence and the voltage test sequence to generate an adaptive test scheme; a leakage current test data acquisition module: used to generate an environmental test sequence according to the multiple environmental parameter test ranges, and to generate a voltage test sequence according to the operating voltage test range, and to generate an adaptive test scheme based on the adaptive test scheme; The test scheme sets environmental parameters and applies working voltage, obtains leakage current test data of the target low-power chip through a current sensor, and constructs a leakage current data matrix with the leakage current test data; a first analysis result acquisition module is used to extract row vector data of the leakage current data matrix in sequence, analyze the voltage-leakage current characteristics under the same environmental parameter conditions, and obtain a first analysis result; a second analysis result acquisition module is used to extract column vector data of the leakage current data matrix in sequence, analyze the environment-leakage current characteristics under the same working voltage conditions, and obtain a second analysis result; an associated evaluation module is used to perform an associated evaluation on the target low-power chip based on the first analysis result and the second analysis result, and obtain a leakage current characteristic evaluation result of the target low-power chip.

[0008] One or more technical solutions provided in this application have at least the following technical effects or advantages: By adopting a technical solution that determines multiple environmental parameter test ranges and operating voltage test ranges based on chip characteristic data and generates an adaptive test solution, the impact of environmental changes and voltage fluctuations on test results during the leakage current test of low-power chips is solved, achieving the technical effect of precisely controlling test conditions and improving the accuracy and stability of test data, thereby realizing a comprehensive evaluation of the leakage current characteristics of low-power chips.

[0009] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A flow chart of a leakage current testing and analysis method for a low-power chip is provided for an embodiment of the present application.

[0011] Figure 2 A structural schematic diagram of a leakage current test and analysis platform for a low-power chip is provided for an embodiment of the present application.

[0012] Explanation of the reference numerals: chip characteristic data acquisition module 11 , environmental test sequence generation module 12 , leakage current test data acquisition module 13 , first analysis result acquisition module 14 , second analysis result acquisition module 15 , association evaluation module 16 . DETAILED DESCRIPTION

[0013] The overall idea of ​​the technical solution provided by this application is as follows: The embodiment of the present application provides a leakage current test analysis method and platform for low-power chips. By collecting the characteristic data of low-power chips, determining the test range of their environmental parameters and operating voltage, and generating an adaptive test scheme. The scheme comprehensively considers factors such as temperature, humidity, electromagnetic interference, and voltage changes to perform leakage current testing to ensure the accuracy of the test process and the reliability of chip performance evaluation.

[0014] After introducing the basic principles of the present application, various non-limiting implementation methods of the present application will be specifically described below in conjunction with the drawings in the specification.

[0015] Embodiment 1, as Figure 1 As shown, an embodiment of the present application provides a leakage current test and analysis method for a low-power chip, the method comprising: Step S100: Collect chip characteristic data of the target low-power chip, and determine multiple environmental parameter test ranges and operating voltage test ranges of the target low-power chip according to the chip characteristic data, wherein the multiple environmental parameter test ranges include a temperature test range, a humidity test range and an electromagnetic interference test range.

[0016] Specifically, chip characteristic data refers to data that describes chip performance, structure, and usage conditions, including chip design information, material properties, manufacturing process parameters, etc. It reflects the basic working principle and characteristics of the chip and is the basis for the formulation of the test plan. The environmental parameter test range indicates the range of environmental parameters simulated when testing the chip. For example, the upper and lower limits of temperature, humidity, and electromagnetic interference conditions. Different test ranges are used to evaluate the leakage current characteristics of the chip under various environmental changes. The operating voltage test range refers to the voltage range applied to the chip during the test, usually including the upper and lower fluctuation range of the rated operating voltage of the chip. It is used to evaluate the leakage current performance of the chip under different voltage conditions.

[0017] First, collect the characteristic data of the chip, and use this data to analyze the working performance of the chip under specific conditions. In order to obtain an accurate test range, the chip characteristic data can be compared and analyzed with the historical data of multiple similar chips stored in the operation database. Using data analysis tools (such as Python's Pandas, NumPy and other data processing libraries), a collection of chip samples with similar characteristics can be screened out from the database, and statistical analysis can be performed on the temperature, humidity and electromagnetic interference conditions experienced by these samples in the actual working environment, so as to determine a reasonable environmental parameter test range. Similarly, by analyzing the concentrated intervals of humidity and electromagnetic interference, the test range of other environmental parameters can be obtained.

[0018] Then, use the data analysis tool to set the test range of the operating voltage, and calculate the upper and lower limits of the voltage by screening and sorting the operating voltage data of similar chips to ensure that the test conditions are close to the actual working environment of the chip.

[0019] By determining the test range of the chip's environmental parameters and operating voltage, the test solution can simulate the leakage current performance under real working conditions based on the characteristics of the target chip, thereby improving the accuracy and applicability of the test and making the test results more reflective of the chip's actual performance under different environmental and voltage conditions.

[0020] Step S200: Generate an environmental test sequence according to the multiple environmental parameter test ranges, generate a voltage test sequence according to the operating voltage test range, combine the environmental test sequence and the voltage test sequence, and generate an adaptive test solution.

[0021] Specifically, an environmental test sequence refers to a set of ordered test points generated according to the test range of environmental parameters (such as temperature, humidity, electromagnetic interference, etc.). These test points are used to simulate different environmental conditions one by one in order to comprehensively evaluate the performance of the chip. For example, temperature test points may include multiple values ​​such as -20°C, 0°C, 25°C, and 85°C. A voltage test sequence is a set of ordered test points generated according to the working voltage test range of the chip, covering voltage values ​​from low to high. The voltage test sequence can be used to apply different voltages to observe the changes in the leakage current of the chip under different voltage conditions, such as multi-level voltage points from 0.9V to 1.2V. An adaptive test scheme refers to a test plan formed by combining an environmental test sequence and a voltage test sequence. It contains a combination of multiple sets of environmental and voltage conditions, which can flexibly adapt to the characteristics of the chip and environmental changes.

[0022] First, generate the respective test sequences according to the environmental parameter test range. The environmental parameter test range usually includes temperature, humidity and electromagnetic interference range. In order to generate the test sequence, each parameter range can be divided.

[0023] Subsequently, these environmental test points are arranged and combined to form all possible environmental combination sequences. For the voltage test range, it is also divided into multiple voltage test points, and a voltage test sequence arranged in low to high order is generated.

[0024] Next, the environmental test sequence is combined with the voltage test sequence to form an adaptive test scheme in a matrix manner. The rows of the matrix can represent different environmental combinations, the columns represent different voltage conditions, and each element of the matrix represents a set of environmental and voltage combinations. In this way, a full-range coverage test matrix is ​​generated to ensure that the tests of the chip under different voltage conditions under each set of environmental parameters are recorded.

[0025] Through the adaptive test scheme, the test system can comprehensively evaluate the leakage current characteristics of the chip under various environmental and voltage conditions. This scheme ensures the extensiveness and representativeness of the test, so that the leakage current data can reflect the actual performance of the chip under different actual conditions, thus providing reliable data support for chip quality evaluation and optimization.

[0026] Step S300: Based on the adaptive test scheme, environmental parameters are set and working voltage is applied, leakage current test data of the target low-power chip is acquired through a current sensor, and a leakage current data matrix is ​​constructed with the leakage current test data.

[0027] Specifically, an adaptive test scheme is a test scheme generated according to the specific test requirements of the target chip, combining a combination of different environmental parameters and operating voltages. The adaptive test scheme is designed to simulate the performance of the chip under a variety of actual working conditions in order to more accurately test the leakage current characteristics of the chip. Environmental parameters refer to the external environmental conditions set during the test, such as temperature, humidity, electromagnetic interference, etc. These parameters affect the working state and leakage current performance of the chip. The operating voltage refers to the voltage applied to the chip when it is working, which is usually one of the basic driving parameters for the operation of the chip. Under different voltages, the leakage current of the chip will vary. Current sensors are sensing devices used to detect the working current of the chip. The leakage current data matrix is ​​a table or matrix structure used to store leakage current data measured under different environmental parameters and voltage conditions. The rows and columns of the matrix represent different environmental conditions and voltage values, respectively, making the data organization clearer and easier to analyze.

[0028] First, set the environmental parameters and operating voltage according to the adaptive test scheme. For example, when testing temperature parameters, set the ambient temperature to vary between 0°C, 25°C, and 50°C; the humidity to vary between 40%, 60%, and 80%, and the voltage to vary between 1.0V, 1.1V, and 1.2V. The combination of environment and voltage is the test condition in the adaptive test scheme. Each combination simulates a different operating environment to help reveal the current performance of the target chip in actual use.

[0029] Next, different combinations of conditions are set one by one, and the leakage current data of the chip under these conditions is measured by the current sensor. The use of the current sensor can be combined with measurement equipment such as an oscilloscope or a multimeter to collect accurate leakage current readings through a high-precision sensor.

[0030] After obtaining the test data, fill the leakage current data into the leakage current data matrix according to different environmental and voltage conditions. Each row in the matrix represents the leakage current data of different voltages under the same environmental conditions, and each column represents the leakage current data of different environments under the same voltage conditions. This organized matrix makes the data clear at a glance, which is convenient for subsequent analysis and chart display.

[0031] The construction of leakage current data matrix provides intuitive data information, which can clearly show the leakage current performance of the chip under different conditions. Through matrix data analysis, the sensitivity of leakage current to specific environmental parameters or voltage can be found, which helps designers to optimize chip design, reduce power consumption, and improve chip reliability and energy efficiency in practical applications.

[0032] Step S400: extracting row vector data of the leakage current data matrix in sequence, analyzing the voltage-leakage current characteristics under the same environmental parameter conditions, and obtaining a first analysis result.

[0033] Specifically, the row vector refers to the data set of each row in the matrix, which represents the change of leakage current measurement value with voltage under specific environmental parameters. By extracting the row vector, the influence of voltage on leakage current can be observed. The voltage-leakage current characteristic refers to the relationship curve between the leakage current of the chip and the operating voltage under fixed environmental parameters. Analyzing this characteristic can help understand the power consumption trend of the chip under different voltages and identify abnormal current performance. The first analysis result is a preliminary result based on the voltage-leakage current characteristic, which reveals the current performance of the chip under different environmental parameters and helps the subsequent power consumption optimization.

[0034] First, extract row vector data from the leakage current data matrix row by row, that is, under the same environmental parameters (such as fixed temperature and humidity), obtain the leakage current value of the chip under different voltage conditions. Next, draw the voltage-leakage current characteristic curve based on these row vectors. This can be done using data processing tools, such as Matplotlib or Excel in Python, to plot each row of vector data as a curve on the chart, thereby intuitively showing the relationship curve between voltage and leakage current. Generally, as the voltage increases, the leakage current shows a specific upward trend. However, if there are obvious deviations or abnormal points in the curve (such as a sudden increase or instability in the leakage current), it may reflect the working reliability of the chip under this condition.

[0035] By analyzing the voltage-leakage current characteristics through row vectors, we can intuitively identify the leakage current performance and voltage response characteristics of the chip under different environmental parameters. This analysis helps to identify the power consumption bottleneck and reliability issues of the chip and provide optimization directions.

[0036] Step S500: extracting column vector data of the leakage current data matrix in sequence, analyzing the environment-leakage current characteristics under the same working voltage condition, and obtaining a second analysis result.

[0037] Specifically, the column vector in the column vector data refers to each column of data extracted from the leakage current data matrix. Each column represents the leakage current data under different environmental conditions under the same voltage conditions. The environment-leakage current characteristic refers to the leakage current under different environmental conditions. The second analysis result is based on the analysis conclusion obtained from the column vector data (i.e., analyzing the impact of different environmental conditions on leakage current under the same operating voltage conditions). It helps to understand the environmental sensitivity of chip leakage current under the same voltage conditions and provides data support for further optimization.

[0038] First, we need to extract the column vector data of the leakage current data matrix. The leakage current data matrix contains the leakage current test data under different environmental and voltage conditions, each column corresponds to a different voltage test point, and each row corresponds to a different environmental condition.

[0039] Next, analyze the environmental-leakage current characteristics under the same operating voltage conditions. This analysis means that the same column of data will be focused on to compare the trend of leakage current changes with the environment under different environmental conditions. This process is usually completed by statistical analysis or curve fitting. For example, by plotting the curve of leakage current changes with temperature, you can intuitively see the trend of leakage current changes at different temperatures. If the leakage current increases significantly with increasing temperature, it means that the leakage current of the chip is sensitive to temperature. The analysis process can be performed using statistical analysis tools or data processing software (such as MATLAB, NumPy in Python, SciPy library, etc.). For example, in Python, NumPy can be used to process data matrices, and the relationship between leakage current and environmental conditions can be found by extracting column vectors and performing numerical analysis.

[0040] The second analysis result is generated based on the summary of the analysis results of the column vector data, usually a curve of the leakage current changing with environmental conditions or a comprehensive evaluation. Through this analysis result, the stability of the chip under different environments can be understood and possible optimization directions can be found.

[0041] By extracting the column vector data of the leakage current data matrix in sequence and analyzing the environmental characteristics of the leakage current under the same voltage conditions, the performance fluctuations of the chip under different environmental conditions can be revealed. Through this analysis, the sensitivity of the chip to environmental changes under a specific voltage can be clarified, which provides an important basis for chip design optimization and application scenario selection.

[0042] Step S600: performing an associated evaluation on the target low-power chip based on the first analysis result and the second analysis result to obtain a leakage current characteristic evaluation result of the target low-power chip.

[0043] Specifically, the correlation evaluation combines the first analysis result and the second analysis result for comprehensive analysis to obtain a more comprehensive leakage current characteristic evaluation result. It can reveal the comprehensive behavior of leakage current under different environmental and voltage conditions, thereby helping to evaluate the overall performance of the target low-power chip. The leakage current characteristic evaluation result is the final conclusion after combining the first analysis result with the second analysis result to evaluate the leakage current performance of the target chip. This evaluation result usually includes the fluctuation of leakage current under various environmental and voltage conditions, as well as the stability and reliability of the chip.

[0044] First, we need to perform a correlation evaluation based on the first analysis result and the second analysis result. First, the first analysis result provides the characteristics of the leakage current changing with voltage under different environmental conditions; while the second analysis result provides the impact of environmental factors on the leakage current under the same voltage conditions. Combining these two analysis results, we can comprehensively evaluate the performance of the chip in a complex environment.

[0045] Integrate the first and second analysis results. First, match and integrate the results obtained by the voltage-leakage current characteristic analysis under environmental parameter conditions and the environmental-leakage current characteristic analysis under the same operating voltage conditions. For example, if the first analysis result shows that the leakage current will increase significantly in a high temperature environment, and the second analysis result shows that the leakage current will also increase in a high humidity environment, these factors can be combined to evaluate the overall performance of the chip.

[0046] By correlating the two analysis results, we can obtain the comprehensive characteristics of leakage current under different environments and voltages. This process can be done by weighted calculation, regression analysis or multidimensional data analysis.

[0047] Through this correlation evaluation step, the leakage current characteristic evaluation results of the target chip can be accurately obtained. This evaluation result helps provide direction for chip optimization, especially in the design stage, it can discover potential problems in advance, such as excessive leakage current or excessive sensitivity to the environment, so as to optimize the chip's materials and design to make it more adaptable to various environmental conditions in actual applications.

[0048] Furthermore, multiple environmental parameter test ranges and operating voltage test ranges of the target low-power chip are determined based on the chip characteristic data, wherein the multiple environmental parameter test ranges include a temperature test range, a humidity test range and an electromagnetic interference test range, including: constructing a retrieval constraint based on the chip characteristic data, performing data retrieval in a chip operation database based on the retrieval constraint, and obtaining a similar chip operation sample set, including multiple similar chip operation samples, wherein each similar chip operation sample has corresponding chip operation environment data and chip operating voltage data; performing concentrated interval analysis on multiple environmental parameters in the chip operation environment data of multiple similar chip operation samples, obtaining concentrated intervals of multiple environmental parameters, and forming an environmental parameter test range, wherein the multiple environmental parameters include at least temperature, humidity and electromagnetic interference; performing concentrated interval analysis on the chip operating voltage data of multiple similar chip operation samples, and obtaining an operating voltage test range.

[0049] Specifically, retrieval constraints refer to rules or conditions for filtering out data that meets specific conditions from a database. These constraints are usually formulated based on the characteristic data of the chip (such as design parameters or processes) and are used to lock in chip data samples with similar characteristics to the target chip. A similar chip operation sample set refers to a set of chip data that is similar to the target chip in terms of performance, process or working conditions, which is screened out from the database. These samples contain the operating data of such chips under different environmental conditions and voltage conditions, and are an important reference for setting the subsequent test range. Concentrated interval analysis refers to determining the intervals that appear in the data set by statistically analyzing the distribution range of a certain parameter of similar chips in the operating environment. The concentrated interval represents the actual operating condition range of most chips, providing a reference for setting the test range.

[0050] First, according to the characteristic data of the target chip (such as manufacturing process, operating frequency, etc.), set the search constraint conditions to filter out similar chip operation sample sets that meet specific conditions. The search tool usually uses database query statements (such as SQL queries) to extract chip data that meets the conditions from the chip operation database. Assuming that the design process of the target chip is 28nm and the operating frequency is 1GHz, the search condition can be "process = 28nmAND frequency = 1GHz" to filter out chip sample data with similar processes and frequencies.

[0051] Next, based on the screened similar chip samples, the chip operating environment data is analyzed in a centralized interval to determine a reasonable environmental parameter test range. Centralized interval analysis can be implemented through statistical tools (such as statistical libraries Pandas and SciPy in Python). Taking temperature parameters as an example, assuming that the operating temperature of similar chips is mainly concentrated between 0℃ and 70℃, 0℃ to 70℃ can be used as the temperature test range. Similarly, by statistically analyzing the distribution of humidity and electromagnetic interference, the appropriate humidity and electromagnetic interference test ranges can be obtained.

[0052] For the concentrated interval analysis of the operating voltage data, the operating voltage data of the screened similar chips are usually sorted and statistically analyzed to obtain the voltage range.

[0053] The environmental parameters and voltage test range obtained by this method are closer to the actual working environment of the chip, which enhances the applicability and accuracy of the test scheme, enables the leakage current characteristic test of the target chip to more effectively reflect its performance under real working conditions, improves the reliability of the test results, and provides accurate reference data for subsequent chip optimization.

[0054] Furthermore, a centralized interval analysis is performed on the chip operating voltage data of multiple similar chip operation samples to obtain an operating voltage test range, including: sorting the chip operating voltage data of multiple similar chip operation samples from large to small according to the numerical value, obtaining the voltage data sorting result, and determining the voltage median according to the voltage data sorting result; extracting the maximum voltage in the voltage data sorting result, obtaining the median between the voltage median and the maximum voltage as the test voltage upper limit value; extracting the minimum voltage in the voltage data sorting result, obtaining the median between the minimum voltage value and the voltage median as the test voltage lower limit value; generating an operating voltage test range according to the test voltage upper limit value and the test voltage lower limit value.

[0055] Specifically, the voltage data sorting result refers to a data set after the operating voltage data of multiple chip samples are arranged from large to small or from small to large. It can better understand the voltage distribution. The median refers to the data value in the middle position of the sorted data set. The median is often used to eliminate the impact of extreme values ​​on the analysis results. The upper limit value of the test voltage is the middle value between the median voltage and the maximum voltage; the lower limit value is the middle value between the median voltage and the minimum voltage.

[0056] First, we extract the operating voltage data of similar chips from the database and sort the data from large to small. Sorting can be achieved through programming tools, such as using the sorted() function in Python to sort the data. After the sorting is completed, the median of the voltage is found according to the sorting results in the data set, and then the maximum and minimum values ​​are extracted from the sorting results, and the median between the median and the maximum value, and the median between the median and the minimum value are calculated respectively.

[0057] Finally, the calculated upper and lower limits are used as the boundary values ​​of the test voltage to generate a voltage test range, which will be used for subsequent leakage current characteristic tests to be closer to the actual working environment of the chip.

[0058] The voltage test range obtained by this method can focus the test on the voltage range where the chip actually operates, avoiding meaningless extreme values. This not only improves the test efficiency, but also more accurately reflects the leakage current characteristics of the chip within the actual voltage range, providing efficient data support for chip reliability analysis and optimization.

[0059] Furthermore, an environmental test sequence is generated according to the multiple environmental parameter test ranges, and a voltage test sequence is generated according to the working voltage test range, and the environmental test sequence and the voltage test sequence are combined to generate an adaptive test scheme, including: dividing the temperature test range into multiple temperature test points according to the temperature step, dividing the humidity test range into multiple humidity test points according to the humidity step, and dividing the electromagnetic interference test range into multiple electromagnetic interference test points according to the electromagnetic interference step; arranging and combining multiple temperature test points, multiple humidity test points and multiple electromagnetic interference test points to generate an environmental parameter combination set; screening the environmental parameter combination set based on preset environmental parameter combination constraints to obtain a valid environmental parameter combination set to generate the environmental test sequence, wherein the environmental parameter combination constraint is a combination restriction condition set based on physical laws, actual application scenarios and chip feature data; dividing the working voltage test range into multiple voltage test points according to the voltage step, and generating the voltage test sequence in order from small to large; combining the environmental test sequence and the voltage test sequence in a matrix form to generate the adaptive test scheme.

[0060] Specifically, the temperature test range, humidity test range, and electromagnetic interference test range are parameter ranges set to simulate the working conditions of the chip under different environmental conditions. The temperature test range indicates the temperature range in which the test is performed, the humidity test range indicates the humidity range of the test environment, and the electromagnetic interference test range indicates the intensity range of the electromagnetic interference applied during the test. The temperature step, humidity step, and electromagnetic interference step are interval values ​​used to divide the test range into several test points. The environmental parameter combination set is a data set obtained by arranging and combining the test points of multiple environmental parameters such as temperature, humidity, and electromagnetic interference. These combinations represent various situations in which the chip is tested under different environmental conditions. The environmental parameter combination constraints are to select meaningful combinations for chip performance evaluation from the environmental parameter combination set. These constraints are set based on the physical characteristics of the chip design, environmental changes in actual application scenarios, and the operating characteristics of the chip. The voltage test range refers to the operating voltage range that the chip can withstand, and the voltage test sequence divides this range into multiple test points according to a certain step size so that different voltages can be applied step by step for testing. The adaptive test scheme combines the environmental test sequence and the voltage test sequence in a matrix form to generate a scheme that covers all necessary test conditions. It can adaptively perform leakage current testing according to environmental changes and voltage changes.

[0061] First, based on the test ranges of temperature, humidity, and electromagnetic interference, these ranges are divided into multiple test points according to the predetermined step size. For example, if the temperature test range is -20°C to 80°C and the temperature step size is 10°C, then the temperature test points will include -20°C, 0°C, 10°C, 20°C, etc., until 80°C. Similarly, the humidity range is from 20% to 90%, and the humidity step size is 10%, thus obtaining multiple humidity test points.

[0062] Then, the test points of temperature, humidity and electromagnetic interference are arranged and combined to obtain the environmental parameter combination set. For example, assuming that there are 4 test points for temperature, 3 test points for humidity and 2 test points for electromagnetic interference, then by arranging and combining the test points of these three parameters, 4×3×2=24 different environmental combinations can be obtained. These combinations will simulate the working conditions of the chip under various environmental conditions.

[0063] Next, based on the preset environmental parameter combination constraints, effective environmental combinations that are meaningful for testing are screened out. For example, if certain environmental combinations (such as high humidity at extremely low temperatures) have no significant effect on chip performance, or if these environmental combinations occur less frequently, then these combinations can be excluded, and ultimately an effective environmental test sequence is obtained. At the same time, the voltage test range is divided into multiple test points according to the voltage step size.

[0064] Finally, the environmental test sequence and the voltage test sequence are combined in a matrix form. For example, each row can represent an environmental combination, and each column represents the test of different voltage points under the environmental combination. In this way, all necessary environmental and voltage conditions can be covered in a unified test plan.

[0065] This step generates a comprehensive adaptive test solution to ensure that the leakage current performance of low-power chips under various environmental and voltage conditions can be fully tested. This method not only improves the test coverage by finely dividing environmental parameters and voltages, but also avoids unnecessary redundant tests, thereby saving time and cost. By screening effective environmental combinations, the test conditions can be further optimized to make the leakage current test of the chip more accurate and efficient. Ultimately, this will improve the chip's stability to environmental changes and voltage fluctuations in actual applications, ensuring its reliability under a variety of working conditions.

[0066] Furthermore, the row vector data of the leakage current data matrix are extracted in sequence, the voltage-leakage current characteristics under the same environmental parameter conditions are analyzed, and a first analysis result is obtained, including: obtaining the expected voltage-leakage current characteristics under different environmental parameter conditions, and generating multiple expected voltage-leakage current curves; extracting the first expected voltage-leakage current curve under the first environmental parameter condition; according to the leakage current data matrix, extracting the row vector data of the first environmental parameter condition, obtaining the corresponding actual voltage-leakage current characteristics, and generating a first actual voltage-leakage current curve; performing deviation evaluation on the actual voltage-leakage current curve based on the expected voltage-leakage current curve, obtaining a first curve evaluation result, and adding it to multiple curve evaluation results; generating the first analysis result according to the multiple curve evaluation results.

[0067] Specifically, the expected voltage-leakage current characteristic is a voltage-leakage current curve based on theoretical or design expectations, which is used to compare with actual measurement results. It represents the ideal leakage current performance of the chip under certain environmental parameters. The actual voltage-leakage current characteristic is based on data obtained from actual tests, indicating the relationship between the voltage and leakage current of the chip in the actual test environment. Deviation assessment is to compare the actual voltage-leakage current curve with the expected voltage-leakage current curve, calculate the difference between the two, and evaluate the performance deviation of the chip under actual conditions. The curve evaluation result is the data summarizing the deviation evaluation results between the expected curve and the actual curve, reflecting the degree of deviation of the chip leakage current characteristics.

[0068] First, the leakage current data matrix is ​​established by testing the leakage current under different environmental conditions (such as temperature, humidity, electromagnetic interference) and voltage to generate the data matrix. For example, assuming the temperature is 25°C, the humidity is 60%, and the voltage changes from 0V to 3.3V in steps of 0.3V, a matrix is ​​finally generated, and each row represents the leakage current data under a certain environmental condition.

[0069] Next, extract the row vector data: extract the data of each row from the matrix in turn. For example, if the current environmental conditions are a temperature of 25°C and a humidity of 60%, extract all voltage points and corresponding leakage current values ​​that match this environmental condition to form a set of data. Then, generate the expected voltage-leakage current curve: generate an expected voltage-leakage current curve based on the theoretical design or expected performance of the chip. This expected curve represents the ideal performance of the chip under normal conditions. For example, assume that the expected curve is an approximate linear or exponential relationship that describes how the leakage current should change at each voltage point.

[0070] Next, extract the actual voltage-leakage current characteristics: extract the row vector data that matches the actual test conditions from the leakage current data matrix. With this data, draw the actual voltage-leakage current curve. Then, compare the actual voltage-leakage current curve with the expected voltage-leakage current curve. By calculating the difference between the two curves, a deviation assessment result can be obtained, reflecting the deviation between the chip's actual working environment and the expected performance.

[0071] Finally, the first analysis result is generated: by evaluating the deviation between the expected curve and the actual curve under multiple environmental conditions, all evaluation results are summarized to generate the first analysis result. This result can provide detailed information about chip performance, identify potential problems and optimize them.

[0072] This step can help developers deeply understand the working characteristics of the chip under various environmental conditions, especially the leakage current characteristics, by extracting the leakage current data matrix and performing detailed analysis. By comparing with the expected voltage-leakage current curve, problems in chip design can be discovered in time, and the reliability and performance of the chip can be optimized. Ultimately, this helps to improve the stability and adaptability of the chip, ensuring that its performance in actual applications meets the expected requirements.

[0073] Furthermore, based on the multiple curve evaluation results, the first analysis result is generated, including: obtaining full environmental combination data based on multiple environmental parameter test ranges; calculating a first environmental weight based on the frequency of occurrence of the first environmental parameter condition in the full environmental combination data, and adding it to multiple environmental weights; and performing weighted calculation on the multiple environmental weights and the multiple curve evaluation results to obtain the first analysis result.

[0074] Specifically, the full environmental combination data refers to all environmental combination data generated based on the test range of multiple environmental parameters (such as temperature, humidity, electromagnetic interference, etc.). It includes all combinations of environmental conditions and is used to comprehensively evaluate the performance of the chip under different conditions. The environmental weight refers to the weight value corresponding to the frequency of occurrence of a specific environmental condition or combination in the full environmental combination data. Environmental conditions with high weights mean that the condition appears more frequently during the test and has a greater influence.

[0075] Weighted calculation of curve evaluation results refers to combining the curve evaluation results under multiple environmental conditions with the corresponding environmental weights to calculate a comprehensive evaluation result in a weighted manner. This helps to more accurately evaluate the overall performance of the chip under different environmental conditions.

[0076] First, you need to obtain the full environmental combination data. This means generating all possible combination data for each environmental parameter test range (such as temperature range, humidity range, and electromagnetic interference range). The full environmental combination data generated in this way is: different cross combinations of temperature, humidity, and electromagnetic interference.

[0077] Next, calculate the environmental weight. The environmental weight is determined by calculating the frequency of each environmental condition in the full combination data. The weight reflects the importance of the condition to the test result. Then, perform a weighted calculation on the curve evaluation results. After obtaining the curve evaluation results corresponding to each environmental combination, it is necessary to combine the weight of each environmental condition with the corresponding curve evaluation results. For example, suppose that under a certain environmental condition, the curve evaluation results show that the chip leakage current deviation is large, while under another environmental condition, the curve evaluation results are more ideal. By weighting these evaluation results, a more accurate analysis result can be obtained, reflecting the impact of more important environmental conditions on leakage current performance.

[0078] Finally, the first analysis result is generated. Through weighted calculation, a comprehensive analysis result is finally obtained. This result can reflect the performance of the chip under all environmental conditions and help developers identify the most critical environmental factors, thus providing a basis for subsequent chip optimization.

[0079] This weighted calculation method can more accurately and comprehensively consider the impact of various environmental parameters on leakage current characteristics, thereby obtaining a more comprehensive and reliable chip performance analysis result. This can not only identify the most influential environmental conditions, but also provide a strong basis for chip optimization and adjustment. Ultimately, the performance of the chip in real applications can be significantly improved, reducing potential problems in the design.

[0080] Furthermore, an associated evaluation is performed on the target low-power chip based on the first analysis result and the second analysis result to obtain a leakage current characteristic evaluation result of the target low-power chip, including: obtaining voltage changes and environmental changes based on the application scenario of the target low-power chip, wherein the voltage changes characterize the degree of voltage fluctuation in the application scenario, and the environmental changes characterize the degree of environmental fluctuation in the application scenario; determining a first weight coefficient based on the voltage changes, and determining a second weight coefficient based on the environmental changes; performing a weighted calculation on the first analysis result and the first weight coefficient to obtain a voltage dimension evaluation score; performing a weighted calculation on the second analysis result and the second weight coefficient to obtain an environmental dimension evaluation score; and generating a leakage current characteristic evaluation result of the target low-power chip based on the voltage dimension evaluation score and the environmental dimension evaluation score.

[0081] Specifically, voltage variation refers to the fluctuation range and frequency of voltage in the actual application scenario of the target low-power chip. Environmental variation refers to the degree of fluctuation of environmental factors in the application scenario of the chip. In different scenarios, the amplitude of temperature, humidity and electromagnetic interference varies differently, affecting the stability and leakage current performance of the chip. The weight coefficient is a data ratio used to measure and adjust the importance of different influencing factors. The first weight coefficient is used to indicate the degree of influence of voltage changes, and the second weight coefficient indicates the degree of influence of environmental changes. The voltage dimension evaluation score and the environmental dimension evaluation score are weighted calculation results based on the first analysis result and voltage variation, and the second analysis result and environmental variation, respectively, indicating the leakage current performance of the chip under specific conditions of voltage or environment.

[0082] First, we obtain the weight coefficient according to the voltage change and environmental change in the application scenario, and then perform weighted calculation on the analysis results and the weight to generate the final evaluation result.

[0083] Specifically, first, analyze the actual application scenarios of the target chip. For example, in industrial control applications, there are large voltage fluctuations (high voltage changes), and the ambient temperature and humidity also fluctuate at any time (high environmental changes); in consumer electronics applications, the changes in voltage and environment are relatively stable.

[0084] Determine the weight coefficients of voltage and environment according to the changes in the application scenario. For example, for scenarios with large voltage changes, a higher first weight coefficient (such as 0.7) can be set, while for scenarios with relatively stable environmental changes, a lower second weight coefficient (such as 0.3) can be set. These weight coefficients can be obtained through historical data analysis or scenario assessment tools (such as statistical analysis libraries in MATLAB or Python).

[0085] Multiply the first analysis result (voltage-leakage current characteristics) by the first weight coefficient to obtain the voltage dimension evaluation score. For example, if the first analysis result is 80 and the first weight coefficient is 0.7, the voltage dimension evaluation score is 80×0.7=56. Multiply the second analysis result (environment-leakage current characteristics) by the second weight coefficient to obtain the environment dimension evaluation score. For example, if the second analysis result is 70 and the second weight coefficient is 0.3, the environment dimension evaluation score is 70×0.3=21.

[0086] Based on the voltage dimension and environment dimension evaluation scores, the leakage current characteristic evaluation result of the target chip is comprehensively obtained. A weighted average method can be used to obtain a comprehensive score, which represents the overall leakage current performance of the chip in this application scenario.

[0087] This method can more accurately evaluate the leakage current characteristics of the chip in different application scenarios and identify the stability and reliability of the chip under specific conditions. The final evaluation results can help optimize chip design, improve chip performance in complex application environments, and provide a basis for users to choose suitable chips.

[0088] In summary, the leakage current test and analysis method of a low-power chip provided in the embodiment of the present application has the following technical effects: 1. Through the generation of adaptive test schemes and the optimization of environmental and voltage test sequences, the leakage current performance of low-power chips under different environmental and voltage conditions can be accurately tested, improving the comprehensiveness and accuracy of the test. This method can provide a more scientific basis for the reliability evaluation of low-power chips and ensure the stability of chips in changing environments.

[0089] 2. By constructing retrieval constraints and focusing on interval analysis, it is possible to effectively obtain environmental data and voltage data of similar chips from the chip operation database, thereby determining the appropriate test range. This analysis method ensures the rationality of the test range, avoids overly broad or narrow test conditions, and improves the effectiveness and pertinence of the test.

[0090] 3. By combining environmental and voltage test sequences to generate an adaptive test solution, the test conditions can be flexibly adjusted according to the characteristics and actual needs of the chip. This solution can more comprehensively cover the performance of the chip under different working conditions, ensure that the test results are more reliable and comprehensive, and help optimize the performance of the chip.

[0091] Embodiment 2 is based on the same inventive concept as the leakage current test and analysis method of a low-power chip in the above embodiment. Figure 2 As shown, an embodiment of the present application provides a leakage current test and analysis platform for a low-power chip, the platform comprising: Chip feature data acquisition module 11: used to collect chip feature data of the target low-power chip, and determine multiple environmental parameter test ranges and operating voltage test ranges of the target low-power chip based on the chip feature data, wherein the multiple environmental parameter test ranges include temperature test range, humidity test range and electromagnetic interference test range.

[0092] The environmental test sequence generating module 12 is used to generate an environmental test sequence according to the multiple environmental parameter test ranges, generate a voltage test sequence according to the working voltage test range, and combine the environmental test sequence and the voltage test sequence to generate an adaptive test scheme.

[0093] The leakage current test data acquisition module 13 is used to set environmental parameters and apply working voltage based on the adaptive test scheme, acquire leakage current test data of the target low-power chip through the current sensor, and construct a leakage current data matrix with the leakage current test data.

[0094] The first analysis result acquisition module 14 is used to sequentially extract the row vector data of the leakage current data matrix, analyze the voltage-leakage current characteristics under the same environmental parameter conditions, and acquire the first analysis result.

[0095] The second analysis result acquisition module 15 is used to sequentially extract column vector data of the leakage current data matrix, analyze the environment-leakage current characteristics under the same working voltage condition, and acquire the second analysis result.

[0096] The correlation evaluation module 16 is configured to perform correlation evaluation on the target low-power chip based on the first analysis result and the second analysis result, and obtain a leakage current characteristic evaluation result of the target low-power chip.

[0097] Furthermore, the chip feature data acquisition module 11 is also used to perform the following steps: construct a retrieval constraint according to the chip feature data, perform data retrieval in the chip operation database based on the retrieval constraint, and obtain a set of similar chip operation samples, including multiple similar chip operation samples, wherein each similar chip operation sample has corresponding chip operation environment data and chip operating voltage data; perform centralized interval analysis on multiple environmental parameters in the chip operation environment data of multiple similar chip operation samples, obtain centralized intervals of multiple environmental parameters, and form an environmental parameter test range, wherein the multiple environmental parameters include at least temperature, humidity and electromagnetic interference; perform centralized interval analysis on the chip operating voltage data of multiple similar chip operation samples to obtain an operating voltage test range.

[0098] Furthermore, the chip feature data acquisition module 11 is also used to perform the following steps: sort the chip operating voltage data of multiple similar chip running samples from large to small according to the numerical value, obtain the voltage data sorting result, and determine the voltage median according to the voltage data sorting result; extract the maximum voltage in the voltage data sorting result, obtain the median between the voltage median and the maximum voltage, as the test voltage upper limit value; extract the minimum voltage in the voltage data sorting result, obtain the median between the minimum voltage value and the voltage median, as the test voltage lower limit value; generate the operating voltage test range according to the test voltage upper limit value and the test voltage lower limit value.

[0099] Furthermore, the environmental test sequence generation module 12 is also used to perform the following steps: divide the temperature test range into multiple temperature test points according to the temperature step, divide the humidity test range into multiple humidity test points according to the humidity step, and divide the electromagnetic interference test range into multiple electromagnetic interference test points according to the electromagnetic interference step; arrange and combine multiple temperature test points, multiple humidity test points and multiple electromagnetic interference test points to generate an environmental parameter combination set; screen the environmental parameter combination set based on preset environmental parameter combination constraints to obtain a valid environmental parameter combination set to generate the environmental test sequence, wherein the environmental parameter combination constraint is a combination restriction condition set based on physical laws, actual application scenarios and chip feature data; divide the working voltage test range into multiple voltage test points according to the voltage step, and generate the voltage test sequence in order from small to large; combine the environmental test sequence and the voltage test sequence in a matrix form to generate the adaptive test scheme.

[0100] Furthermore, the first analysis result acquisition module 14 is also used to perform the following steps: obtain the expected voltage-leakage current characteristics under different environmental parameter conditions, and generate multiple expected voltage-leakage current curves; extract the first expected voltage-leakage current curve under the first environmental parameter condition; according to the leakage current data matrix, extract the row vector data of the first environmental parameter condition, obtain the corresponding actual voltage-leakage current characteristics, and generate a first actual voltage-leakage current curve; perform deviation evaluation on the actual voltage-leakage current curve based on the expected voltage-leakage current curve, obtain a first curve evaluation result, and add it to multiple curve evaluation results; based on the multiple curve evaluation results, generate the first analysis result.

[0101] Furthermore, the first analysis result acquisition module 14 is also used to perform the following steps: obtain full environmental combination data based on multiple environmental parameter test ranges; calculate the first environmental weight based on the frequency of occurrence of the first environmental parameter condition in the full environmental combination data, and add it to multiple environmental weights; perform weighted calculation on the multiple environmental weights and the multiple curve evaluation results to obtain the first analysis result.

[0102] Furthermore, the associated evaluation module 16 is also used to perform the following steps: based on the application scenario of the target low-power chip, obtain voltage changes and environmental changes, wherein the voltage changes characterize the degree of voltage fluctuation in the application scenario, and the environmental changes characterize the degree of environment fluctuation in the application scenario; determine a first weight coefficient based on the voltage changes, and determine a second weight coefficient based on the environmental changes; perform weighted calculation on the first analysis result and the first weight coefficient to obtain a voltage dimension evaluation score; perform weighted calculation on the second analysis result and the second weight coefficient to obtain an environmental dimension evaluation score; generate a leakage current characteristic evaluation result of the target low-power chip based on the voltage dimension evaluation score and the environmental dimension evaluation score.

[0103] Any step of the method described above can be stored as a computer instruction or program in an unlimited computer memory, and can be called and recognized by an unlimited computer processor to implement any method in the embodiments of the present application, without any unnecessary restrictions.

[0104] Furthermore, the first or second mentioned above not only represents an order relationship, but also represents a specific concept, and / or refers to the selection of multiple elements individually or in whole. Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the present application and its equivalent technologies, the present application intends to include these modifications and variations.

Claims

1. A leakage current test and analysis method for a low-power chip, characterized in that: include: Collect chip feature data of the target low-power chip, and determine multiple environmental parameter test ranges and operating voltage test ranges of the target low-power chip according to the chip feature data, wherein the multiple environmental parameter test ranges include a temperature test range, a humidity test range, and an electromagnetic interference test range; Generate an environmental test sequence according to the multiple environmental parameter test ranges, generate a voltage test sequence according to the working voltage test range, combine the environmental test sequence and the voltage test sequence to generate an adaptive test scheme; Based on the adaptive test scheme, environmental parameters are set and working voltage is applied, leakage current test data of the target low-power chip is obtained through a current sensor, and a leakage current data matrix is ​​constructed with the leakage current test data; Sequentially extracting row vector data of the leakage current data matrix, analyzing the voltage-leakage current characteristics under the same environmental parameter conditions, and obtaining a first analysis result; Sequentially extracting column vector data of the leakage current data matrix, analyzing the environment-leakage current characteristics under the same working voltage condition, and obtaining a second analysis result; Based on the first analysis result and the second analysis result, an associated evaluation is performed on the target low-power chip to obtain a leakage current characteristic evaluation result of the target low-power chip.

2. The method for testing and analyzing leakage current of a low-power chip according to claim 1, characterized in that: Determine multiple environmental parameter test ranges and operating voltage test ranges of the target low-power chip according to the chip characteristic data, wherein the multiple environmental parameter test ranges include a temperature test range, a humidity test range, and an electromagnetic interference test range, including: Constructing a retrieval constraint according to the chip feature data, performing data retrieval in a chip operation database based on the retrieval constraint, and acquiring a similar chip operation sample set, including a plurality of similar chip operation samples, wherein each similar chip operation sample has corresponding chip operation environment data and chip operating voltage data; Performing concentrated interval analysis on multiple environmental parameters in chip operating environment data of multiple similar chip operating samples, obtaining concentrated intervals of multiple environmental parameters, and forming an environmental parameter test range, wherein the multiple environmental parameters include at least temperature, humidity, and electromagnetic interference; Perform centralized interval analysis on the chip operating voltage data of multiple similar chip running samples to obtain the operating voltage test range.

3. The method for testing and analyzing leakage current of a low-power chip according to claim 2, characterized in that: Perform centralized interval analysis on the chip operating voltage data of multiple similar chip running samples to obtain the operating voltage test range, including: Sorting chip operating voltage data of multiple similar chip operation samples from large to small according to numerical values, obtaining voltage data sorting results, and determining a voltage median according to the voltage data sorting results; Extracting the maximum voltage value in the voltage data sorting result, and obtaining the median between the voltage median and the maximum voltage value as the test voltage upper limit value; Extracting the minimum voltage value in the voltage data sorting result, and obtaining the median between the minimum voltage value and the voltage median as the test voltage lower limit value; An operating voltage test range is generated according to the test voltage upper limit value and the test voltage lower limit value.

4. The method for testing and analyzing leakage current of a low-power chip according to claim 1, characterized in that: Generating an environmental test sequence according to the multiple environmental parameter test ranges, generating a voltage test sequence according to the working voltage test range, combining the environmental test sequence and the voltage test sequence to generate an adaptive test scheme, including: Dividing the temperature test range into a plurality of temperature test points according to the temperature step length, dividing the humidity test range into a plurality of humidity test points according to the humidity step length, and dividing the electromagnetic interference test range into a plurality of electromagnetic interference test points according to the electromagnetic interference step length; Arrange and combine multiple temperature test points, multiple humidity test points and multiple electromagnetic interference test points to generate an environmental parameter combination set; The environmental parameter combination set is screened based on preset environmental parameter combination constraints to obtain a valid environmental parameter combination set, and the environmental test sequence is generated, wherein the environmental parameter combination constraint is a combination restriction condition set based on physical laws, actual application scenarios and chip feature data; Dividing the working voltage test range into a plurality of voltage test points according to the voltage step length, and generating the voltage test sequence in order from small to large; The environmental test sequence and the voltage test sequence are combined in a matrix form to generate the adaptive test scheme.

5. The method for testing and analyzing leakage current of a low-power chip according to claim 1, characterized in that: Extracting row vector data of the leakage current data matrix in sequence, analyzing the voltage-leakage current characteristics under the same environmental parameter conditions, and obtaining a first analysis result, including: Obtain the expected voltage-leakage current characteristics under different environmental parameter conditions and generate multiple expected voltage-leakage current curves; Extracting a first expected voltage-leakage current curve under a first environmental parameter condition; Extracting row vector data of the first environmental parameter condition according to the leakage current data matrix, obtaining the corresponding actual voltage-leakage current characteristic, and generating a first actual voltage-leakage current curve; Performing deviation evaluation on the actual voltage-leakage current curve based on the expected voltage-leakage current curve, obtaining a first curve evaluation result, and adding the result to the plurality of curve evaluation results; The first analysis result is generated according to the plurality of curve evaluation results.

6. The method for testing and analyzing leakage current of a low-power chip according to claim 5, characterized in that: Generating the first analysis result according to the plurality of curve evaluation results includes: Obtain full environmental combination data based on multiple environmental parameter test ranges; Calculate a first environmental weight according to the frequency of occurrence of the first environmental parameter condition in the full amount of environmental combination data, and add it to the multiple environmental weights; The multiple environmental weights and the multiple curve evaluation results are weighted and calculated to obtain a first analysis result.

7. The method for testing and analyzing leakage current of a low-power chip according to claim 1, characterized in that: Performing an associated evaluation on the target low-power chip based on the first analysis result and the second analysis result to obtain a leakage current characteristic evaluation result of the target low-power chip includes: Based on the application scenario of the target low-power chip, the voltage change and the environment change are obtained, wherein the voltage change represents the degree of voltage fluctuation in the application scenario, and the environment change represents the degree of environment fluctuation in the application scenario; Determine a first weight coefficient according to the voltage change, and determine a second weight coefficient according to the environment change; Performing weighted calculation on the first analysis result and the first weight coefficient to obtain a voltage dimension evaluation score; Performing weighted calculation on the second analysis result and the second weight coefficient to obtain an environmental dimension evaluation score; A leakage current characteristic evaluation result of the target low-power chip is generated according to the voltage dimension evaluation score and the environment dimension evaluation score.

8. A leakage current test and analysis platform for low-power chips, characterized in that: For executing the method according to any one of claims 1 to 7, the platform comprises: Chip feature data acquisition module: used to collect chip feature data of the target low-power chip, and determine multiple environmental parameter test ranges and operating voltage test ranges of the target low-power chip according to the chip feature data, wherein the multiple environmental parameter test ranges include temperature test range, humidity test range and electromagnetic interference test range; An environmental test sequence generation module: used to generate an environmental test sequence according to the multiple environmental parameter test ranges, and to generate a voltage test sequence according to the working voltage test range, and to combine the environmental test sequence and the voltage test sequence to generate an adaptive test scheme; A leakage current test data acquisition module is used to set environmental parameters and apply working voltage based on the adaptive test scheme, acquire leakage current test data of the target low-power chip through a current sensor, and construct a leakage current data matrix with the leakage current test data; A first analysis result acquisition module: used to sequentially extract row vector data of the leakage current data matrix, analyze the voltage-leakage current characteristics under the same environmental parameter conditions, and acquire a first analysis result; A second analysis result acquisition module: used to sequentially extract column vector data of the leakage current data matrix, analyze the environment-leakage current characteristics under the same working voltage conditions, and acquire a second analysis result; An associated evaluation module is used to perform an associated evaluation on the target low-power chip based on the first analysis result and the second analysis result, and obtain a leakage current characteristic evaluation result of the target low-power chip.

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