Tunable photodetector and on-chip optical computing architecture

Abstract

The application provides an adjustable photodetector and an on-chip optical computing architecture, which can change the weight of photocurrent by using external electrical signals to realize adjustable photodetection without using a silicon-based electro-optical modulation unit. The adjustable photodetector comprises: a first doped region connected with a first electrode for grounding; a second doped region forming a first PN junction with the first doped region; an optical absorption region in contact with the first PN junction and connected with an incident light waveguide for receiving an input optical signal; a third doped region forming a second PN junction with the second doped region and connected with a second electrode for connecting a voltage source and outputting a photocurrent, the voltage source enabling the first PN junction to be in an inverse bias state, and the photocurrent being converted from the input optical signal; and a fourth doped region forming a third PN junction with the second doped region and connected with a third electrode for receiving a control voltage, the control voltage being used for regulating the weight of the photocurrent.

Description

Technical Field

[0001] This invention relates to the field of optical computing, and in particular to an tunable photodetector for performing multiplication calculations, and an on-chip optical computing architecture incorporating the tunable photodetector. Background Technology

[0002] With the emergence of applications requiring massive computing power, such as artificial intelligence and virtual reality, accelerating matrix-vector multiplication (MVM) has become increasingly important. However, due to the slowdown of Moore's Law, traditional electronic chips such as GPUs are gradually approaching their computing power bottlenecks, requiring manufacturers to increase costs exponentially in exchange for improved computing power. Meanwhile, the parameters of models continue to grow exponentially, making it increasingly difficult to improve computing power through the development of traditional electronic chips.

[0003] Therefore, in the past, various architectures have been proposed to realize complex operations through optical computing. In these architectures, multiple multiplication units are often used to form an array, and light is used as the propagation carrier to realize multiplication calculation by modulating electrical signals on the light.

[0004] Figure 9 This is a schematic diagram illustrating the principle architecture of a multiplication unit in existing optical computing. For example... Figure 9 As shown, existing optical computing multiplication units mainly consist of two parts: an electro-optic modulation unit, which performs optical domain multiplication calculations; and a photoelectric conversion unit, which performs photoelectric conversion. Specifically, as... Figure 9 As shown, optical signal a and electrical signal b are input to the electro-optic modulation unit, which performs optical domain multiplication and outputs the optical domain calculation result a×b. The photoelectric conversion unit is responsible for converting the optical domain multiplication result a×b into current, which is the electrical domain a×b, for subsequent signal processing and storage.

[0005] Existing electro-optic modulation units mainly fall into three categories: The first is carrier-injection type Mach-Zehnder interferometers (MZIs) or micro-ring resonators (MRRs), which achieve electro-optic modulation through thermal or electrical tuning; the second is carrier-accumulation type MZIs or MRRs, which achieve electro-optic modulation through electrical tuning; and the third is carrier-depletion type MZIs or MRRs. All three types of electro-optic modulation units exhibit insertion loss, which decreases in the order of type I > type II > type III. Furthermore, existing photoelectric conversion units primarily utilize photodiodes. Summary of the Invention

[0006] The technical problem to be solved by the present invention

[0007] As mentioned above, in existing multiplication units, regardless of the type used, silicon-based electro-optic modulation units all exhibit a certain degree of optical domain insertion loss. This loss becomes even more severe when forming large-scale multiplication arrays.

[0008] In addition, silicon-based electro-optic modulation units are generally large in size, on the order of hundreds of micrometers. Therefore, when forming a multiplication array, the computational density of the multiplication units will be greatly reduced.

[0009] In addition, silicon-based electro-optic modulation units also introduce a certain degree of electrical energy consumption. This energy consumption is particularly severe when the units are configured into large-scale multiplication arrays.

[0010] The present invention was made in view of the above-mentioned problems, and its object is to provide a tunable photodetector and an on-chip optical computing architecture having the tunable photodetector, which can use an external electrical signal to change the weight of the photocurrent to achieve tunable photodetection without using a silicon-based electro-optic modulation unit, thereby reducing optical insertion loss, increasing computing density, and reducing electrical domain power consumption.

[0011] Technical solutions to solve technical problems

[0012] To address the aforementioned problems, the tunable photodetector according to a first aspect of the present invention comprises: a first doped region connected to a first electrode for grounding; a second doped region forming a first PN junction with the first doped region; a light-absorbing region contacting the first PN junction and connected to an incident light waveguide for receiving an input light signal; a third doped region forming a second PN junction with the second doped region and connected to a second electrode for connecting a voltage source and outputting a photocurrent, wherein the voltage source causes the first PN junction to be in an inverted bias state, and the photocurrent is converted from the input light signal; and a fourth doped region forming a third PN junction with the second doped region and connected to a third electrode for receiving a control voltage, wherein the control voltage is used to adjust the weight of the photocurrent.

[0013] Optionally, the first doped region is disposed on one side of the second doped region, the light-absorbing region is disposed on the upper surface of the first doped region and the second doped region, or is partially embedded in the upper surface of the first doped region and the second doped region, and the third doped region and the fourth doped region are disposed on the other side of the second doped region opposite to the first doped region.

[0014] Optionally, the light-absorbing region is disposed on the upper surface of the second doped region, or partially embedded in the upper surface of the second doped region, wherein the first doped region is formed by doping the upper surface of the light-absorbing region.

[0015] Optionally, the third doped region and the fourth doped region are disposed on the same side of the second doped region.

[0016] Optionally, the third doped region and the fourth doped region are respectively disposed on the sides of the second doped region.

[0017] Optionally, the doping type of the first doped region is P-type, or the doping type of the first doped region is N-type.

[0018] Furthermore, to address the aforementioned issues, the on-chip optical computing architecture according to the second aspect of the present invention is used to implement vector-matrix multiplication of an input vector and a weight matrix. The on-chip optical computing architecture includes: an electro-optic conversion unit that converts the input electrical signal corresponding to each element of the input vector into an input optical signal; and a computation matrix unit comprising an array of at least one tunable photodetector according to the first aspect of the present invention. The input optical signal from the photoelectric conversion unit is input to the incident waveguide of the tunable photodetector. The first electrode of the tunable photodetector is grounded, the second electrode of the tunable photodetector is connected to the voltage source, a control voltage corresponding to each element of the weight matrix is ​​input to the third electrode of the tunable photodetector, and the photocurrents output from the second electrodes of the tunable photodetector in the same column are summed into an output current as the calculation result of the vector-matrix multiplication.

[0019] Optionally, the on-chip optical computing architecture further includes a transimpedance amplifier unit, which includes a transimpedance amplifier that amplifies the output current from the same column of the computing matrix unit and converts it into an output voltage for output.

[0020] Optionally, the transimpedance amplifier is a resistive transimpedance amplifier or a capacitive transimpedance amplifier.

[0021] Optionally, the photoelectric conversion unit includes: a laser that outputs laser light; and an electro-optic converter that modulates the input electrical signal onto the laser light to obtain the input optical signal.

[0022] Optionally, the photoelectric conversion unit includes a direct-modulated laser that directly modulates the input electrical signal into the input optical signal.

[0023] Invention Effects

[0024] According to the tunable photodetector and the on-chip optical computing architecture with the tunable photodetector of the present invention, the weight of the photocurrent can be changed by using an external electrical signal to achieve tunable photodetection without using a silicon-based electro-optic modulation unit, thereby reducing optical insertion loss, increasing computing density, and reducing electrical domain power consumption. Attached Figure Description

[0025] Figure 1 This is a schematic diagram showing the structure of the tunable photodetector according to Embodiment 1.

[0026] Figure 2 It is used for Figure 1 A schematic diagram illustrating the working principle of an adjustable photodetector.

[0027] Figure 3 This is a schematic diagram illustrating an example of the adjustment characteristic curve of an adjustable photodetector.

[0028] Figure 4 This is a schematic diagram showing the structure of the adjustable photodetector involved in a variation of Embodiment 1.

[0029] Figure 5 It is used for Figure 4 A schematic diagram illustrating the working principle of an adjustable photodetector.

[0030] Figure 6 This is a schematic diagram illustrating the structure of the on-chip optical computing architecture according to Embodiment 2.

[0031] Figure 7(a) is a circuit diagram showing an example of a transimpedance amplifier, and Figure 7(b) is a circuit diagram showing another example of a transimpedance amplifier.

[0032] Figure 8 This is a schematic diagram illustrating the structure of the on-chip optical computing architecture involved in a variation of Embodiment 2.

[0033] Figure 9 This is a schematic diagram illustrating the principle architecture of the multiplication unit in existing optical computing. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for illustration and explanation of the embodiments of this application and are not intended to limit the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0035] It should be noted that the technical solutions of the various embodiments of this application can be combined with each other, but only if they are based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by this application.

[0036] Implementation Method 1

[0037] Figure 1 This is a schematic diagram illustrating the structure of the tunable photodetector according to Embodiment 1. This tunable photodetector can be integrated on-chip with other chips and electronic components to form a more complex on-chip optical computing architecture.

[0038] like Figure 1 As shown, the tunable photodetector includes a first doped region 101, a second doped region 102, a light absorption region 201, a third doped region 103, and a fourth doped region 104.

[0039] The first doped region 101 may be made of semiconductor materials such as silicon or group III-V compounds. In this embodiment, the doping type of the first doped region 101 is P-type. The first doped region 101 is connected to a first electrode 301, which is used for grounding.

[0040] The second doped region 102 may be made of semiconductor materials such as silicon or group III-V compounds. In this embodiment, the doping type of the second doped region 102 is opposite to that of the first doped region 101, being N-type, and the first doped region 101 is in contact with the second doped region 102. Thus, a PN junction is formed between the first doped region 101 and the second doped region 102. In this embodiment, this PN junction is referred to as the first PN junction. Furthermore, in this embodiment, the first doped region 101 is disposed on one side of the second doped region 102 (the left side in the figure), but the present invention is not limited thereto. Examples of other positional relationships between the first doped region 101 and the second doped region 102 will be described below.

[0041] The material selected for the light absorption region 201 is capable of absorbing optical signals and converting them into electrical signals. Depending on the required optical wavelength, semiconductor materials such as germanium, III-V compound semiconductors, and silicon can be used. The light absorption region 201 is in contact with the aforementioned first PN junction and is connected to the incident light waveguide 401. In this embodiment, the light absorption region 201 is embedded in the upper surfaces of the first doped region 101 and the second doped region 102, but the invention is not limited to this. The light absorption region 201 does not necessarily have to be embedded in the upper surfaces of the first doped region 101 and the second doped region 102; it can simply be disposed on the upper surfaces of the first doped region 101 and the second doped region 102, as long as it can simultaneously contact both the first doped region 101 and the second doped region 102.

[0042] The incident waveguide 401 is used to receive the input optical signal to the photodetector and is made of a material that does not absorb or weakly absorbs the input optical signal. Depending on the requirements of different optical wavelengths, waveguide materials such as silicon, III-V compound semiconductors, and silicon nitride can be used.

[0043] The third doped region 103 can be made of semiconductor materials such as silicon or group III-V compounds. In this embodiment, the doping type of the third doped region 103 is opposite to that of the second doped region 102, which is P-type, and the third doped region 103 is in contact with the second doped region 102. Thus, a PN junction is formed between the third doped region 103 and the second doped region 102. In this embodiment, this PN junction is referred to as the second PN junction. In addition, in this embodiment, the third doped region 103 is disposed on the other side of the second doped region 102 opposite to the first doped region 101 (the right side in the figure), but the present invention is not limited to this. As long as a PN junction can be formed between the third doped region 103 and the second doped region 102, and the layout of the doped regions does not affect the input and output of optical and electrical signals, the third doped region 103 can be disposed at any position of the second doped region 102.

[0044] The third doped region 103 is connected to a second electrode 302, which is used to connect to a voltage source (not shown) and outputs a photocurrent as the detection result of the adjustable photodetector. In this embodiment, the voltage source provides a positive voltage to the adjustable photodetector, thereby, together with the grounding of the first electrode 301, causing the first PN junction to be in a reverse bias state. This allows the photodiode (PD) composed of the first doped region 101, the second doped region 102, and the light absorption region 201 to operate in a reverse bias state, thereby enabling the detection of the input optical signal. Furthermore, the photocurrent output from the second electrode 302 is a current converted from the input optical signal input to the incident light waveguide 201. The specific conversion method of the photocurrent will be described in detail below.

[0045] The fourth doped region 104 can be made of semiconductor materials such as silicon or group III-V compounds. In this embodiment, the doping type of the fourth doped region 104 is opposite to that of the second doped region 102, which is P-type, and the fourth doped region 104 is in contact with the second doped region 102. Thus, a PN junction is formed between the fourth doped region 104 and the second doped region 102. In this embodiment, this PN junction is referred to as the third PN junction. In addition, in this embodiment, the fourth doped region 104 is disposed on the other side of the second doped region 102 opposite to the first doped region 101 (the right side in the figure), but the present invention is not limited to this. As long as a PN junction can be formed between the fourth doped region 104 and the second doped region 102, and the layout of the doped regions does not affect the input and output of optical and electrical signals, the fourth doped region 104 can be disposed at any position of the second doped region 102.

[0046] The fourth doped region 104 is connected to a third electrode 303, which is used to receive a control voltage, which functions as an external electrical signal to regulate the weight of the photocurrent output from the second electrode 302.

[0047] The working principle of the adjustable photodetector in this embodiment will be explained below.

[0048] Figure 2 It is used for Figure 1 A schematic diagram illustrating the working principle of an adjustable photodetector. Figure 2 To be understood as Figure 1 The structure was cross-sectioned and from Figure 1 The cross-sectional view is obtained by looking upwards from below, but for ease of explanation, the image shows... Figure 1 The fourth doped region 104 was transferred to the upper surface of the second doped region 102, and the lead-out directions of each electrode were adjusted. Furthermore, Figure 2 The incident light waveguide 401 is omitted, and the light absorption region 201 adopts a structure embedded in the upper surface of the first doped region 101 and the second doped region 102.

[0049] like Figure 2 As shown, firstly, the first electrode 301, which is connected to the anode of the adjustable photodetector, is grounded, and a positive voltage V is applied to the cathode through the second electrode 302, which is connected to a voltage source (not shown). cThis forward biases the second PN junction between the P-type third doped region 103 and the N-type second doped region 102. Consequently, a positive voltage can be guided through the second doped region 102 to the second doped region side (N-side) of the first PN junction between the P-type first doped region 101 and the N-type second doped region 102, forming a reverse bias with the grounded first doped region side (P-side). Therefore, the photodiode (PD) composed of the first doped region 101, the second doped region 102, and the light-absorbing region 201 operates in a reverse-biased state.

[0050] Next, the input optical signal, which is fed into the optical absorption region 201 through the incident optical waveguide, is absorbed by the Ge material in the optical absorption region 201, generating photogenerated carriers. These photogenerated carriers then undergo directional movement under the influence of the external electric field generated by the reverse bias in the first PN junction, thereby generating a photocurrent I. photo .

[0051] At this time, a positive control voltage V is applied to the fourth doped region 104 through the third electrode 303. g Approximately when V g <V c When the gate terminal (i.e., the fourth doped region 104 of the P-type and the second doped region 102 of the N-type) is reverse-biased and cut off, the second PN junction at the cathode terminal is forward-biased and turned on. The photocurrent generated in Ge of the light absorption region 201 flows out from the second electrode 302 at the cathode terminal, forming the output current I. s .

[0052] Then, as the control voltage Vs gradually increases, a portion of the photocurrent will be shunted from the gate terminal, approximately when Vs increases. g >V c At this time, the third PN junction at the gate is forward-biased and the second PN junction at the cathode is reverse-biased and cut off. The photocurrent generated in Ge of the light absorption region 201 flows out from the gate, while there is almost no output current I. s It flows out from the second electrode 302 at the cathode end.

[0053] Figure 3 This is a schematic diagram illustrating an example of the adjustment characteristic curve of an adjustable photodetector, showing the relationship between the bias voltage on the third electrode 303 and the percentage of the total photocurrent generated in Ge, as described above. Figure 3As shown, taking the case where a positive voltage of approximately 2V is applied to the cathode through the second electrode 302 as an example, when the control voltage applied to the third electrode 303 is less than 2V (1.8V), almost 100% of the photocurrent flows through the second electrode 302. As the control voltage gradually increases, a portion of the photocurrent is shunted from the gate terminal, thus the photocurrent flowing through the second electrode 302 gradually decreases. When the control voltage equals 2V, almost half of the photocurrent is shunted from the gate terminal, so the proportion of the photocurrent flowing through the second electrode 302 is approximately 50%. Subsequently, as the control voltage further increases, the photocurrent flowing through the second electrode 302 further decreases until it is almost zero.

[0054] Depend on Figure 3 It can be seen that by adjusting the control voltage V g It can change the output current I flowing through the cathode. s This refers to the weighting of the photocurrent. If the weighting of the photocurrent is set as R(V)... g Let the photocurrent generated by Ge in the light absorption region 201 be I. photo Then the output current I s It can be represented by the following formula (1).

[0055] [Mathematical Expression 1]

[0056] I s =I photo *R(V g )

[0057] The structure and working principle of the adjustable photodetector according to Embodiment 1 of the present invention have been described above. Figure 1 In the structure of the tunable photodetector, the doped region 103 in the lower right corner of the figure is defined as the third doped region, and the doped region 104 in the upper right corner is defined as the fourth doped region. The second electrode 302 and the third electrode 303 connected to them are defined respectively. However, this structure is merely an example. Alternatively, the doped region 104 in the upper right corner can be defined as the third doped region, and the doped region 103 in the lower right corner as the fourth doped region, with the second and third electrodes redefined accordingly. In other words, whichever electrode 302 or 303 serves as the output terminal of the photocurrent, the other can simply serve as the input terminal of the control voltage.

[0058] Furthermore, the above description shows that the first doped region 101 is P-type, and correspondingly, the second doped region 102 is N-type, and the third and fourth doped regions 103 and 104 are P-type. However, the present invention is not limited to this; the doping types of the first doped region 101, the third doped region 103, and the fourth doped region 104 can be changed to N-type, and correspondingly, the doping type of the second doped region 102 can be changed to P-type. In this case, the first electrode 301 connected to the first doped region 101 remains grounded. Simply changing the voltage source input to the second electrode 302 to a negative voltage and also changing the control voltage on the third electrode 303 to a negative voltage will still ensure that the first PN junction between the second doped region 102 and the first doped region 101 is in a reverse-biased operating state.

[0059] As described above, the tunable photodetector according to this embodiment can adjust the weight of the photocurrent corresponding to the input optical signal input from the incident light waveguide 401 by adjusting an external electrical signal connected to the third electrode 303. Structurally, it eliminates the need for a silicon-based electro-optic modulation unit and integrates the multiplication unit into the photoelectric conversion unit. As a result, it can significantly reduce optical insertion loss, decrease the size of the tunable photodetector, and reduce electrical power consumption.

[0060] Variations

[0061] The above description illustrates an embodiment of a so-called LPIN (Horizontal Field) type photodetector in which both doped regions 101 and 102 constituting a PN junction are disposed below the light absorption region 201. Next, an embodiment of a so-called VPIN (Vertical Field) type photodetector will be described, in which the first doped region 101 of the two doped regions constituting a PN junction is formed by doping the upper surface of the light absorption region 201.

[0062] Figure 4 This is a schematic diagram showing the structure of the adjustable photodetector according to a variation of Embodiment 1. Figure 5 It is used for Figure 4 A schematic diagram illustrating the working principle of an adjustable photodetector can be used to explain this. Figure 5 To be understood as Figure 1 The structure was cross-sectioned and from Figure 4 The cross-sectional view is obtained by observing from above and below. Figure 4 and Figure 5 In the middle, regarding the above Figure 1 and Figure 2 The same structure is labeled with the same number. The following mainly refers to the same structure. Figure 1 , Figure 2 The differences in their structures will be explained.

[0063] like Figure 4 and Figure 5 As shown, the light-absorbing region 201 is embedded in the upper surface of the second doped region 102, and the first doped region 101 is formed by P doping the upper surface of the light-absorbing region 201. Here, as described above, the light-absorbing region 201 can also be disposed on the upper surface of the second doped region 102 instead of being embedded, as long as the light-absorbing region 201 and the second doped region 102 can be in contact.

[0064] In this modified example, the third doped region 103 and the fourth doped region 104 are respectively disposed on the left and right sides of the second doped region 102, but the present invention is not limited thereto. The third doped region 103 and the fourth doped region 104 may also be disposed on the same side (left or right) of the second doped region 102, or at any other position, as long as a second PN junction can be formed between the third doped region 103 and the second doped region 102, and a third PN junction can be formed between the fourth doped region 104 and the second doped region 102.

[0065] like Figure 5 As shown, by performing P-type doping on the upper surface of the light absorption region 201 and N-type doping on the second doped region 102 in the region below the light absorption region 201, a first PN junction can also be formed longitudinally between the first doped region 101 and the second doped region 102, and this first PN junction can be made in contact with the light absorption region 201. Thus, compared with the above... Figure 2 Similar to the structure in the first PN junction, the input optical signal, which is input to the optical absorption region 201 through the incident optical waveguide, is absorbed by the Ge material in the optical absorption region 201, and the resulting photogenerated carriers generate a photocurrent I in the first PN junction. photo Furthermore, the voltage V applied to the ground on the first electrode 301 and the second electrode 302 is... c and the control voltage V applied to the third electrode 303 g Combined, by adjusting the control voltage V g The magnitude of the current I flowing through the cathode can be changed according to the above formula (1). s That is, the weighting of the photocurrent R(V) g ).

[0066] This also enables the weighted adjustment of photocurrent without the need for silicon-based electro-optic modulation units, thereby significantly reducing optical insertion loss, decreasing the size of tunable photodetectors, and reducing electrical power consumption.

[0067] Implementation Method 2

[0068] The following describes how to implement the input vector X(x1, x2, ..., x) using the adjustable photodetector in Embodiment 1 and its variations. N) and weight matrix W(w 11 , ..., w mn , ...w M,N This invention describes an on-chip optical computing architecture using N*M vector matrix multiplication. In this embodiment, M=N=4 is used as an example, but the invention is not limited to this. M and N can be arbitrarily set, even to M=N=1.

[0069] Figure 6 This is a schematic diagram illustrating the structure of the on-chip optical computing architecture according to Embodiment 2. (As shown...) Figure 6 As shown, the on-chip optical computing architecture includes a photoelectric conversion unit 10 and a computing matrix unit 20.

[0070] The photoelectric conversion unit 10 converts multiple input electrical signals x1, x2, x3, x4 corresponding to each element of the input vector X(x1, x2, x3, x4) into multiple input optical signals, which are then provided to the calculation matrix unit 20 described later.

[0071] Specifically, in this embodiment, the photoelectric conversion unit 10 includes a laser and an electro-optic converter (EO). The laser generates laser light and fans the generated laser light into multiple electro-optic converters. Each electro-optic converter modulates the corresponding input electrical signal x1, x2, x3, x4 into the laser light from the laser, thereby obtaining multiple input optical signals.

[0072] The computation matrix unit 20 includes an array of at least one (here, corresponding to the size of the vectors and matrices involved in the computation, 4*4 = 16) tunable photodetectors as described in Embodiment 1 and its variations, with each multiplication unit (MU) in the array corresponding to a tunable photodetector. In this embodiment, each input optical signal from the photoelectric conversion unit 10 is input to the incident light waveguide of the corresponding row of the tunable photodetector, the first electrode of each tunable photodetector is grounded (Gnd), and the second electrode of each tunable photodetector is connected to a voltage source (V). DD Connected to the weight matrix W(w) 11 , ..., w 44 The corresponding control voltage w for each element of ) 11 , ..., w 44 The input is given to the third electrode of each tunable photodetector, and the photocurrents of each column of tunable photodetectors are summed up. The total photocurrents output from the second electrode of the same column of tunable photodetectors are then combined into multiple output currents I1, ..., I4, which are used as the calculation results of vector matrix multiplication.

[0073] In addition, such as Figure 6As shown, the on-chip optical computing architecture may also include a transimpedance amplifier unit 30. In this embodiment, the transimpedance amplifier unit 30 includes multiple transimpedance amplifiers (TIAs), each of which amplifies and converts the output currents I1, ..., I4 from the same column of the computing matrix unit 20 into corresponding output voltages y1, y2, y3, y4 for sampling and data acquisition by peripheral analog-to-digital converters (ADCs).

[0074] Figure 7(a) is a circuit diagram showing one example of a transimpedance amplifier, and Figure 7(b) is a circuit diagram showing another example of a transimpedance amplifier. The transimpedance amplifier can be a resistive transimpedance amplifier as shown in Figure 7(a) or a capacitive transimpedance amplifier as shown in Figure 7(b). By selecting the resistors and capacitors, the conversion from output current I (I1, ..., I4) to output voltage y (y1, y2, y3, y4) can be achieved.

[0075] Variations

[0076] The above description illustrates an embodiment in which the photoelectric conversion unit 10 is constructed using a single laser and multiple electro-optical converters (EOs). An embodiment in which the photoelectric conversion unit 10 is constructed using multiple directly modulated lasers will be described below.

[0077] Figure 8 This is a schematic diagram illustrating the structure of the on-chip optical computing architecture involved in a variation of Embodiment 2. For example... Figure 8 As shown, the photoelectric conversion unit 10 includes multiple directly modulated lasers. Each directly modulated laser can be, for example, a DFB laser, a vertical cavity surface laser, etc., which directly modulates the input electrical signals x1, x2, x3, x4 into multiple input optical signals, and then couples them into the incident light waveguide of the tunable photodetector in the corresponding row of the calculation matrix unit 20.

[0078] According to the on-chip optical computing architecture involved in this embodiment and its variations, vector matrix multiplication can be implemented with a simple structure, and a large number of silicon-based electro-optic modulation units are eliminated in the computing matrix unit. Therefore, even when processing large-scale vector matrix multiplication, optical insertion loss can be significantly reduced, computing area can be saved, computing density can be significantly increased, and electrical domain power consumption can be significantly reduced.

[0079] The foregoing description of the tunable photodetector and on-chip optical computing architecture involved in this invention should be considered as merely illustrative and not restrictive. The scope of this disclosure is defined by the claims, not by the above-described embodiments, and also includes all modifications and variations within the meaning and scope equivalent to the claims.

[0080] Industrial practicality

[0081] As described above, the tunable photodetector and on-chip optical computing architecture of the present invention are useful for implementing efficient matrix-vector multiplication on-chip.

[0082] Label Explanation

[0083] 10 photoelectric conversion units

[0084] 20 computational matrix units

[0085] 30 transimpedance amplifier units

[0086] 101 First Doped Region

[0087] 102 Second Doped Region

[0088] 103 Third Doped Region

[0089] 104 fourth doped region

[0090] 201 light absorption region

[0091] 301 First Electrode

[0092] 302 Second Electrode

[0093] 303 third electrode

[0094] 401 Incident Waveguide.

Claims

1. An adjustable photodetector, characterized in that, include: A first doped region, the first doped region being connected to a first electrode for grounding; A second doped region, wherein a first PN junction is formed between the second doped region and the first doped region; The light absorption region is in contact with the first PN junction and is connected to an incident light waveguide for receiving input light signals. A third doped region is formed between the third doped region and the second doped region, and a second electrode is connected to it for connecting a voltage source and outputting photocurrent. The voltage source puts the first PN junction in an inverted bias state, and the photocurrent is converted from the input optical signal. as well as A fourth doped region is formed with the second doped region by a third PN junction and connected to a third electrode for receiving a control voltage, which is used to regulate the weight of the photocurrent.

2. The adjustable photodetector as described in claim 1, characterized in that, The first doped region is disposed on one side of the second doped region. The light-absorbing region is disposed on the upper surface of the first doped region and the second doped region, or is partially embedded in the upper surface of the first doped region and the second doped region. The third doped region and the fourth doped region are disposed on the opposite side of the second doped region to the first doped region.

3. The adjustable photodetector as described in claim 1, characterized in that, The light-absorbing region is disposed on the upper surface of the second doped region, or partially embedded in the upper surface of the second doped region. The first doped region is formed by doping the upper surface of the light-absorbing region.

4. The adjustable photodetector as described in claim 3, characterized in that, The third doped region and the fourth doped region are disposed on the same side of the second doped region.

5. The adjustable photodetector as described in claim 3, characterized in that, The third doped region and the fourth doped region are respectively disposed on the sides of the second doped region.

6. The tunable photodetector according to any one of claims 1 to 5, characterized in that, The first doped region is P-type. Alternatively, the doping type of the first doped region is N-type.

7. An on-chip optical computing architecture, wherein the on-chip optical computing architecture is used to implement vector-matrix multiplication of an input vector and a weight matrix, characterized in that, include: An electro-optical conversion unit converts the input electrical signal corresponding to each element of the input vector into an input optical signal; as well as A computational matrix unit comprising an array of at least one tunable photodetector as described in any one of claims 1 to 6, wherein the input optical signal from the photoelectric conversion unit is input to the incident waveguide of the tunable photodetector, the first electrode of the tunable photodetector is grounded, the second electrode of the tunable photodetector is connected to the voltage source, a control voltage corresponding to each element of the weight matrix is ​​input to the third electrode of the tunable photodetector, and the photocurrents output from the second electrodes of the tunable photodetectors in the same column are summed into an output current as the calculation result of the vector matrix multiplication.

8. The on-chip optical computing architecture as described in claim 7, characterized in that, It also includes a transimpedance amplifier unit, which includes a transimpedance amplifier that amplifies the output current from the same column of the computation matrix unit and converts it into an output voltage for output.

9. The on-chip optical computing architecture as described in claim 8, characterized in that, The transimpedance amplifier is either a resistive transimpedance amplifier or a capacitive transimpedance amplifier.

10. The on-chip optical computing architecture as described in any one of claims 7 to 9, characterized in that, The photoelectric conversion unit includes: A laser that outputs laser light; and An electro-optic converter modulates the input electrical signal onto the laser to obtain the input optical signal.

11. The on-chip optical computing architecture as described in any one of claims 7 to 9, characterized in that, The photoelectric conversion unit includes a direct-modulation laser, which directly modulates the input electrical signal into the input optical signal.

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