Low power state machine and clock gating per port granularity for cxl switch chips

Abstract

The application discloses a low-power state machine and a clock gating method with port granularity for a CXL switch chip, comprising: obtaining the activity parameters of each port of the switch in multiple dimensions; independently determining the idle level to which the port belongs; independently managing a low-power state machine for each port, the state of which is associated with the idle level; initiating or exiting the corresponding type of link low-power state in response to the state conversion of the low-power state machine; cooperatively controlling the clock supply of part or all of the logic sub-modules in the port; receiving a wake-up signal or a new transaction request for the port. By independently monitoring the activity state of each port and matching the corresponding idle level, fine low-power management with port granularity is achieved. The low-power state machine is coupled with the link power state and the internal clock gating depth, so that the idle port can turn off the clock of part of the logic module as needed to reduce dynamic power consumption, and quickly restore the clock supply when waking up to reduce the response delay.

Description

Technical Field

[0001] This invention relates to a low-power state machine for a CXL switch chip and a clock gating method at the port level, and particularly to the field of computer interconnect and data center architecture technology. Background Technology

[0002] CXL (Compute Express Link) is a high-speed cache coherent interconnect protocol built on the PCIe physical layer. Its power management mechanism mainly inherits the link-level power management of PCIe. CXL link power management defines link states such as L0, L0p, L1, and L2.

[0003] In CXL switches containing dozens to hundreds of ports, not all ports are always operating at full capacity. Some ports may be underutilized due to idle connected devices or fluctuating traffic. However, existing link-level power management solutions have the following drawbacks: First, they cannot perceive the actual activity status of ports within the switch, causing the clock allocation network and logic modules of idle ports to continue operating at full speed, resulting in considerable power waste. Second, clock gating decisions are usually based on global states, lacking a fine-grained control mechanism linked to port-level activity status. Third, when a port is activated from an idle state, the clock recovery and link wake-up processes are executed sequentially, leading to increased response latency.

[0004] Therefore, how to achieve fine-grained low-power state management and clock-gated collaborative control based on port granularity has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] This invention provides a low-power state machine for a CXL switch chip and a port-level clock gating method to overcome the technical problem that existing technologies cannot perform fine-grained low-power control and clock gating based on port granularity, thereby achieving the defect of reducing idle port power consumption and improving energy efficiency on demand.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] This invention discloses a low-power state machine for a CXL switch chip and a port-level clock gating method, comprising: acquiring multi-dimensional activity parameters of each port of the switch; independently determining the idle level of each port based on its own activity parameters; independently managing a low-power state machine for each port according to the idle level at the port level, wherein the state of the low-power state machine is associated with the idle level; initiating or exiting a corresponding type of link low-power state in response to the state transition of the low-power state machine; coordinating the clock supply to some or all logic sub-modules within the port based on the current state of the low-power state machine of each port; and receiving wake-up signals or new transaction requests for the port.

[0008] Furthermore, the idle level includes four levels: L0-ACTIVE, L0p-LIGHT, L1-IDLE, and L2-DEEP; the states of the low-power state machine include: S0-ACTIVE, S0p-LIGHT, S1-IDLE, and S2-DEEP, each corresponding to one of the idle levels.

[0009] As one implementation, the activity parameters include at least one of the following: instantaneous traffic, idle duration, transaction arrival interval, queue depth, and number of active virtual channels (VCS).

[0010] Furthermore, the logical sub-module of the port includes at least one of the following: input buffer clock domain, routing lookup logic clock domain, arbitrator clock domain, cross switch interface clock domain, and control status register clock domain.

[0011] As one implementation, when the low-power state machine is in the state of S0p-LIGHT, clock gating is performed on the arbitrator clock domain and the cross switch interface clock domain; when the low-power state machine is in the state of S1-IDLE, clock gating is further performed on the input buffer clock domain and the routing lookup logic clock domain; when the low-power state machine is in the state of S2-DEEP, clock gating is performed on the clock domains of almost all modules inside the port.

[0012] Furthermore, the step of independently determining the idle level of a port based on its own activity parameters includes: updating the estimated values ​​of the mean and variance of the traffic using an exponentially weighted moving average algorithm based on the historical sequence of the instantaneous traffic of the port; and dynamically calculating a threshold parameter for determining the idle level of the port based on the updated estimated values ​​of the mean and variance of the traffic.

[0013] As one implementation method, the average flow rate μ_t is obtained through the formula Updated, variance σ_t^2 via formula Update, where α and β are smoothing factors, and R_t is the current instantaneous flow rate; the dynamically calculated instantaneous flow rate threshold T1_t is obtained through the formula. Determined, where k is the coefficient factor.

[0014] Furthermore, the triggering conditions for the state transition of the low-power state machine include: using an integral counter, triggering a transition to a lower power state only when the idle level to which the port belongs continuously meets the degradation condition and reaches a first preset threshold; using an integral counter, triggering a transition to a higher power state only when the idle level to which the port belongs continuously meets the upgrade condition and reaches a second preset threshold; wherein, the first preset threshold is greater than the second preset threshold.

[0015] In one implementation, the low-power state machine transitions from the S0-ACTIVE state to the S0p-LIGHT state by requiring the integral counter to determine the port's idle level as L0p-LIGHT or deeper for N consecutive cycles; the low-power state machine transitions from the S0p-LIGHT state to the S0-ACTIVE state by requiring the integral counter to determine the port's idle level as L0-ACTIVE for N consecutive cycles; wherein, N_down_hyst > N_up_hyst.

[0016] Furthermore, the coordinated control of the clock supply to some or all logic sub-modules within the port also includes: recording the actual delay data of the port waking up from a low-power state; and dynamically determining the maximum idle level that the port is allowed to enter based on the comparison result of historical wake-up delay data and a preset delay target.

[0017] As one implementation, if the maximum delay in the historical wake-up delay data exceeds the preset delay target, the port is restricted to only being in the idle level corresponding to the S0-ACTIVE state.

[0018] Furthermore, after receiving a wake-up signal or a new transaction request for the port, the process includes: in response to the wake-up signal or the new transaction request, initiating the following two processes in parallel: gradually restoring the clock supply of the logical submodule of the port; and initiating a link state recovery negotiation with the peer device.

[0019] As one implementation, the gradual restoration of the clock supply to the logic submodule of the port includes a hierarchical restoration in a preset order, the order of which includes at least: the control status register clock domain, the input buffer clock domain, and the routing lookup logic clock domain.

[0020] Furthermore, the low-power state machine and port-level clock gating method of the CXL Switch chip also include: in response to all associated ports under the same virtual channel VCS entering a specific low-power state, clock gating is performed on the global logic module serving the VCS.

[0021] In one implementation, the activity parameters are obtained through a port counter inside the port.

[0022] Furthermore, the initiation or exit of the corresponding type of link low-power state follows the negotiation mechanism of the link power management state L0p, L1, or L2 of the CXL protocol.

[0023] This application provides a CXL switch, comprising: a port activity monitoring unit configured to acquire multi-dimensional activity parameters of each port of the switch, and independently determine the idle level of each port based on its own activity parameters; an adaptive low-power state machine unit configured to independently manage a low-power state machine for each port according to the idle level at the port granularity, wherein the state of the low-power state machine is associated with the idle level, and initiates or exits a corresponding type of link low-power state in response to the state transition of the low-power state machine; and a cooperative clock gating execution engine configured to, for each port, based on the current state of the low-power state machine, cooperatively control the clock supply to some or all logic sub-modules within the port, and receive wake-up signals or new transaction requests for the port.

[0024] This application provides an electronic device, including a memory and a processor. The memory stores a computer program, and when the processor executes the program, it implements a low-power state machine of a CXL Switch chip and a clock gating method at the port granularity.

[0025] This application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements a low-power state machine for a CXL Switch chip and a clock gating method at the port granularity.

[0026] The beneficial effects achieved by this invention are as follows: By acquiring multi-dimensional activity parameters for each port of the switch and independently determining its idle level, fine-grained perception of port activity status is realized. Based on this, a low-power state machine is independently managed for each port, and the state machine's state is associated with the idle level, achieving independent state management at the port level and avoiding mutual interference between different ports. Furthermore, based on the current state of each port's state machine, the clock supply to its internal logic submodules is coordinated and controlled, deeply coupling low-power decisions with clock gating. This allows clock gating to be executed precisely on demand, significantly reducing the dynamic power consumption of idle ports. Simultaneously, by receiving wake-up signals and initiating clock recovery and link recovery negotiations in parallel, the response latency of port wake-up is effectively reduced, improving system performance. Attached Figure Description

[0027] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0028] Figure 1 This is a flowchart of the present invention. Detailed Implementation

[0029] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0030] Example 1

[0031] Explanation of technical terms:

[0032] "Port" refers to the physical communication interface of the CXL switch that connects to external devices.

[0033] "Activity parameters" refer to quantitative indicators that reflect the current and historical communication activity status of a port, such as instantaneous data rate and duration of no communication.

[0034] "Idle level" refers to a refined classification of the non-full-load operating state of a port based on activity parameters. "Low-power state machine" refers to a logical control entity that is maintained independently for each port, and whose state is associated with the idle level. It drives the switching of link power states.

[0035] "Logic submodule" refers to a circuit unit with an independent clock domain that constitutes the internal data processing and forwarding functions of a port.

[0036] "Cooperative control" refers to the unified and logically related opening and closing management of the clock supply of multiple logic sub-modules according to the instructions of the low-power state machine.

[0037] like Figure 1As shown, a low-power state machine for a CXL Switch chip and a port-level clock gating method include: Step S101, for each port of the switch, acquiring the port's activity parameters in multiple dimensions; Step S102, independently determining the idle level of each port based on its own activity parameters; Step S103, independently managing a low-power state machine for each port according to the idle level at the port level, wherein the state of the low-power state machine is associated with the idle level; Step S104, initiating or exiting a corresponding type of link low-power state in response to the state transition of the low-power state machine; Step S105, coordinating the clock supply to some or all logic sub-modules within the port based on the current state of the low-power state machine of each port; Step S106, receiving a wake-up signal or a new transaction request for the port.

[0038] In this embodiment, steps S101 to S106 work collaboratively. Through steps S101 and S102, each port can independently determine its refined idle level based on its own multi-dimensional real-time activity parameters, providing a precise sensing basis for subsequent low-power decisions. Step S103 maintains an independent low-power state machine for each port, associating its state with the sensed idle level, achieving independent state management at the port level. Different ports can perform state transitions without interference based on their own traffic patterns. Step S104 links the transitions of the internal state machine with standard CXL link power management states (such as L0p, L1, L2), ensuring protocol compatibility of the solution. Step S105, based on the precise state of each port's state machine, performs differentiated clock gating corresponding to the state depth for each internal logic submodule, precisely reducing the clock power consumption of idle modules. These steps together form a closed loop of "monitoring-decision-execution," solving the problem of the inability to perform refined power management at the port level in existing technologies, and significantly reducing the dynamic power consumption of idle ports and inactive modules. Step S106 serves as a trigger point, providing an entry point for the reverse recovery of the state (from low power to full activity).

[0039] Taking a specific application scenario as an example, in an AI inference cluster, CXL switch port A (serving bursty inference tasks) connected to multiple GPU cards may be idle for a long time without any tasks, while port B (serving the memory pool) continuously receives data flow. According to the method of this application, the activity monitoring unit of port A (step S101) continuously collects its instantaneous traffic and idle duration. When these parameters meet the conditions (step S102), port A is determined to be at the "L1-IDLE" level. Subsequently, its independently managed low-power state machine (step S103) enters the corresponding state "S1-IDLE" and triggers negotiation with the peer GPU card to enter the CXL L1 link low-power state (step S104). At the same time, based on the S1-IDLE state, the coordinated clock gating engine (step S105) shuts down the clocks of sub-modules such as the input buffer and routing lookup logic of port A, while the clocks of the logic sub-modules of port B remain fully on, without affecting each other. When a new inference task arrives, a wake-up signal is received (step S106), triggering the wake-up acceleration process on port A. Clock recovery and link activation are executed in parallel to quickly restore service.

[0040] In one embodiment, regarding the determination of the idle level mentioned above, the method defines four idle levels: L0-ACTIVE, L0p-LIGHT, L1-IDLE, and L2-DEEP. The states of the low-power state machine include: S0-ACTIVE, S0p-LIGHT, S1-IDLE, and S2-DEEP, each corresponding to a specific idle level. Specifically, the S0-ACTIVE state corresponds to the L0-ACTIVE level where the port is running at full speed, with no clock gating; the S0p-LIGHT state corresponds to the L0p-LIGHT level of slight idleness; the S1-IDLE state corresponds to the L1-IDLE level of moderate idleness; and the S2-DEEP state corresponds to the L2-DEEP level of deep idleness. By establishing this one-to-one correspondence, the state machine's transition decisions can be closely tied to the actual port activity level. Furthermore, based on the above principles, adopting this four-level state and level correspondence method can bring the beneficial effect of differentiated low-power strategies adapted to ports with different idle levels. This ensures that lightly idle ports are only slightly affected (e.g., only some modules are gated, resulting in low wake-up latency), while deeply idle ports can achieve maximum energy saving (many modules are gated), achieving the best balance between power consumption optimization and wake-up latency. As a specific implementation, when determining the idle level L0p-LIGHT, it can be determined that the instantaneous traffic is below threshold T1 and the queue depth is below threshold Q1, but there is still sporadic control traffic; when determining L1-IDLE, it can be determined that the port has been idle for more than the threshold T_idle1 and the number of active VCSs is 0; when determining L2-DEEP, it can be determined that the port has been idle for a long time exceeding the threshold T_idle2 and there are no pending transactions. The corresponding link low-power states are: S0p-LIGHT state associated with CXL L0p state, S1-IDLE state associated with CXL L1 state, and S2-DEEP state associated with CXL L2 state.

[0041] In one embodiment, the activity parameters obtained by this method include at least one of the following: instantaneous traffic, idle duration, transaction arrival interval, queue depth, and number of active virtual channel (VCS). Instantaneous traffic reflects the real-time bandwidth utilization of the port; idle duration indicates the absolute time during which the port remains inactive; transaction arrival interval describes the arrival pattern of service requests; queue depth shows the occupancy of the port buffer; and the number of active VCSs reflects the number of currently active logical channels on the port. By comprehensively utilizing these multiple dimensions of activity parameters for idle level determination, compared to schemes that rely on only a single parameter (such as simple idle duration), the true activity state of the port can be more comprehensively and accurately depicted, thereby reducing misjudgments. Furthermore, based on the above principles, this multi-dimensional parameter combination approach can bring about a more refined and reliable idle level determination, avoiding erroneous low-power state switching caused by fluctuations in a single parameter (such as instantaneous traffic spikes), and enhancing the robustness of the low-power control system. As a specific implementation, the port activity monitoring unit can use the hardware counter inside the port to count the instantaneous traffic (MB / s) in real time, calculate the idle time and transaction arrival interval through timestamps, read the queue depth from the cache status register, and count the number of active VCSs from the VCS attribution table.

[0042] In one embodiment, the port's logic sub-modules include at least one of the following: an input buffer clock domain, a routing lookup logic clock domain, an arbitrator clock domain, a crossbar switch interface clock domain, and a control status register clock domain. These sub-modules are the core functional units constituting port data reception, routing decision-making, output arbitration, data exchange, and configuration access, and typically have independently controllable clock domains. Decoupling port functions according to these naturally divided clock domains provides a good infrastructure for subsequent state-based fine-grained clock gating. Furthermore, based on the above principles, dividing the port's logic into multiple independently gating clock domains can bring the beneficial effects of finer-grained power consumption optimization and precise on-demand shutdown. Since the necessity of different sub-modules varies in different idle states (for example, in slightly idle states, the routing lookup logic may still need to work to process sporadic control packets, while the crossbar switch interface can be turned off), this division allows the clock gating strategy to be deeply matched with the port's functional states, maximizing energy-saving potential. As a specific implementation, the input buffer clock domain drives the port input FIFO read / write logic, the routing lookup logic clock domain drives the address decoding and routing table lookup circuit, the arbitrator clock domain drives the port output arbitration logic, the cross switch interface clock domain drives the data transmission interface circuit with the central switching matrix, and the control status register clock domain drives the port configuration and status register.

[0043] In one embodiment, when the low-power state machine is in the S0p-LIGHT state, clock gating is performed on the arbitrator clock domain and the crossbar switch interface clock domain; when the low-power state machine is in the S1-IDLE state, clock gating is further performed on the input buffer clock domain and the routing lookup logic clock domain; when the low-power state machine is in the S2-DEEP state, clock gating is performed on the clock domains of almost all modules inside the port. This series of operations constitutes a hierarchical clock gating strategy. In the S0p-LIGHT state, since the port may still have sporadic activity, the clocks of the input buffer and routing lookup logic are retained to ensure that control transactions can be received and processed; while the arbitrator and crossbar switch interfaces can be safely shut down when slightly idle. After entering the S1-IDLE state, the port has almost no transactions, the input buffer and routing lookup logic can also be shut down, and only the control status register (CSR) clock is retained to respond to possible wake-up or configuration access. After reaching the S2-DEEP state, the port is idle for a long time, and almost all internal module clocks are gating to maximize energy saving, and only the necessary wake-up detection circuit clock is retained. Furthermore, based on the above principles, this hierarchical gating strategy can achieve the beneficial effects of power consumption reduction being strictly proportional to state depth, and wake-up latency and gating depth being controllable. The gating depth increases progressively with the state depth, achieving gradual power savings; at the same time, since different states retain different clock domains, their wake-up recovery times also differ (e.g., S0p-LIGHT recovers quickly, S2-DEEP recovers slowly), providing a clear operational benchmark for balancing power consumption and latency.

[0044] In one embodiment, the aforementioned method of independently determining the idle level of each port based on its own activity parameters specifically includes: updating the estimated values ​​of the traffic mean and variance using an exponentially weighted moving average algorithm based on the historical sequence of the port's instantaneous traffic; and dynamically calculating a threshold parameter for determining the idle level of the port based on the updated estimated values ​​of the traffic mean and variance. The traffic mean reflects the long-term trend of traffic, while the variance characterizes the volatility of traffic. Traditional fixed thresholds cannot adapt to long-term changes in port traffic patterns (such as from bursty traffic to sustained low traffic). Using an exponentially weighted moving average algorithm to dynamically estimate the mean and variance can smooth short-term noise and track long-term trends. Generating a judgment threshold (such as an instantaneous traffic threshold) based on the dynamically calculated mean and variance allows the judgment criteria to adapt to the unique traffic statistics of the port. Furthermore, combining the above principles, this dynamic threshold calculation method can bring the beneficial effects of low-power judgment adapting to the long-term port traffic pattern and improving system robustness. When port traffic characteristics drift, the threshold will be automatically adjusted to avoid continuous misjudgment caused by the fixed threshold becoming outdated (such as never being able to enter low power or frequently entering low power incorrectly), thus ensuring the long-term effectiveness of the low power control strategy.

[0045] In one embodiment, the average flow rate μ_t is obtained through the formula... Updated, variance σ_t^2 via formula Update, where α and β are smoothing factors, and R_t is the current instantaneous flow rate; the dynamically calculated instantaneous flow rate threshold T1_t is obtained through the formula. Determined, where k is the coefficient factor. Formula This makes the new mean estimate a weighted average of the current sample value and historical estimates, with α controlling the degree of focus on recent data. (Formula) Similarly, the variance estimate is updated to reflect the fluctuations in flow around the mean. Threshold The threshold is set at k standard deviations above the mean; when the instantaneous flow R_t is below this threshold, the port is tended to be considered idle. The coefficient k can be used to adjust the strictness of the judgment: the larger the k value, the higher the threshold, and the more conservative (strict) the judgment of idleness; the smaller the k value, the closer the threshold is to the mean, and the more aggressive (lenient) the judgment. Furthermore, combining the above principles, this specific update and calculation formula can bring the beneficial effects of a clear threshold generation process and flexible parameter configuration to adapt to different scenario requirements. The smoothing factors α and β, and the coefficient factor k can all be configurable parameters, allowing for fine-tuning according to specific application scenarios (such as latency sensitivity, flow patterns), enhancing the applicability of the method. As a specific implementation, typical values ​​for α and β can be 0.2, and typical values ​​for k can be 1.5, and they can be set independently. In addition, the idle duration threshold T_idle1_t can also be dynamically calculated based on the average packet length and average flow of historical transactions, for example, through the formula... The values ​​are determined by the following: L_avg is the average packet length, R_avg is the average flow rate, γ is the proportionality coefficient, and T_idle1_min and T_idle1_max are the upper and lower limits of the design constraints.

[0046] In one embodiment, the triggering conditions for the state transition of the low-power state machine include: using an integral counter, triggering a transition to a lower power state only when the idle level to which the port belongs continuously meets the degradation conditions to a first preset threshold; using an integral counter, triggering a transition to a higher power state only when the idle level to which the port belongs continuously meets the upgrade conditions to a second preset threshold; wherein the first preset threshold is greater than the second preset threshold. The integral counter is used to accumulate the level determination results within a continuous sampling period. Degradation (such as from S0-ACTIVE to S0p-LIGHT) requires the idle level to continuously meet the conditions to reach a large counting threshold (the first preset threshold), which introduces a "hysteresis" effect, requiring the port to exhibit a stable and continuous idle trend before allowing entry into a deeper low-power state, preventing frequent degradation due to instantaneous fluctuations. Upgrading (such as from S0p-LIGHT to S0-ACTIVE) requires the active level to continuously meet the conditions to reach a small counting threshold (the second preset threshold), which ensures that the port can quickly respond and restore full-speed state once real traffic arrives, minimizing performance impact. This asymmetric threshold (first preset threshold > second preset threshold) embodies the design principle of "cautious degradation, rapid upgrade." Furthermore, combining the above principles, the state transition condition triggered by this asymmetric integral can effectively suppress state oscillations and balance power consumption optimization with response sensitivity. It prevents the low-power state machine from frequently switching between high and low states due to minor parameter fluctuations near the critical activity level, which would otherwise incur additional power consumption and latency overhead; simultaneously, it ensures timely service recovery.

[0047] In one embodiment, the low-power state machine transitions from the S0-ACTIVE state to the S0p-LIGHT state, requiring the integral counter to determine the port's idle level as L0p-LIGHT or deeper for N consecutive cycles; the low-power state machine transitions from the S0p-LIGHT state to the S0-ACTIVE state, requiring the integral counter to determine the port's idle level as L0-ACTIVE for N consecutive cycles; where N_down_hyst > N_up_hyst. Specifically, let the degradation integral counter be C_down_t. In each sampling period t, if the current level Grade_t (L0-ACTIVE=0, L0p-LIGHT=1,…) is greater than or equal to 1 (L0p-LIGHT) and the previous period's Grade_{t-1} is also greater than or equal to 1, then C_down_t = C_down_{t-1} + 1; otherwise, it is cleared to zero. The transition from S0-ACTIVE to S0p-LIGHT is triggered only when C_down_t accumulates to N_down_hyst (e.g., 5). Similarly, let the upgrade integral counter be C_up_t. C_up_t is incremented only when Grade_t and Grade_{t-1} are both 0 for two consecutive cycles (L0-ACTIVE); otherwise, it is reset to zero. The transition from S0p-LIGHT to S0-ACTIVE is triggered when C_up_t reaches N_up_hyst (e.g., 2). Since N_down_hyst > N_up_hyst, downgrading requires more sustained idle evidence than upgrading, achieving asymmetric hysteresis. Furthermore, combining the above principles, adopting this specific counter rule can bring the beneficial effects of simple and clear logic implementation, easy parameter configuration and tuning. N_down_hyst and N_up_hyst can be used as programmable register values, and different values ​​can be set according to the type of device connected to the port (such as Type 1 latency-sensitive, Type 2 compute-intensive, and Type 3 memory-extended) to further optimize the performance-power balance in different scenarios.

[0048] In one embodiment, the aforementioned coordinated control of the clock supply to some or all logic submodules within the port further includes: recording the actual wake-up latency data of the port from a low-power state; and dynamically determining the maximum idle level that the port is allowed to enter based on a comparison of historical wake-up latency data with a preset latency target. The actual wake-up latency (D_wake) is a key indicator for measuring the performance impact of the low-power strategy. Recording historical D_wake data (e.g., storing the latency values ​​of the most recent W wake-ups) can assess the actual wake-up time of the port from different depths of state under the current environment (considering voltage, temperature, process variations, etc.). The preset latency target (D_target) represents the maximum wake-up latency that the port can tolerate, and is typically set according to the type of device it is connected to. By comparing historical latency statistics (such as maximum latency D_max, average latency D_avg) with D_target, the deepest idle level (Lv_max_allowed) that the port is currently allowed to enter can be dynamically determined. For example, if D_max exceeds D_target, only the S0-ACTIVE state is allowed, and any clock gating is prohibited; if D_avg is much smaller than D_target, entering the S2-DEEP state is allowed. This forms a feedback control loop. Furthermore, combining the above principles, this dynamic depth adjustment method based on historical delay feedback can achieve the beneficial effects of adaptively balancing the power consumption and performance of a single port and ensuring that the wake-up delay does not exceed the limit. It solves the problem that fixed hierarchical strategies cannot adapt to changes in wake-up time of individual ports due to environmental factors or aging, enabling each port to enter a low-power state as deeply as possible while ensuring performance constraints, achieving personalized optimal energy efficiency.

[0049] In one embodiment, if the maximum latency in the historical wake-up latency data exceeds the preset latency target, the port is restricted to the idle level corresponding to the S0-ACTIVE state. This is a safety protection strategy in the aforementioned feedback control loop. The maximum latency (D_max) represents the worst-case wake-up time. Once D_max exceeds the preset performance target (D_target), it indicates that even entering a mild low-power state (such as S0p-LIGHT), the latency requirement may not be met in the worst case. In this case, the safest approach is to force the port to be in the S0-ACTIVE state only, i.e., disable all clock gating, to ensure wake-up performance at any time. This prioritizes performance determinism and Quality of Service (QoS), preventing critical service latency from exceeding limits due to excessive pursuit of energy saving. Furthermore, combined with the above principles, adopting this strict out-of-bounds protection rule can bring the beneficial effect of ensuring that critical performance indicators are not exceeded and improving system reliability. As a safety valve, it can automatically revert to a performance-priority mode when the system environment changes (such as temperature rise causing circuit slowdown), avoiding unpredictable performance degradation introduced by low-power management.

[0050] In one embodiment, after receiving the wake-up signal or new transaction request for the port as mentioned above, the process includes: responding to the wake-up signal or new transaction request and initiating the following two processes in parallel: gradually restoring the clock supply of the logical sub-module of the port; and initiating link state recovery negotiation with the peer device. Traditionally, this is done serially: first, the clock is fully restored, then the link wake-up negotiation is performed, with a total delay equal to the sum of the two. This embodiment changes these two originally serial and time-consuming processes to be started in parallel. When the wake-up signal is detected, on the one hand, the clock recovery process begins immediately, sequentially reactivating the clocks of each sub-module; on the other hand, a negotiation request to restore the link to the L0 fully active state with the peer device is also sent simultaneously. Since these two processes are physically and procedurally independent, parallel execution can significantly shorten the total time from wake-up detection to port full readiness. Furthermore, combining the above principles, this parallel wake-up execution method can significantly reduce the response latency of the port recovering from a low-power state and improve system service speed. This is particularly important for latency-sensitive applications, enabling low-power technology to save energy while minimizing the impact on user experience.

[0051] In one embodiment, the aforementioned gradual restoration of the clock supply to the logic submodule of the port includes a hierarchical restoration in a preset order, which includes at least the control status register (CSR) clock domain, the input buffer clock domain, and the routing lookup logic clock domain. This preset order ensures the correctness and efficiency of the restoration process. Generally, the clock of the control status register (CSR) is restored first, allowing the CPU or state machine to access the port configuration, confirm the status, and provide a control basis for subsequent operations. Next, the input buffer clock domain is restored, allowing the port to begin receiving and temporarily storing newly arrived transaction data. Then, the routing lookup logic clock domain is restored to perform address resolution and routing decisions on the received data. Subsequently, the arbitrator clock domain and the crossbar switch interface clock domain can be restored to complete data forwarding. This hierarchical, sequential restoration method avoids the current surges and timing chaos that may result from simultaneously powering on all modules, and also ensures that functional restoration matches the data processing flow, allowing for simultaneous restoration and processing, further improving efficiency. Furthermore, based on the above principles, this hierarchical sequential restoration method can bring the beneficial effects of a smooth and controllable wake-up process, reduced instantaneous power consumption peaks, and optimized restoration time. It ensures that the restoration of logical functions and the restoration of clock supply are synchronized in timing during the wake-up acceleration process, which is a key component for achieving efficient parallel wake-up.

[0052] In one embodiment, the low-power state machine and port-level clock gating method of the CXL Switch chip further include: in response to all associated ports under the same virtual channel (VCS) entering a specific low-power state, performing clock gating on the global logic modules serving the VCS. A virtual channel (VCS) is a logical communication channel that may be associated with multiple physical ports. When all physical ports serving the same VCS enter a low-power state (such as S1-IDLE or deeper), it means that the VCS currently has no active end-to-end communication. At this time, some global logic modules serving the VCS (such as VCS-specific queue management logic, flow control logic, consistency directory logic, etc.) may also be idle. Under these conditions, performing clock gating on the global logic modules of the VCS can achieve a deeper level of energy saving than port-level gating, further exploring the potential for power optimization. Furthermore, combining the above principles, adopting this VCS-aware collaborative gating method can bring beneficial effects such as achieving multi-level, hierarchical energy saving and maximizing chip-level energy efficiency. It extends power management granularity from the port level to the logic channel level, enabling energy-saving strategies to be combined with the system's logical topology to achieve more intelligent power control.

[0053] In one embodiment, as a more specific implementation, the activity parameter can be directly obtained through hardware resources such as the port counter, timestamp circuit, and status register within the port, without external system intervention, ensuring real-time monitoring and low overhead. In another embodiment, as a more specific implementation, the initiation or exit of the corresponding type of link low-power state strictly follows the entry and exit negotiation mechanism of the link power management state (such as L0p, L1, or L2) defined by the CXL protocol, ensuring that the implementation of this method is compatible with the standardized ecosystem.

[0054] It should be noted that in some optional implementations, the hardware implementation of clock recovery can be specially designed to further accelerate the wake-up process. For example, the clock gating unit can employ an array of multiple micro-buffers with non-uniform drive strength. Some high-drive-strength buffers are used to quickly establish the clock amplitude, while some low-drive-strength buffers are used to maintain a low-power clock. During wake-up, a subset of the high-drive buffers can be enabled first to quickly recover the clock, achieving a faster clock recovery speed. Alternatively, an auxiliary phase-locked loop (PLL) can be placed near the port. When the port enters deep sleep, the auxiliary PLL pre-charges the control voltage of its voltage-controlled oscillator to near the lock value and maintains it. During wake-up, the auxiliary PLL can be immediately enabled, providing a clock close to the target frequency in a very short time for initial wake-up use, running in parallel with the main PLL's re-locking process, further reducing clock recovery delay. For example, the registers of a low-power state machine can adopt a nested data retention structure. By utilizing the thermal-electric coupling effect, the logic state information is temporarily retained by transferring it to the lower floating gate structure during deep sleep or when the main power supply voltage drops. It is then restored when the machine is woken up. This achieves data retention while avoiding the use of additional holding voltage rails, thus saving area and power consumption.

[0055] In other alternative implementations, to address the reliability issues of port physical connections caused by temperature variations or mechanical aging, compensation can be achieved by incorporating external mechanical structures. For example, a pre-tensioned spring made of shape memory alloy combined with a wedge-shaped slider can be used. When temperature changes cause variations in the connector gap, the spring force changes, driving the slider to move and adaptively compensate for the gap, maintaining good contact and a seal. Alternatively, a rotary locking sleeve with non-equidistant helical grooves and a ratchet anti-reverse mechanism can be designed. When the port enters a low-power state, it is mechanically locked to prevent accidental insertion or removal; it is then unlocked upon wake-up. Another option is to utilize a variable cross-section elastic torsion beam for energy storage, instantaneously releasing energy when the port needs to be woken up. This energy is then rapidly and in parallel via a purely mechanical method to toggle a clock gate switch and trigger a link state machine reset, achieving physical-level wake-up acceleration and buffering.

[0056] It should also be noted that, in some optional implementations, the activity parameter determination logic mentioned above can be robustly enhanced. For example, the concept of transient jitter dead zone can be introduced, which not only checks whether the instantaneous flow value exceeds the threshold, but also calculates the stability score of the flow changes over the most recent multiple cycles, and combines it with the variance of historical flow for a comprehensive judgment, in order to filter out critical oscillations caused by clock jitter or link glitches. Another example is the virtual construction of a hardware degradation drift factor. By monitoring the timing margin changes of the critical path after each deep wake-up, an exponential decay weighted model is used to estimate the transistor aging degree, and parameters such as the idle determination threshold are dynamically scaled accordingly, enabling the low-power strategy to adapt to the long-term performance drift of the chip and maintain long-term effectiveness.

[0057] This application embodiment also provides a CXL switch, which includes: a port activity monitoring unit configured to acquire multi-dimensional activity parameters for each port of the switch, and independently determine the idle level of each port based on its own activity parameters; an adaptive low-power state machine unit configured to independently manage a low-power state machine for each port according to the idle level at the port granularity, wherein the state of the low-power state machine is associated with the idle level, and initiates or exits a corresponding type of link low-power state in response to the state transition of the low-power state machine; and a cooperative clock gating execution engine configured to, for each port, based on the current state of the low-power state machine, cooperatively control the clock supply to some or all logic sub-modules within the port, and receive wake-up signals or new transaction requests for the port. The three units in this device embodiment respectively implement the relevant steps in the aforementioned method embodiment, and have corresponding beneficial effects.

[0058] This application also provides an electronic device, including a memory and a processor. The memory stores a computer program, and when the processor executes the program, it implements a low-power state machine for the CXL Switch chip and a port-level clock gating method. This electronic device may be, for example, a network interface card (NIC) with integrated CXL switching functionality, a switch device, or a related control unit on a server motherboard.

[0059] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements a low-power state machine and a port-level clock gating method for a CXL Switch chip. The computer-readable storage medium can be a non-volatile storage medium, such as flash memory or a hard disk.

[0060] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A low-power state machine for a CXL switch chip and a port-level clock gating method, characterized in that, This includes obtaining the activity parameters of each port of the switch in multiple dimensions; The idle level of each port is determined independently based on its own activity parameters; Based on the idle level of the port granularity, a low-power state machine is managed independently for each port, wherein the state of the low-power state machine is associated with the idle level; In response to the state transition of the low-power state machine, initiate or exit the corresponding type of link low-power state; Based on the current state of the low-power state machine of each port, the clock supply to some or all logic submodules within the port is coordinated and controlled. Receive wake-up signals or new transaction requests for the port.

2. The low-power state machine of the CXL Switch chip and the port-level clock gating method according to claim 1, characterized in that, The idle levels include four levels: L0-ACTIVE, L0p-LIGHT, L1-IDLE, and L2-DEEP. The states of the low-power state machine include: S0-ACTIVE, S0p-LIGHT, S1-IDLE, and S2-DEEP, each corresponding to the idle level.

3. The low-power state machine of the CXL Switch chip and the port-level clock gating method according to claim 2, characterized in that, The activity parameters include at least one of the following: instantaneous traffic, idle time, transaction arrival interval, queue depth, and number of active virtual channel VCSs.

4. The low-power state machine of the CXL Switch chip and the port-level clock gating method according to claim 2 or 3, characterized in that, The port's logical submodules include at least one of the following: input buffer clock domain, routing lookup logic clock domain, arbitrator clock domain, cross switch interface clock domain, and control status register clock domain.

5. The low-power state machine of the CXL Switch chip and the port-level clock gating method according to claim 2, characterized in that, When the state of the low-power state machine is S0p-LIGHT, clock gating is performed on the arbiter clock domain and the cross switch interface clock domain. When the state of the low-power state machine is S1-IDLE, clock gating is further performed on the input buffer clock domain and the routing lookup logic clock domain; When the state of the low-power state machine is S2-DEEP, clock gating is performed on the clock domain of almost all modules inside the port.

6. The low-power state machine of the CXL Switch chip and the port-level clock gating method according to any one of claims 1 to 5, characterized in that, The step of independently determining the idle level of a port based on its own activity parameters includes: updating the estimated values ​​of the mean and variance of the traffic flow using an exponentially weighted moving average algorithm based on the historical sequence of the instantaneous traffic flow of the port. Based on the updated estimates of the mean and variance of the traffic, a threshold parameter for determining the idle level of the port is dynamically calculated.

7. The low-power state machine of the CXL Switch chip and the port-level clock gating method according to claim 6, characterized in that, The average flow rate μ_t is obtained through the formula Updated, variance σ_t^2 via formula Update, where α and β are smoothing factors, and R_t is the current instantaneous flow rate; The dynamically calculated instantaneous flow threshold T1_t is obtained through the formula. Determined, where k is the coefficient factor.

8. The low-power state machine of the CXL Switch chip and the port-granular clock gating method according to any one of claims 1 to 7, characterized in that, The triggering conditions for the state transitions of the low-power state machine include: Using an integral counter, a transition to a lower power consumption state is triggered only when the idle level to which the port belongs continuously meets the degradation conditions and reaches a first preset threshold. Using an integral counter, a transition to a higher power consumption state is triggered only when the idle level to which the port belongs continuously meets the upgrade conditions and reaches a second preset threshold. Wherein, the first preset threshold is greater than the second preset threshold.

9. The low-power state machine of the CXL Switch chip and the port-level clock gating method according to claim 8, characterized in that, The low-power state machine needs the integral counter to determine the port idle level as L0p-LIGHT or deeper for N consecutive N_down_hyst cycles to transition from the S0-ACTIVE state to the S0p-LIGHT state. The low-power state machine needs the integral counter to determine the port idle level as L0-ACTIVE for N consecutive N_up_hyst cycles to transition from the S0p-LIGHT state to the S0-ACTIVE state. Where N_down_hyst > N_up_hyst.

10. The low-power state machine of the CXL Switch chip and the port-level clock gating method according to any one of claims 1 to 9, characterized in that, The coordinated control of clock supply to some or all logic submodules within the port also includes: Record the actual latency data of the port waking up from a low-power state; Based on the comparison between historical wake-up latency data and preset latency targets, the maximum idle level that the port is allowed to enter is dynamically determined.

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