Interrupt control method and circuit applied to powerpc processor

Abstract

The application discloses an interrupt control method and circuit applied to a PowerPC processor and relates to the technical field of multi-core processors. The method receives a plurality of interrupt source signals, and after synchronization, monitoring and shielding processing, the plurality of interrupt source signals are routed as a plurality of output types. For specific type interrupts, an output is generated through a logic or operation; for int type interrupts, an in service filo data structure is used to save the currently processed interrupt, and priority arbitration and comparison logic are combined to realize interrupt nesting. The application supports three working modes of bypass, mixing and external agent and an interrupt multicast function, and uses a 128-bit register array to realize flexible splicing of timer logic. The application improves interrupt response speed, perfects a priority nesting mechanism and is suitable for high-performance multi-core communication processors.

Description

Technical Field

[0001] This invention belongs to the field of embedded multi-core processor chip architecture technology, and in particular relates to an interrupt control method and circuit applied to PowerPC processors. Background Technology

[0002] With the rapid development of 5G communication, network security, and storage systems, embedded multi-core communication processor chips are constantly evolving towards high performance, multi-core capabilities, and high integration. Modern multi-core processors need to run control plane and data plane services simultaneously, support hybrid architectures of symmetric multiprocessing (SMP) and asymmetric multiprocessing (AMP), and efficiently schedule a large number of external and internal peripherals such as Ethernet, PCIe, SATA, USB, DMA, encryption engines, RAID engines, and DPAA. In this complex system architecture, the interrupt controller, as the core hub for information interaction between the processor core and various peripherals and internal modules, directly determines the overall system response speed, task scheduling efficiency, and operational reliability.

[0003] However, traditional interrupt controllers have gradually revealed the following technical shortcomings when faced with the complex multi-core, multi-peripheral application scenarios mentioned above: First, the multi-core interrupt routing capability is insufficient. Traditional interrupt controllers typically employ relatively fixed routing mechanisms, which cannot achieve flexible unicast, multicast, and broadcast functions, making it difficult to meet the needs of multi-core processors in different operating modes, such as SMP / AMP hybrid architectures, for efficient task distribution and load balancing.

[0004] Secondly, the number of interrupt sources is enormous and lacks unified management. Modern system-on-chips (SoCs) integrate a large number of functional modules, leading to a surge in the number of interrupt sources. Traditional solutions lack a unified interrupt numbering and mapping mechanism, resulting in complex low-level driver development and high software adaptation and maintenance costs.

[0005] Secondly, the priority scheduling and nesting mechanism is imperfect. When handling high real-time tasks, traditional interrupt controllers often cannot efficiently and accurately handle the preemption and nesting of low-priority interrupts by high-priority interrupts, resulting in the response latency of high real-time tasks not being strictly guaranteed.

[0006] Finally, there is a lack of hardware-level security isolation mechanisms. Traditional interrupt controllers are relatively weak in access control, and in complex multi-core shared environments, they are prone to unauthorized access and illegal routing due to improper configuration or malicious access, posing system security risks.

[0007] Therefore, those skilled in the art urgently need a high-performance, flexibly configurable, and highly secure interrupt control method and circuit for multi-core communication processors to solve the above-mentioned technical problems. Summary of the Invention

[0008] In view of the shortcomings of existing technologies, such as insufficient multi-core interrupt routing capabilities, complex interrupt source management, imperfect priority and nesting mechanisms, and lack of hardware-level security isolation, the purpose of this invention is to provide a flexible, low-latency interrupt control method and circuit for PowerPC processors that supports complex nesting and has high security.

[0009] To achieve the above objectives, the technical solution of the present invention is implemented as follows: This invention provides an interrupt control method for PowerPC processors, comprising the following steps: Receive interrupt source signals, including external interrupts, internal interrupts, inter-core interrupts, message interrupts, shared message interrupts, timer interrupts, SOC error interrupts, and WDT interrupts; The interrupt source signal originating from the asynchronous clock domain is synchronized and monitored according to the configured level or edge validity to generate an interrupt request signal; The interrupt request signal is masked. The processed interrupt signals are routed to different output types according to the configuration. The output types include cint, mcp, IRQ_OUT_B, sie, and int. For interrupt output signals of types cint, mcp, IRQ_OUT_B, and sie, the interrupt source signals configured as the corresponding output interrupt types will be logically ORed to generate the corresponding interrupt output signals, and the interrupt sources that generate the interrupt output signals are limited to external interrupts and internal interrupts. For interrupt output signals of type int, the in service filo data structure is used to store the interrupt currently being processed. Arbitration is performed according to the priority of the interrupt source, and the arbitration priority is compared with the priority stored in the in service filo data structure to realize interrupt nesting, and the interrupt request with the highest priority is output.

[0010] Furthermore, the interrupt control method supports three operating modes: bypass mode, hybrid mode, and external agent mode; In bypass mode, only external interrupt 0 is valid, and the outputs of cint, mcp, and sie are all logic 0. The output logic of the IRQ_OUT_B signal is: perform a logical AND operation on each internal interrupt signal and its corresponding mask enable configuration inverted, and then perform a logical OR operation on all the results. In mixed mode, when the output interrupt type is int, the interrupt number is obtained by reading the register through software; In external proxy mode, the int output is always logic 0, and the processor directly receives and reads the interrupt signal through the CoreInt core interrupt interface.

[0011] Furthermore, for interrupts of type int, a priority-based interrupt nesting mechanism is supported, specifically including: Set the real-time task priority register CTPR so that interrupt sources participate in scheduling when their priority is greater than the register's value; When the processor responds to an interrupt, it pushes the currently arbitrated interrupt and its priority into the in-service filo data structure; When a new interrupt source is arbitrated, its priority is compared with the priority of the top of the in-service filo data structure stack. If the new interrupt has a higher priority, it is responded to and pushed onto the stack; otherwise, it is not responded to. When the processor finishes processing the current interrupt, it pops the in-service filo data structure by writing to the End of Interrupt (EOI) register.

[0012] Furthermore, for interrupts of type int, the software returns a pseudo-interrupt number when reading the interrupt number register in the following situations: The interrupt source is level-sensitive and becomes invalid before being responded to; The masking configuration of the interrupt source was modified to be enabled before the interrupt was responded to; The real-time task priority register is configured to a higher priority before the interrupt is responded to. No interrupt was generated, but the software responded.

[0013] Furthermore, the timer interrupt is generated by the internal timer logic, which uses a timer composed of a 128-bit register array, divided into four 32-bit parts; Each 32-bit section contains a 1-bit timer toggle flag and a 31-bit counter. After counting begins, the count value is decremented from the initial count value. When it reaches 0, the initial value is reloaded and the count restarts. At the same time, the toggle flag is toggled once.

[0014] Furthermore, the timer logic supports configuring timer concatenation to form longer timers, including concatenation combinations to form 63-bit, 95-bit, or 128-bit timers; For concatenated registers, except for the high-order bits, the other bits can be configured to load the starting count value or a preset all-1 value when the timer counts down to 0. During the counting process, if the configuration is to concatenate and no preset all-1 value is configured, the corresponding bit of the base value register is loaded when the count reaches 0; if the count does not reach 0, a decrement operation is performed once every clock cycle.

[0015] Furthermore, the interrupt control method supports multicast functionality, allowing interrupts to be delivered to multiple processors simultaneously. When the external or internal interrupt source is configured with the output type set to cint or mcp, it can be configured to be passed to multiple processors. When the output type of the processor core interrupt and timer interrupt source is configured to be int, it can be passed to multiple processors. The interrupt control method also sends non-maskable interrupt signals and hardware reset signals to the processor by writing to the registers in software, and configures them to be passed to multiple processors.

[0016] Based on the same concept, the present invention also provides an interrupt control circuit for a PowerPC processor, comprising: Synchronization processing logic is used to synchronize asynchronous interrupt signals. Monitoring logic is used to generate valid interrupt request signals based on the configuration. The blocking logic is used to block corresponding interrupt requests based on the configuration. Priority arbitration logic is used to arbitrate the highest priority interrupt from the current interrupt request signals; In the service filo logic, it is used to save nested interrupts that are currently being processed by the processor but have not yet been completed; The priority comparison logic is used to compare the priority determined by the priority arbitration logic with the priority stored in the in-service filo logic. If the arbitration result is higher, the interruption request signal will be raised. The circuit supports routing interrupt sources to outputs of types cint, mcp, IRQ_OUT_B, sie, and int. Outputs of types cint, mcp, IRQ_OUT_B, and sie are generated by performing a logical OR operation on the interrupt source configured as the corresponding type.

[0017] Furthermore, the priority arbitration logic adopts an 8-level arbitration structure, in which multiple data blocks are arbitrated in pairs through a comparator, and finally a highest priority interrupt request is obtained. The data structure stored in the service filo logic is a 4-bit interrupt priority plus a one-hot encoded interrupt source number.

[0018] Furthermore, the interrupt control circuit includes timer logic, employing a 128-bit register array divided into four 32-bit sections; The timer logic supports the concatenation of configuration registers to form timers of different bit widths; For the loading value of the timer, if it is configured not to be concatenated or to be the highest bit of the concatenated timer, the high bit is cleared when loading the initial value; if it is configured to be a non-highest bit of the concatenated timer, the corresponding bit of the base value register is loaded.

[0019] Compared with the prior art, the interrupt control method and circuit of the present invention applied to PowerPC processors have the following advantages: (1) Improved flexibility of multi-core interrupt routing. This invention supports interrupt multicast function, which can configure external interrupts, internal interrupts, inter-core interrupts and timer interrupts to be delivered to multiple processors at the same time, meeting the needs of multi-core processors for efficient task distribution and load balancing in a hybrid architecture of symmetric multiprocessing and asymmetric multiprocessing.

[0020] (2) Unified management and efficient mapping of interrupt sources are achieved. This invention classifies and maps interrupts across the entire chip in a unified manner and assigns interrupt numbers in a unified manner, which effectively solves the problem of complex driver development caused by the large number of interrupt sources and greatly reduces the adaptation and maintenance costs of the underlying software.

[0021] (3) The priority scheduling and nesting mechanism has been improved to ensure high real-time services. This invention adopts an 8-level arbitration tree structure combined with an in-service filo data structure to achieve efficient and accurate interrupt priority arbitration and nesting processing, selecting the highest priority interrupt with extremely low logical latency, thus ensuring the response speed of high real-time tasks. In addition, the external agent mode eliminates the need for software to read and write registers, and the interrupt signal is directly transmitted by the hardware, further improving the system's response efficiency.

[0022] (4) It provides hardware-level security isolation and high configurability. This invention achieves hardware-level access control and security isolation through shielding logic and real-time task priority registers, effectively preventing unauthorized access and illegal routing. At the same time, the system supports three working modes: bypass, hybrid, and external agent, and supports flexible timer configuration from 32 bits to 128 bits, which greatly enhances the adaptability and flexibility of the interrupt controller in different application scenarios. Attached Figure Description

[0023] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a schematic diagram of the overall structure of an interrupt control circuit applied to a PowerPC processor, provided by an embodiment of the present invention. Figure 2 This is a schematic diagram of the in-service filo data structure provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the priority arbitration circuit structure provided in an embodiment of the present invention. Detailed Implementation

[0024] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0025] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0026] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0027] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0028] This invention provides an interrupt control method for PowerPC processors, comprising the following steps: Receive interrupt source signals, including external interrupts, internal interrupts, inter-core interrupts, message interrupts, shared message interrupts, timer interrupts, SOC error interrupts, and watchdog timer (WDT) interrupts; The interrupt source signal originating from the asynchronous clock domain is synchronized and monitored according to the configured level or edge validity to generate an interrupt request signal; The interrupt request signal is masked. The processed interrupt signals are routed to different output types according to the configuration. The output types include cint, mcp, IRQ_OUT_B, sie, and int. For interrupt output signals of types cint, mcp, IRQ_OUT_B, and sie, the interrupt source signals configured as the corresponding output interrupt types will be logically ORed to generate the corresponding interrupt output signals, and the interrupt sources that generate the interrupt output signals are limited to external interrupts and internal interrupts. For interrupt output signals of type int, the in service filo data structure is used to store the interrupt currently being processed. Arbitration is performed according to the priority of the interrupt source, and the arbitration priority is compared with the priority stored in the in service filo data structure to realize interrupt nesting, and the interrupt request with the highest priority is output.

[0029] like Figure 1 As shown, the present invention also provides an interrupt control circuit applied to a PowerPC processor, comprising: Synchronization processing logic is used to synchronize asynchronous interrupt signals. Monitoring logic is used to generate valid interrupt request signals based on the configuration. The blocking logic is used to block corresponding interrupt requests based on the configuration. Priority arbitration logic is used to arbitrate the highest priority interrupt from the current interrupt request signals; In the service filo logic, it is used to save nested interrupts that are currently being processed by the processor but have not yet been completed; The priority comparison logic is used to compare the priority determined by the priority arbitration logic with the priority stored in the in-service filo logic. If the arbitration result is higher, the interruption request signal will be raised. The circuit supports routing interrupt sources to outputs of types cint, mcp, IRQ_OUT_B, sie, and int. Outputs of types cint, mcp, IRQ_OUT_B, and sie are generated by performing a logical OR operation on the interrupt source configured as the corresponding type.

[0030] In this embodiment, the interrupt control circuit aims to address issues such as insufficient interrupt routing capabilities, imperfect priority mechanisms, and lack of hardware-level security isolation in multi-core communication processors. It is particularly suitable for high-performance embedded processor systems supporting hybrid architectures of symmetric and asymmetric multiprocessing. The overall interrupt controller is physically divided into synchronization processing logic, monitoring logic, and masking logic (i.e.,...). Figure 1The core functional components include mask logic, priority arbitration logic, in-service filo logic, timer interrupt, and configuration register module.

[0031] In a preferred embodiment of the present invention, the interrupt source classification and input interface are as follows: like Figure 1 As shown on the left, this system uniformly classifies and maps all chip interrupts. Interrupt sources include various types, specifically external interrupts, internal interrupts, SOC (System-on-a-Chip) error interrupts, WDT interrupts, processor core interrupts, message interrupts, shared message interrupts, and timer interrupts.

[0032] There are a total of twelve external interrupts, which originate from the interrupt request pins outside the chip. These pins can be multiplexed with general-purpose input / output pins or debug event pins to save chip pin resources.

[0033] There are a total of 127 internal interrupts, originating from various functional modules within the chip, including but not limited to the Double Data Rate Controller, Peripheral Component Interconnect Enhancement Controller, Universal Serial Bus Controller, Serial Advanced Technology Attachment Controller, Direct Memory Access Controller, Embedded Secure Digital Host Controller, Enhanced Serial Peripheral Interface, Integrated Circuit Bus Controller, Dual Universal Asynchronous Receiver / Transmitter, Enhanced Local Bus Controller, Universal Input / Output Controller, Coherent Platform Controller, Clock Control Frequency Module, Platform Storage Management Unit, Packet Processing Accelerator, Disk Array Engine, and Operation Control Power Management Module, etc.

[0034] The SOC has a total of 32 error interrupts, mainly covering serious system events such as machine check errors, thermal fault alarms, security alarms, and reset requests.

[0035] The WDT interrupt has a total of eight channels and is used to monitor the running status of system software.

[0036] In addition, the system generates inter-core interrupts for communication between multiple cores; message interrupts; shared message interrupts; and timer interrupts generated by timer logic. All of these interrupt sources are uniformly assigned interrupt numbers within the system for unified software processing.

[0037] In a preferred embodiment of the present invention, the synchronization processing logic is as follows: External interrupts, internal interrupts, SOC error interrupts, and WDT interrupts often originate from different clock domains—for example, the peripheral clock domain differs from the processor core clock domain—and are therefore asynchronous signals. Thus, after being input to the interrupt controller, they must first undergo synchronization processing logic.

[0038] Synchronous processing logic is typically implemented using a two- or three-stage cascaded flip-flop structure. The asynchronous signal first enters the first-stage flip-flop, and after sampling on the next clock edge, it is output to the second-stage flip-flop. This timing mechanism effectively eliminates metastability risks, ensures signal stability in the processor's clock domain, and prevents malfunctions in subsequent logic circuits.

[0039] In a preferred embodiment of the present invention, the monitoring logic is as follows: The system supports flexible configuration for both external and internal interrupts, allowing users to select the sampling method via software, including active high, active low, rising edge active, or falling edge active. Therefore, after synchronization processing, the signal enters the monitoring logic.

[0040] The monitoring logic generates a valid interrupt request signal based on the above configuration.

[0041] If configured to be active high, the monitoring logic will directly output a synchronized high-level signal.

[0042] If configured to be active low, monitor the inverted signal of the synchronized output signal of the logic.

[0043] If configured to be active on rising edge, the monitoring logic will detect the rising edge of the signal through the circuit. Specifically, the logic is to perform an AND operation between the current sample value and the previous sample value, and generate a single-cycle pulse signal as an interrupt request.

[0044] If configured to be fall-edge enabled, the monitoring logic will detect the low-level transition of the signal and generate a corresponding pulse signal.

[0045] In a preferred embodiment of the present invention, the shielding logic is as follows: The system supports software-configurable masking for all interrupt sources. For example... Figure 1 As shown, the signals processed by the monitoring logic, as well as the signals generated by the processor core interrupt, message interrupt, shared message interrupt, and timer logic, are all connected to the shielding logic.

[0046] The masking logic is used to mask corresponding interrupt requests according to the configuration. When masking is effective, the interrupt request signal will be blocked, the output logic will be low, and it will not be further transmitted to the internal system for arbitration or routing operations. This provides hardware-level security isolation, preventing unauthorized routing or unauthorized access, and ensuring that critical tasks are not interfered with by low-priority interrupts.

[0047] like Figure 1 As shown in the bottom right corner, the system also includes a non-maskable interrupt generation module (i.e., core_nmi gen). The `core_hreset` module and the `core_nmi` module are used to generate the non-maskable interrupt signal (`core_nmi`) and the hardware reset signal (`core_hreset`), respectively. Figure 1 As shown in the lower left corner, the system is connected to the configuration register module (i.e., CSR (Control and Status Register)) via the IPI SkyBlueLine interface. This interface is used to receive software configuration parameters, including mask enable, priority, interrupt type, etc., thereby realizing the dynamic configuration of each module of the interrupt controller.

[0048] Example 1: Interrupt Output Types and Generation Mechanism Preprocessed interrupt signals are routed to different output types according to the configuration. The interrupt output types supported by this system include cint, mcp, IRQ_OUT_B, sie, and int.

[0049] like Figure 1 As shown, the signal output by the shielding logic is distributed to the cint generation module, mcp generation module, IRQ_OUT_B generation module, sie generation module, and priority arbitration logic.

[0050] For interrupts of types cint, mcp, IRQ_OUT_B, and sie, the system does not employ a complex interrupt nesting mechanism, but rather a simple logical OR operation. Specifically, all interrupt source signals configured as the corresponding output interrupt type are ORed to generate the corresponding output interrupt signal. It is important to note that, according to system design specifications, when the output interrupt type is cint, mcp, IRQ_OUT_B, or sie, the interrupt source can only be either an external interrupt or an internal interrupt; other interrupt source types, such as timer interrupts or inter-core interrupts, are not allowed.

[0051] In this embodiment, the output logic of cint is as follows: In bypass mode, the cint output is always logic zero. In non-bypass mode, if any external interrupt source is valid and its configured output interrupt type is cint, or if any internal interrupt source is valid and its configured output interrupt type is cint, then the output interrupt cint is valid, i.e., the output is logic high.

[0052] In this embodiment, the mcp output logic is as follows: In bypass mode, the mcp output is always logic zero. In non-bypass mode, the output interrupt mcp is valid if any external interrupt source is valid and its configured output interrupt type is mcp, or if any internal interrupt source is valid and its configured output interrupt type is mcp.

[0053] In this embodiment, the SIE output logic is as follows: In bypass mode, the SIE output is always logic zero. In non-bypass mode, the SIE output is valid if any external interrupt source is valid and its configured output interrupt type is SIE, or if any internal interrupt source is valid and its configured output interrupt type is SIE.

[0054] In this embodiment, the IRQ_OUT_B output logic is as follows: The processing of this signal is somewhat unique, primarily for compatibility with older or specific external interrupt controllers. In bypass mode, the output logic of IRQ_OUT_B involves performing an inverted AND operation on each internal interrupt and its corresponding mask enable configuration, followed by an OR operation on all results. Its mathematical expression is as follows: ; in, Indicates the first An internal interrupt signal, Indicates the first The internal interrupt masking configuration is set up so that logic 1 represents masking and logic 0 represents not masking. Represents the logical NOT operation. This represents the logical AND operation. Represents a logical OR operation.

[0055] In non-bypass mode, if any external interrupt source is valid and its configured output interrupt type is IRQ_OUT_B, or if any internal interrupt source is valid and its configured output interrupt type is IRQ_OUT_B, then the output interrupt IRQ_OUT_B is valid.

[0056] Example 2: Three Working Modes This interrupt controller supports three operating modes to adapt to different system architecture requirements: external agent mode, hybrid mode, and bypass mode.

[0057] In this embodiment, the bypass mode is as follows: In this mode, most functions of the interrupt controller are bypassed, primarily for simplified configuration or compatibility with traditional interrupt controllers. Only external interrupt zero is active; external interrupts one and above are inactive. Internal interrupts that are not configured to be masked are directly connected to the IRQ_OUT_B output after an OR operation. Interrupts generated internally by the interrupt controller, such as timer interrupts and inter-core interrupts, are disabled. In this mode, the outputs of cint, mcp, and sie are all logic zero.

[0058] In this embodiment, the hybrid mode is as follows: This is the most commonly used mode. In this mode, when the output interrupt type is int, the interrupt handler needs to read the interrupt number. The software obtains the interrupt number of the current interrupt by reading the register.

[0059] In this embodiment, the external proxy pattern is as follows: This mode was designed to improve interrupt response speed. In this mode, interrupts are not output via the int signal; the int output is always logic zero. Instead, the processor directly receives and reads the interrupt signal through the core interrupt interface. Figure 1 As shown, the priority comparison module output is connected to the core interrupt interface. This process eliminates the need for software register read / write operations; the hardware automatically handles the vector transfer to the central processing unit, significantly improving response speed. In mixed mode, the interrupt is output via the int signal.

[0060] Example 3: Priority scheduling and nesting mechanism for int type interrupts For interrupts of type int, the system supports complex priority scheduling and nesting mechanisms, which is one of the core innovations of this invention.

[0061] In this embodiment, the priority configuration and CTPR register are as follows: When the output interrupt type is int, the mask enable and priority of each interrupt source can be configured. The system schedules interrupts according to the mask enable and priority of each interrupt source, with higher priority interrupts being scheduled first.

[0062] The system contains a 4-bit read-write real-time task priority register. An interrupt source can only participate in scheduling if its priority value is greater than this register value. This allows software to dynamically adjust the current processor's interrupt response threshold, enabling task-level priority management.

[0063] In this embodiment, the priority arbitration logic is as follows: like Figure 3 As shown, the priority arbitration logic adopts a multi-level arbitration structure. In this embodiment, an eight-level arbitration structure is used to ultimately obtain a one-bit highest priority interrupt request.

[0064] The arbitration tree consists of multiple data blocks, each of which contains a four-bit priority and a one-bit validity flag.

[0065] The first level contains 184 data blocks, corresponding to 184 potential interrupt sources. Each block is arbitrated in pairs using a comparator, and 92 winners are selected to advance to the next level.

[0066] The second level contains ninety-two data blocks, which are compared pairwise to select forty-six winners.

[0067] The third level contains forty-six data blocks, from which twenty-three winners are selected.

[0068] The fourth level contains twenty-three data blocks, with eleven pairs compared in pairs. The remaining one advances directly, resulting in a total of twelve winners.

[0069] The fifth level contains twelve data blocks, from which six winners are selected.

[0070] Level 6 contains six data blocks, from which three winners are selected.

[0071] Level 7 consists of three data blocks. Each pair is compared, and the remaining block advances directly, resulting in two winners.

[0072] Level 8 contains two data blocks, which are compared by a comparator, and finally output a highest priority interrupt request.

[0073] This tree structure ensures that the highest priority interrupt can be selected with extremely low logical latency when a large number of interrupt sources are concurrent.

[0074] In this embodiment, the interrupt nesting and in-service filo logic are as follows: For interrupts of type int, interrupt nesting is implemented using the in-service filo (LIFO) data structure. For example... Figure 2 As shown, the data structure stored in the service filo is a four-bit interrupt priority (i.e., pri[3], pri[2], pri[1] and pri[0]) plus a one-hot encoded interrupt source number (i.e., inter src 0 vld flag, inter src 1 vld flag ... inter src n vld flag). One-hot encoding means that only one bit in the multi-bit data is a logic 1, which is used to uniquely identify the interrupt source.

[0075] An int-type output interrupt signal is generated by arbitrating all interrupt sources configured as int-type outputs and comparing their priorities with the currently processed interrupt priorities stored in the inservice filo. For example... Figure 1 As shown, the output of the priority arbitration module enters the priority comparison module, and the data in service filo also enters the priority comparison module.

[0076] The specific nesting process is as follows: Response phase: If the current interrupt is responded to by the processor, i.e. the software reads the interrupt confirmation register, the currently arbitrated interrupt and its priority are pushed into the service file as the interrupt currently being processed.

[0077] Nested judgment: If a new interrupt source is subsequently arbitrated, its priority is compared with the priority at the top of the in-service filo queue. If the new interrupt priority is lower than the priority in the queue, the new interrupt request is not responded to, and the current interrupt continues to execute; otherwise, it is responded to, nesting occurs, and the interrupt is pushed into the in-service filo queue. This implements the function of a high-priority interrupt interrupting a low-priority interrupt.

[0078] Termination phase: If the currently processed interrupt has been completed, the processor pops the queue by writing to the termination interrupt register, restoring the processing state of the previous level interrupt.

[0079] Overflow protection: When the queue is full, for example, when the nesting level reaches the hardware limit, even if there is a new high-priority interrupt, it will not be responded to until the processor writes to the end interrupt register, thereby freeing up space in the queue before it can continue to respond to new interrupts.

[0080] In this embodiment, the pseudo interrupt number is handled as follows: For interrupts of type int, a pseudo-interrupt number is returned if the software reads the interrupt number register in the following cases: First, an int interrupt is generated. The interrupt source is level-sensitive, and the interrupt source becomes invalid and the signal disappears before it is responded to.

[0081] Second, when an interrupt is generated, the masking configuration of the interrupt source is modified to be effective by the software before the interrupt is responded to.

[0082] Third, when an interrupt occurs, the real-time task priority register is configured to a higher priority before the interrupt is responded to, causing the current interrupt priority to no longer meet the scheduling conditions.

[0083] Fourth, the int interrupt was not actually generated, but the software performed an int interrupt response operation, that is, it misread the interrupt confirmation register.

[0084] The default value for the pseudo interrupt number is hexadecimal FFFF, but it can be configured to other values.

[0085] Reading the interrupt number register indicates that an interrupt has begun to be executed, while writing to the end interrupt register indicates that the interrupt has been completed.

[0086] Example 4: Timer Logic The timer interrupt is generated by the timer inside the interrupt controller. This system can implement timers with a width of 32 bits to 127 bits through flexible splicing and loading value configuration to meet timing requirements of different precision.

[0087] In this embodiment, the basic structure is as follows: Each timer interrupt is generated by a set of timers, which contains four 32-bit registers. The 32nd bit, or most significant bit, of each register is the timer toggle flag, and the remaining 31 bits are the counter bits.

[0088] The timer can be configured with its starting count value. After counting begins, it decrements from the starting count value. When it reaches zero, the starting value is reloaded and the timer restarts. At the same time, the toggle flag is toggled once, changing from zero to one and from one to zero. The change in the toggle flag can be used to trigger an interrupt.

[0089] In this embodiment, the timer splicing configuration is as follows: The system can be configured to concatenate timers to create longer timers that support larger count values. The timer logic uses a 127-bit register array, which is divided into four 32-bit parts.

[0090] Register zero corresponds to the lower 32 bits.

[0091] Register 1 corresponds to bits 32 to 63.

[0092] Register 2 corresponds to bits 64 to 95.

[0093] Register 3 corresponds to bits 96 to 127.

[0094] The splicing combination can be configured as follows: Configuration A: Register zero and one are concatenated, while two and three are not concatenated. This forms one 63-bit timer and two 31-bit timers.

[0095] Configuration B: Registers 1 and 2 are concatenated, while registers 0 and 3 are not concatenated. This forms one 63-bit timer and two 31-bit timers.

[0096] Configuration C: Register zero, one, and two are concatenated, while three is not concatenated. This forms a 95-bit timer and a 31-bit timer.

[0097] Configuration D: Registers 2 and 3 are concatenated, while zeros and ones are not concatenated. This forms a 63-bit timer and a 31-bit timer.

[0098] Configuration E: Concatenate register zero and one, and concatenate register two and three. This forms two 63-bit timers.

[0099] Configuration F: Concatenate registers one, two, and three, excluding zero. This forms a 95-bit timer and a 31-bit timer.

[0100] Configure G: Concatenate registers 0, 1, 2, and 3 to form a 127-bit timer.

[0101] For the concatenated register, except for the high 31 bits, the other bits can be configured with the load value when the timer counts down to zero: the starting count value or hexadecimal FFFFFFFF.

[0102] In this embodiment, the counting logic and the calculation of the loaded value are as follows: The counting method of each segment timer is described in detail below.

[0103] For the lower 32 bits: When counting begins, if configured not to concatenate, an initial value is loaded and the highest bit is cleared to zero; if configured to concatenate, the initial value is loaded from the lower 32 bits of the base register.

[0104] During the counting process, if the configuration is non-concatenation, the value is loaded when the count reaches zero, and the highest bit is inverted. Here, the highest bit is used as a flip flag to achieve automatic flipping.

[0105] If configured to concatenate and load hexadecimal FFFFFFFF, the loaded value will be all 32 bits when the count reaches zero.

[0106] If configured to concatenate and not configured to load hexadecimal FFFFFFFF, the value loaded when the count reaches zero is the lower 32 bits of the base register.

[0107] If the count has not reached zero, a decrement operation is performed once every clock cycle.

[0108] For the thirty-second to sixty-third digits: When counting begins, if configured not to concatenate or to concatenate the highest 32 bits of the timer, the initial value is loaded and the highest bit is cleared to zero.

[0109] If configured as a splicing timer other than the highest 32 bits, the corresponding bit of the base value register is loaded with the initial value.

[0110] During the counting process, if the configuration is to not splice or to splice the highest 32 bits of the timer, the value is loaded when the count reaches zero, and the highest bit is inverted.

[0111] During the counting process, if the non-maximum 32 bits of the splicing timer are configured and the hexadecimal value FFFFFFFF is loaded, then when the count reaches zero, the loaded value is all 32 bits of one.

[0112] If the non-maximum 32 bits of the splicing timer are configured and not configured to load hexadecimal FFFFFFFF, then when the count reaches zero, the corresponding bit of the base register is loaded.

[0113] If the count does not reach zero during the counting process, a decrement operation is performed once every clock cycle.

[0114] For the portion from sixty-fourth to ninety-fifth: The logic is the same as the previous paragraph. When used as the most significant bit, the initial value is loaded and the most significant bit is cleared. When the count reaches zero, the value is loaded and the most significant bit is inverted. When used as a non-most significant bit for concatenation, the corresponding bit in the base value register is loaded. When the count reaches zero, all ones or the base value is loaded according to the configuration.

[0115] For the portion from ninety-six to one hundred and twenty-seven: When counting begins, if configured not to concatenate or to concatenate the highest 32 bits of the timer, the initial value is loaded and the highest bit is cleared to zero.

[0116] If configured as a splicing timer other than the highest 32 bits, the corresponding bit of the base value register is loaded with the initial value.

[0117] During the counting process, if the configuration is to not splice or to splice the highest 32 bits of the timer, the value is loaded when the count reaches zero, and the highest bit is inverted.

[0118] During the counting process, if the non-maximum 32 bits of the splicing timer are configured and the hexadecimal value FFFFFFFF is loaded, then when the count reaches zero, the loaded value is all 32 bits of one.

[0119] If the timer is configured to use a non-maximum 32 bits and is not configured to load hexadecimal FFFFFFFF, then when the count reaches zero, the corresponding bit in the base register will be loaded. Logically, the base register itself should be loaded here to ensure counting continuity.

[0120] If the count does not reach zero during the counting process, a decrement operation is performed once every clock cycle.

[0121] For timer logic, an interrupt signal is generated when a timer counts to zero.

[0122] Example 5: Multicast and Special Signal Control Interrupts of types cint, mcp, and int support multicast functionality, which means that interrupts are simultaneously delivered to multiple processor cores, making them suitable for task distribution in symmetric multiprocessing architectures.

[0123] Specifically, when the output type of external interrupts and internal interrupt sources is configured as cint and mcp, it can be set to be passed to multiple processors through configuration registers.

[0124] When the output type of the processor core interrupt and timer interrupt source is configured as int, it can be configured to be passed to multiple processors.

[0125] In addition, non-maskable interrupt signals and hardware reset signals can also be configured to be passed to multiple processors to achieve global reset or global emergency interrupt.

[0126] The system also supports sending non-maskable interrupts to the processor via software register writes and passing them to the processor via non-maskable interrupt signals. Non-maskable interrupts are typically used to handle serious hardware errors.

[0127] Simultaneously, a reset signal can be sent to the processor via software writing to the registers, and then transmitted to the processor via a hardware reset signal, thus achieving a software-triggered hardware reset.

[0128] In summary, the interrupt control method and circuit for PowerPC processors provided by this invention have the following significant advantages compared with the prior art: First, this invention significantly improves interrupt response speed and overall system efficiency. By designing an external proxy mode, the processor can directly receive interrupts and read interrupt signals through the core interrupt interface, completely eliminating the cumbersome operation of obtaining interrupt vectors through software read / write registers in the traditional hybrid mode. The vector transfer is automatically completed by the hardware, thereby greatly reducing interrupt response latency. Simultaneously, in terms of priority arbitration, this invention innovatively adopts an 8-level arbitration tree structure, arbitrating up to 184 potential interrupt sources pairwise through multi-level comparators. This tree topology ensures that when a large number of interrupt sources make concurrent requests, the single highest-priority interrupt request can be quickly selected with extremely low logic gate latency, providing a solid hardware guarantee for high real-time services.

[0129] Secondly, this invention improves the priority scheduling and interrupt nesting mechanism, ensuring system stability in complex task environments. By introducing an in-service FILO (Last-In-First-Out) data structure, the system can accurately record the currently processed interrupt level and its priority. When a new high-priority interrupt arrives, the hardware can automatically compare it with the priority of the top of the stack and achieve seamless preemption and nesting. After the interrupt is processed, writing to the end interrupt register automatically pops the top data from the stack, restoring the execution state of the previous interrupt. In addition, the system sets a real-time task priority register, allowing the software to dynamically adjust the interrupt response threshold. A pseudo-interrupt number return mechanism is designed for abnormal situations such as the disappearance of level-sensitive signals and sudden changes in masking configuration, effectively preventing software misreading and system crashes, and significantly improving the robustness of the system.

[0130] Furthermore, this invention offers extremely high configuration flexibility and system compatibility. The system supports three operating modes: bypass mode, hybrid mode, and external proxy mode. This not only meets the complex requirements of modern high-performance processors but also allows for compatibility with traditional external interrupt controllers through specific logic or operations in bypass mode. Simultaneously, this invention supports interrupt multicast functionality, allowing external interrupts, internal interrupts, inter-core interrupts, and timer interrupts to be configured to be simultaneously delivered to multiple processor cores, perfectly adapting to the task distribution and load balancing requirements of hybrid symmetrical and asymmetric multiprocessing architectures.

[0131] Finally, this invention achieves high-precision, wide-range hardware timing functionality and robust hardware-level security isolation. The timer logic employs a 128-bit register array and supports flexible configuration, allowing for timer widths ranging from 31 to 128 bits depending on actual needs. Combined with a unique timing toggle flag mechanism, it enables precise timing over ultra-long periods without frequent software intervention. Furthermore, through comprehensive shielding logic configuration, the system provides hardware-level security isolation for various interrupt sources, effectively preventing unauthorized access and illegal routing in a multi-core shared environment, thus ensuring the security of core data and critical tasks.

[0132] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An interrupt control method applied to a PowerPC processor, characterized in that, Includes the following steps: Receive interrupt source signals, including external interrupts, internal interrupts, inter-core interrupts, message interrupts, shared message interrupts, timer interrupts, SOC error interrupts, and WDT interrupts; The interrupt source signal originating from the asynchronous clock domain is synchronized and monitored according to the configured level or edge validity to generate an interrupt request signal; The interrupt request signal is masked. The processed interrupt signals are routed to different output types according to the configuration. The output types include cint, mcp, IRQ_OUT_B, sie, and int. For interrupt output signals of types cint, mcp, IRQ_OUT_B, and sie, the interrupt source signals configured as the corresponding output interrupt types will be logically ORed to generate the corresponding interrupt output signals, and the interrupt sources that generate the interrupt output signals are limited to external interrupts and internal interrupts. For interrupt output signals of type int, the in service filo data structure is used to store the interrupt currently being processed. Arbitration is performed according to the priority of the interrupt source, and the arbitration priority is compared with the priority stored in the in service filo data structure to realize interrupt nesting, and the interrupt request with the highest priority is output.

2. The interrupt control method applied to a PowerPC processor according to claim 1, characterized in that, The interrupt control method supports three operating modes: bypass mode, hybrid mode, and external agent mode; In bypass mode, only external interrupt 0 is valid, and the outputs of cint, mcp, and sie are all logic 0. The output logic of the IRQ_OUT_B signal is: perform a logical AND operation on each internal interrupt signal and its corresponding mask enable configuration inverted, and then perform a logical OR operation on all the results. In mixed mode, when the output interrupt type is int, the interrupt number is obtained by reading the register through software; In external proxy mode, the int output is always logic 0, and the processor directly receives and reads the interrupt signal through the CoreInt core interrupt interface.

3. The interrupt control method applied to a PowerPC processor according to claim 1, characterized in that, For interrupts of type int, a priority-based interrupt nesting mechanism is supported, specifically including: Set the real-time task priority register CTPR so that interrupt sources participate in scheduling when their priority is greater than the register's value; When the processor responds to an interrupt, it pushes the currently arbitrated interrupt and its priority into the in-service filo data structure; When a new interrupt source is arbitrated, its priority is compared with the priority of the top of the in-service filo data structure stack. If the new interrupt has a higher priority, it is responded to and pushed onto the stack; otherwise, it is not responded to. When the processor finishes processing the current interrupt, it pops the in-service filo data structure by writing to the End of Interrupt (EOI) register.

4. The interrupt control method applied to a PowerPC processor according to claim 3, characterized in that, For interrupts of type int, the software returns a pseudo-interrupt number when reading the interrupt number register in the following cases: The interrupt source is level-sensitive and becomes invalid before being responded to; The masking configuration of the interrupt source was modified to be enabled before the interrupt was responded to; The real-time task priority register is configured to a higher priority before the interrupt is responded to. No interrupt was generated, but the software responded.

5. The interrupt control method applied to a PowerPC processor according to claim 1, characterized in that, The timer interrupt is generated by the internal timer logic, which uses a timer consisting of a 128-bit register array, divided into four 32-bit parts. Each 32-bit section contains a 1-bit timer toggle flag and a 31-bit counter. After counting begins, the count value is decremented from the initial count value. When it reaches 0, the initial value is reloaded and the count restarts. At the same time, the toggle flag is toggled once.

6. The interrupt control method applied to a PowerPC processor according to claim 5, characterized in that, The timer logic supports configuring timer concatenation to form longer timers, including concatenation combinations to form 63-bit, 95-bit, or 128-bit timers; For concatenated registers, except for the high-order bits, the other bits can be configured to load the starting count value or a preset all-1 value when the timer counts down to 0. During the counting process, if the configuration is to concatenate and no preset all-1 value is configured, the corresponding bit of the base value register is loaded when the count reaches 0; if the count does not reach 0, a decrement operation is performed once every clock cycle.

7. The interrupt control method applied to a PowerPC processor according to claim 1, characterized in that, The interrupt control method supports multicast functionality, allowing interrupts to be delivered to multiple processors simultaneously. When the external or internal interrupt source is configured with the output type set to cint or mcp, it can be configured to be passed to multiple processors. When the output type of the processor core interrupt and timer interrupt source is configured to be int, it can be passed to multiple processors. The interrupt control method also sends non-maskable interrupt signals and hardware reset signals to the processor by writing to the registers in software, and configures them to be passed to multiple processors.

8. An interrupt control circuit applied to a PowerPC processor, employing the interrupt control method for a PowerPC processor as described in any one of claims 1-7, characterized in that, include: Synchronization processing logic is used to synchronize asynchronous interrupt signals. Monitoring logic is used to generate valid interrupt request signals based on the configuration. The blocking logic is used to block corresponding interrupt requests based on the configuration. Priority arbitration logic is used to arbitrate the highest priority interrupt from the current interrupt request signals; In the service filo logic, it is used to save nested interrupts that are currently being processed by the processor but have not yet been completed; The priority comparison logic is used to compare the priority determined by the priority arbitration logic with the priority stored in the in-service filo logic. If the arbitration result is higher, the interruption request signal will be raised. The circuit supports routing interrupt sources to outputs of types cint, mcp, IRQ_OUT_B, sie, and int. Outputs of types cint, mcp, IRQ_OUT_B, and sie are generated by performing a logical OR operation on the interrupt source configured as the corresponding type.

9. The interrupt control circuit applied to a PowerPC processor according to claim 8, characterized in that, The priority arbitration logic adopts an 8-level arbitration structure, in which multiple data blocks are arbitrated in pairs through a comparator, and finally a highest priority interrupt request is obtained. The data structure stored in the service filo logic is a 4-bit interrupt priority plus a one-hot encoded interrupt source number.

10. The interrupt control circuit applied to a PowerPC processor according to claim 8, characterized in that, The interrupt control circuit includes timer logic and uses a 128-bit register array, divided into four 32-bit parts. The timer logic supports the concatenation of configuration registers to form timers of different bit widths; For the loading value of the timer, if it is configured not to be concatenated or to be the highest bit of the concatenated timer, the high bit is cleared to zero when loading the initial value; if it is configured to be a non-highest bit of the concatenated timer, the corresponding bit of the base value register is loaded.

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