Calibration method and apparatus, system for a chip

Abstract

The application relates to the chip calibration technical field and discloses a calibration method for a chip, which comprises the following steps: after being heated to a characteristic temperature, the chip is adjusted, and an adjustment value corresponding to the characteristic temperature is obtained; wherein the characteristic temperature is an ambient temperature obtained based on a temperature drift characteristic curve, and a temperature characteristic section is a curve part corresponding to a target standard voltage range in the temperature characteristic curve; the adjustment value corresponding to the characteristic temperature is written into a nonvolatile memory; after the chip is powered on and runs, in the case that an actual ambient temperature reaches a characteristic temperature critical value, the target adjustment value corresponding to the characteristic temperature is read from the nonvolatile memory; and the target adjustment value is written into a calibration register to complete the adjustment. The method can guarantee the working precision of the chip in a full temperature range under strict voltage tolerance requirements, and optimizes the running performance and reliability in an extreme environment. The application further discloses a calibration device and system for the chip.

Description

Technical Field

[0001] This application relates to the field of chip calibration technology, and for example to a calibration method, apparatus, and system for chips. Background Technology

[0002] Currently, in modern high-performance, high-reliability chips (such as automotive-grade MCUs, industrial processors, and communication chips), the accuracy and stability of the internal clock source and power supply module are crucial. Internal clock sources include, for example, OSCs (Oscillators), and power supply modules include, for example, LDOs (Low Dropout Regulators). Due to variations in semiconductor manufacturing processes, these analog circuits require post-production adjustments to calibrate their outputs to the design target values.

[0003] The relevant technology employs single-temperature point tuning. During the wafer testing or finished product testing phase of the chip, the clock frequency or power supply voltage is typically tuned under typical conditions (room temperature such as 25°C, nominal voltage), and the final set of tuned values ​​is written into a one-time programmable memory. In all subsequent applications, regardless of the operating environment, the chip consistently uses these parameters optimized under typical conditions.

[0004] In the process of implementing the embodiments of this disclosure, at least the following problems were found in the related art: The electrical characteristics of transistors and passive components are highly temperature-dependent. For example, carrier mobility decreases with increasing temperature, leading to a reduction in drive current; the threshold voltage also shifts with temperature. This causes a circuit tuned optimally under typical conditions to exhibit significant output drift at high or low temperatures. For instance, a low-speed clock that is accurately tuned to 32kHz under typical conditions may be as slow as 30kHz at -40°C and as fast as 35kHz at 125°C. Similarly, the output voltage of an LDO also drifts with temperature.

[0005] This temperature drift can cause serious problems: 1) Clock frequency deviation may lead to timing violations in digital logic, causing functional errors; 2) Power supply voltage variations may affect the performance of analog circuits, and even cause abnormal switching speeds of logic gates. To ensure that chips pass high and low temperature tests, the traditional compromise is to relax product specifications, such as allowing clock frequency deviations of ±10% or even greater at extreme temperatures, or allowing wider tolerances for power supply voltage. While this improves test yield, it sacrifices the actual performance and reliability of the chip in extreme environments, creating potential risks for long-term stable operation of the product in harsh application scenarios (such as automotive engine compartments and outdoor base stations).

[0006] Therefore, there is an urgent need for a new technology that can overcome the limitations of single-point adjustment and ensure that the chip can maintain high performance and high stability across the entire temperature range.

[0007] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0008] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0009] This disclosure provides a calibration method, apparatus, and system for chips to ensure the chip's operating accuracy across the entire temperature range under strict voltage tolerance requirements, and to optimize its performance and reliability in extreme environments.

[0010] In some embodiments, the method includes: heating the chip to a characteristic temperature and then adjusting it to obtain an adjustment value corresponding to the characteristic temperature; wherein the characteristic temperature is the ambient temperature obtained based on a temperature drift characteristic curve, the temperature drift characteristic curve is the remaining curve in the temperature characteristic curve excluding the temperature characteristic segment, and the temperature characteristic segment is the part of the temperature characteristic curve corresponding to the target standard voltage range; writing the adjustment value corresponding to the characteristic temperature to a non-volatile memory; after the chip is powered on and running, when the actual ambient temperature reaches the characteristic temperature critical value, reading the target adjustment value corresponding to the characteristic temperature from the non-volatile memory; wherein the characteristic temperature critical value is the upper and lower limit threshold of the reference characteristic temperature range obtained based on the temperature drift characteristic curve and the offset of the target standard voltage range; and writing the target adjustment value to a calibration register to complete the adjustment.

[0011] In some embodiments, the temperature characteristic curve represents the correspondence between ambient temperature and output voltage; the characteristic temperature and characteristic temperature range are obtained as follows: a temperature characteristic segment corresponding to the target standard voltage range is extracted from the temperature characteristic curve; the temperature range corresponding to the temperature characteristic segment is determined as a first reference characteristic temperature range; the ambient temperature of the temperature characteristic segment under the target standard voltage is determined as the first characteristic temperature; wherein, the target standard voltage is the center value of the target standard voltage range; and / or, a temperature drift characteristic segment corresponding to the reference standard voltage range is extracted from the temperature drift characteristic curve; wherein, the reference standard voltage range is the voltage range of the target standard voltage range offset by a preset voltage offset, the preset voltage offset being an even multiple of the voltage deviation, and the voltage deviation being less than or equal to the voltage offset corresponding to the target standard voltage range; the temperature range corresponding to the temperature drift characteristic segment is determined as a second reference characteristic temperature range; the ambient temperature of the temperature drift characteristic segment under the reference standard voltage is determined as the second characteristic temperature; wherein, the reference standard voltage is the center value of the reference standard voltage range.

[0012] In some embodiments, the temperature drift characteristic curve includes a high-temperature characteristic curve, which is the temperature characteristic curve corresponding to a voltage higher than the upper limit threshold of the target standard voltage, and the reference standard voltage range is the voltage range after the target standard voltage range is shifted upwards by a voltage deviation; extracting the temperature drift characteristic segment corresponding to the reference standard voltage range from the temperature drift characteristic curve includes: extracting the temperature characteristic curve corresponding to the reference standard voltage range from the high-temperature characteristic curve as the high-temperature characteristic segment; determining the temperature range corresponding to the temperature drift characteristic segment as the second reference characteristic temperature range includes: determining the temperature range corresponding to the high-temperature characteristic segment as the second reference characteristic temperature range; determining the ambient temperature of the temperature drift characteristic segment under the reference standard voltage as the second characteristic temperature includes: determining the ambient temperature of the high-temperature characteristic segment under the reference standard voltage as the second characteristic temperature. Temperature; or, the temperature drift characteristic curve includes a low-temperature characteristic curve, which is the temperature characteristic curve corresponding to the lower limit threshold of the target standard voltage, and the reference standard voltage range is the voltage range after the target standard voltage range is shifted down by voltage deviation; extracting the temperature drift characteristic segment corresponding to the reference standard voltage range from the temperature drift characteristic curve, including: extracting the temperature characteristic curve corresponding to the reference standard voltage range from the low-temperature characteristic curve as the low-temperature characteristic segment; determining the temperature range corresponding to the temperature drift characteristic segment as the second reference characteristic temperature range, including: determining the temperature range corresponding to the low-temperature characteristic segment as the second reference characteristic temperature range; determining the ambient temperature of the temperature drift characteristic segment under the reference standard voltage as the second characteristic temperature, including: determining the ambient temperature of the high-temperature characteristic segment under the reference standard voltage as the second characteristic temperature.

[0013] In some embodiments, determining the ambient temperature of the temperature drift characteristic segment under the reference standard voltage as the second characteristic temperature further includes: when the ambient temperature of the high-temperature characteristic segment cannot be found under the reference standard voltage, determining the ambient temperature of the high-temperature characteristic segment under the first critical reference voltage as the second characteristic temperature; wherein the first critical reference voltage is the center value of the output voltage range corresponding to the remaining high-temperature characteristic segment; or, when the ambient temperature of the low-temperature characteristic segment cannot be found under the reference standard voltage, determining the ambient temperature of the low-temperature characteristic segment under the second critical reference voltage as the second characteristic temperature; wherein the second critical reference voltage is the center value of the output voltage range corresponding to the remaining low-temperature characteristic segment.

[0014] In some embodiments, when the voltage deviation is less than the voltage offset corresponding to the target standard voltage range, reading the target adjustment value corresponding to the characteristic temperature from the non-volatile memory includes: when more than two adjustment values ​​corresponding to the characteristic temperature are read from the non-volatile memory, taking the adjustment value corresponding to the characteristic temperature that is closest to the actual ambient temperature as the target adjustment value corresponding to the characteristic temperature.

[0015] In some embodiments, the actual ambient temperature is determined to reach the characteristic temperature threshold as follows: the actual ambient temperature is higher than the lower limit threshold of the characteristic temperature and lower than the upper limit threshold of the characteristic temperature.

[0016] In some embodiments, the chip includes a temperature sensor for reading the actual ambient temperature; when the actual ambient temperature reaches a characteristic temperature threshold, reading the target adjustment value corresponding to the characteristic temperature from non-volatile memory includes: when the actual ambient temperature is higher than the lower limit threshold of the characteristic temperature, generating an interrupt signal; responding to the interrupt signal via the CPU, determining the storage address of the target adjustment value corresponding to the characteristic temperature, and reading the target adjustment value corresponding to the characteristic temperature from non-volatile memory according to the storage address; or, when the actual ambient temperature is higher than the lower limit threshold of the characteristic temperature, responding to the interrupt signal via DMA, starting a hardware state machine, reading the characteristic temperature and querying the storage address, and reading the target adjustment value corresponding to the characteristic temperature from non-volatile memory via the bus.

[0017] In some embodiments, the apparatus includes a processor and a memory storing program instructions, wherein the processor is configured to perform the chip calibration method described above when the program instructions are executed.

[0018] In some embodiments, the system includes: a chip; a testing device; and a calibration device for the chip as described above, mounted on the chip and / or the testing device.

[0019] In some embodiments, the chip includes: a non-volatile memory configured to write a trim value corresponding to a characteristic temperature to the device under test; a calibration register; a CPU configured to read a target trim value corresponding to a characteristic temperature from the non-volatile memory; and a DMA configured to read a target trim value corresponding to a characteristic temperature from the non-volatile memory.

[0020] The calibration method, apparatus, and system for chips provided in this disclosure can achieve the following technical effects: Based on the temperature characteristic curve, the system divides the temperature characteristic range and temperature drift characteristic curve, extracts the characteristic temperature and reference characteristic temperature range, and stores the corresponding adjustment values ​​in non-volatile memory. After the chip is powered on, it determines whether the characteristic temperature critical value has been reached based on the actual ambient temperature, reads the target adjustment value corresponding to the characteristic temperature, and writes it to the calibration register to complete the adjustment. This application abandons the traditional approach of relying solely on a single-point adjustment value at room temperature throughout the entire process. Instead, it configures dedicated adjustment values ​​for different temperature ranges, effectively compensating for the electrical characteristic deviation of transistors and passive devices caused by changes in ambient temperature, and significantly suppressing temperature deviations of key parameters such as clock frequency and LDO output voltage. This avoids digital logic timing violations and functional failures caused by clock frequency deviations under extreme high and low temperature environments, ensures the stability of the power supply voltage, and maintains the operating performance of analog circuits and the normal switching speed of logic gates. Therefore, this application can adapt to high and low temperature operating conditions without relaxing product specifications, and can still guarantee the chip's operating accuracy across the entire temperature range under strict voltage tolerance requirements. It optimizes the operating performance and reliability in extreme environments, fully meeting the long-term stable operation requirements of chips in demanding application scenarios such as automotive electronics and outdoor base stations.

[0021] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein: Figure 1 This is a hardware schematic diagram of a chip provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of a chip calibration method provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of another chip calibration method provided in this disclosure embodiment; Figure 4 This is a schematic diagram of another calibration method for chips provided in an embodiment of this disclosure; Figure 5This is a schematic diagram of a temperature characteristic curve provided in an embodiment of this disclosure; Figure 6 This is a schematic diagram of a chip calibration device provided in an embodiment of this disclosure; Figure 7 This is a schematic diagram of a chip calibration system provided in an embodiment of this disclosure. Detailed Implementation

[0023] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0024] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0025] Unless otherwise stated, the term "multiple" means two or more.

[0026] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0027] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0028] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.

[0029] In this embodiment of the disclosure, smart home appliances refer to home appliances formed by introducing microprocessors, sensor technology and network communication technology into home appliances. They have the characteristics of intelligent control, intelligent sensing and intelligent application. The operation of smart home appliances often relies on the application and processing of modern technologies such as the Internet of Things, the Internet and electronic chips. For example, smart home appliances can be connected to electronic devices to enable users to remotely control and manage smart home appliances.

[0030] Combination Figure 1 As shown, this embodiment of the disclosure provides a chip 10, including a CPU (Central Processing Unit) 101, non-volatile memory 102, DMA (Direct Memory Access) 103, a calibration register 104, and a temperature sensor 105. The temperature sensor 105 is used to read the actual ambient temperature. Specifically, the temperature sensor 105 reads the actual ambient temperature at preset intervals.

[0031] In this embodiment of the disclosure, the temperature characteristic curve represents the relationship between the ambient temperature and the output voltage of the chip.

[0032] Based on the above chip, combined with Figure 2 As shown, this disclosure provides a calibration method for a chip, including: S01, After heating to the characteristic temperature, the chip is adjusted to obtain the adjustment value corresponding to the characteristic temperature. Here, the characteristic temperature is the ambient temperature obtained based on the temperature drift characteristic curve. The temperature drift characteristic curve is the remaining curve in the temperature characteristic curve excluding the temperature characteristic section. The temperature characteristic section is the part of the temperature characteristic curve corresponding to the target standard voltage range.

[0033] S02, write the adjustment value corresponding to the characteristic temperature to the non-volatile memory.

[0034] S03: After the chip powers on and operates, when the actual ambient temperature reaches the characteristic temperature critical value, the target adjustment value corresponding to the characteristic temperature is read from the non-volatile memory. The characteristic temperature critical value is the upper and lower limit threshold of the reference characteristic temperature range obtained based on the temperature drift characteristic curve and the offset of the target standard voltage range.

[0035] S04, Write the target adjustment value to the calibration register to complete the adjustment.

[0036] The chip calibration method provided in this disclosure divides temperature characteristic segments and temperature drift characteristic curves based on temperature characteristic curves, extracts characteristic temperatures and reference characteristic temperature ranges, and stores corresponding adjustment values ​​in non-volatile memory. After the chip is powered on, it determines whether the characteristic temperature critical value has been reached based on the actual ambient temperature, reads the target adjustment value corresponding to the characteristic temperature, and writes it to the calibration register to complete the adjustment. This application abandons the traditional approach that relies solely on a single-point adjustment value at room temperature throughout the entire process. Instead, it configures dedicated adjustment values ​​for different temperature ranges, effectively compensating for electrical characteristic deviations of transistors and passive devices caused by changes in ambient temperature, and significantly suppressing temperature deviations of key parameters such as clock frequency and LDO output voltage. It avoids digital logic timing violations and functional failures caused by clock frequency deviations under extreme high and low temperature environments, ensures the stability of the power supply voltage, and maintains the operating performance of analog circuits and the normal switching speed of logic gates. Therefore, this application can adapt to high and low temperature conditions without relaxing product specifications, and can still ensure the chip's working accuracy across the entire temperature range under strict voltage tolerance requirements, optimize the operating performance and reliability in extreme environments, and fully meet the long-term stable operation requirements of chips in demanding application scenarios such as automotive electronics and outdoor base stations.

[0037] It should be noted that after heating to the characteristic temperature, the chip is adjusted. Obtaining the adjustment value corresponding to the characteristic temperature and writing the adjustment value corresponding to the characteristic temperature to the non-volatile memory are performed by the test equipment. After the chip is powered on and running, when the actual ambient temperature reaches the critical value of the characteristic temperature, the chip performs the adjustment by reading the target adjustment value corresponding to the characteristic temperature from the non-volatile memory and writing the target adjustment value to the calibration register.

[0038] Optionally, combined Figure 3 As shown, the test equipment obtains the characteristic temperature and characteristic temperature range in the following manner: S11, the test equipment extracts the temperature characteristic segment corresponding to the target standard voltage range in the temperature characteristic curve.

[0039] S12, the test equipment determines the temperature range corresponding to the temperature characteristic section as the first reference characteristic temperature range.

[0040] In this step, the boundary property of the first reference characteristic temperature range is either a left-open, right-closed interval or a left-closed, right-open interval. This embodiment of the present disclosure does not impose specific limitations on this.

[0041] S13, the testing equipment determines the ambient temperature of the temperature characteristic range under the target standard voltage as the first characteristic temperature. The target standard voltage is the center value of the target standard voltage range.

[0042] And / or, Combination Figure 4 As shown, the test equipment obtains the characteristic temperature and characteristic temperature range in the following manner: S21, the test equipment extracts the temperature drift characteristic segment corresponding to the reference standard voltage range from the temperature drift characteristic curve. The reference standard voltage range is the voltage range of the target standard voltage range offset by a preset voltage offset. The preset voltage offset is an even multiple of the voltage deviation, and the voltage deviation is less than or equal to the voltage offset corresponding to the target standard voltage range.

[0043] In this step, the target standard voltage range deviates from a preset voltage offset by an amount, including: a forward offset of the target standard voltage range from the preset voltage offset, or a reverse offset of the target standard voltage range from the preset voltage offset. A forward offset means the target standard voltage upper threshold is summed with the preset voltage offset, and the target standard voltage lower threshold is summed with the preset voltage offset. A reverse offset means the target standard voltage upper threshold is subtracted from the preset voltage offset, and the target standard voltage lower threshold is subtracted from the preset voltage offset. Understandably, there may be multiple sets of reference standard voltage ranges, and the number of sets is determined based on the temperature characteristic curve and the corresponding ambient temperature range.

[0044] S22, the test equipment determines the temperature range corresponding to the temperature drift characteristic section as the second reference characteristic temperature range.

[0045] In this step, the boundary property of the second reference characteristic temperature range is either a left-open, right-closed interval or a left-closed, right-open interval. This embodiment of the present disclosure does not impose a specific limitation on this. It should be noted that the boundary property of the second reference characteristic temperature range is the same as that of the first reference characteristic temperature range.

[0046] Furthermore, when the voltage deviation equals the voltage offset corresponding to the target standard voltage range, adjacent first and second reference characteristic temperature ranges do not overlap. When the voltage deviation is less than the voltage offset corresponding to the target standard voltage range, adjacent first and second reference characteristic temperature ranges overlap. It is understandable that when the testing equipment determines multiple second reference characteristic temperature ranges, if the voltage deviation is less than the voltage offset corresponding to the target standard voltage range, adjacent second reference characteristic temperature ranges overlap.

[0047] S23, the ambient temperature of the temperature drift characteristic range under the reference standard voltage is determined by the testing equipment as the second characteristic temperature. The reference standard voltage is the center value of the reference standard voltage range.

[0048] In this way, by extracting the temperature characteristic segment corresponding to the target standard voltage range from the temperature characteristic curve, the temperature range corresponding to this segment is determined and calibrated as the first reference characteristic temperature range. The ambient temperature of the temperature characteristic segment under the target standard voltage is then determined as the first characteristic temperature. This method can accurately pinpoint the temperature range and corresponding characteristic temperature within which the chip's output voltage conforms to the design standard. Using this as a adjustment point ensures that the chip's output voltage is close to the target standard voltage within its normal operating temperature range, avoiding voltage drift under normal operating conditions.

[0049] The remaining portion of the temperature characteristic curve is divided into temperature drift characteristic curves. A reference standard voltage range is obtained by combining this with the voltage deviation. The temperature drift characteristic segment corresponding to the reference standard voltage range is extracted from the temperature drift characteristic curve. The temperature range corresponding to this segment is then determined as the second reference characteristic temperature range, and the ambient temperature of the temperature drift characteristic segment under the reference standard voltage is determined as the second characteristic temperature. This method extracts features from the curve portion that deviates from the target standard voltage range, corresponding to high and low temperature operating conditions (prone to temperature drift). The characteristic temperature is determined through voltage deviation matching, capturing the variation pattern of the output voltage under extreme temperatures, providing a basis for adjustment under extreme temperatures.

[0050] By extracting the aforementioned characteristic temperature and reference characteristic temperature range in parallel, segmented feature analysis of the full-temperature-range curve is achieved, simultaneously covering the target standard voltage range and voltage drift range, distinguishing the differences in electrical characteristics across different temperature zones. Using this as a reference, corresponding adjustment values ​​are configured and calibration is performed, enabling differentiated compensation for different temperature ranges and voltage offset trends, effectively suppressing output voltage drift caused by temperature changes in transistors and passive devices. This embodiment no longer uses a single temperature point as the adjustment reference for the entire temperature range, but instead divides the temperature characteristic curve into multiple sets of reference characteristic temperature ranges and characteristic temperatures, ensuring a high degree of matching between the adjustment values ​​and the actual temperature characteristics of the chip. This embodiment can stabilize the output voltage within the target standard voltage range across the entire temperature range without relaxing product voltage tolerance specifications, effectively avoiding performance degradation of analog circuits and abnormal logic gate operation caused by voltage drift, and improving the chip's full-temperature-range operating accuracy, stability, and reliability.

[0051] Optionally, the temperature drift characteristic curve includes a high temperature characteristic curve, which is the temperature characteristic curve corresponding to the upper limit threshold of the target standard voltage, and the reference standard voltage range is the voltage range after the voltage deviation is shifted upward from the target standard voltage range.

[0052] The test equipment extracts the temperature drift characteristic segment corresponding to the reference standard voltage range from the temperature drift characteristic curve, including: extracting the temperature characteristic curve corresponding to the reference standard voltage range from the high temperature characteristic curve as the high temperature characteristic segment.

[0053] The testing equipment determines the temperature range corresponding to the temperature drift characteristic section as the second reference characteristic temperature range, including: determining the temperature range corresponding to the high temperature characteristic section as the second reference characteristic temperature range.

[0054] The testing equipment determines the ambient temperature of the temperature drift characteristic range under the reference standard voltage as the second characteristic temperature, including: determining the ambient temperature of the high temperature characteristic range under the reference standard voltage as the second characteristic temperature.

[0055] or, The temperature drift characteristic curve includes the low temperature characteristic curve, which is the temperature characteristic curve corresponding to the lower limit threshold of the target standard voltage. The reference standard voltage range is the voltage range after the voltage deviation is shifted down from the target standard voltage range.

[0056] The test equipment extracts the temperature drift characteristic segment corresponding to the reference standard voltage range from the temperature drift characteristic curve, including: extracting the temperature characteristic curve corresponding to the reference standard voltage range from the low temperature characteristic curve as the low temperature characteristic segment.

[0057] The testing equipment determines the temperature range corresponding to the temperature drift characteristic section as the second reference characteristic temperature range, including: determining the temperature range corresponding to the low temperature characteristic section as the second reference characteristic temperature range.

[0058] The testing equipment determines the ambient temperature of the temperature drift characteristic range under the reference standard voltage as the second characteristic temperature, including: determining the ambient temperature of the low temperature characteristic range under the reference standard voltage as the second characteristic temperature.

[0059] Thus, this embodiment of the disclosure subdivides the temperature drift characteristic curve into a high-temperature characteristic curve and a low-temperature characteristic curve. These characteristic curves correspond to two types of offset conditions: the output voltage exceeding the upper threshold of the target standard voltage and the output voltage falling below the lower threshold of the target standard voltage, respectively. For the high-voltage scenario, the high-temperature characteristic segment is extracted, and a second reference characteristic temperature range and a second characteristic temperature are defined. For the low-voltage scenario, the low-temperature characteristic segment is extracted, and a second reference characteristic temperature and a second characteristic temperature are defined. The above segment extraction, reference characteristic temperature range, and characteristic temperature determination method achieves the partitioning of two abnormal operating conditions: positive voltage drift and negative voltage drift. This accurately distinguishes the different trends of upward output voltage drift under high-temperature conditions and downward output voltage drift under low-temperature conditions, providing a judgment benchmark and basis for differentiated adjustment. Therefore, a dedicated adjustment value can be matched according to the voltage drift direction to achieve targeted and precise temperature drift compensation, avoiding abnormal operation of analog circuits and power supply overload caused by the voltage exceeding the upper threshold of the target standard voltage, and also preventing faults such as insufficient logic gate drive and circuit failure caused by the voltage falling below the lower threshold of the target standard voltage. This detailed design fully covers both forward and reverse voltage drift scenarios, enabling more precise analysis of the temperature characteristic curve and significantly improving the targeting and accuracy of adjustment and compensation. It eliminates the need to relax voltage tolerance specifications throughout the entire process, stabilizing the output voltage within the target standard voltage range across the entire temperature spectrum. This further enhances the chip's stability and reliability under extreme high and low temperature conditions, making it fully suitable for demanding applications such as automotive electronics and outdoor base stations.

[0060] Optionally, the testing equipment determines the ambient temperature of the temperature drift characteristic range under the reference standard voltage as the second characteristic temperature, and also includes: When the ambient temperature of the high-temperature characteristic range cannot be found under the reference standard voltage, the ambient temperature of the high-temperature characteristic range under the first critical reference voltage is determined as the second characteristic temperature. Here, the first critical reference voltage is the center value of the output voltage range corresponding to the remaining high-temperature characteristic range, and the remaining high-temperature characteristic range is the high-temperature characteristic range that cannot be found under the reference standard voltage.

[0061] or, When the ambient temperature of the low-temperature characteristic range cannot be found under the reference standard voltage, the ambient temperature of the low-temperature characteristic range under the second critical reference voltage is determined as the second characteristic temperature. The second critical reference voltage is the center value of the output voltage range corresponding to the remaining low-temperature characteristic range, which is the low-temperature characteristic range that cannot be found under the reference standard voltage.

[0062] Thus, for regions very close to the endpoints of the temperature range on the temperature characteristic curve, when the reference standard voltage cannot correspond to the ambient temperature of the high-temperature characteristic section (i.e., the reference standard voltage and the high-temperature characteristic section cannot intersect), the ambient temperature of that temperature characteristic section at the center value of the output voltage range corresponding to the remaining high-temperature characteristic section is taken as the second characteristic temperature. Similarly, the ambient temperature of that temperature characteristic section at the center value of the output voltage range corresponding to the remaining low-temperature characteristic section is taken as the second characteristic temperature.

[0063] In some alternative embodiments, Figure 5 This is a schematic diagram of a temperature characteristic curve provided in an embodiment of this disclosure. Wherein, L represents the LDO temperature characteristic curve, with the horizontal axis representing ambient temperature and the vertical axis representing output voltage. The temperature range of the temperature characteristic curve is [-40, 125], in °C (degrees Celsius).

[0064] L0 represents the temperature characteristic range, L1 represents the high-temperature characteristic range, and L2 represents the low-temperature characteristic range. 10 For the remaining high-temperature characteristic range, L 20 The remaining low-temperature characteristic range is defined by V1 as the first critical reference voltage and V2 as the second critical reference voltage. The target standard voltage range is [0.99, 1.21], in volts (V). The target standard voltage is 1.1V.

[0065] The voltage deviation is taken as the voltage offset corresponding to the target standard voltage range, that is, the voltage deviation is 0.11V. Accordingly, the preset voltage offset is an even multiple of 0.11, specifically 0.22, 0.44, 0.88... The reference standard voltage range in the above temperature range includes two sets, namely [1.21, 1.43] and [0.77, 0.99].

[0066] Based on the above-described method for determining characteristic temperature and characteristic temperature range, the first reference characteristic temperature range is determined to be (10, 50]℃, and the first characteristic temperature is 25℃. The second reference characteristic temperature range and the second characteristic temperature are also determined. Specific values ​​are shown in Table 1.

[0067] For writing the corresponding adjustment value for the characteristic temperature to the non-volatile memory, please refer to Table 2.

[0068] Table 1. Summary of Second Reference Characteristic Temperature Range and Second Characteristic Temperature

[0069] Table 2. Schematic diagram of non-volatile memory storage

[0070] Optionally, if the voltage deviation is less than the voltage offset corresponding to the target standard voltage range, the target adjustment value corresponding to the characteristic temperature is read from the non-volatile memory, including: If more than two adjustment values ​​corresponding to a feature temperature are read from non-volatile memory, the adjustment value corresponding to the feature temperature that is closest to the actual ambient temperature is taken as the target adjustment value corresponding to the feature temperature.

[0071] In this way, when more than two trim values ​​corresponding to the characteristic temperature are read from the non-volatile memory, the nearest trim value is used to prevent output voltage instability and jumps. At the same time, the non-volatile memory can save the trim values ​​when the power is off, ensuring that the parameter configuration and operating characteristics remain consistent after repeated power-ups and shutdowns of the chip.

[0072] Optionally, the chip determines the characteristic temperature threshold by the following method: The actual ambient temperature is higher than the lower limit threshold of the characteristic temperature but lower than the upper limit threshold of the characteristic temperature.

[0073] In this way, by setting the actual ambient temperature to be higher than the lower limit threshold of the characteristic temperature but lower than the upper limit threshold of the characteristic temperature, the state of the ambient temperature reaching the critical value of the characteristic temperature can be accurately identified, providing an accurate basis for subsequent loading of target adjustment values ​​and adjustment operations, and ensuring that the adjustment operations are executed in a timely manner.

[0074] Optionally, when the actual ambient temperature reaches the characteristic temperature critical value, the chip reads the target adjustment value corresponding to the characteristic temperature from the non-volatile memory, including: When the actual ambient temperature is higher than the lower limit threshold of the characteristic temperature, the chip generates an interrupt signal.

[0075] The chip responds to the interrupt signal via the CPU, determines the storage address of the target adjustment value corresponding to the characteristic temperature, and reads the target adjustment value corresponding to the characteristic temperature from the non-volatile memory according to the storage address.

[0076] or, When the actual ambient temperature is higher than the lower limit threshold of the characteristic temperature, the chip responds to the interrupt signal via DMA, starts the hardware state machine, reads the characteristic temperature and queries the memory address, and reads the target adjustment value corresponding to the characteristic temperature from the non-volatile memory via the bus.

[0077] Thus, when the actual ambient temperature exceeds the lower limit of the characteristic temperature threshold, the chip can generate and respond to an interrupt signal, determine the storage address of the target adjustment value corresponding to the characteristic temperature, and read the target adjustment value from the non-volatile memory according to the storage address, thereby reading the target adjustment value through software. Alternatively, the chip can respond to the interrupt signal via DMA and start a hardware state machine to read the characteristic temperature, query the storage address, and read the target adjustment value corresponding to the characteristic temperature from the bus non-volatile memory, thus reading the target adjustment value in hardware, without any CPU software involvement. In this way, the chip can obtain the target adjustment value through both software and hardware methods, achieving flexible reading of the target adjustment value.

[0078] Optionally, when the actual ambient temperature reaches the characteristic temperature critical value, the chip reads the target adjustment value corresponding to the characteristic temperature from the non-volatile memory, including: When the actual ambient temperature reaches the critical value of the characteristic temperature, the chip receives the actual ambient temperature through the bus and responds to the interrupt signal through the CPU to determine the storage address of the target adjustment value corresponding to the characteristic temperature, and reads the target adjustment value corresponding to the characteristic temperature from the non-volatile memory according to the storage address.

[0079] In this way, even when the chip is not equipped with a temperature sensor, it can still receive the actual ambient temperature from the outside via the bus and complete the query and loading of the target adjustment value.

[0080] In practical applications, automotive-grade microcontroller chips (hereinafter referred to as chips) include LDOs and temperature sensors. The target standard voltage of the LDO is 1.1V, with a voltage tolerance of ±10%, meaning the target standard voltage range is [0.99, 1.21]. The chip's operating range is -40℃ to 125℃. The temperature sensor is used to read the actual ambient temperature at preset intervals. The temperature characteristic curve of the LDO is shown below. Figure 5 As shown.

[0081] The calibration method for the chip specifically involves the following steps: S101, the test equipment extracts the temperature characteristic segment corresponding to the target standard voltage range in the temperature characteristic curve, and determines the temperature range corresponding to this segment as the first reference characteristic temperature range (10, 50]℃, and determines the ambient temperature of the temperature characteristic segment under the target standard voltage as the first characteristic temperature 25℃.

[0082] S102, the testing equipment extracts the temperature drift characteristic segment corresponding to the reference standard voltage range from the temperature drift characteristic curve, and determines the temperature range corresponding to this segment as the second reference characteristic temperature range, and determines the ambient temperature of the temperature drift characteristic segment under the reference standard voltage as the second characteristic temperature. Refer to Table 1 for specific values.

[0083] S103, the test device writes the adjustment value corresponding to the above characteristic temperature to the non-volatile memory.

[0084] S104: After the chip is powered on, the actual ambient temperature rises from the room temperature of 25°C to the characteristic temperature of 50°C, generating an interrupt signal.

[0085] S105, the DMA responds to the interrupt signal and starts the hardware state machine. The state machine reads the actual ambient temperature through its internal hardware logic and compares it with preset rules to calculate the corresponding Flash storage address (for example, the address corresponding to the second characteristic temperature of 70°C is 0x0C). It then reads the target adjustment value corresponding to the second characteristic temperature of 70°C from the Flash storage address 0x0C via the bus.

[0086] S106, the DMA writes the target adjustment value corresponding to the second characteristic temperature of 70°C into the LDO calibration register.

[0087] S107, the LDO adjusts its internal circuitry according to the aforementioned target adjustment value to stabilize its output voltage at 1.1V.

[0088] The above process is completed within microseconds, without CPU intervention, achieving a rapid adaptive response at the millisecond level. Using this method, regardless of ambient temperature variations across the entire temperature range, the LDO output remains stable within the target standard voltage range, ensuring high chip test yield and operational reliability under extreme conditions.

[0089] Combination Figure 6 As shown, this disclosure provides a chip calibration apparatus 70, including a processor 700 and a memory 701. Optionally, the apparatus 70 may further include a communication interface 702 and a bus 703. The processor 700, communication interface 702, and memory 701 can communicate with each other via the bus 703. The communication interface 702 can be used for information transmission. The processor 700 can call logical instructions in the memory 701 to execute the chip calibration method of the above embodiment.

[0090] Furthermore, the logic instructions in the aforementioned memory 701 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0091] The memory 701, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 100 executes functional applications and data processing by running the program instructions / modules stored in the memory 701, that is, it implements the calibration method for the chip in the above embodiments.

[0092] The memory 701 may include a program storage area and a data storage area. The program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 701 may include high-speed random access memory and may also include non-volatile memory.

[0093] Combination Figure 7 As shown, this disclosure provides a calibration system 1 for a chip, including a chip, a testing device, and the aforementioned calibration device 70 for the chip. The calibration device 70 is mounted on the chip and / or the testing device. The mounting relationship described herein is not limited to placement within the chip and / or the testing device, but also includes mounting connections with other components of the chip and / or the testing device, including but not limited to physical connections, electrical connections, or signal transmission connections. Those skilled in the art will understand that the calibration device 70 for the chip can be adapted to feasible chip bodies and testing device bodies to achieve other feasible embodiments.

[0094] This disclosure provides a computer-readable storage medium storing computer-executable instructions configured to perform the above-described calibration method for a chip.

[0095] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this disclosure. The aforementioned storage medium can be a non-transitory storage medium, such as a USB flash drive, external hard drive, read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk, etc., and other media capable of storing program code.

[0096] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the claims. As used in the description of embodiments and claims, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used in this application means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.

[0097] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0098] The methods and products disclosed in the embodiments herein (including but not limited to devices and equipment) can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to implement this embodiment according to actual needs. In addition, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0099] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. A calibration method for chips, characterized in that, include: After heating to the characteristic temperature, the chip is adjusted to obtain the adjustment value corresponding to the characteristic temperature; Among them, the characteristic temperature is the ambient temperature obtained based on the temperature drift characteristic curve. The temperature drift characteristic curve is the remaining curve in the temperature characteristic curve except for the temperature characteristic section. The temperature characteristic section is the part of the temperature characteristic curve corresponding to the target standard voltage range. Write the trim value corresponding to the characteristic temperature to non-volatile memory; After the chip is powered on and running, when the actual ambient temperature reaches the critical value of the characteristic temperature, the target adjustment value corresponding to the characteristic temperature is read from the non-volatile memory; where the critical value of the characteristic temperature is the upper and lower limit threshold of the reference characteristic temperature range obtained based on the temperature drift characteristic curve and the offset of the target standard voltage range. Write the target adjustment value to the calibration register to complete the adjustment.

2. The calibration method according to claim 1, characterized in that, The temperature characteristic curve represents the relationship between ambient temperature and output voltage; the characteristic temperature and characteristic temperature range are obtained as follows: Extract the temperature characteristic segment corresponding to the target standard voltage range from the temperature characteristic curve; The temperature range corresponding to the temperature characteristic segment is determined as the first reference characteristic temperature range; The ambient temperature of the temperature characteristic range under the target standard voltage is defined as the first characteristic temperature; where the target standard voltage is the center value of the target standard voltage range. And / or, Extract the temperature drift characteristic segment corresponding to the reference standard voltage range from the temperature drift characteristic curve; where the reference standard voltage range is the voltage range of the target standard voltage range offset by a preset voltage offset, the preset voltage offset is an even multiple of the voltage deviation, and the voltage deviation is less than or equal to the voltage offset corresponding to the target standard voltage range. The temperature range corresponding to the temperature drift characteristic section is determined as the second reference characteristic temperature range. The ambient temperature of the temperature drift characteristic range under the reference standard voltage is defined as the second characteristic temperature; where the reference standard voltage is the center value of the reference standard voltage range.

3. The calibration method according to claim 2, characterized in that, The temperature drift characteristic curve includes the high temperature characteristic curve, which is the temperature characteristic curve corresponding to the upper limit threshold of the target standard voltage. The reference standard voltage range is the voltage range after the voltage deviation is shifted upward from the target standard voltage range. Extract the temperature drift characteristic segment corresponding to the reference standard voltage range from the temperature drift characteristic curve, including: extract the temperature characteristic curve corresponding to the reference standard voltage range from the high temperature characteristic curve as the high temperature characteristic segment; Determining the temperature range corresponding to the temperature drift characteristic section as the second reference characteristic temperature range includes: determining the temperature range corresponding to the high temperature characteristic section as the second reference characteristic temperature range; Determining the ambient temperature of the temperature drift characteristic range under the reference standard voltage as the second characteristic temperature includes: determining the ambient temperature of the high temperature characteristic range under the reference standard voltage as the second characteristic temperature; or, The temperature drift characteristic curve includes the low temperature characteristic curve, which is the temperature characteristic curve corresponding to the lower limit threshold of the target standard voltage. The reference standard voltage range is the voltage range after the voltage deviation is shifted down from the target standard voltage range. Extract the temperature drift characteristic segment corresponding to the reference standard voltage range from the temperature drift characteristic curve, including: extract the temperature characteristic curve corresponding to the reference standard voltage range from the low temperature characteristic curve as the low temperature characteristic segment; Determining the temperature range corresponding to the temperature drift characteristic section as the second reference characteristic temperature range includes: determining the temperature range corresponding to the low temperature characteristic section as the second reference characteristic temperature range. The ambient temperature of the temperature drift characteristic range under the reference standard voltage is determined as the second characteristic temperature, including: the ambient temperature of the low temperature characteristic range under the reference standard voltage is determined as the second characteristic temperature.

4. The method according to claim 3, characterized in that, The second characteristic temperature is determined by defining the ambient temperature of the temperature drift characteristic range under the reference standard voltage as the second characteristic temperature, which also includes: When the ambient temperature of the high-temperature characteristic section cannot be found under the reference standard voltage, the ambient temperature of the high-temperature characteristic section under the first critical reference voltage is determined as the second characteristic temperature; wherein, the first critical reference voltage is the center value of the output voltage range corresponding to the remaining high-temperature characteristic section. or, When the ambient temperature of the low-temperature characteristic range cannot be found under the reference standard voltage, the ambient temperature of the low-temperature characteristic range under the second critical reference voltage is determined as the second characteristic temperature; wherein, the second critical reference voltage is the center value of the output voltage range corresponding to the remaining low-temperature characteristic range.

5. The method according to claim 2, characterized in that, When the voltage deviation is less than the voltage offset corresponding to the target standard voltage range, the target adjustment value corresponding to the characteristic temperature is read from the non-volatile memory, including: If more than two adjustment values ​​corresponding to a feature temperature are read from non-volatile memory, the adjustment value corresponding to the feature temperature that is closest to the actual ambient temperature is taken as the target adjustment value corresponding to the feature temperature.

6. The method according to claim 1, characterized in that, The critical value for reaching the characteristic temperature of the actual ambient temperature is determined as follows: The actual ambient temperature is higher than the lower limit threshold of the characteristic temperature but lower than the upper limit threshold of the characteristic temperature.

7. The method according to claim 6, characterized in that, The chip includes a temperature sensor used to read the actual ambient temperature; when the actual ambient temperature reaches a characteristic temperature threshold, it reads the target adjustment value corresponding to the characteristic temperature from non-volatile memory, including: An interrupt signal is generated when the actual ambient temperature is higher than the lower limit threshold of the characteristic temperature. The CPU responds to the interrupt signal, determines the storage address of the target adjustment value corresponding to the characteristic temperature, and reads the target adjustment value corresponding to the characteristic temperature from the non-volatile memory according to the storage address. or, When the actual ambient temperature is higher than the lower limit threshold of the characteristic temperature, the interrupt signal is responded to via DMA, and the hardware state machine is started. The characteristic temperature is read and the memory address is queried. The target adjustment value corresponding to the characteristic temperature is read from the non-volatile memory via the bus.

8. A calibration apparatus for a chip, comprising a processor and a memory storing program instructions, characterized in that, The processor is configured to perform the chip calibration method as described in any one of claims 1 to 7 when executing the program instructions.

9. A calibration system for chips, characterized in that, include: chip; Test equipment; The calibration apparatus for a chip as described in claim 8 is installed on the chip and / or testing equipment.

10. The calibration system according to claim 9, characterized in that, The chip includes: Non-volatile memory is configured to write a trim value corresponding to a characteristic temperature to the device under test; Calibration register; The CPU is configured to read the target trim value corresponding to the characteristic temperature from non-volatile memory; DMA is configured to read the target trim value corresponding to the characteristic temperature from non-volatile memory.

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