A partial discharge detection system based on FPGA-ARM heterogeneous architecture

Abstract

The application discloses a partial discharge detection system based on FPGA-ARM heterogeneous architecture, which comprises a data acquisition module, an FPGA processing module, an ARM processing module 8 and an AI acceleration module 9; the data acquisition module synchronously acquires partial discharge sensing signals, is connected with the FPGA processing module and outputs a digital signal stream; the ARM processing module 8 is provided with a storage bus space for connecting the FPGA processing module; the FPGA processing module comprises an on-chip memory, a hardware logic processing unit 7 and a bus slave interface, and the on-chip memory is directly mapped to the ARM processing module 8 through the bus slave interface. Through deep heterogeneous cooperation of FPGA and ARM and bus bridge shared storage architecture, the application realizes continuous and uninterrupted acquisition of high-speed data flow, hardware parallel deterministic preprocessing and zero-delay data sharing between processors, and significantly improves system real-time performance and data exchange efficiency.

Description

Technical Field

[0001] This invention relates to the field of partial discharge detection technology, and in particular to a partial discharge detection system based on an FPGA-ARM heterogeneous architecture. Background Technology

[0002] Partial discharge is an important early sign of insulation degradation in high-voltage electrical equipment. Partial discharge pulses are typically characterized by short duration, steep leading edge, random occurrence, and amplitude significantly affected by ambient noise. The detection system not only needs to obtain the pulse amplitude, but also needs to record the timestamp, power frequency phase, pulse width, frequency domain energy, and the arrival order of multiple channels at the moment the pulse occurs.

[0003] Existing partial discharge detection equipment often employs a structure of "high-speed sampling circuit + general-purpose processor" or "FPGA acquisition + external memory + ARM processing". This structure is prone to problems such as large raw data transfer volume, uncertain processing link latency, unstable inter-channel timing organization, and high overall power consumption when facing sampling rates of hundreds of megabits per second, multi-channel synchronous sampling, and transient event capture. Especially when relying on serial interfaces such as UART and SPI or external SDRAM for relay, there is a significant isolation between the front-end sampling rhythm and the back-end processing rhythm, making it difficult to simultaneously achieve real-time performance, low power consumption, and intelligent diagnostic capabilities in portable, battery-powered field devices. Summary of the Invention

[0004] The purpose of this invention is to provide a partial discharge detection system based on an FPGA-ARM heterogeneous architecture, which solves the problems of large amount of raw data transfer, uncertain processing delay, difficulty in aligning multi-channel events, and high power consumption in existing portable partial discharge detection devices.

[0005] Technical solution

[0006] A partial discharge detection system based on an FPGA-ARM heterogeneous architecture includes: a data acquisition module, an FPGA processing module, an ARM processing module, and an AI acceleration module; the data acquisition module synchronously acquires partial discharge sensing signals, connects to the FPGA processing module, and outputs a digital signal stream; the ARM processing module is provided with a storage bus space for connecting to the FPGA processing module;

[0007] The FPGA processing module includes: on-chip memory, hardware logic processing unit and bus slave interface, wherein the on-chip memory is directly mapped to the ARM processing module through the bus slave interface;

[0008] The on-chip memory is provided with an original sampling ping-pong buffer, a feature data register area, a configuration status register area, and a diagnostic algorithm working area; the hardware logic processing unit obtains the digital signal stream input to the original sampling ping-pong buffer, performs data processing on the digital signal stream, and extracts feature vectors to the feature data register area;

[0009] The AI ​​acceleration module acquires the feature vector, outputs the classification confidence of the partial discharge type based on the pre-trained convolutional neural network, and inputs it into the ARM processing module. The ARM processing module outputs the partial discharge type and localization result based on the probabilistic fusion model.

[0010] Preferably, the data acquisition module includes: an ultra-high frequency sensing channel, an ultrasonic sensing channel, an analog conditioning circuit, a multi-channel analog-to-digital converter, and a parallel low-voltage differential signal interface; the analog conditioning circuit includes: a programmable gain amplifier and a gain feedback branch.

[0011] Preferably, the original sampling ping-pong buffer includes a first buffer area and a second buffer area, and the hardware logic processing unit includes a read / write arbitration control logic component. The read / write arbitration control logic component obtains request inputs from the first buffer area and the second buffer area, alternately writes to the digital signal stream, and reads data from the first buffer area or the second buffer area when it is full.

[0012] Preferably, the hardware logic processing unit is configured with a pre-trigger cache mode and a post-trigger cache mode. Specifically, it sets the trigger condition for the pulse detection result, associates the pre-trigger preset sampling point and the post-trigger preset sampling point with the same event window, and writes the window index of the event window into the feature data register area.

[0013] Preferably, the hardware logic processing unit includes: a digital filtering module, a fast Fourier transform acceleration module, a pulse detection logic module, a peak hold module, a pulse width statistics module, and a synchronous phase counter module; the synchronous phase counter module acquires the phase count of the power frequency signal output and latches the phase value;

[0014] The triggering conditions of the pulse detection logic module include one or more combinations of programmable amplitude threshold, pulse width threshold, rising edge slope threshold, and frequency band energy threshold.

[0015] Preferably, the AI ​​acceleration module is equipped with an online threshold adaptive processing component, which extracts background noise statistics based on a historical pulse feature library and inputs dynamic threshold parameters to the FPGA processing module.

[0016] Preferably, the AI ​​acceleration module includes: a deep convolution hardware unit, a pointwise convolution hardware unit, a normalization and activation hardware unit, a pooling hardware unit, and a local instruction memory; the deep convolution hardware unit and the pointwise convolution hardware unit perform feature loading, convolution calculation, and result writing back in a double-buffered manner.

[0017] Preferably, the probabilistic fusion model is a Bayesian network model, which includes evidence nodes, hidden nodes, and output nodes. The evidence nodes include: UHF channel classification confidence, ultrasonic channel classification confidence, pulse power frequency phase, pulse repetition rate, and multi-channel arrival time difference. The hidden nodes include: true fault type and fault location coordinates. The output nodes include: discharge type node and location node.

[0018] Preferably, the ARM processing module acquires the multi-channel arrival time difference, calculates the arrival time difference between different sensing channels for the same discharge event based on the spatial arrangement parameters of each sensor, and outputs the positioning result.

[0019] Preferably, it further includes: a battery power supply module and a dynamic power management control circuit, wherein the dynamic power management control circuit acquires the task load information of the FPGA processing module, the ARM processing module and the AI ​​acceleration module, and outputs energy management instructions.

[0020] Beneficial effects

[0021] This invention reduces data transfer overhead caused by traditional serial protocols or external memory transfers by directly mapping the FPGA on-chip memory to the ARM memory bus space, enabling the ARM processing module to read event-level feature data in a timely manner. Through ping-pong buffering, pre-triggering buffering, and post-triggering buffering, it parallelizes acquisition, processing, and reading under high-speed sampling conditions, reducing the risk of missed transient pulse detection. By performing pulse detection, phase latching, timestamp recording, and feature extraction on the FPGA side, it compresses the Gbps-level raw sampling stream into event-level feature vectors, reducing subsequent bus bandwidth and processor computational burden. Low-precision convolutional inference is performed by an AI acceleration module, and probabilistic fusion is performed by the ARM processing module, balancing millisecond-level recognition speed and multi-source diagnostic reliability. Dynamic thresholding, adaptive gain, and dynamic power management enable the system to adapt to on-site electromagnetic noise and battery power constraints, making it suitable for portable partial discharge detection scenarios. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the system connection structure of the present invention;

[0023] The markings in the diagram are as follows: 1-Ultra-high frequency sensor; 2-Ultrasonic sensor; 3-Data acquisition module; 4-FPGA processing module; 5-Raw sampling ping-pong buffer; 6-Feature data register; 7-Hardware logic processing unit 7; 8-ARM processing module; 9-AI acceleration module; 10-Ethernet communication interface; 11-External host. Detailed Implementation

[0024] The technical solution of the present invention will be further described below with reference to the embodiments and accompanying drawings.

[0025] A partial discharge detection system based on an FPGA-ARM heterogeneous architecture includes: a data acquisition module 3, an FPGA processing module 4 using an Altera EP2S60 series chip, an ARM processing module 8 using an NXP LPC1788 processor, and an AI acceleration module 9. The data acquisition module 3 synchronously acquires partial discharge sensing signals, is electrically connected to the FPGA processing module 4, and outputs a digital signal stream. The ARM processing module 8 is equipped with a storage bus space for connecting to the FPGA processing module 4. The system aims to achieve a balance between high performance and low power consumption in high-speed data acquisition, real-time signal processing, and intelligent identification and diagnosis, making it particularly suitable for portable on-site detection scenarios.

[0026] The FPGA processing module 4 includes an on-chip memory, a hardware logic processing unit 7, and a bus slave interface. The feature data register 6 area of ​​the on-chip memory is directly mapped to the storage bus space of the ARM processing module 8 through the bus slave interface. By compressing the data source, the amount of data that needs to be moved is reduced by several orders of magnitude, which fundamentally alleviates the bus bandwidth pressure and the processor's computing load.

[0027] The on-chip memory is divided into a raw sampling ping-pong buffer 5, a feature data register area 6, a configuration status register area, and a diagnostic algorithm working area. The hardware logic processing unit 7 acquires the digital signal stream input to the raw sampling ping-pong buffer 5, performs pulse detection and event time latching data processing on the digital signal stream, and extracts the feature vector to the feature data register area 6. The feature vector contains channel identifier, amplitude, phase, timestamp, and frequency domain energy information.

[0028] AI acceleration module 9 acquires feature vectors, outputs classification confidence of partial discharge type based on pre-trained convolutional neural network and inputs it to ARM processing module 8. ARM processing module 8 outputs partial discharge type and localization result based on probabilistic fusion model, forming an end-to-end decision-making closed loop from millisecond-level identification to accurate real-time diagnosis.

[0029] Due to the constraints of 64Mbit on-chip storage and low power consumption, the convolutional neural network adopts the lightweight network structure MobileNetV2 and uses the INT8 fixed-point data format. The network weights and activation values ​​are stored in the on-chip memory or the local memory of the AI ​​acceleration module 9 after quantization and compression.

[0030] The input data for the pre-trained convolutional neural network (CNN) model is a 256-dimensional feature vector output from the FPGA front-end pipeline. This feature vector consists of the pulse's phase, amplitude, timestamp, and frequency domain energy distribution. The output is a 1×256 one-dimensional feature map, or a reconstructed 16×16 two-dimensional feature map input to the network. The pre-trained CNN model includes one 3×3 standard convolutional layer with a stride of 2, four bottleneck residual blocks (with a depthwise separable convolutional kernel of size 3×3), one global average pooling layer, and one fully connected classification layer. The total number of parameters in the pre-trained CNN model is less than 0.5M, and the model file size is approximately 1.2MB after INT8 quantization. It then outputs four classification confidence scores, corresponding to insulator surface discharge, floating potential discharge, free metal particle discharge, and noise.

[0031] The pre-trained convolutional neural network model was pre-trained offline on a cloud server using a large-scale localized emission dataset, containing 100,000 samples for each of the four classes mentioned above. The training framework used was TensorFlow Lite, and the training was completed until convergence, with a convergence classification accuracy of >98%.

[0032] The training adopts a post-training quantization method to adapt to the INT8 fixed-point computing capability of the AI ​​acceleration module 9, compressing the weights and activation values ​​of the 32-bit floating-point model to 8-bit integers. Specifically, quantization-aware training is used to fine-tune the model for 3 epochs to compensate for the accuracy loss caused by quantization. The classification accuracy of the pre-trained convolutional neural network model after quantization is 97.2% on the test set, compared with 98.1% for the floating-point model, with an accuracy loss of <1%. The size of the pre-trained convolutional neural network model is compressed from 12MB to 1.2MB, adapting to the 64Mbit on-chip storage space, occupying 20%.

[0033] The deployment and inference on AI acceleration module 9 specifically involve quantizing the pre-trained convolutional neural network model and converting it into an instruction stream, which is then stored in the local instruction memory of AI acceleration module 9. The inference process includes:

[0034] a1. ARM uses memory mapping to write the feature vectors output by the FPGA to a specified address in shared memory.

[0035] a2. AI acceleration module 9 retrieves feature vectors from shared memory via DMA, taking less than 10μs.

[0036] a3. AI acceleration module 9 executes the INT8 inference pipeline: depthwise convolution → pointwise convolution → BN+ReLU → pooling → fully connected. The computation and data loading of each layer are achieved in parallel pipeline through internal ping-pong buffers.

[0037] a4. After inference is completed, write the four confidence levels back to the register area of ​​the memory bus space.

[0038] a5. Total delay for a single inference attempt < 800 μs.

[0039] In a further embodiment of this example, the data acquisition module 3 includes: an ultra-high frequency sensing channel, an ultrasonic sensing channel, an analog conditioning circuit, a multi-channel analog-to-digital converter, and a parallel low-voltage differential signal interface; the analog conditioning circuit includes: a programmable gain amplifier and a gain feedback branch controlled by the multi-channel digital-to-analog converter.

[0040] The multi-channel analog-to-digital converter is a dual-channel or multi-channel synchronous sampling analog-to-digital converter, using the ADS5541 chip. The sampling resolution is no less than 12 bits, the sampling rate is no less than 100MSPS, and the sampling clock of each channel comes from the same clock reference, ensuring that the time of each sensor signal is strictly aligned, providing a consistent data foundation for subsequent multi-dimensional joint analysis and spatial positioning.

[0041] In a further implementation of this embodiment, the original sampling ping-pong buffer 5 includes: a first buffer area and a second buffer area. The hardware logic processing unit 7 includes: a read / write arbitration control logic component, which adopts a time-based time-sharing access or priority arbitration mechanism to ensure data consistency within the same physical storage block. The read / write arbitration control logic component obtains request inputs from the first buffer area and the second buffer area. The request inputs include a full flag, a read empty flag, and an access request priority. It alternately writes to the digital signal stream and reads data from the first buffer area or the second buffer area when it is full.

[0042] In a further implementation of this embodiment, the hardware logic processing unit 7 is provided with a pre-trigger cache mode and a post-trigger cache mode. Specifically, the pulse detection result trigger condition is set, the pre-trigger preset sampling point and the post-trigger preset sampling point are associated with the same event window, and the window index of the event window is written into the feature data register 6 area.

[0043] In a further implementation of this embodiment, the hardware logic processing unit 7 includes: a digital filtering module, a fast Fourier transform acceleration module, a pulse detection logic module, a peak hold module, a pulse width statistics module, and a synchronous phase counter module; the synchronous hardware counter module acquires an external power frequency period reference signal, performs synchronous auto-incrementing counting processing, and latches and outputs the pulse power frequency phase information at the instant the pulse trigger signal is received, accurately recording the phase angle from 0 to 360 degrees, providing high-quality key feature data for generating a phase-resolved spectrum.

[0044] The triggering conditions of the pulse detection logic module include one or more combinations of programmable amplitude threshold, pulse width threshold, rising edge slope threshold, and frequency band energy threshold. The pulse detection logic module acquires the digital signal stream, performs comparison and judgment processing based on the programmable threshold, and outputs a pulse trigger signal when the signal amplitude exceeds the programmable threshold. The pulse detection logic module achieves real-time pulse capture with a 5ns timestamp accuracy through hardware parallel logic, ensuring 100% capture of random discharge pulses without omission.

[0045] In a further implementation of this embodiment, the AI ​​acceleration module 9 is equipped with an online threshold adaptive processing component. The online threshold adaptive processing component extracts background noise statistics based on the historical pulse feature library and inputs dynamic threshold parameters to the pulse detection logic module of the FPGA processing module 4.

[0046] The online threshold adaptive processing unit performs environmental background noise feature extraction based on a historical pulse feature library, outputting dynamic threshold parameters to the pulse detection logic module. This intelligently distinguishes between genuine fault pulses and random electromagnetic interference in the field, reducing the false alarm rate of fault detection to 0.3%.

[0047] In a further implementation of this embodiment, the AI ​​acceleration module 9 is a low-precision fixed-point arithmetic microarchitecture, including: a deep convolution hardware unit, a pointwise convolution hardware unit, a normalization and activation hardware unit, a pooling hardware unit, and a local instruction memory; the deep convolution hardware unit and the pointwise convolution hardware unit perform feature loading, convolution calculation, and result writing back through a double buffering method.

[0048] The AI ​​acceleration module 9 acquires feature vectors and converts them into INT8 low-precision data format, outputting feature data. Then, it performs spatial feature extraction processing through a deep convolution hardware unit, and outputs it to a pointwise convolution hardware unit to perform channel fusion processing, which greatly reduces the computational complexity and number of parameters of the model. Finally, it is input to the normalization and activation unit for tight coupling processing, avoiding frequent transfer of intermediate results between on-chip storage levels, reducing inference latency and system power consumption, and outputting classification confidence.

[0049] The AI ​​acceleration module 9 and the ARM processing module 8 directly read the weight parameters and probability node parameters through the storage bus space, avoiding the increase in printed circuit board area, interface power consumption, and signal integrity challenges caused by the introduction of off-chip memory.

[0050] In a further implementation of this embodiment, the probabilistic fusion model is a Bayesian network model running on an ARM Cortex-A processor, performing multi-sensor decision-level fusion to improve diagnostic reliability and positioning accuracy. The Bayesian network model includes evidence nodes, hidden nodes, and output nodes. The evidence nodes include: UHF channel classification confidence, ultrasonic channel classification confidence, pulse power frequency phase, pulse repetition rate, and multi-channel arrival time difference. The hidden nodes include: true fault type and fault location coordinates. The output nodes include: discharge type node and location node.

[0051] The prior knowledge of the Bayesian network model references the phase distribution characteristics of typical discharge modes in GB / T 7354-2018 "Partial Discharge Measurement". The experimental data comes from various discharge simulations in the laboratory environment. The confidence distribution of UHF and AE channels and the correlation probability with the fault type are statistically analyzed. Then, experts in the field of partial discharge detection fine-tune the conditional probabilities to form a conditional probability table. All probability tables are stored in sparse matrix form, with a total data volume of about 12KB, which is much smaller than the on-chip storage capacity.

[0052] The Bayesian network model uses the cluster tree propagation algorithm for accurate inference. Its time complexity is linear with respect to the number of nodes, making it suitable for the limited computing power of the ARM Cortex-A. The specific execution steps are as follows:

[0053] b1. The ARM processing module 8 reads the confidence vectors of the UHF sensor 1 and the ultrasonic sensor 2 channels from the storage bus space;

[0054] b2. Input the confidence level as evidence into the evidence nodes of the Bayesian network model;

[0055] b3. Run the clique tree propagation algorithm to calculate the posterior probability distribution of the Fault Type node;

[0056] b4. If the maximum posterior probability exceeds a preset threshold (0.85), output the corresponding fault type; otherwise, output "Unable to determine" and trigger data upload to the host computer for manual review.

[0057] b5. For location estimation, the mean value is taken as the positioning result based on the posterior probability distribution of the Location_X node.

[0058] According to actual performance tests, the time for a single inference is about 1.2ms, and the average positioning accuracy error after fusion is 22cm, of which the single channel of UHF sensor 1 is 45cm and the single channel of ultrasonic sensor 2 is 68cm. The false alarm rate after fusion is reduced to 0.3%, of which the single channel of UHF sensor 1 is 1.2% and the single channel of ultrasonic sensor 2 is 2.5%.

[0059] The FPGA processing module 4 preprocesses the original 100MSPS data stream into a 256-dimensional feature vector. Then, the AI ​​acceleration module 9 outputs the feature vector as four-class confidence scores. The multi-channel confidence scores are then fused through a Bayesian network model to output the final diagnostic result. The total closed-loop delay from ADC sampling to outputting the diagnostic conclusion is approximately 2.0ms, meeting the millisecond-level real-time diagnostic requirements.

[0060] In a further implementation of this embodiment, the ARM processing module 8 acquires the timestamp sequence and classification confidence of the multi-channel partial discharge signals, performs posterior probability network calculation processing, and weights and fuses the timestamp sequence and classification confidence. Multi-sensor data-level fusion technology is used to improve the robustness of the decision-making process, outputting partial discharge diagnosis and location results with a location accuracy of less than 30 centimeters.

[0061] A further implementation of this embodiment also includes: a battery power supply module and a dynamic power management control circuit. The dynamic power management control circuit acquires the task load information of the FPGA processing module 4, the ARM processing module 8 and the AI ​​acceleration module 9, outputs energy management instructions, and controls the maximum operating power to be less than or equal to 9.6 watts, so that the overall weight of the system can be controlled at about 2.1kg, achieving a long-lasting battery life of more than 10 hours of continuous operation, meeting the needs of complex industrial mobile inspection scenarios such as outdoor and high-altitude environments.

[0062] A further embodiment of this invention includes an Ethernet communication interface 10 circuit supporting a 100 Mbps transmission rate connected to the ARM processing module 8.

[0063] The ARM processing module 8 acquires the partial discharge diagnosis and location results, and encapsulates them to generate communication data packets that support large data transmission formats based on Transmission Control Protocol and Internet Protocol.

[0064] The ARM processing module 8 performs data transmission control operations through the Ethernet communication interface 10 circuit, outputting communication data packets to the external host 11. The external host 11's return path is independent of the on-chip core data transfer path, so it does not affect the microsecond-level latency of the real-time detection and diagnosis closed loop on the device side.

[0065] Example 2

[0066] This embodiment describes the workflow of a partial discharge detection system based on an FPGA-ARM heterogeneous architecture, specifically as follows:

[0067] Step 1: The dual-channel ADC simultaneously acquires UHF and AE sensor signals at a sampling rate of 100MSPS and sends them to the FPGA processing module 4 via LVDS.

[0068] Step 2: The ping-pong buffer control module of FPGA processing module 4 alternately writes the sampled data into buffers A and B;

[0069] Step 3: When the buffer is full, the FFT IP core of FPGA processing module 4 performs frequency domain transformation on the time domain data, and then performs threshold comparison to detect pulses;

[0070] Step 4: When a pulse is detected, the feature extraction module calculates the pulse peak value, phase and timing information relative to the power frequency cycle in real time to form a feature vector. The feature vector is 8 bytes / pulse and then written to the feature register area in the shared memory.

[0071] Step 5: The ARM processing module 8 directly reads the feature vector through memory mapping and sends it to the AI ​​engine for INT8 inference to obtain the confidence score of each category.

[0072] Step 6: The ARM processing module 8 inputs the confidence scores of the UHF and AE channels into the Bayesian network and calculates the final fault type and location result based on the time difference of arrival method.

[0073] Step 7: The diagnostic results are uploaded to the host computer via Ethernet and simultaneously displayed on the local LCD.

[0074] This embodiment conducts a detection experiment on partial discharge in a 110kV GIS device, setting up a simulated discharge source with known location and type in the laboratory. The test results are as follows:

[0075] Table 1 Test Results

[0076] Test Project Measurement results in this embodiment Continuous sampling frequency 100MHz Pulse capture rate 100% Signal processing delay 7.6µs,<8µs AI engine single inference latency <1ms Whole machine diagnostic closed-loop delay <15ms False alarm rate at a background noise threshold of <50% 0.3% Fault location accuracy Average error 22cm, maximum error 35cm System power consumption 9.2W Equipment weight 2.1kg Continuous working time 10.5h Online threshold self-learning convergence time The false alarm rate reaches a stable level approximately 2 minutes after startup.

[0077] Compared with the traditional discrete FPGA+ARM detection scheme that communicates through external SDRAM, the same ADC and processor models are used, but the FPGA and ARM exchange data through external SDRAM, as shown in Table 2.

[0078] Table 2 Comparison of Scheme Data

[0079] index External SDRAM solution Shared storage solutions Data exchange delay 2ms Zero latency Maximum power consumption of the system 16.5W 9.2W False alarm rate 3.5% 0.3% Positioning accuracy >1m 22cm Continuous data acquisition integrity Occasional missing numbers 100% continuous

[0080] This embodiment demonstrates that, through deep heterogeneous collaboration between FPGA and ARM, bus bridging and shared storage, hardware-based preprocessing pipeline, and AI engine acceleration, this invention achieves 100MSPS continuous sampling, microsecond-level real-time processing, 30cm-level positioning accuracy, and an ultra-low false alarm rate of 0.3% on a portable platform with ≤9.6W power consumption and a weight of 2.1kg, demonstrating significant inventiveness and practical value.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A partial discharge detection system based on an FPGA-ARM heterogeneous architecture, characterized in that, include: The system includes a data acquisition module, an FPGA processing module, an ARM processing module, and an AI acceleration module. The data acquisition module synchronously acquires partial discharge sensing signals, connects to the FPGA processing module, and outputs a digital signal stream. The ARM processing module is provided with a storage bus space for connecting to the FPGA processing module; The FPGA processing module includes: on-chip memory, hardware logic processing unit and bus slave interface, wherein the on-chip memory is directly mapped to the ARM processing module through the bus slave interface; The on-chip memory is provided with an original sampling ping-pong buffer, a feature data register area, a configuration status register area, and a diagnostic algorithm working area; the hardware logic processing unit obtains the digital signal stream input to the original sampling ping-pong buffer, performs data processing on the digital signal stream, and extracts feature vectors to the feature data register area; The AI ​​acceleration module acquires the feature vector, outputs the classification confidence of the partial discharge type based on the pre-trained convolutional neural network, and inputs it into the ARM processing module. The ARM processing module outputs the partial discharge type and localization result based on the probabilistic fusion model.

2. The partial discharge detection system based on FPGA-ARM heterogeneous architecture according to claim 1, characterized in that, The data acquisition module includes: an ultra-high frequency sensing channel, an ultrasonic sensing channel, an analog conditioning circuit, a multi-channel analog-to-digital converter, and a parallel low-voltage differential signal interface; the analog conditioning circuit includes: a programmable gain amplifier and a gain feedback branch.

3. The partial discharge detection system based on FPGA-ARM heterogeneous architecture according to claim 1, characterized in that, The original sampling ping-pong buffer includes a first buffer area and a second buffer area. The hardware logic processing unit includes a read / write arbitration control logic component. The read / write arbitration control logic component obtains request inputs from the first buffer area and the second buffer area, alternately writes to the digital signal stream, and reads data from the first buffer area or the second buffer area when it is full.

4. The partial discharge detection system based on FPGA-ARM heterogeneous architecture according to claim 1, characterized in that, The hardware logic processing unit is configured with a pre-trigger cache mode and a post-trigger cache mode. Specifically, it sets the trigger condition for the pulse detection result, associates the pre-trigger preset sampling point and the post-trigger preset sampling point with the same event window, and writes the window index of the event window into the feature data register area.

5. The partial discharge detection system based on FPGA-ARM heterogeneous architecture according to claim 1, characterized in that, The hardware logic processing unit includes: a digital filtering module, a fast Fourier transform acceleration module, a pulse detection logic module, a peak hold module, a pulse width statistics module, and a synchronous phase counter module; the synchronous phase counter module acquires the phase count of the power frequency signal output and latches the phase value; The triggering conditions of the pulse detection logic module include one or more combinations of programmable amplitude threshold, pulse width threshold, rising edge slope threshold, and frequency band energy threshold.

6. The partial discharge detection system based on FPGA-ARM heterogeneous architecture according to claim 1, characterized in that, The AI ​​acceleration module is equipped with an online threshold adaptive processing component, which extracts background noise statistics based on a historical pulse feature library and inputs dynamic threshold parameters to the FPGA processing module.

7. The partial discharge detection system based on FPGA-ARM heterogeneous architecture according to claim 1, characterized in that, The AI ​​acceleration module includes: a deep convolution hardware unit, a pointwise convolution hardware unit, a normalization and activation hardware unit, a pooling hardware unit, and a local instruction memory; the deep convolution hardware unit and the pointwise convolution hardware unit perform feature loading, convolution calculation, and result writing back through a double buffering method.

8. The partial discharge detection system based on FPGA-ARM heterogeneous architecture according to claim 1, characterized in that, The probabilistic fusion model is a Bayesian network model, which includes evidence nodes, hidden nodes, and output nodes. The evidence nodes include: UHF channel classification confidence level, ultrasonic channel classification confidence level, pulse power frequency phase, pulse repetition rate, and multi-channel arrival time difference; the hidden nodes include: actual fault type and fault location coordinates; the output nodes include: discharge type node and location node.

9. The partial discharge detection system based on FPGA-ARM heterogeneous architecture according to claim 8, characterized in that, The ARM processing module acquires the arrival time difference of the multi-channel, calculates the arrival time difference of the same discharge event between different sensing channels based on the spatial arrangement parameters of each sensor, and outputs the positioning result.

10. The partial discharge detection system based on FPGA-ARM heterogeneous architecture according to claim 1, characterized in that, Also includes: The battery power supply module and the dynamic power management control circuit are included. The dynamic power management control circuit acquires the task load information of the FPGA processing module, the ARM processing module and the AI ​​acceleration module, and outputs energy management instructions.

Images