Nor flash memory chip and wear leveling control method thereof

Abstract

The application relates to a NOR Flash memory chip and a wear leveling control method thereof, and belongs to the technical field of semiconductor memories. The chip comprises an address information register, a control logic unit and a plurality of dies; each die comprises an independent nonvolatile OSEG register, a volatile OSEG online register, an offset decoding circuit and a storage array. The chip is provided with three-level independent address cycle mapping rules at the sector level, the segment level and the die level, local area accurate wear leveling can be realized through sector offset and segment offset, the whole chip can be uniformly controlled through die-level offset, over-aging of a single storage block is completely avoided, and the overall service life of a large-capacity NOR Flash chip is effectively prolonged; and the OSEG register group is adopted to double-store and back up the three-level offsets, so that long-term stable and safe operation of the chip can be guaranteed.

Description

Technical Field

[0001] This application relates to the field of semiconductor storage technology, and in particular to a NOR Flash memory chip and a wear leveling control method thereof. Background Technology

[0002] The NOR Flash (non-volatile flash memory) chip market is currently accelerating its upgrade from medium-capacity 64Mb-256Mb to large-capacity 512Mb-2Gb. In high-capacity application scenarios, core data such as device program startup code, system configuration files, and runtime logs are mostly stored in the low address range of the memory, causing the front sectors of the chip to bear the vast majority of erase and write operations for a long time. Under this situation, uneven wear of memory blocks is very likely to occur: low address sectors age and fail prematurely due to high-frequency erase and write, which leads to the scrapping of the entire chip, while a large amount of storage resources in the high address range are idle for a long time and cannot be fully utilized, which significantly reduces the overall lifespan and space utilization of NOR Flash.

[0003] Existing technologies mostly employ software-level wear leveling strategies, primarily relying on dynamic address mapping in file systems and FTL (Flash Translation Layer) technology to achieve wear leveling compensation. However, these software solutions have significant drawbacks: First, the continuous maintenance of the logical address to physical address mapping table requires scarce system RAM (Random Access Memory) resources; second, frequent garbage collection and data migration operations can easily introduce write latency and cause system performance fluctuations; third, the complex software algorithm process further increases the probability of data corruption in abnormal power outage scenarios. Summary of the Invention

[0004] Based on this, it is necessary to address the aforementioned technical issues by providing a hardware-level NOR Flash memory chip and its wear leveling control method that starts from the chip's underlying logic, does not rely on complex calculations in upper-level software, and does not occupy system RAM. This method is particularly suitable for applications of large-capacity (e.g., 512Mb-2Gb and above) NOR Flash in the fields of IoT, automotive electronics, and industrial control.

[0005] A NOR Flash memory chip includes: an address information register, a control logic unit, and multiple dies; wherein each die contains an independent OSEG register group, an offset decoding circuit, and a memory array, and the OSEG register group includes a non-volatile OSEG register and a volatile OSEG in-line register; The address information register is used to temporarily store multi-level logical addresses in the host instructions received by the chip. The addresses are sorted from low to high as follows: sector-level logical addresses within segments, segment-level logical addresses within dies, and die-level logical addresses within the chip. The control logic unit is used to parse the target die number or all die numbers in the logical address, and configure the multi-level offset stored in the OSEG register group of the target die or all dies according to the instruction type and configuration mode; the multi-level offset controls the sector offset of sector-level address circular mapping, controls the segment offset of segment-level address circular mapping, and controls the die offset of die-level address circular mapping. The offset decoding circuit within each die is connected to the address information register and the corresponding OSEG register group within the die. The offset decoding circuit is configured to perform three-level address cyclic mapping operations: sector-level, segment-level, and die-level. It sums and moduloes the sector-level logical address, segment-level logical address, and die-level logical address with the offsets of the corresponding levels in the OSEG register group, thereby mapping each level of logical address to the actual physical address corresponding to the read, write, and erase operations of the memory array within the die, achieving global balancing and dynamic transfer of wear hotspots within the chip.

[0006] In one embodiment, the control logic unit is configured as follows: When the received instruction configuration mode is manual mode and the instruction type is write OSEG instruction, the new offset is synchronously written to the non-volatile OSEG register and the volatile OSEG online register of the target die, and the new offset configuration takes effect immediately after the writing is completed. When the received instruction configuration mode is manual mode and the instruction type is read OSEG instruction, read the offset stored in the volatile OSEG inline register of the target die; When the received instruction configuration mode is automatic mode and the instruction type is Die erase instruction, after the target Die is erased, the sector offset and segment offset in the non-volatile OSEG register and the volatile OSEG online register of the target Die are updated synchronously. When the received instruction is configured in automatic mode and the instruction type is a chip erase instruction, after the full chip erasure (i.e., all dies) is executed, the die offset in the non-volatile OSEG register and the volatile OSEG online register of all dies is updated synchronously.

[0007] In one embodiment, after erasing the target die, the sector offset and segment offset in the non-volatile OSEG register and the volatile OSEG inline register of the target die are updated as follows: Simultaneously, increase the sector offset and segment offset in both the non-volatile OSEG register and the volatile OSEG inline register of the target die by one step.

[0008] In one embodiment, after erasing the entire chip, i.e., all dies, the die offsets in the non-volatile OSEG registers and volatile OSEG inline registers of all dies are updated as follows: Synchronously increment the Die offset in both the non-volatile OSEG registers and the volatile OSEG inline registers of all Dies by one step.

[0009] In one embodiment, the step size is 1, and a modulo operation loop is used, with the modulo being the total number of dies in the chip, the total number of segments in each die, and the total number of sectors in each segment.

[0010] In one embodiment, the non-volatile OSEG register and the volatile OSEG online register in each die are both 16 bits, where the bit field OSEG[7:0] is the sector offset, the bit field OSEG[9:8] is the segment offset, the bit field OSEG[13:11] is the die offset, and the bit field OSEG

[15] is the auto-enable bit.

[0011] In one embodiment, the three-level address circular mapping operation performed by the offset decoding circuitry within each die includes: Sector-level address circular mapping: Physical sector address = (sector-level logical address + OSEG[7:0]) mod the total number of sectors in each segment; where mod represents the modulo operation; Segment-level address circular mapping: physical segment address = (segment-level logical address + OSEG[9:8]) mod the total number of segments in each die; Die-level address cyclic mapping: Physical Die address = (Die-level logical address + OSEG[13:11]) mod total number of dies in the chip.

[0012] In one embodiment, when the chip is powered on and reset, the multi-level offsets stored in the non-volatile OSEG registers in each die are automatically loaded into the volatile OSEG online registers in the same die, and the volatile OSEG online registers are not affected by the chip reset.

[0013] In one embodiment, addressing within the address information register has a loopback characteristic, meaning it automatically wraps around when the logical address exceeds the highest address.

[0014] The wear leveling control method for a NOR Flash memory chip described above includes: The address information register temporarily stores the logical address in the host instruction received by the chip; The control logic unit parses the target die number or all die numbers in the logical address and configures the offset stored in the OSEG register group of the target die or all dies according to the instruction type and configuration mode. Based on the logical address stored in the address information register and the corresponding level offset stored in the OSEG register group, the offset decoding circuit in the target die or all dies performs summation and modulo operation to complete the address cyclic mapping operation of the corresponding level. This maps the logical address to the real physical address corresponding to the read, write and erase operations of the memory array in the die, realizing the global balancing and dynamic transfer of wear hotspots inside the chip.

[0015] The aforementioned NOR Flash memory chip and its wear leveling control method have the following advantages compared to existing technologies: 1. The chip innovatively sets up three independent address cycle mapping rules at the sector level, segment level, and die level, which strictly conform to the memory architecture of sectors nested in segments and segments nested in dies. The three levels of offset realize the rotation of the smallest unit of the sector, the rotation of large blocks of segments, and the overall rotation of the entire die, forming a fully covered multi-level wear leveling system. Precise wear leveling of local areas can be achieved through sector offset and segment offset, and the entire chip can be uniformly managed through die-level offset. It is suitable for complex memory structures with multiple chip units and multiple partitions, with high degree of control and wide applicability.

[0016] 2. The entire process of address mapping and wear leveling is implemented in pure hardware, which has the advantages of zero host resource overhead and no performance jitter. It is completely transparent to the upper-layer software and does not require software to participate in data migration and address calculation. When performing wear leveling, it is only necessary to update the corresponding level offset parameters through instructions. The summation and modulo operation of logical address and offset are completed by pure combinational logic. There is no table lookup delay and the response speed is fast. It can dynamically rotate physical storage blocks in real time, evenly distribute wear hotspots generated by high-frequency operations, completely avoid excessive aging of a single storage block, effectively extend the overall service life of large-capacity NOR Flash chips, and ensure the stable operation of the storage system throughout the process.

[0017] 3. The OSEG register group is used to perform dual storage backup of the three-level offset. Configuration updates can be written to both channels simultaneously and take effect immediately without reset. It also has atomic configuration update characteristics, eliminating the risk of data inconsistency when power is lost. It can realize the retention of offset parameters when power is lost and automatic recovery when power is restored. It completely solves problems such as address mapping disorder caused by parameter loss and synchronization failure, and failure of wear leveling strategy. It significantly improves the reliability of chip operation from the mechanism and ensures the long-term stable and safe operation of NOR Flash memory chip. Attached Figure Description

[0018] Figure 1This is a schematic diagram of the internal functional modules of a NOR Flash memory chip in one embodiment; Figure 2 This is a schematic diagram of the address mapping relationship in one embodiment (taking sector-level offset as an example); Figure 3 This is a schematic diagram of the automatic wear leveling process for the Die erase command in one embodiment; Figure 4 This is a schematic diagram of the automatic wear leveling process for chip erase instructions in one embodiment. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0020] In one embodiment, such as Figure 1 As shown, a NOR Flash memory chip is provided, including: an address information register, a control logic unit, and multiple dies; wherein each die contains an independent OSEG (Offset Configuration Register) register group, offset decoding circuitry, and memory array, and the OSEG register group includes non-volatile OSEG registers and volatile OSEG in-circuit registers. The chip receives host instructions through a host interface or an I / O (input / output) controller.

[0021] The address information register is used to temporarily store multi-level logical addresses in the host instructions received by the chip. These addresses are ordered from low to high as follows: sector-level logical addresses within segments, segment-level logical addresses within dies, and die-level logical addresses within the chip. It can also store addresses within bytes. The control logic unit is used to parse the target die number or all die numbers in the logical address using an internal instruction decoder. Based on the instruction type and configuration mode, it configures the multi-level offsets stored in the OSEG register group of the target die or all dies. These multi-level offsets control the sector offsets in the cyclic mapping of sector-level addresses and control the segment... The system includes segment offsets for level-1 address cyclic mapping and die offsets for controlling die-level address cyclic mapping. The offset decoding circuit within each die is connected to the address information register and the corresponding OSEG register set within the die. The offset decoding circuit is configured to perform three-level address cyclic mapping operations: sector-level, segment-level, and die-level. It sums and modulo-calculates the sector-level logical address, segment-level logical address, and die-level logical address with the offsets of the corresponding levels in the OSEG register set, thereby mapping each level of logical address to the actual physical address corresponding to the read, write, and erase operations of the die's internal memory array. This achieves global balancing and dynamic transfer of wear hotspots within the chip.

[0022] The above-mentioned NOR This Flash memory chip features an innovative three-level independent address rotation mapping system: sector-level, segment-level, and die-level. This system strictly adheres to storage architectures where sectors are nested within segments and segments within dies. Through sector-level rotation, segment-level rotation, and die-level rotation, it constructs a comprehensive, multi-layered wear leveling system. This system can achieve precise wear leveling in localized areas using sector and segment offsets, and can also manage the entire chip uniformly through die-level offsets. It is well-suited for complex storage structures with multiple chip units and partitions, offering high flexibility and wide applicability. Furthermore, address mapping and wear leveling are implemented purely in hardware, completely transparent to upper-layer software. No software involvement in data movement or address calculation is required, resulting in zero host resource overhead and no performance jitter. Simply updating the corresponding level offset parameters via instructions allows for rapid addition and modulo operations of logical addresses and offsets using pure combinational logic, eliminating lookup latency. This enables real-time dynamic rotation of physical storage blocks, evenly distributing wear hotspots generated by high-frequency operations, preventing excessive aging of single storage blocks, and effectively extending the lifespan of large-capacity NOR flash memory. The overall lifespan of the Flash chip is ensured, continuously guaranteeing stable system performance. Simultaneously, dual storage backup of the three-level offset is achieved through the OSEG register group. Configuration can be written synchronously to both channels, taking effect instantly without reset, and configuration updates are atomic, eliminating the risk of data inconsistency during power outages. It enables power-off saving of offset parameters and automatic recovery upon power-on, completely resolving issues such as address mapping disorder and wear leveling strategy failure caused by parameter loss and synchronization anomalies. This fundamentally improves chip reliability, ensuring the long-term safe and stable operation of the NOR Flash memory chip.

[0023] In one embodiment, such as Figure 1 As shown, the control logic unit also includes a manual wear leveling controller and an automatic wear leveling controller.

[0024] The manual wear leveling controller is configured to: when the received instruction configuration mode is manual and the instruction type is a write OSEG instruction (11h), synchronously write the new offset into the non-volatile OSEG register and the volatile OSEG online register of the target die, and the new offset configuration takes effect immediately after the write is completed; when the received instruction configuration mode is manual and the instruction type is a read OSEG instruction (15h), read the offset stored in the volatile OSEG online register of the target die; The automatic wear leveling controller is configured to: when the received instruction configuration mode is automatic and the instruction type is a die erase instruction, after executing the erase of the target die, synchronously update the sector offset and segment offset in the non-volatile OSEG register and the volatile OSEG online register of the target die; when the received instruction configuration mode is automatic and the instruction type is a chip erase instruction, after executing the erase of the entire chip, i.e., all dies, synchronously update the die offset in the non-volatile OSEG register and the volatile OSEG online register of all dies.

[0025] It should be understood that in automatic mode, the offset is automatically updated after each erase operation of the target die or all dies. This ensures that when subsequent read and write instructions use a fixed logical address, the data will be automatically written to the next physical storage block, and will not be repeatedly written to the area that was just erased, thus completely eliminating the problems of data corruption and accidental overwriting.

[0026] In one embodiment, after erasing the target die, the sector offset and segment offset in the non-volatile OSEG register and the volatile OSEG inline register of the target die are updated as follows: Simultaneously, increase the sector offset and segment offset in both the non-volatile OSEG register and the volatile OSEG inline register of the target die by one step.

[0027] In one embodiment, after erasing the entire chip, i.e., all dies, the die offsets in the non-volatile OSEG registers and volatile OSEG inline registers of all dies are updated as follows: Synchronously increment the Die offset in both the non-volatile OSEG registers and the volatile OSEG inline registers of all Dies by one step.

[0028] In one embodiment, the step size is 1, and a modulo operation loop is used, with the modulo being the total number of dies in the chip, the total number of segments in each die, and the total number of sectors in each segment.

[0029] In one embodiment, the non-volatile OSEG register and the volatile OSEG online register in each die are both 16 bits, where the bit field OSEG[7:0] is the sector offset, the bit field OSEG[9:8] is the segment offset, the bit field OSEG[13:11] is the die offset, and the bit field OSEG

[15] is the auto-enable bit.

[0030] In one embodiment, the three-level address circular mapping operation performed by the offset decoding circuitry within each die includes: Sector-level address circular mapping: Physical sector address = (sector-level logical address + OSEG[7:0]) mod the total number of sectors in each segment; where mod represents the modulo operation; Segment-level address circular mapping: physical segment address = (segment-level logical address + OSEG[9:8]) mod the total number of segments in each die; Die-level address cyclic mapping: Physical Die address = (Die-level logical address + OSEG[13:11]) mod total number of dies in the chip.

[0031] It should be understood that by setting three levels of independent address cyclic mapping rules—die-level, segment-level, and sector-level—fine-grained address control across all levels can be achieved. Specifically, sector-level offsets correspond to address rotation of the smallest storage unit within a segment, segment-level offsets correspond to address rotation of large regions within a die, and die-level offsets achieve overall address rotation of all storage units across the entire chip. These three levels strictly adhere to the physical storage architecture of sectors nested within segments, and segments nested within dies. Based on this three-level independent offset system, this application can individually control local storage areas through sector and segment-level offsets to achieve precise wear leveling in local areas, and can also uniformly control the address mapping strategy of the entire chip through die-level offsets. This allows for perfect adaptation to complex storage hardware architectures with multiple dies and partitions, offering wider applicability and greater controllability.

[0032] In one embodiment, when the chip is powered on and reset, the multi-level offsets stored in the non-volatile OSEG registers in each die are automatically loaded into the volatile OSEG online registers in the same die, and the volatile OSEG online registers are not affected by the chip reset.

[0033] In one embodiment, addressing within the address information register has a loopback characteristic, meaning it automatically wraps around when the logical address exceeds the highest address.

[0034] In a specific embodiment, a specific implementation of a NOR Flash memory chip proposed in this application is introduced, taking a capacity of 4Gb and including 8 dies (each die is 512Mb) as an example. Each die is divided into 4 segments (128Mb), each segment is divided into 256 sectors (64KB), and the non-volatile OSEG register and volatile OSEG online register in each die are both 16 bits. The bit field OSEG[7:0] is the sector offset, the bit field OSEG[9:8] is the segment offset, the bit field OSEG[13:11] is the die offset, and the bit field OSEG

[15] is the auto-enable bit.

[0035] In this embodiment, the chip performs three-level address circular mapping operations at the sector level, segment level, and die level as follows: Sector-level address circular mapping: physical sector address = (sector-level logical address + OSEG[7:0]) mod 256; where mod represents modulo operation; Figure 2 It shows the address mapping relationship of sector-level offsets; Segmented address circular mapping: physical segment address = (segmented logical address + OSEG[9:8]) mod 4; Die-level address circular mapping: physical die address = (die-level logical address + OSEG[13:11]) mod 8.

[0036] In this embodiment, the control logic unit is configured as follows: Manual Instruction Mode: The host sends instruction 11h + Die0 address + data 0x0101 (Segment offset + 1, Sector offset + 1). The control logic unit simultaneously writes 0x0101 to both the non-volatile OSEG register and the volatile OSEG in-circuit register of Die0. Immediately afterwards, the host sends a page programming instruction to write to logical address 0x000000. The offset decoding circuit uses the updated volatile OSEG in-circuit register to correctly write the data to the physical address Sector1. This eliminates the risk of data corruption caused by writing to physical Sector0 due to an outdated volatile OSEG in-circuit register.

[0037] Automatic command mode (OSEG

[15] =0) — Die erase command: such as Figure 3 As shown, the host sends a Die erase command to Die0. After Die completes the erase, it automatically increments both the segment-level offset and the sector-level offset of Die0 by 1, and simultaneously updates the non-volatile OSEG register and the volatile OSEG inline register of Die0. Subsequent accesses to logical Sector0 will be mapped to the new physical Sector. This automatic command mode ensures that Die.OSEG is empty before the flush, eliminating the risk of data corruption.

[0038] Automatic instruction mode—chip erase instruction: such as Figure 4 As shown, the host sends a chip erase command. After erasing all dies, the chip offset value of all dies is incremented by 1 (mod 8), and the non-volatile OSEG register and volatile OSEG online register of all dies are updated simultaneously. Afterwards, logical Die0 is mapped to physical Die1, achieving die-level balancing. This automatic mode ensures that there is no data in any die before the OSEG is refreshed, eliminating the risk of data corruption.

[0039] In one embodiment, a wear leveling control method for a NOR Flash memory chip is provided, the method comprising: The address information register temporarily stores the logical address in the host instruction received by the chip; The control logic unit parses the target die number or all die numbers in the logical address and configures the offset stored in the OSEG register group of the target die or all dies according to the instruction type and configuration mode. Based on the logical address stored in the address information register and the corresponding level offset stored in the OSEG register group, the offset decoding circuit in the target die or all dies performs summation and modulo operation to complete the address cyclic mapping operation of the corresponding level. This maps the logical address to the real physical address corresponding to the read, write and erase operations of the memory array in the die, realizing the global balancing and dynamic transfer of wear hotspots inside the chip.

[0040] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0041] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application.

Claims

1. A NOR Flash memory chip, characterized in that, It includes an address information register, a control logic unit, and multiple dies; each die contains an independent OSEG register group, offset decoding circuitry, and memory array, wherein the OSEG register group includes a non-volatile OSEG register and a volatile OSEG in-line register; wherein OSEG is an offset configuration register; The address information register is used to temporarily store multi-level logical addresses in the host instructions received by the chip, which are sorted from low to high according to the address level as sector-level logical addresses within segments, segment-level logical addresses within dies, and die-level logical addresses within the chip. The control logic unit is used to parse the target die number or all die numbers in the logical address, and configure the multi-level offset stored in the OSEG register group of the target die or all dies according to the instruction type and configuration mode; the multi-level offset controls the sector offset of the sector-level address circular mapping, controls the segment offset of the segment-level address circular mapping, and controls the die offset of the die-level address circular mapping. The offset decoding circuit within each die is connected to the address information register and the corresponding OSEG register group within the die. The offset decoding circuit is configured to perform three-level address cyclic mapping operations at the sector level, segment level, and die level. It sums and moduloes the sector-level logical address, segment-level logical address, and die-level logical address with the offsets of the corresponding levels in the OSEG register group, thereby mapping each level of logical address to the real physical address corresponding to the read, write, and erase operations of the memory array within the die, realizing the global balancing and dynamic transfer of wear hotspots inside the chip. The control logic unit is configured as follows: When the received instruction configuration mode is manual mode and the instruction type is write OSEG instruction, the new offset is synchronously written to the non-volatile OSEG register and the volatile OSEG online register of the target die, and the new offset configuration takes effect immediately after the writing is completed. When the received instruction configuration mode is manual mode and the instruction type is read OSEG instruction, read the offset stored in the volatile OSEG inline register of the target die; When the received instruction configuration mode is automatic mode and the instruction type is Die erase instruction, after the target Die is erased, the sector offset and segment offset in the non-volatile OSEG register and the volatile OSEG online register of the target Die are updated synchronously. When the received instruction is configured in automatic mode and the instruction type is a chip erase instruction, after the full chip erasure (i.e., all dies) is executed, the die offset in the non-volatile OSEG register and the volatile OSEG online register of all dies is updated synchronously.

2. A NOR Flash memory chip according to claim 1, characterized in that, After erasing the target die, the sector offsets and segment offsets in the non-volatile OSEG register and the volatile OSEG inline register of the target die are updated as follows: Simultaneously, increase the sector offset and segment offset in both the non-volatile OSEG register and the volatile OSEG inline register of the target die by one step.

3. A NOR Flash memory chip according to claim 1, characterized in that, After erasing the entire chip (i.e., all dies), the die offsets in the non-volatile OSEG register and the volatile OSEG inline register of all dies are updated as follows: Synchronously increment the Die offset in both the non-volatile OSEG registers and the volatile OSEG inline registers of all Dies by one step.

4. A NOR Flash memory chip according to claim 2 or 3, characterized in that, The step size is 1, and a modulo operation loop is used, with the modulo being the total number of dies in the chip, the total number of segments in each die, and the total number of sectors in each segment.

5. A NOR Flash memory chip according to claim 1, characterized in that, The non-volatile OSEG register and the volatile OSEG online register in each die are both 16 bits, where the bit field OSEG[7:0] is the sector offset, the bit field OSEG[9:8] is the segment offset, the bit field OSEG[13:11] is the die offset, and the bit field OSEG[15] is the auto-enable bit.

6. A NOR Flash memory chip according to claim 5, characterized in that, The three-level address circular mapping operation rules performed by the offset decoding circuit within each die include: Sector-level address circular mapping: Physical sector address = (sector-level logical address + OSEG[7:0]) mod the total number of sectors in each segment; where mod represents the modulo operation; Segment-level address circular mapping: physical segment address = (segment-level logical address + OSEG[9:8]) mod the total number of segments in each die; Die-level address cyclic mapping: Physical Die address = (Die-level logical address + OSEG[13:11]) mod total number of dies in the chip.

7. A NOR Flash memory chip according to claim 1, characterized in that, When the chip is powered on and reset, the multi-level offsets stored in the non-volatile OSEG registers in each die are automatically loaded into the volatile OSEG online registers in the same die. The volatile OSEG online registers are not affected by the chip reset.

8. A NOR Flash memory chip according to claim 1, characterized in that, The addressing in the address information register has a loopback characteristic, that is, it automatically loops back when the logical address exceeds the highest address.

9. A wear leveling control method applied to a NOR Flash memory chip according to any one of claims 1 to 8, characterized in that, The method includes: The address information register temporarily stores the logical address in the host instruction received by the chip; The control logic unit parses the target die number or all die numbers in the logical address and configures the offset stored in the OSEG register group of the target die or all dies according to the instruction type and configuration mode; where OSEG is the offset configuration register. Based on the logical address stored in the address information register and the offset of the corresponding level stored in the OSEG register group, the offset decoding circuit in the target die or all dies performs summation and modulo operation to complete the address cyclic mapping operation of the corresponding level, mapping the logical address to the real physical address corresponding to the read, write and erase operation of the memory array in the die, realizing the global balancing and dynamic transfer of wear hotspots inside the chip. The control logic unit is configured as follows: When the received instruction configuration mode is manual mode and the instruction type is write OSEG instruction, the new offset is synchronously written to the non-volatile OSEG register and the volatile OSEG online register of the target die, and the new offset configuration takes effect immediately after the writing is completed. When the received instruction configuration mode is manual mode and the instruction type is read OSEG instruction, read the offset stored in the volatile OSEG inline register of the target die; When the received instruction configuration mode is automatic mode and the instruction type is Die erase instruction, after the target Die is erased, the sector offset and segment offset in the non-volatile OSEG register and the volatile OSEG online register of the target Die are updated synchronously. When the received instruction is configured in automatic mode and the instruction type is a chip erase instruction, after the full chip erasure (i.e., all dies) is executed, the die offset in the non-volatile OSEG register and the volatile OSEG online register of all dies is updated synchronously.

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