Inverted red VCSEL epitaxial structure and preparation method thereof

Abstract

The present application relates to the field of optoelectronic technology, and in particular to a flip red VCSEL epitaxial structure and a preparation method thereof. The flip red VCSEL epitaxial structure provided by the present application comprises, from bottom to top, an upper mirror layer and a laminated structure. The upper mirror layer comprises, from bottom to top, a lower electrical injection area, a silicon wafer and a metal mirror layer. The laminated structure comprises, from bottom to top, a P-type ohmic contact layer, a P-type confinement layer, an active layer, an N-type confinement layer, an N-type DBR layer and an N-type ohmic contact layer. The N-type ohmic contact layer is provided with an upper electrical injection area on the side away from the N-type DBR layer. The present application uses an upper mirror layer to replace a conventional upper DBR, and realizes a flip structure for light emission from the N-type DBR layer through substrate replacement. The epitaxial growth time is greatly shortened, the production cost is reduced, the device series resistance is significantly reduced, the optical loss is reduced, and the output power and the electro-optical conversion efficiency of the red VCSEL device are effectively improved.

Description

Technical Field

[0001] This invention relates to the field of optoelectronics technology, specifically to a flip-chip red VCSEL epitaxial structure and its fabrication method. Background Technology

[0002] Vertical-cavity surface-emitting lasers (VCSELs) are widely used in optical communication, optical interconnection, sensing and detection, laser display, and medical aesthetics due to their advantages such as high beam quality, low threshold current, ease of two-dimensional integration, and circular symmetry of the emitted beam. Red-light VCSELs with emission wavelengths around 650nm are particularly valuable in plastic fiber communication, laser pointing, biomedical diagnostics, and RGB full-color displays because they fall within the wavelength range most sensitive to the human eye and match the low-loss window of plastic optical fibers.

[0003] A typical VCSEL structure includes an upper distributed Bragg reflector (DBR), a lower DBR, and an active region sandwiched between them. The DBR is composed of multiple layers of semiconductor materials with alternating high and low refractive indices, achieving high reflectivity through Bragg reflection at specific wavelengths. In the fabrication of traditional red VCSELs, the lower DBR is typically grown epitaxially, using semiconductor material systems (such as AlGaInP / AlGaAs or AlGaAs / AlAs) to alternately grow dozens or even hundreds of periodic pairs to obtain the required high reflectivity (usually >99.5%), ensuring the optical performance of the resonant cavity and the laser output effect.

[0004] However, existing VCSEL structures have the following problems: First, the epitaxial growth stage requires the fabrication of dozens or even hundreds of pairs of periodically high-reflectivity semiconductor DBRs, with a total growth thickness reaching 10 μm, which greatly prolongs the growth time, reduces equipment capacity, and keeps material and process costs high; Second, the discontinuity of the conduction band and valence band at the interface between adjacent heterojunctions of the semiconductor DBR forms a high heterojunction barrier, resulting in high vertical carrier transport resistance, leading to high device series resistance and significant Joule heat loss. This not only reduces the electro-optical conversion efficiency of the device but also exacerbates the red light active... The temperature rise in regions (such as InAlGaP quantum wells) severely reduces the internal quantum efficiency, causing rapid degradation of device performance. Third, residual defects and interlayer roughness in DBR materials easily lead to light absorption and scattering losses, increasing the optical loss of the resonant cavity and weakening the output power and slope efficiency of the device. In addition, for the 650nm red light band, the refractive index difference of existing semiconductor materials is limited, and high-period-number DBRs are difficult to achieve near 100% extreme total internal reflection. The optical field confinement capability of the resonant cavity is insufficient, making it difficult to meet the application requirements of high-power, high-efficiency red VCSELs. Summary of the Invention

[0005] To address the problems of long growth cycle, high heterojunction series resistance, internal residual defects, large interlayer roughness, and difficulty in achieving ideal total internal reflection in the 650nm wavelength band of existing VCSEL structures, this invention provides a flip-chip red VCSEL epitaxial structure and its fabrication method.

[0006] The technical solution of this invention is as follows: In a first aspect, the present invention provides a flip-chip red VCSEL epitaxial structure, comprising, from bottom to top, an upper reflector layer and a stacked structure. The upper reflector layer comprises, from bottom to top, a lower injection region, a silicon wafer, and a metal reflector layer. The stacked structure comprises, from bottom to top, a P-type ohmic contact layer, a P-type confinement layer, an active layer, an N-type confinement layer, an N-type DBR layer, and an N-type ohmic contact layer. An upper injection region is provided on the side of the N-type ohmic contact layer away from the N-type DBR layer.

[0007] Furthermore, in the upper reflective mirror layer, the thickness of the metal reflective mirror layer is 500~1000nm, the thickness of the silicon wafer is 200~400μm, and the thickness of the lower electric injection region is 2~2.5μm; the silicon wafer takes into account both mechanical support strength and heat dissipation efficiency.

[0008] Furthermore, the resistivity of the silicon wafer is (1~2)×10⁻⁶. -4 The metal reflective mirror layer is made of Ag and has a reflectivity of >99.9% in the 650nm red light band and an extremely wide reflection bandwidth. It also has excellent conductivity and can achieve both high reflectivity and low resistance.

[0009] Furthermore, the P-type ohmic contact layer has a second metal mirror layer deposited on the side near the upper mirror layer, forming a double mirror bonding structure, which further improves the interface reflectivity and reduces the transmission loss of light at the bonding interface; at the same time, it enhances the bonding strength between the upper mirror layer and the stacked structure, reduces the interface contact resistance, and improves the current injection efficiency.

[0010] Furthermore, the material of the second metal reflector layer is Ag; it forms a homogeneous bond with the Ag metal reflector of the upper reflector layer, ensuring the consistency and stability of reflectivity.

[0011] Furthermore, the thickness of the P-type ohmic contact layer is 30~50nm, which minimizes photon scattering and absorption loss caused by P-type doping while ensuring good ohmic contact; the thickness of the second metal mirror layer is 500~1000nm.

[0012] Furthermore, the material of the lower electrode injection region is a Ti / Au alloy, and the total thickness of the lower electrode injection region is 2~2.5μm; the Ti layer serves as an adhesion layer to improve the bonding force between the metal electrode and the silicon wafer; the Au layer serves as the main conductive layer to provide extremely low contact resistance.

[0013] Furthermore, the material of the power injection region is an Au / Ge / Ni alloy, and the thickness of each metal layer in the Au / Ge / Ni alloy is 100~500nm respectively; forming a low-resistance, stable ohmic contact, ensuring that the contact resistance is minimized, while improving the adhesion between the electrode and the N-type ohmic contact layer.

[0014] Secondly, the present invention provides a method for fabricating the above-mentioned flip-chip red VCSEL epitaxial structure, comprising the following steps: (1) Epitaxial growth: The N-type buffer layer, N-type etch stop layer, N-type ohmic contact layer, N-type DBR layer, N-type confinement layer, active layer, P-type confinement layer and P-type ohmic contact layer are sequentially epitaxially deposited on the N-type substrate using metal-organic vapor phase epitaxy process; (2) The upper reflector layer is bonded to the P-type ohmic contact layer, and then the N-type substrate, N-type buffer layer and N-type etching stop layer are removed in sequence by chemical etching. The high heat dissipation silicon wafer is bonded to the P-type side by bonding process to shorten the heat conduction path from the active area to the heat dissipation substrate. (3) Using ICP process, etching is performed to the upper reflective layer to form a mesa; (4) An insulating layer is deposited on the side wall of the mesa. The insulating layer is preferably SiO2 and the thickness of the insulating layer is 200~500nm, preferably 400nm. The deposited insulating layer can prevent leakage current from the side wall of the mesa and improve the electrical reliability of the device. (5) An electro-injection region is deposited on the N-type ohmic contact layer to obtain an epitaxial structure; (6) The epitaxial structure is cut into VCSEL chips using ICP process.

[0015] Furthermore, prior to step (2), the following operation is performed: a second metal mirror layer is deposited on the side of the P-type ohmic contact layer near the upper mirror layer by vacuum evaporation process.

[0016] The beneficial effects of this invention are as follows: 1. The flip-chip red VCSEL epitaxial structure provided by this invention uses an upper reflective layer containing a metal reflective layer to replace the traditional upper DBR, eliminating the epitaxial growth process of dozens of cycles of high-reflectivity DBR in the traditional structure, significantly shortening the epitaxial growth time, reducing equipment and material costs, and improving production efficiency; at the same time, the metal reflective layer directly participates in electrical conduction, and its excellent conductivity can significantly reduce the series resistance of the device, eliminate the voltage drop caused by the heterojunction interface barrier in the traditional upper DBR, reduce Joule heat loss, and effectively improve the electro-optical conversion efficiency of the device.

[0017] 2. In the flip-chip red VCSEL epitaxial structure provided by the present invention, the metal mirror layer has a flat reflective interface, which can reduce light scattering loss; at the same time, the metal mirror layer material, such as Ag, has near total reflection characteristics in the 650nm red light band, which significantly enhances the optical field confinement capability of the resonant cavity and improves the output power and slope efficiency of the laser.

[0018] 3. The flip-chip red VCSEL epitaxial structure provided by the present invention adopts a flip-chip structure design so that photons are emitted from the traditional lower DBR side. By utilizing the characteristic that the photon absorption cross section of N-type doped material is much lower than that of P-type doped material, the free carrier absorption loss introduced by the high concentration of doping in the upper DBR in the traditional upright structure is avoided, further reducing the optical loss of the resonant cavity and improving the optical performance of the device.

[0019] 4. The flip-chip red VCSEL epitaxial structure provided by this invention allows the silicon wafer and the active region to be directly attached through a metal mirror layer, which significantly shortens the path for heat generated in the active region to be conducted to the outside, effectively suppressing the degradation of the internal quantum efficiency of the red active material due to temperature rise; at the same time, it realizes the separation of the electrothermal path and the optical path, with Joule heat being efficiently conducted upward through the silicon wafer, and the optical signal being emitted downward from the lower DBR side, and the two transmission paths do not interfere with each other, fundamentally optimizing the thermal management capability of the device. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a cross-sectional schematic diagram of the structure obtained by epitaxial growth in step (1) of Example 1.

[0022] Figure 2 This is a cross-sectional schematic diagram of the structure of the upper reflective mirror layer in Example 1.

[0023] Figure 3 This is a cross-sectional schematic diagram of the inverted red VCSEL epitaxial structure prepared in Example 1.

[0024] Figure 4 This is a cross-sectional schematic diagram of the red VCSEL epitaxial structure prepared in proportion.

[0025] Figure 5 These are the PIV (optical power-current-voltage) test curves of the VCSEL chips prepared in Example 1 and the comparative example; where the all-black square lines are the PI (optical power-current) curve of Example 1, the blank square lines are the VI (voltage-current) curve of Example 1, the all-black circular lines are the PI curve of the comparative example, and the blank circular lines are the VI curve of the comparative example.

[0026] In the figure, 1-N-type substrate, 2-N-type buffer layer, 3-N-type etch stop layer, 4-N-type ohmic contact layer, 5-N-type DBR layer, 6-N-type confinement layer, 7-active layer, 8-P-type confinement layer, 9-P-type ohmic contact layer, 101-metal mirror layer, 102-silicon wafer, 103-lower injection region, 11-insulating layer, 12-upper injection region, 13-P-type DBR layer, 14-injection region. Detailed Implementation

[0027] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0028] The epitaxially grown structure in the following embodiments includes, along the epitaxial growth direction, an N-type substrate 1, an N-type buffer layer 2, an N-type etch stop layer 3, an N-type ohmic contact layer 4, an N-type DBR layer 5, an N-type confinement layer 6, an active layer 7, a P-type confinement layer 8, and a P-type ohmic contact layer 9.

[0029] In this process, the N-type substrate 1 is made of GaAs substrate, which is N-type doped, and is used to grow epitaxial layer structures on its surface; the N-type buffer layer 2 is made of the same material as the N-type substrate 1 with a lattice matching; the N-type etching stop layer 3 is made of a material with a significantly different etching rate than the materials of the N-type substrate 1 and the N-type DBR layer 5 to achieve selective etching, preferably a GaInP layer, which will automatically stop at the GaInP layer when the mesa is fabricated using the ICP method, thus protecting the N-type DBR layer 5 and the N-type confinement layer 6 from over-etching; the N-type ohmic contact layer 4 is a conventional metal material for achieving ohmic contact, preferably a GaAs layer; N-type DBR layer 5 is composed of Al x1 Ga 1-x1 As / Al x2 Ga 1-x2 The material is composed of As, where 0.8 ≤ x1 ≤ 1, 0.1 ≤ x2 ≤ 0.3, and the number of periods is 10 to 40 pairs. The number of periods of this N-type DBR layer 5 is adapted to the lasing wavelength of the active region to achieve photon reflection. In traditional VCSEL epitaxial structures, the reflectivity of the N-type DBR layer is required to be 97.5% to 99%, but the reflectivity of this invention is not strictly limited to this range. The reflectivity of the N-type DBR layer 5 is required to be >90%, and the doping concentration is 3 × 10⁻⁶. 17 ~2×10 18 cm -3 Preferably 7×10 17 cm -3 A wet oxidation process was used to treat the Al in the N-type DBR layer 5. x1 Ga 1-x1 The As layer is selectively oxidized to serve as a region that confines the optical field and current. The N-type confinement layer 6 is lattice-matched with GaAs (Al). x3 Ga 1-x3 ) 0.5 In 0.5 The P-layer has a thickness of 0.6 ≤ x3 ≤ 1, preferably x3 = 0.9, a thickness of 100~300 nm, preferably 150 nm, and a doping concentration of 6 × 10⁻⁶. 17 cm -3 ; Active layer 7 is composed of Ga y In 1-y P quantum well layer and (Al) x4 Ga 1-x4 ) 0.5 In 0.5 The P quantum barrier layers are arranged alternately, and the number of alternating pairs can be selected between 2 and 5, preferably 3 pairs. Among them, 0.4≤y≤0.6, the thickness is 3nm~10nm, preferably 6.5nm; 0.5≤x3≤0.75, the thickness is 3nm~15nm, preferably 8nm. The structure, thickness and number of pairs of the active layer 7 can be determined according to the lasing wavelength requirements of the VCSEL device. The active layer 7 is unintentionally doped. The p-type confinement layer 8 is lattice-matched to the GaAs substrate (Al). x5 Ga 1-x5 ) 0.5 In 0.5 The P-layer has a thickness of 0.6 ≤ x5 ≤ 1, preferably x5 = 0.9, a thickness of 100~300 nm, preferably 150 nm, and a doping concentration of 3 × 10⁻⁶. 17 cm-3 The material of the P-type ohmic contact layer 9 is an Au layer.

[0030] Example 1 A flip-chip red VCSEL epitaxial structure, such as Figure 3 As shown, from bottom to top, the structure includes an upper reflector layer and a stacked structure. The upper reflector layer includes a lower electrical injection region 103, a silicon wafer 102, and a metal reflector layer 101. In the upper reflector layer, the metal reflector layer 101 is made of a 500nm thick Ag layer, and the silicon wafer 102 has a thickness of 200μm and a resistivity of 1×10⁻⁶. -4 Ω·cm; the material of the lower electrical injection region 103 is a Ti / Au alloy, with a Ti thickness of 300nm and an Au thickness of 2μm; the stacked structure, from bottom to top, includes a P-type ohmic contact layer 9, a P-type confinement layer 8, an active layer 7, an N-type confinement layer 6, an N-type DBR layer 5, and an N-type ohmic contact layer 4; the material of the P-type ohmic contact layer 9 is a 50nm thick Au layer, and a second metal mirror layer 101 is deposited on the side of the P-type ohmic contact layer 9 near the upper mirror layer, the material of the second metal mirror layer 101 being a 500nm thick Ag layer; the P-type confinement layer 8 is a 150nm thick (Al) layer. 0.9 Ga 0.1 ) 0.5 In 0.5 P-layer, with a doping concentration of 3 × 10⁻⁶ 17 cm -3 The active layer 7 consists of three pairs of Ga... 0.5 In 0.5 P quantum well layer and (Al) 0.7 Ga 0.3 ) 0.5 In 0.5 The P quantum barrier layers are arranged alternately, with each pair containing Ga 0.5 In 0.5 The thickness of the P quantum well layer is 6.5 nm, (Al 0.7 Ga 0.3 ) 0.5 In 0.5 The thickness of the P quantum barrier layer is 8 nm; the N-type confinement layer 6 is 150 nm thick (Al). 0.9 Ga 0.1 ) 0.5 In 0.5 P-layer, with a doping concentration of 6 × 10⁻⁶ 17 cm -3 The N-type DBR layer 5 consists of 20 cycles of Al 0.91 Ga 0.09 As / Al 0.15 Ga 0.85 Composed of As material, with a doping concentration of 7×10⁻⁶.17 cm -3 The N-type ohmic contact layer 4 is a GaAs layer; the side of the N-type ohmic contact layer 4 away from the N-type DBR layer 5 is provided with an electric injection region 12, the material of the electric injection region 12 is an Au / Ge / Ni alloy, the thickness of Au is 100nm, the thickness of Ge is 200nm, and the thickness of Ni is 500nm.

[0031] The above-mentioned method for fabricating the flip-chip red VCSEL epitaxial structure includes the following steps: (1) Extensional growth: such as Figure 1 As shown, metal-organic vapor phase epitaxy is used to sequentially epitaxially deposit an N-type buffer layer 2, an N-type etch stop layer 3, an N-type ohmic contact layer 4, an N-type DBR layer 5, an N-type confinement layer 6, an active layer 7, a P-type confinement layer 8, and a P-type ohmic contact layer 9 on an N-type substrate 1. (2) As Figure 2 The upper reflector layer shown is bonded to the P-type ohmic contact layer 9. Then, the N-type substrate 1, the N-type buffer layer 2 and the N-type etching stop layer 3 are removed sequentially by chemical etching. The high heat dissipation silicon wafer 102 is bonded to the P-type side by bonding process, which shortens the heat conduction path from the active region to the heat dissipation substrate. (3) Using ICP process, etching is performed to the upper reflective layer to form a mesa; (4) A SiO2 insulating layer 11 with a thickness of 400 nm is deposited on the side wall of the platform; (5) An electric injection region 12 is deposited on the N-type ohmic contact layer 4 to obtain an epitaxial structure; (6) Using ICP process, the epitaxial structure is cut into 8mil VCSEL chips.

[0032] Example 2 A flip-chip red VCSEL epitaxial structure comprises, from bottom to top, an upper mirror layer and a stacked structure. The upper mirror layer includes, from bottom to top, a lower injection region 103, a silicon wafer 102, and a metal mirror layer 101. In the upper mirror layer, the metal mirror layer 101 is an Ag layer with a thickness of 1 μm, and the silicon wafer 102 has a thickness of 400 μm. The resistivity of the silicon wafer 102 is 2 × 10⁻⁶. -4Ω·cm; the material of the lower electrical injection region 103 is a Ti / Au alloy, with a Ti thickness of 200nm and an Au thickness of 2μm; the stacked structure, from bottom to top, includes a P-type ohmic contact layer 9, a P-type confinement layer 8, an active layer 7, an N-type confinement layer 6, an N-type DBR layer 5, and an N-type ohmic contact layer 4; the material of the P-type ohmic contact layer 9 is an Au layer with a thickness of 50nm, and a second metal mirror layer 101 is deposited on the side of the P-type ohmic contact layer 9 near the upper mirror layer, the second metal mirror layer 101 being an Ag layer with a thickness of 1μm; the P-type confinement layer 8 is an Al layer with a thickness of 150nm. 0.9 Ga 0.1 ) 0.5 In 0.5 P-layer, with a doping concentration of 3 × 10⁻⁶ 17 cm -3 The active layer 7 consists of three pairs of Ga... 0.5 In 0.5 P quantum well layer and (Al) 0.7 Ga 0.3 ) 0.5 In 0.5 The P quantum barrier layers are arranged alternately, with each pair containing Ga 0.5 In 0.5 The thickness of the P quantum well layer is 6.5 nm, (Al 0.7 Ga 0.3 ) 0.5 In 0.5 The thickness of the P quantum barrier layer is 8 nm; the N-type confinement layer 6 is 150 nm thick (Al). 0.9 Ga 0.1 ) 0.5 In 0.5 P-layer, with a doping concentration of 6 × 10⁻⁶ 17 cm -3 The N-type DBR layer 5 consists of 20 cycles of Al 0.91 Ga 0.09 As / Al 0.15 Ga 0.85 Composed of As material, with a doping concentration of 7×10⁻⁶. 17 cm -3 The N-type ohmic contact layer 4 is a GaAs layer; the side of the N-type ohmic contact layer 4 away from the N-type DBR layer 5 is provided with an electric injection region 12, the material of the electric injection region 12 is an Au / Ge / Ni alloy, the thickness of Au is 100nm, the thickness of Ge is 200nm, and the thickness of Ni is 500nm.

[0033] The above-mentioned method for fabricating the flip-chip red VCSEL epitaxial structure includes the following steps: (1) Epitaxial growth: Using metal-organic vapor phase epitaxy, N-type buffer layer 2, N-type etch stop layer 3, N-type ohmic contact layer 4, N-type DBR layer 5, N-type confinement layer 6, active layer 7, P-type confinement layer 8 and P-type ohmic contact layer 9 are sequentially epitaxially deposited on N-type substrate 1. (2) The upper reflector layer is bonded to the P-type ohmic contact layer 9, and then the N-type substrate 1, N-type buffer layer 2 and N-type etching stop layer 3 are removed in sequence by chemical etching. The high heat dissipation silicon wafer 102 is bonded to the P-type side by bonding process to shorten the heat conduction path from the active area to the heat dissipation substrate. (3) Using ICP process, etching is performed to the upper reflective layer to form a mesa; (4) A SiO2 insulating layer 11 with a thickness of 200 nm is deposited on the side wall of the platform; (5) An electric injection region 12 is deposited on the N-type ohmic contact layer 4 to obtain an epitaxial structure; (6) Using ICP process, the epitaxial structure is cut into 8mil VCSEL chips.

[0034] Example 3 A flip-chip red VCSEL epitaxial structure comprises, from bottom to top, an upper mirror layer and a stacked structure. The upper mirror layer includes, from bottom to top, a lower injection region 103, a silicon wafer 102, and a metal mirror layer 101. In the upper mirror layer, the metal mirror layer 101 is a 500 nm thick Ag layer, and the silicon wafer 102 has a thickness of 300 μm. The resistivity of the silicon wafer 102 is 1 × 10⁻⁶. -4 Ω·cm; the material of the lower electrical injection region 103 is a Ti / Au alloy, with a Ti thickness of 500nm and an Au thickness of 2μm; the stacked structure, from bottom to top, includes a P-type ohmic contact layer 9, a P-type confinement layer 8, an active layer 7, an N-type confinement layer 6, an N-type DBR layer 5, and an N-type ohmic contact layer 4; the material of the P-type ohmic contact layer 9 is a 50nm thick Au layer, and a second metal mirror layer 101 is deposited on the side of the P-type ohmic contact layer 9 near the upper mirror layer, the second metal mirror layer 101 being a 1μm thick Ag layer; the P-type confinement layer 8 is a 150nm thick (Al) layer. 0.9 Ga 0.1 ) 0.5 In 0.5 P-layer, with a doping concentration of 3 × 10⁻⁶ 17 cm -3 The active layer 7 consists of three pairs of Ga... 0.5 In 0.5 P quantum well layer and (Al) 0.7 Ga 0.3 ) 0.5 In 0.5 The P quantum barrier layers are arranged alternately, with each pair containing Ga0.5 In 0.5 The thickness of the P quantum well layer is 6.5 nm, (Al 0.7 Ga 0.3 ) 0.5 In 0.5 The thickness of the P quantum barrier layer is 8 nm; the N-type confinement layer 6 is 150 nm thick (Al). 0.9 Ga 0.1 ) 0.5 In 0.5 P-layer, with a doping concentration of 6 × 10⁻⁶ 17 cm -3 The N-type DBR layer 5 consists of 20 cycles of Al 0.91 Ga 0.09 As / Al 0.15 Ga 0.85 Composed of As material, with a doping concentration of 7×10⁻⁶. 17 cm -3 The N-type ohmic contact layer 4 is a GaAs layer; the side of the N-type ohmic contact layer 4 away from the N-type DBR layer 5 is provided with an electric injection region 12, the material of the electric injection region 12 is an Au / Ge / Ni alloy, the thickness of Au is 100nm, the thickness of Ge is 200nm, and the thickness of Ni is 500nm.

[0035] The above-mentioned method for fabricating the flip-chip red VCSEL epitaxial structure includes the following steps: (1) Epitaxial growth: Using metal-organic vapor phase epitaxy, N-type buffer layer 2, N-type etch stop layer 3, N-type ohmic contact layer 4, N-type DBR layer 5, N-type confinement layer 6, active layer 7, P-type confinement layer 8 and P-type ohmic contact layer 9 are sequentially epitaxially deposited on N-type substrate 1. (2) The upper reflector layer is bonded to the P-type ohmic contact layer 9, and then the N-type substrate 1, N-type buffer layer 2 and N-type etching stop layer 3 are removed in sequence by chemical etching. The high heat dissipation silicon wafer 102 is bonded to the P-type side by bonding process to shorten the heat conduction path from the active area to the heat dissipation substrate. (3) Using ICP process, etching is performed to the upper reflective layer to form a mesa; (4) A SiO2 insulating layer 11 with a thickness of 500 nm is deposited on the side wall of the platform; (5) An electric injection region 12 is deposited on the N-type ohmic contact layer 4 to obtain an epitaxial structure; (6) Using ICP process, the epitaxial structure is cut into 8mil VCSEL chips.

[0036] Comparative Example A red-light VCSEL epitaxial structure, such as Figure 4As shown, from bottom to top, it includes an N-type substrate 1, an N-type buffer layer 2, an N-type DBR layer 5, an N-type confinement layer 6, an active layer 7, a P-type confinement layer 8, a P-type DBR layer 13, a P-type ohmic contact layer 9, and an electro-injection region 14; the electro-injection region 14 is made of a Ti / Au alloy, with a Ti thickness of 500 nm and an Au thickness of 2 μm; the P-type ohmic contact layer 9 is made of a 50 nm thick Au layer; the P-type DBR layer 13 consists of 20 Al layers... 0.15 Ga 0.85 As / Al 0.91 Ga 0.09 Composed of As material, with a doping concentration of 7×10⁻⁶. 17 cm -3 The P-type confinement layer 8 is 150 nm thick (Al). 0.9 Ga 0.1 ) 0.5 In 0.5 P-layer, with a doping concentration of 3 × 10⁻⁶ 17 cm -3 The active layer 7 consists of three pairs of Ga... 0.5 In 0.5 P quantum well layer and (Al) 0.7 Ga 0.3 ) 0.5 In 0.5 The P quantum barrier layers are arranged alternately, with each pair containing Ga 0.5 In 0.5 The thickness of the P quantum well layer is 6.5 nm, (Al 0.7 Ga 0.3 ) 0.5 In 0.5 The thickness of the P quantum barrier layer is 8 nm; the N-type confinement layer 6 is 150 nm thick (Al). 0.9 Ga 0.1 ) 0.5 In 0.5 P-layer, with a doping concentration of 6 × 10⁻⁶ 17 cm -3 The N-type DBR layer 5 consists of 20 cycles of Al 0.91 Ga 0.09 As / Al 0.15 Ga 0.85 Composed of As material, with a doping concentration of 7×10⁻⁶. 17 cm -3 The N-type ohmic contact layer 4 is a GaAs layer.

[0037] The above-mentioned method for fabricating red VCSEL epitaxial structures includes the following steps: (1) Epitaxial growth: N-type buffer layer 2, N-type DBR layer 5, N-type confinement layer 6, quantum well active layer 7, P-type confinement layer 8, P-type DBR layer 13, P-type ohmic contact layer 9 and electrical injection region are sequentially epitaxially deposited on N-type substrate 1; (2) Using ICP process, etch to the N-type buffer layer 2 to form a mesa; (4) A SiO2 insulating layer 11 with a thickness of 400 nm is deposited on the side wall of the platform; (5) An electro-implantation region 14 is deposited on the P-type ohmic contact layer 9 to obtain an epitaxial structure; (6) Using ICP process, the epitaxial structure is cut into 8mil VCSEL chips.

[0038] Test case The VCSEL chips prepared in Example 1 and the comparative example were subjected to PIV photoelectric property testing. The testing method is as follows: (1) Place the VCSEL chip to be tested on the temperature control platform (300K), use a probe station to connect the positive and negative terminals of the source / measurement unit, connect the P-type electrode to the positive terminal and the N-type electrode to the negative terminal, and place the light output window of the VCSEL directly in front of the light collection port of the integrating sphere. Connect the detector to the light output port of the integrating sphere. (2) Set the initial injection current I_start=0mA and the termination injection current I_end to the expected maximum operating current. The scanning direction increases in one step from low to high. (3) The scanning current is output from the source / measurement unit. After the current stabilizes at each current point, the voltage and optical power at both ends of the VCSEL are collected synchronously, and the voltage-current data and optical power-current data are recorded. (4) After all scans are completed, plot the optical power-current (PI) curve and the voltage-current (VI) curve, i.e., the PIV photoelectric characteristic curve.

[0039] Test results are as follows Figure 5 As shown, the series resistance of the flip-chip red VCSEL device prepared in Example 1 is significantly lower than that of the comparative device, which is directly reflected in the steeper slope of its VI curve. Simultaneously, the PI curve shows that, under the same injection current conditions, the optical output power of the device in Example 1 is significantly higher than that of the comparative device. Therefore, the electro-optical conversion efficiency of the device in Example 1 is also significantly improved. These results fully demonstrate that by using a metal Ag mirror to replace the traditional upper DBR (i.e., the P-type DBR layer), combined with flip-chip structure and substrate removal techniques, the series resistance of the device is effectively reduced, Joule heat loss is decreased, and thus higher electro-optical conversion efficiency is achieved.

[0040] Although the present invention has been described in detail with reference to the accompanying drawings and preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made to the embodiments of the present invention by those skilled in the art without departing from the spirit and essence of the invention, and such modifications or substitutions should all be within the scope of the present invention. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should also be covered within the protection scope of the present invention.

Claims

1. A flip-chip red VCSEL epitaxial structure, characterized in that, The structure consists of an upper reflector layer and a stacked structure from bottom to top. The upper reflector layer includes a lower electrical injection region, a silicon wafer, and a metal reflector layer from bottom to top. The stacked structure includes a P-type ohmic contact layer, a P-type confinement layer, an active layer, an N-type confinement layer, an N-type DBR layer, and an N-type ohmic contact layer from bottom to top. The side of the N-type ohmic contact layer away from the N-type DBR layer has an upper electrical injection region.

2. The flip-chip red VCSEL epitaxial structure as described in claim 1, characterized in that, In the upper reflective mirror layer, the thickness of the metal reflective mirror layer is 500~1000nm, the thickness of the silicon wafer is 200~400μm, and the thickness of the lower electric injection region is 2~2.5μm.

3. The flip-chip red VCSEL epitaxial structure as described in claim 2, characterized in that, The resistivity of the silicon wafer is (1~2)×10⁻⁶. -4 Ω·cm, the material of the metal reflective mirror layer is Ag.

4. The flip-chip red VCSEL epitaxial structure as described in claim 1, characterized in that, The P-type ohmic contact layer has a second metal mirror layer deposited on the side near the upper mirror layer.

5. The flip-chip red VCSEL epitaxial structure as described in claim 4, characterized in that, The material of the second metal reflective mirror layer is Ag.

6. The flip-chip red VCSEL epitaxial structure as described in claim 5, characterized in that, The thickness of the P-type ohmic contact layer is 30~50nm, and the thickness of the second metal reflective layer is 500~1000nm.

7. The flip-chip red VCSEL epitaxial structure as described in claim 1, characterized in that, The material of the lower electrode injection region is a Ti / Au alloy, and the total thickness of the lower electrode injection region is 2~2.5μm.

8. The flip-chip red VCSEL epitaxial structure as described in claim 1, characterized in that, The material of the power injection region is an Au / Ge / Ni alloy, and the thickness of each metal layer in the Au / Ge / Ni alloy is 100~500nm.

9. A method for fabricating a flip-chip red VCSEL epitaxial structure as described in any one of claims 1 to 8, characterized in that, Includes the following steps: (1) Epitaxial growth: The N-type buffer layer, N-type etch stop layer, N-type ohmic contact layer, N-type DBR layer, N-type confinement layer, active layer, P-type confinement layer and P-type ohmic contact layer are sequentially epitaxially deposited on the N-type substrate using metal-organic vapor phase epitaxy process; (2) Bond the upper reflector layer to the P-type ohmic contact layer, and then remove the N-type substrate, N-type buffer layer and N-type etching stop layer in sequence by chemical etching. (3) Using ICP process, etching is performed to the upper reflective layer to form a mesa; (4) An insulating layer is deposited on the side wall of the table, with a thickness of 200~500nm; (5) An electro-injection region is deposited on the N-type ohmic contact layer to obtain an epitaxial structure; (6) The epitaxial structure is cut into VCSEL chips using ICP process.

10. The preparation method according to claim 9, characterized in that, Before step (2), the following operation is performed: a second metal mirror layer is deposited on the side of the P-type ohmic contact layer near the upper mirror layer by vacuum evaporation process.

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