A digital current-mode LLC control circuit and method

Abstract

The application discloses a kind of digital current type LLC control circuit and method, comprising: output voltage sampling circuit, resonant cavity current sampling circuit, integrated MCU and driver;Method is through the EVT event generated by capturing the COMP flip of MCU internal comparator, timer TMR capture value is transmitted to period register PRD by DMA, on the premise that additional logic chip such as CPLD / FPGA is not increased, realizing LLC bridge arm upper and lower tube symmetric frequency conversion control;While according to the linear calculation voltage ring PI output upper limit of current switching frequency period value, complete single cycle current limiting protection.The application circuit structure is simplified, low in cost, solves the problem that digital current type LLC is difficult to realize upper and lower tube symmetric control, cannot single cycle current limiting, improves LLC converter operation symmetry and reliability.

Description

Technical Field

[0001] This invention relates to the field of LLC converter technology, and in particular to a digital current-mode LLC control circuit and method. Background Technology

[0002] LLC resonant converters can easily achieve soft switching of power devices on the primary and secondary sides, and are widely used in medium and high power high frequency switching power supplies. Their control is divided into voltage type and current type. Current type LLC loads have better dynamic response and stronger input voltage adaptability, making them more suitable for AC input scenarios.

[0003] Traditional current-mode LLCs mostly use analog chip control, which has a long development cycle and is difficult to customize. Existing digital current-mode LLCs are prone to excessive resonant cavity current due to the asymmetry of the resonant cavity current during use. At the same time, the few solutions that achieve symmetrical control require the addition of CPLD / FPGA chips, which is costly and difficult to engineer. In addition, traditional current limiting strategies rely on the current loop and need to wait for the loop response, which cannot achieve single-cycle current limiting and cannot meet the requirements of high-precision and high-reliability LLC control. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies, such as the fact that "traditional current-type LLCs mostly use analog chip control, which has a long development cycle and is difficult to customize; existing digital current-type LLCs are prone to excessive resonant cavity current due to asymmetry in resonant cavity current during use; at the same time, a few schemes that achieve symmetrical control require additional CPLD / FPGA chips, which are costly and difficult to engineer; in addition, traditional current limiting strategies rely on current loops, which require waiting for loop response and cannot achieve single-cycle current limiting, making it difficult to meet the requirements of high-precision and high-reliability LLC control." Therefore, this invention proposes a digital current-type LLC control circuit and method.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: A digital current-type LLC control circuit includes: an output voltage sampling circuit, a resonant cavity current sampling circuit, an MCU, and a driver; The MCU integrates a central processing unit (CPU), an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a comparator (COMP), general-purpose input / output ports (GPIO), and a timer module (TMR). The output of the output voltage sampling circuit is connected to the ADC pin of the MCU, the output of the resonant cavity current sampling circuit is connected to the GPIO pin of the MCU, and the output of the MCU's timer module TMR is connected to the power transistor of the LLC main circuit bridge arm via a driver.

[0006] As a preferred embodiment of the digital current-type LLC control circuit of the present invention, the output voltage sampling circuit includes a sampling resistor R1, a sampling resistor R2, and a filter capacitor C1; One end of the sampling resistor R1 is connected to the positive terminal of the LLC output, and the other end of the sampling resistor R1 is connected to one end of the sampling resistor R2 and one end of the filter capacitor C1. The other end of the sampling resistor R2 is grounded, and the other end of the filter capacitor C1 is grounded. The outputs of the two ends of the filter capacitor C1 are connected to the ADC pin of the MCU.

[0007] In a preferred embodiment of the digital current-type LLC control circuit of the present invention, the resonant cavity current sampling circuit includes a current transformer CT1, rectifier diodes D1~D4, a signal conversion resistor R4, an integrating resistor R3, and an integrating capacitor C2. The primary side of the current transformer CT1 is connected in series with the LLC resonant cavity, one end of the secondary side is connected to the anode of rectifier diode D1 and the cathode of rectifier diode D2, and the other end of the secondary side is connected to the anode of rectifier diode D3 and the cathode of rectifier diode D4. The cathodes of D1 and D3 are connected to one end of the signal conversion resistor R4, and the other end of the signal conversion resistor R4 is grounded. The cathodes of D1 and D3 are also connected to one end of the integrating resistor R3, and the other end of the integrating resistor R3 is connected to one end of the integrating capacitor C2 and the GPIO pin of the MCU. The anodes of D2 and D4 and the other end of the integrating capacitor C2 are connected to the ground terminal.

[0008] In a preferred embodiment of the digital current-type LLC control circuit of the present invention, the first output port of the MCU timer module TMR is connected to the gate of the power transistor of the upper arm of the LLC via a driver, and the second output port of the TMR is connected to the gate of the power transistor of the lower arm of the LLC via a driver.

[0009] As a preferred embodiment of the digital current-type LLC control method of the present invention, it includes the following steps: S1. The MCU acquires the output voltage through the ADC, calculates the difference between the acquired digital value and the digital reference, and then performs PI calculation through the CPU to obtain the closed-loop output digital value, which is then output by the digital-to-analog converter (DAC) to obtain the vpi voltage. S2. Acquire the resonant cavity current and convert it into a resonant cavity current signal vcs; when vcs exceeds vpi, the comparator COMP is triggered to flip and generate an EVT event. The timer TMR captures CAP and transmits it to the timer TMR's period register PRD via DMA to realize symmetrical frequency conversion control of the upper and lower transistors of the LLC bridge arm. S3. Calculate the upper limit of the voltage loop PI output based on the current switching frequency period value to achieve single-cycle current limiting.

[0010] As a preferred embodiment of the digital current-type LLC control method described in this invention, when the power transistor of the upper bridge arm of the LLC is turned on, the resonant cavity current is transmitted through the isolation of the current transformer CT1, rectified by diodes D1~D4, converted into a voltage signal by the signal conversion resistor R4, and then integrated and filtered by the integrating resistor R3 and the integrating capacitor C2 to form a smooth resonant cavity current signal vcs.

[0011] As a preferred embodiment of the digital current-type LLC control method of the present invention, when the resonant cavity current signal vcs is greater than the vpi voltage, the MCU comparator COMP level flips to generate an EVT event, the timer TMR captures the CAP value and transmits it to the period register PRD through DMA, and the switching frequency is adjusted to make the pulse width of the upper and lower bridge arm power transistors consistent.

[0012] As a preferred embodiment of the digital current-type LLC control method of the present invention, the maximum output current Imax is used as the current limiting threshold, the highest frequency corresponding to vpi is set as vmin, the lowest frequency corresponding to vpi is set as vmax, and the voltage loop output upper limit vpi_lim is linearly calculated in combination with the current switching cycle T, the highest frequency cycle Tmin, and the lowest frequency cycle Tmax to achieve cycle-by-cycle current limiting protection.

[0013] Compared with the prior art, the beneficial effects of the present invention are: Symmetrical frequency conversion control can be achieved using only the internal modules of the MCU, without the need to add additional logic chips such as CPLD / FPGA. The circuit structure is simplified, the cost is lower, and the engineering implementation is simpler.

[0014] By using EVT events, CAP capture, and DMA transfer, symmetrical driving of the upper and lower transistors of the LLC bridge arm is precisely achieved, avoiding problems such as asymmetrical and excessive resonant cavity current and improving operational stability.

[0015] A single-cycle current limiting protection is achieved by using a switching cycle linear algorithm, which eliminates the need to wait for the current loop response. This results in fast current limiting speed, high accuracy, and effective protection of power devices. Attached Figure Description

[0016] Figure 1 This is a circuit diagram of a digital current-type LLC control circuit proposed in this invention; Figure 2 This is a timing diagram of a digital current-type LLC control method proposed in this invention; Figure 3 This is a diagram of the single-cycle current limiting strategy of the present invention. Detailed Implementation

[0017] The embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and should not be construed as limiting the scope of the invention.

[0018] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "set up," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0019] Reference Figures 1-3 A digital current-type LLC control circuit includes an output voltage sampling circuit, a resonant cavity current sampling circuit, an MCU, and a driver. The MCU integrates a central processing unit (CPU), an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a comparator (COMP), general-purpose input / output ports (GPIO), and a timer module (TMR). The output of the output voltage sampling circuit is connected to the ADC pin of the MCU's analog-to-digital converter module. The output of the resonant cavity current sampling circuit is connected to the GPIO pin of the MCU's general-purpose input / output port. The output of the MCU's timer module TMR is connected to the power transistor of the LLC main circuit bridge arm via a driver.

[0020] Considering the need for accurate sampling of the LLC output voltage, while avoiding interference introduced into the sampling circuit and ensuring the stability of the sampling signal, the output voltage sampling circuit includes sampling resistor R1, sampling resistor R2, and filter capacitor C1. One end of sampling resistor R1 is connected to the positive terminal of the LLC output, and the other end of sampling resistor R1 is connected to one end of sampling resistor R2 and one end of filter capacitor C1. The other end of sampling resistor R2 is grounded, and the other end of filter capacitor C1 is grounded. The outputs of both ends of filter capacitor C1 are connected to the ADC pin of the MCU.

[0021] Furthermore, considering the need to convert the LLC resonant cavity current into a voltage signal recognizable by the MCU, and to ensure that the sampled signal is smooth and distortion-free, and that the current-to-voltage conversion circuit is complete and reliable, the resonant cavity current sampling circuit includes a current transformer CT1, rectifier diodes D1~D4, a signal conversion resistor R4, an integrating resistor R3, and an integrating capacitor C2. The primary side of the current transformer CT1 is connected in series with the LLC resonant cavity, one end of the secondary side is connected to the anode of rectifier diode D1 and the cathode of rectifier diode D2, and the other end of the secondary side is connected to the anode of rectifier diode D3 and the cathode of rectifier diode D4. The cathodes of D1 and D3 are connected to one end of the signal conversion resistor R4, and the other end of the signal conversion resistor R4 is grounded. The cathodes of D1 and D3 are also connected to one end of the integrating resistor R3, and the other end of the integrating resistor R3 is connected to one end of the integrating capacitor C2 and the GPIO pin of the MCU. The anodes of D2 and D4, and the other end of the integrating capacitor C2 are connected to the ground terminal.

[0022] Furthermore, considering that the MCU timer output signal has insufficient driving capability and cannot directly drive the LLC power transistor, and that the upper and lower bridge arm power transistors need to be controlled separately to achieve symmetrical driving, the first output port of the MCU timer module TMR is connected to the gate of the LLC upper bridge arm power transistor via a driver, and the second output port of the TMR is connected to the gate of the LLC lower bridge arm power transistor via a driver.

[0023] A digital current-mode LLC control method includes the following steps: The MCU acquires the output voltage through the analog-to-digital converter (ADC), calculates the difference between the acquired digital value and a digital reference, and performs a PI calculation in the CPU to obtain the closed-loop output digital value. This value is then output through the digital-to-analog converter (DAC) to obtain the VPI voltage.

[0024] When LLC-A is pulled high, the upper transistor of the bridge arm is turned on, and the resonant cavity current begins to rise. The resonant cavity current is isolated by the current transformer CT1 and transmitted to the MCU side. After rectification by diodes D1~D4, it forms a resonant cavity current signal. This signal is converted into a voltage signal by the signal conversion resistor R4. Then, through the integrating resistor R3 and the integrating capacitor C2, it forms the resonant cavity current signal vcs.

[0025] When the resonant cavity current signal vcs exceeds vpi, the COMP output of the MCU's comparator module flips, generating an EVT event. The timer module TMR captures CAP and transfers it to the period value PRD of the timer module TMR via DMA. Then, LLC-B can emit a PWM wave with the same pulse width as LLC-A. This achieves symmetrical frequency conversion control of the upper and lower transistors of the current-type bridge arm.

[0026] Under the condition of maximum output current Imax, the vpi corresponding to the highest frequency is assigned the value vmin, and the vpi amplitude corresponding to the lowest frequency is assigned the value vmax, according to the formula... The maximum output limit of the voltage loop, vpi_lim, is calculated, where T, Tmin, and Tmax are the period values ​​corresponding to the current switching frequency, the highest frequency, and the lowest frequency, respectively, thereby achieving single-cycle current limiting.

[0027] It is worth noting that the entire device is controlled by a controller. Since the controller is a common device and belongs to existing mature technology, its electrical connection relationship and specific circuit structure will not be described in detail here.

[0028] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the technical scope disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention. In the description of the present invention, it should be noted that the terms "upper," "lower," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, the terms "first," "second," or "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

Claims

1. A digital current-mode LLC control circuit, characterized in that, include: Output voltage sampling circuit, resonant cavity current sampling circuit, MCU, and driver; The MCU includes a central processing unit (CPU), an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a comparator (COMP), general-purpose input / output ports (GPIO), and a timer module (TMR). The output of the output voltage sampling circuit is connected to the ADC pin of the MCU, the output of the resonant cavity current sampling circuit is connected to the GPIO pin of the MCU, and the output of the MCU's timer module TMR is connected to the power transistor of the LLC main circuit bridge arm.

2. The digital current-type LLC control circuit according to claim 1, characterized in that: The output voltage sampling circuit includes sampling resistor R1, sampling resistor R2, and filter capacitor C1; One end of the sampling resistor R1 is connected to the positive terminal of the LLC output, and the other end of the sampling resistor R1 is connected to one end of the sampling resistor R2 and one end of the filter capacitor C1. The other end of the sampling resistor R2 is grounded, and the other end of the filter capacitor C1 is grounded. The outputs of the two ends of the filter capacitor C1 are connected to the ADC pin of the MCU.

3. The digital current-type LLC control circuit according to claim 1, characterized in that: The resonant cavity current sampling circuit includes a current transformer CT1, rectifier diodes D1~D4, a signal conversion resistor R4, an integrating resistor R3, and an integrating capacitor C2. The primary side of the current transformer CT1 is connected in series with the LLC resonant cavity, one end of the secondary side is connected to the anode of rectifier diode D1 and the cathode of rectifier diode D2, and the other end of the secondary side is connected to the anode of rectifier diode D3 and the cathode of rectifier diode D4. The cathodes of D1 and D3 are connected to one end of the signal conversion resistor R4, and the other end of the signal conversion resistor R4 is grounded. The cathodes of D1 and D3 are also connected to one end of the integrating resistor R3, and the other end of the integrating resistor R3 is connected to one end of the integrating capacitor C2 and the GPIO pin of the MCU. The anodes of D2 and D4, and the other end of the integrating capacitor C2 are connected to the ground terminal.

4. The digital current-type LLC control circuit according to claim 1, characterized in that: The first output port of the MCU timer module TMR is connected to the gate of the upper arm power transistor of the LLC via a driver, and the second output port of the TMR is connected to the gate of the lower arm power transistor of the LLC via a driver.

5. A digital current-type LLC control method, implemented based on the circuit described in any one of claims 1 to 4, characterized in that, Includes the following steps: S1. The MCU acquires the output voltage through the ADC, calculates the difference between the acquired digital value and the digital reference, and then performs PI calculation through the CPU to obtain the closed-loop output digital value, which is then output by the digital-to-analog converter (DAC) to obtain the vpi voltage. S2. Acquire the resonant cavity current and convert it into a resonant cavity current signal vcs; When VCS exceeds VPI, the comparator COMP is triggered to flip, generating an EVT event. The timer TMR captures CAP and transfers it to the timer TMR's period register PRD via DMA, realizing symmetrical frequency conversion control of the upper and lower transistors of the LLC bridge arm. S3. Calculate the upper limit of the voltage loop PI output based on the current switching frequency period value to achieve single-cycle current limiting.

6. The digital current-type LLC control method according to claim 5, characterized in that: When the power transistor of the upper arm of LLC is turned on, the resonant cavity current is transmitted through the isolation of the current transformer CT1, rectified by diodes D1~D4, converted into a voltage signal by the signal conversion resistor R4, and then integrated and filtered by the integrating resistor R3 and the integrating capacitor C2 to form a smooth resonant cavity current signal vcs.

7. The digital current-type LLC control method according to claim 5, characterized in that: When the resonant cavity current signal vcs is greater than the vpi voltage, the MCU comparator COMP level flips to generate an EVT event. The timer TMR captures the CAP value and transfers it to the period register PRD through DMA. The switching frequency is adjusted to make the pulse width of the upper and lower bridge arm power transistors consistent.

8. The digital current-type LLC control method according to claim 5, characterized in that: Using the maximum output current Imax as the current limiting threshold, the highest frequency corresponding to vpi is set as vmin and the lowest frequency corresponding to vpi is set as vmax. The upper limit of the voltage loop output vpi_lim is linearly calculated by combining the current switching cycle T, the highest frequency cycle Tmin, and the lowest frequency cycle Tmax, so as to realize cycle-by-cycle current limiting protection.

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