Semiconductor device and method of manufacturing the same, electronic device
By using a second sacrificial structure as a protective layer during the semiconductor device manufacturing process, combined with wet and dry etching, the problem of easy damage to semiconductor material layers in existing technologies is solved, and the dimensional uniformity and performance stability of semiconductor devices are achieved.
Patent Information
- Application Number
- CN202510208358.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-24
- Publication Date
- 2026-08-25
AI Technical Summary
In the semiconductor device manufacturing process, existing technologies can easily damage the semiconductor material layer when removing the sacrificial structure, affecting dimensional uniformity and leading to performance degradation.
By forming a first sacrificial structure and a second sacrificial structure on both sides of the first via, the second sacrificial structure is brought closer to the trench and via. The second sacrificial structure is used as a barrier layer to protect the semiconductor material layer. The sacrificial structure is removed by a combination of wet and dry etching.
This ensures the uniformity of etching of parasitic portions of the semiconductor material layer under the same etching environment, avoids the impact of size differences, and ensures the integrity and performance of semiconductor devices.
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Figure CN122641007A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor device technology, and more specifically, to a semiconductor device and its manufacturing method, and an electronic device. Background Technology
[0002] With the development of integrated circuit technology, the critical dimensions of semiconductor devices are shrinking, and the types and number of semiconductor devices contained in a single chip are increasing, making it possible for even the slightest differences in the manufacturing process to affect the performance of semiconductor devices.
[0003] To minimize product costs, the goal is to fabricate as many semiconductor devices as possible on a substrate with limited area. Since the advent of Moore's Law, the industry has proposed various structural designs and process optimizations for semiconductor devices to meet current product demands. Summary of the Invention
[0004] This application addresses the shortcomings of existing methods by proposing a semiconductor device, its manufacturing method, and an electronic device, which can effectively improve the performance of the semiconductor device.
[0005] In a first aspect, embodiments of this application provide a method for manufacturing a semiconductor device, comprising: A stacked structure is formed on a substrate. The stacked structure includes multiple layers of first dielectric layers and multiple layers of first insulating layers stacked alternately, and has a first trench, a row of first vias and a row of second vias spaced apart along a first direction. The first trench extends along a second direction. The first direction and the second direction intersect and are both parallel to the substrate. The multilayer first insulating layer on both sides of the first trench is replaced with a multilayer first conductive layer extending along the second direction, and the multilayer first insulating layer on the outer periphery of the second via is replaced with a multilayer first electrode structure; the first conductive layer and the first electrode structure are both exposed in the first via. Between any two adjacent first conductive layers and between the first electrode structure, a second sacrificial structure and a first sacrificial structure are formed sequentially around the periphery of the first via. A conformal semiconductor material layer, a gate insulating layer, and a gate layer are sequentially deposited within the first via. Based on the second via and the first trench, the first sacrificial structure and the second sacrificial structure are removed sequentially to expose the semiconductor material layer; The exposed semiconductor material layer and gate insulating layer are removed sequentially, and the remaining semiconductor material layer and gate insulating layer each form a semiconductor structure and a gate insulating structure, respectively.
[0006] In some possible embodiments, the multiple layers of first insulating layers on both sides of the first trench are replaced with multiple layers of first conductive layers extending along the second direction, including: Based on the first trench, the exposed multilayer first insulating layer on the sidewall of the first trench is etched back to form a first groove; a first conductive layer extending in a second direction is formed in the first groove.
[0007] In some possible embodiments, the multilayer first insulating layer around the second via is replaced with a multilayer first electrode structure, including: Based on the second via, the multilayer first insulating layer exposed on the sidewall of the second via is etched back to form a second groove; a conformal first electrode structure is deposited in the second groove, the first electrode structure covering the inner sidewall of the second groove and having an opening facing the second via.
[0008] In some possible embodiments, a second sacrificial structure and a first sacrificial structure are formed sequentially around the periphery of the first via between any two adjacent first conductive layers and between the first electrode structure, including: Based on the first via, a first sacrificial layer is deposited, and the first sacrificial layer conformally covers each first conductive layer and each first electrode structure; Based on the first via, the first sacrificial layer is etched laterally to form a first sacrificial structure surrounding the first via; each first conductive layer and each first electrode structure are partially exposed in the first sacrificial structure. A second sacrificial layer is deposited based on the first via, and the second sacrificial layer conformally covers the first sacrificial structure, each layer of the first conductive layer and each layer of the first electrode structure. The second sacrificial layer is etched laterally based on the first via to form a second sacrificial structure that is wound between the first via and the first sacrificial structure; each first conductive layer and each first electrode structure are partially exposed in the second sacrificial structure.
[0009] In some possible embodiments, the second sacrificial structure is made of the same material as the first dielectric layer.
[0010] In some possible embodiments, based on the second via and the first trench, the first sacrificial structure and the second sacrificial structure are removed sequentially to expose the semiconductor material layer, including: Based on the second via and the first trench, the first sacrificial structure is removed by wet etching, and the second sacrificial structure is removed by dry etching, exposing the semiconductor material layer.
[0011] In some possible embodiments, the wet etching rate of the first sacrificial structure is greater than that of the second sacrificial structure; The dry etching rate of the second sacrificial structure is greater than that of the semiconductor material layer.
[0012] In some possible embodiments, the second sacrificial structure is removed using dry etching, including: Dry etching is used to simultaneously remove the second sacrificial structure, the first dielectric layer exposed by the first trench, and the first dielectric layer exposed by the second via.
[0013] In some possible embodiments, the manufacturing method further includes: A conformal second dielectric layer and a second electrode structure are sequentially deposited within the second via. The second dielectric layer fills the opening of the first electrode structure and covers the inner sidewall of the second via. The second electrode structure covers the second dielectric layer and fills the second via. The first electrode structure, the second dielectric layer, and the second electrode structure form a capacitor.
[0014] Secondly, embodiments of this application provide a semiconductor device, including: A semiconductor stacked structure is disposed on a substrate; the semiconductor stacked structure has a first trench spaced apart along a first direction, a row of first vias and a row of second vias, the first trenches extending along a second direction; the first direction and the second direction intersect and are both parallel to the substrate; The first via is provided with a gate layer extending in a direction perpendicular to the substrate and a plurality of gate insulating structures and a plurality of semiconductor structures sequentially and spaced around the periphery of the gate layer. The plurality of semiconductor structures, the plurality of gate insulating structures and the gate layer are used to form a multilayer transistor spaced apart in a direction perpendicular to the substrate. The first trench has multiple first conductive layers on both sides that are connected to the semiconductor structure of the multilayer transistor. The outer periphery of the second via is provided with a multilayer first electrode structure that is connected to the semiconductor structure of the multilayer transistor. On a plane parallel to the substrate, the dimensions of the semiconductor structure are the same in the first direction and the second direction.
[0015] In some possible embodiments, the first conductive layer extends along a second direction and is connected along a first direction to the semiconductor structure of the adjacent transistor.
[0016] In some possible embodiments, the semiconductor stacked structure further includes: The capacitor includes a first electrode structure, a second dielectric layer located within a second via, and a second electrode structure. The first electrode structure has an opening facing the second via; The second dielectric layer fills the opening of the first electrode structure and covers the inner wall of the second via; The second electrode structure covers the second dielectric layer and fills the second via.
[0017] Thirdly, embodiments of this application provide an electronic device, including: a semiconductor device manufactured by any of the semiconductor device manufacturing methods provided in the first aspect above, or any of the semiconductor devices provided in the second aspect above.
[0018] The beneficial technical effects of the technical solutions provided in this application include: In this embodiment, a first sacrificial structure and a second sacrificial structure are formed on both sides of a first via along a first direction, such that the first sacrificial structure is closer to the first trench and the second via than the second sacrificial structure. Therefore, during the subsequent etching process to remove the first sacrificial structure around the semiconductor material layer, the second sacrificial structure acts as a barrier or protective layer, protecting the parasitic portion of the semiconductor material layer along the first direction between any two adjacent first conductive layers and first electrode structures from the etching process. This prevents premature etching and ensures that the dimensions of the parasitic portion of the semiconductor material layer along the first and second directions are substantially the same. Consequently, during the subsequent formal lateral etching process to remove the parasitic portion of the semiconductor material layer, the etching uniformity of the entire circumference of the parasitic portion of the semiconductor material layer is ensured under the same etching environment, reducing the probability or extent of etching affected by differences in parasitic portion size, or preventing the semiconductor structure from being affected by etching, thereby ensuring the integrity and effective performance of the semiconductor device.
[0019] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description
[0020] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application; Figure 2 This is a top view schematic diagram of the film structure after forming a stacked structure on a substrate in a method for manufacturing a semiconductor device according to an embodiment of this application; Figure 3 for Figure 2 Schematic diagram of the cross section at point AA'; Figure 4 for Figure 2 Schematic diagram of the cross section at point BB'; Figures 5-6 Two schematic cross-sectional views of the film structure after forming the first sacrificial layer in a semiconductor device manufacturing method provided in this application embodiment; Figures 7-8 Two schematic cross-sectional views of the film structure after forming the first sacrificial structure in a semiconductor device manufacturing method provided in this application embodiment; Figures 9-10 Two schematic cross-sectional views of the film structure after forming the second sacrificial layer in a semiconductor device manufacturing method provided in this application embodiment; Figures 11-12Two schematic cross-sectional views of the film structure after forming the second sacrificial structure in a semiconductor device manufacturing method provided in this application embodiment; Figures 13-14 Two cross-sectional schematic diagrams of the film structure after forming a semiconductor material layer, a gate insulating layer, and a gate layer in a method for manufacturing a semiconductor device according to an embodiment of this application; Figures 15-16 Two cross-sectional schematic diagrams of the film structure after opening the first trench and the second via in a semiconductor device manufacturing method provided in this application embodiment; Figures 17-18 Two schematic cross-sectional views of the film structure after removing the first sacrificial structure in a semiconductor device manufacturing method provided in this application embodiment; Figures 19-20 Two schematic cross-sectional views of the film structure after removing the second sacrificial structure in a semiconductor device manufacturing method provided in this application embodiment; Figures 21-22 Two cross-sectional schematic diagrams of the film structure after forming the semiconductor structure and the gate insulating structure in a semiconductor device manufacturing method provided in this application embodiment; Figures 23-24 Two schematic cross-sectional views of the film structure after filling the third dielectric layer in a semiconductor device manufacturing method provided in this application embodiment; Figures 25-26 These are two magnified cross-sectional schematic diagrams showing the semiconductor structure and gate insulating structure formed in a semiconductor device manufacturing method provided in this application embodiment.
[0021] Figure label: 100 - Substrate; 110 - Sacrificial material layer; 120 - First sacrificial layer; 121 - First sacrificial structure; 130 - Protective layer; 140 - Second sacrificial layer; 141 - Second sacrificial structure; 150 - Third dielectric layer; 200 - Stacked structure; 210 - First dielectric layer; 220 - First insulating layer; 201 - First trench; 202 - First via; 203 - Second via; 300 - First conductive layer; 400 - Transistor; 410 - Semiconductor structure; 411 - Semiconductor material layer; 420 - Gate insulating structure; 421 - Gate insulating layer; 430 - Gate; 431 - Gate layer; 510 - First electrode structure. Detailed Implementation
[0022] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.
[0023] Those skilled in the art will understand that, unless specifically stated otherwise, the terms "described" and "the" as used herein may also include plural forms. It should be further understood that the term "comprising" as used in this application's specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude implementations of other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by this art. It should be understood that when we say an element is "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or it may mean that the element and the other element are connected through an intermediate element. Furthermore, "connected" or "coupled" as used herein may include wireless connections or wireless coupling. The term "and / or" as used herein refers to at least one of the items defined by the term; for example, "A and / or B" may be implemented as "A," or as "B," or as "A and B."
[0024] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.
[0025] The research and development approach of this application includes: to achieve higher storage density, better performance, and smaller device size, related technologies involve forming a stacked structure of alternating dielectric and insulating layers on a substrate. This stacked structure is then processed to form a multilayer transistor.
[0026] In related technologies, the first dielectric layer around the first via is replaced with a sacrificial structure. A semiconductor material layer, a gate insulating layer, and a gate layer are sequentially formed within the first via that penetrates the stacked structure, covering the inner wall of the first via. By removing the sacrificial structure, a portion of the semiconductor material layer corresponding to the sacrificial structure is exposed. Then, the exposed semiconductor material layer is removed, causing the initial semiconductor material layer to break, forming a multilayer semiconductor structure, and thus forming a multilayer transistor.
[0027] However, the process of removing the sacrificial structure may damage the semiconductor material layer in contact with the sacrificial structure, affecting the dimensional uniformity of the subsequently formed semiconductor structure, which in turn affects the performance of the semiconductor device or even damages the semiconductor device.
[0028] The semiconductor devices, manufacturing methods, and electronic devices provided in this application are intended to solve the aforementioned technical problems in related technologies.
[0029] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.
[0030] This application provides a method for manufacturing a semiconductor device, and the flowchart of the method is shown below. Figure 1 As shown, the method includes steps S101-S106: S101: A stacked structure 200 is formed on the substrate 100. The stacked structure 200 includes multiple layers of first dielectric layers 210 and multiple layers of first insulating layers 220 stacked alternately, and has first trenches 201, a row of first vias 202 and a row of second vias 203 distributed at intervals along a first direction. The first trenches 201 extend along a second direction. The first direction intersects the second direction and is parallel to the substrate 100.
[0031] Optionally, the schematic diagram of the membrane structure obtained after step S101 is as follows: Figures 2-4 As shown.
[0032] S102: Replace the multilayer first insulating layer 220 on both sides of the first trench 201 with a multilayer first conductive layer 300 extending along the second direction, and replace the multilayer first insulating layer 220 on the outer periphery of the second via 203 with a multilayer first electrode structure 510; the first conductive layer 300 and the first electrode structure 510 are both exposed in the first via 202.
[0033] Optionally, after step S102, the process includes: removing the first dielectric layer 210 between any two adjacent first conductive layers 300 and between the first electrode structure 510.
[0034] S103: A second sacrificial structure 141 and a first sacrificial structure 121 are formed between any two adjacent first conductive layers 300 and between the first electrode structure 510, and are sequentially arranged around the periphery of the first via 202.
[0035] Optionally, the schematic diagram of the membrane structure obtained after step S103 is shown below. Figures 11-12 As shown.
[0036] S104: A conformal semiconductor material layer 411, a gate insulating layer 421, and a gate layer 431 are sequentially deposited within the first via 202.
[0037] Optionally, the schematic diagram of the membrane structure obtained after step S104 is shown below. Figures 13-14 As shown.
[0038] S105: Based on the second via 203 and the first trench 201, the first sacrificial structure 121 and the second sacrificial structure 141 are removed in sequence to expose the semiconductor material layer 411.
[0039] Optionally, the schematic diagram of the membrane structure obtained after step S105 is shown below. Figures 19-20 As shown.
[0040] S106: Sequentially remove the exposed semiconductor material layer 411 and gate insulating layer 421, leaving the remaining semiconductor material layer 411 and gate insulating layer 421 to form semiconductor structure 410 and gate insulating structure 420, respectively. Optionally, a schematic diagram of the film structure obtained after step S106 is shown below. Figures 21-22 As shown.
[0041] In this embodiment, after forming a first conductive layer 300 and a first electrode structure 510 on both sides of the first via 202 along the first direction, the first dielectric layer 210 between any two adjacent first conductive layers 300 and first electrode structures 510 is removed, and a first sacrificial structure 121 and a second sacrificial structure 141 are formed therein. After sequentially depositing a conformal semiconductor material layer 411, a gate insulating layer 421, and a gate layer 431 in the first via 202, the first sacrificial structure 121 is closer to the first trench 201 and the second via 203 than the second sacrificial structure 141. Therefore, in the subsequent etching process to remove the first sacrificial structure 121 around the semiconductor material layer 411, the second sacrificial structure 141 can act as a barrier layer or protective layer, protecting the parasitic portion of the semiconductor material layer 411 along the first direction between any two adjacent first conductive layers 300 and first electrode structures 510 from the etching process, preventing premature etching, and ensuring that the dimensions of the parasitic portion of the semiconductor material layer 411 along the first and second directions are substantially the same. Therefore, in the subsequent formal lateral etching process to remove the parasitic portion of the semiconductor material layer 411, the etching uniformity of the parasitic portion of the semiconductor material layer 411 throughout the circumference can be guaranteed under the same etching environment, reducing the probability or degree of etching affected by the size difference of the parasitic portion, or avoiding the semiconductor structure 410 being affected by etching, thereby ensuring the integrity and effective performance of the semiconductor device.
[0042] In some possible embodiments, replacing the multilayer first insulating layer 220 on both sides of the first trench 201 with a multilayer first conductive layer 300 extending along the second direction in step S102 above includes the following steps: Based on the first trench 201, the exposed multilayer first insulating layer 220 on the sidewall of the first trench 201 is etched back to form a first groove (not shown in the figure); a first conductive layer 300 extending in the second direction is formed in the first groove.
[0043] In this embodiment, by etching back the exposed multilayer first insulating layer 220 on the sidewall of the first trench 201, multiple first grooves are formed on both sides of the first trench 201 and extending along the second direction. The first groove near the first via 202 connects the first trench 201 and the first via 202. Therefore, the first conductive layer 300 formed in the first groove can be connected to the semiconductor structure 410 formed in the first via 202.
[0044] Optionally, the first conductive layer 300 can serve as a bit line of a semiconductor device, and the portion of the first conductive layer 300 near the first via 202 in the first direction can serve as the first source and drain of a transistor in the semiconductor device.
[0045] In some possible embodiments, replacing the multilayer first insulating layer 220 around the second via 203 with the multilayer first electrode structure 510 in step S102 above includes the following steps: Based on the second via 203, the multilayer first insulating layer 220 exposed on the sidewall of the second via 203 is etched back to form a second groove (not shown in the figure); a conformal first electrode structure 510 is deposited in the second groove, the first electrode structure 510 covers the inner sidewall of the second groove and has an opening facing the second via 203.
[0046] In this embodiment, the exposed multilayer first insulating layer 220 on the sidewall of the second via 203 is etched back to form multiple second grooves located on the outer periphery of the second via 203, and the second grooves near the first via 202 connect the second via 203 and the first via 202. Therefore, the conformal first electrode structure 510 deposited in the second groove can be connected to the semiconductor structure 410 formed in the first via 202. In some possible embodiments, the step S103 above, in which a second sacrificial structure 141 and a first sacrificial structure 121 are formed sequentially around the periphery of the first via 202 between any two adjacent first conductive layers 300 and between the first electrode structure 510, includes the following steps: A first sacrificial layer 120 is deposited based on the first via 202, and the first sacrificial layer 120 conformally covers each first conductive layer 300 and each first electrode structure 510.
[0047] Optionally, after this step, the method further includes: depositing a conformal protective layer 130 on the sidewall of the first trench 201 and filling it with the sacrificial material layer 110; filling the groove formed by the first electrode structure 510 with the sacrificial material layer 110; and depositing a conformal protective layer 130 on the sidewall of the second via 203 and filling it with the sacrificial material layer 110. A schematic diagram of the film structure obtained after this step is shown below. Figures 5-6 As shown.
[0048] Based on the first via 202, the first sacrificial layer 120 is etched laterally to form a first sacrificial structure 121 surrounding the first via 202; each first conductive layer 300 and each first electrode structure 510 are partially exposed in the first sacrificial structure 121.
[0049] Optionally, the schematic diagram of the membrane structure obtained after this step is as follows: Figures 7-8 As shown.
[0050] A second sacrificial layer 140 is deposited based on the first via 202, and the second sacrificial layer 140 conformally covers the first sacrificial structure 121, each first conductive layer 300 and each first electrode structure 510.
[0051] Optionally, the schematic diagram of the membrane structure obtained after this step is as follows: Figures 9-10 As shown.
[0052] The second sacrificial layer 140 is laterally etched based on the first via 202 to form a second sacrificial structure 141 that is wound between the first via 202 and the first sacrificial structure 121; each first conductive layer 300 and each first electrode structure 510 are partially exposed in the second sacrificial structure 141.
[0053] Optionally, the schematic diagram of the membrane structure obtained after this step is as follows: Figures 11-12 As shown.
[0054] In this embodiment, a first channel is formed between any two adjacent first conductive layers 300, and a second channel is formed between any two adjacent first electrode structures 510. Subsequently, a conformal first sacrificial layer 120 is deposited in the first via 202, each first channel, and each second channel, and then laterally etched to form a first sacrificial structure 121. A portion of the first sacrificial structure 121 is located in the region of the first channel near the first trench 201, and another portion is located in the region of the second channel near the second via 203.
[0055] Next, a conformal second sacrificial layer 140 is deposited in the first via 202, the first channel of each layer, and the second channel of each layer; the second sacrificial layer 140 is laterally etched through the first via 202 to form a second sacrificial structure 141; a portion of the second sacrificial structure 141 is located in the region of the first channel of each layer near the first sacrificial structure 121, and another portion is located in the region of the second channel near the first sacrificial structure 121.
[0056] Therefore, please refer to Figure 11The second sacrificial structure 141 is connected to the first sacrificial structure 121 on one side and communicates with the first via 202 on the other side. This allows the outer periphery of the semiconductor material layer 411 subsequently deposited in the first via 202 to contact the second sacrificial structure 141, thereby protecting the outer periphery of the semiconductor material layer 411 from damage during the process of removing the first sacrificial structure 121.
[0057] In some possible embodiments, the second sacrificial structure 141 is made of the same material as the first dielectric layer 210.
[0058] Considering that in the manufacturing process of semiconductor devices, it is often necessary to open channels (i.e., such as...) Figures 15-16 As shown, the first trench 201 or the second via 203 is opened, and the exposed first dielectric layer 210 is removed using a relevant etching process.
[0059] Therefore, in this embodiment, the material of the first dielectric layer 210 is used as the second sacrificial structure 141. The second sacrificial structure 141 can be directly removed using existing etching processes to expose the semiconductor material layer 411, which can effectively control costs. Moreover, the etching selectivity of the second sacrificial structure 141 compared to other film layer structures is very high, and it will not have much impact on other film layer structures, thus ensuring the integrity of the existing film layer structures.
[0060] In some possible embodiments, step S105 above, which involves sequentially removing the first sacrificial structure 121 and the second sacrificial structure 141 based on the second via 203 and the first trench 201 to expose the semiconductor material layer 411, includes the following steps: like Figures 15-20 Based on the second via 203 and the first trench 201, the first sacrificial structure 121 is removed by wet etching, and the second sacrificial structure 141 is removed by dry etching, exposing the semiconductor material layer 411.
[0061] In this embodiment, the wet etching process for removing the first sacrificial structure 121 will cause some damage to the semiconductor material layer 411. However, in the dry etching process for removing the second sacrificial structure 141, due to the inherent characteristics of the semiconductor material layer 411, by selecting appropriate etching parameters, the semiconductor material layer 411 will not be damaged.
[0062] In some possible embodiments, the wet etching rate of the first sacrificial structure 121 is greater than that of the second sacrificial structure 141. The dry etching rate of the second sacrificial structure 141 is greater than that of the semiconductor material layer 411.
[0063] In this embodiment, the wet etching rate of the first sacrificial structure 121 is greater than the wet etching rate of the second sacrificial structure 141. The faster the wet etching rate of the first sacrificial structure 121 relative to the second sacrificial structure 141, the higher the selectivity, thus ensuring that the second sacrificial structure 141 always protects the outer periphery of the semiconductor material layer 411 from damage during the etching process of the first sacrificial structure 121. The dry etching rate of the second sacrificial structure 141 is greater than the dry etching rate of the semiconductor material layer 411. The faster the dry etching rate of the second sacrificial structure 141 relative to the semiconductor material layer 411, the higher the selectivity, thus ensuring the integrity of the semiconductor material layer 411.
[0064] In some possible embodiments, the second sacrificial structure 141 is removed by dry etching, including: Dry etching is used to simultaneously remove the first dielectric layer 210 exposed by the second sacrificial structure 141, the first trench 201, and the second via 203.
[0065] In this embodiment, the second sacrificial structure 141 and the first dielectric layer 210 have similar inherent properties, enabling them to provide reliable protection for the covered membrane structure. Furthermore, as... Figures 17-20 As shown, during the removal of the second sacrificial structure 141, a portion of the first dielectric layer 210 exposed by the first trench 201 and the second via 203 is also removed. Since the first dielectric layer 210 serves as an isolation and protective layer between the already formed film structures, the process of removing the first dielectric layer 210 has almost no impact on the other formed film structures; it can be removed and then filled.
[0066] Optionally, it may also include, as follows: Figures 23-24 As shown, the third dielectric layer 150 is filled in the first trench 201 or the second via 203 to facilitate the subsequent fabrication of capacitors or other electronic components.
[0067] In some possible embodiments, the method further includes: A conformal second dielectric layer and a second electrode structure are sequentially deposited within the second via 203. The second dielectric layer fills the opening of the first electrode structure 510 and covers the inner sidewall of the second via 203. The second electrode structure covers the second dielectric layer and fills the second via 203. The first electrode structure 510, the second dielectric layer, and the second electrode structure form a capacitor.
[0068] In this embodiment, after the semiconductor structure 410 is formed and the transistor 400 is manufactured, the capacitor is then fabricated. The first electrode structure 510 of the capacitor is electrically connected to the semiconductor structure 410 of the transistor 400, so that the capacitor and the transistor 400 are electrically connected. The charging and discharging operation of the capacitor is controlled by the transistor 400, thereby enabling data reading or writing.
[0069] It should be noted that, in the embodiments of this application, the structure of each film layer of the semiconductor device can be patterned by a patterning process to manufacture each corresponding film layer.
[0070] It should be noted that the "patterning process" mentioned in the embodiments of this application includes processes such as depositing film layers, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography process" mentioned in the embodiments of this application includes processes such as coating film layers, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods; no specific limitations are made here.
[0071] In the description of the embodiments of this application, it should be understood that a "layer" refers to a thin film of a certain material manufactured on a substrate 100 using a deposition or coating process. If the thin film does not require a patterning process or photolithography process during the entire manufacturing process, the thin film can also be called a layer. If the thin film requires a patterning process or photolithography process during the entire manufacturing process, it can be called a thin film before the patterning process and a layer after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern".
[0072] Based on the same inventive concept, embodiments of this application provide a semiconductor device, including: A stacked structure 200 is disposed on a substrate 100; the stacked structure 200 has a first trench 201 spaced apart along a first direction, a row of first vias 202 and a row of second vias 203, the first trench 201 extending along a second direction; the first direction intersects the second direction and is parallel to the substrate 100.
[0073] The first via 202 is provided with a gate layer 431 extending in a direction perpendicular to the substrate 100, and a plurality of gate insulating structures 420 and a plurality of semiconductor structures 410 sequentially and spaced around the gate layer 431. The plurality of semiconductor structures 410, the plurality of gate insulating structures 420 and the gate layer 431 are used to form a multilayer transistor 400 spaced apart in a direction perpendicular to the substrate 100.
[0074] On both sides of the first trench 201, there are multilayer first conductive layers 300 that are connected to the semiconductor structure 410 of the multilayer transistor 400.
[0075] The outer periphery of the second via 203 is provided with a multilayer first electrode structure 510 that is connected to the semiconductor structure 410 of the multilayer transistor 400.
[0076] On a plane parallel to the substrate 100, the semiconductor structure 410 has the same dimensions in the first direction and the second direction.
[0077] In this embodiment, multilayer transistors 400 are sequentially stacked on a protective layer. Each transistor layer 400 includes at least one transistor 400, and each transistor 400 is electrically connected to a capacitor to form a memory cell. Each transistor 400 includes a semiconductor structure 410, a gate insulating structure 420, and a gate layer 431. During manufacturing, the transistor 400 provided in this embodiment ensures the uniformity of etching of the parasitic portion of the semiconductor material layer 411 before the formation of the semiconductor structure 410 throughout the entire circumference under the same etching environment. This reduces the probability or extent of etching being affected by differences in the size of the parasitic portion, or it can prevent the semiconductor structure 410 from being affected by etching. That is, on a plane parallel to the substrate 100, the dimensions of the semiconductor structure 410 in the first direction and the second direction are the same, thereby ensuring the integrity and effective performance of the semiconductor device.
[0078] Optionally, such as Figure 21 As shown, the portion of the gate layer 431 that is directly opposite the semiconductor structure 410 along the direction parallel to the substrate 100 is the gate 430 of the transistor 400.
[0079] In some possible embodiments, the first conductive layer 300 extends along a second direction and is connected along a first direction to the semiconductor structure 410 of the adjacent transistor 400.
[0080] In this embodiment, the portion of the multilayer first conductive layer 300 extending along the second direction on both sides of the first trench 201 near the first via 202 can serve as the first source and drain of the transistor 400, and each first conductive layer 300 is connected to a plurality of transistors 400 arranged along the second direction.
[0081] Optionally, the semiconductor structure 410 is made of a metal oxide semiconductor material or a silicon-containing material. The metal oxide semiconductor material includes IGZO (Indium Gallium Zinc Oxide), ITO (Indium Tin Oxide), and IWO (Indium Wolfmium Oxide). Oxide (indium tungsten oxide), InGaO (indium gallium oxide), ZnO (zinc oxide), InO (indium oxide), InO (indium oxide), InWO (indium tungsten oxide), SnO (tin oxide), TiO (titanium oxide), InSnO (indium tin oxide), ZnON (nitrogen-doped zinc oxide), MgZnO (magnesium zinc oxide), InZnO (indium zinc oxide), InGaZnO (indium gallium zinc oxide), ZrInZnO (zinc zirconium oxide), HfInZnO (hafnium indium zinc oxide), SnInZnO (tin indium zinc oxide), AlZnO (zinc aluminum oxide), AlSnInZnO (zinc aluminum indium oxide), SiInZnO (zinc silicon oxide), ZnSnO (zinc tin oxide), AlZnSnO (zinc aluminum oxide), GaZnSnO (zinc gallium oxide), ZrZnSnO (zinc zirconium oxide), and InGaSiO (indium gallium silicon oxide), etc.
[0082] In this embodiment, as Figures 25-26 As shown, the semiconductor structure 410 has the same dimensions in the first direction and the second direction, ensuring the dimensional uniformity of the semiconductor structure 410 in all directions. This helps to reduce stress concentration and uneven electric field distribution caused by dimensional differences, thereby improving the reliability and durability of the device. It also helps to achieve more uniform electron migration, reduce current leakage, and improve the read / write speed and power efficiency of the memory.
[0083] In some possible embodiments, the stacked structure 200 further includes: The capacitor includes a first electrode structure 510, a second dielectric layer located within a second via 203, and a second electrode structure (not shown in the figure).
[0084] The first electrode structure 510 has an opening facing the second via 203.
[0085] The second dielectric layer fills the opening of the first electrode structure 510 and covers the inner wall of the second via 203.
[0086] The second electrode structure covers the second dielectric layer and fills the second via 203.
[0087] In this embodiment, the first electrode structure 510 of the capacitor is electrically connected to the semiconductor structure 410 of the transistor 400, so that the capacitor is electrically connected to the transistor 400. The charging and discharging operation of the capacitor is controlled by the transistor 400, thereby realizing the reading or writing of data.
[0088] Optionally, the first electrode structure 510 can be reused as the second source / drain of the transistor 400.
[0089] Optionally, the semiconductor device provided in the embodiments of this application includes a three-dimensional dynamic random access memory.
[0090] Based on the same inventive concept, this application provides an electronic device, including: a semiconductor device manufactured by any of the semiconductor device manufacturing methods provided in the foregoing embodiments, or any of the semiconductor devices provided in the foregoing embodiments.
[0091] In this embodiment, since the electronic device uses any of the semiconductor devices provided in the foregoing embodiments, the principle and technical effects are described in the foregoing embodiments and will not be repeated here.
[0092] Optionally, the electronic device includes a smartphone, computer, tablet, artificial intelligence device, wearable device, or power bank.
[0093] It should be noted that the electronic devices are not limited to the above-mentioned types. Those skilled in the art can set any of the semiconductor devices provided in the above embodiments of this application in different devices according to actual application needs, thereby obtaining the electronic devices provided in the embodiments of this application.
[0094] Those skilled in the art will understand that the electronic devices provided in the embodiments of this application can be specifically designed and manufactured for a desired purpose, or may include known devices in general-purpose computers. These devices have any of the semiconductor devices provided in the various embodiments described above.
[0095] By applying the embodiments of this application, at least the following beneficial effects can be achieved: 1. In the subsequent etching process to remove the first sacrificial structure 121 around the semiconductor material layer 411, the second sacrificial structure 141 acts as a barrier layer or protective layer. It protects the parasitic portion of the semiconductor material layer 411 along the first direction between any two adjacent first conductive layers 300 and first electrode structures 510 from the etching process, preventing premature etching and ensuring that the dimensions of the parasitic portion of the semiconductor material layer 411 along the first and second directions are substantially the same. Therefore, in the subsequent formal lateral etching process to remove the parasitic portion of the semiconductor material layer 411, it ensures the etching uniformity of the entire circumference of the parasitic portion of the semiconductor material layer 411 under the same etching environment, reducing the probability or extent of etching affected by differences in parasitic portion size, or preventing the semiconductor structure 410 from being affected by etching, thereby ensuring the integrity and effective performance of the semiconductor device.
[0096] 2. One side of the second sacrificial structure 141 is connected to the first sacrificial structure 121, and the other side is connected to the first via 202. This allows the outer periphery of the semiconductor material layer 411 subsequently deposited in the first via 202 to contact the second sacrificial structure 141, thereby protecting the outer periphery of the semiconductor material layer 411 from damage during the process of removing the first sacrificial structure 121.
[0097] 3. In this embodiment, the material of the first dielectric layer 210 is used as the second sacrificial structure 141. The second sacrificial structure 141 can be directly removed using existing etching processes to expose the semiconductor material layer 411, which can effectively control costs. Moreover, the etching selectivity of the second sacrificial structure 141 compared to other film layer structures is very large, and it will basically not affect other film layer structures, thus ensuring the integrity of the existing film layer structures.
[0098] 4. The wet etching rate of the first sacrificial structure 121 is greater than that of the second sacrificial structure 141. The faster the wet etching rate of the first sacrificial structure 121 relative to the second sacrificial structure 141, the higher the selectivity, thus ensuring that the second sacrificial structure 141 always protects the outer periphery of the semiconductor material layer 411 from damage during the etching process of the first sacrificial structure 121. The dry etching rate of the second sacrificial structure 141 is greater than that of the semiconductor material layer 411. The faster the dry etching rate of the second sacrificial structure 141 relative to the semiconductor material layer 411, the higher the selectivity, thus ensuring the integrity of the semiconductor material layer 411.
[0099] In the description of this application, the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate directions or positional relationships based on the exemplary directions or positional relationships shown in the accompanying drawings. They are used to facilitate the description or simplification of the embodiments of this application and are not intended to indicate or imply that the device or component referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0100] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.
[0101] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.
[0102] The above description is only a partial embodiment of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, include: A stacked structure is formed on a substrate, the stacked structure comprising alternating layers of first dielectric layers and layers of first insulating layers, and having first trenches, a row of first vias and a row of second vias spaced apart along a first direction, the first trenches extending along a second direction; the first direction intersects the second direction and is parallel to the substrate. The multilayer first insulating layer on both sides of the first trench is replaced with a multilayer first conductive layer extending along the second direction, and the multilayer first insulating layer around the second via is replaced with a multilayer first electrode structure; the first conductive layer and the first electrode structure are both exposed in the first via. Between any two adjacent first conductive layers and between the first electrode structure, a second sacrificial structure and a first sacrificial structure are formed sequentially around the periphery of the first via. A conformal semiconductor material layer, a gate insulating layer, and a gate layer are sequentially deposited within the first via. Based on the second via and the first trench, the first sacrificial structure and the second sacrificial structure are removed sequentially to expose the semiconductor material layer; The exposed semiconductor material layer and the gate insulating layer are removed sequentially, and the remaining semiconductor material layer and the gate insulating layer each form a semiconductor structure and a gate insulating structure, respectively.
2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Replacing the multiple layers of the first insulating layer on both sides of the first trench with multiple layers of the first conductive layer extending along the second direction includes: Based on the first trench, the exposed multilayer first insulating layer on the sidewall of the first trench is etched back to form a first groove; and a first conductive layer extending along the second direction is formed in the first groove.
3. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Replacing the multilayer first insulating layer around the second via with a multilayer first electrode structure includes: Based on the second via, the exposed multilayer first insulating layer on the sidewall of the second via is etched back to form a second groove; a conformal first electrode structure is deposited in the second groove, the first electrode structure covering the inner sidewall of the second groove and having an opening facing the second via.
4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Between any two adjacent first conductive layers and between the first electrode structure, a second sacrificial structure and a first sacrificial structure are formed sequentially around the periphery of the first via, including: Based on the first via, a first sacrificial layer is deposited, and the first sacrificial layer conformally covers each layer of the first conductive layer and each layer of the first electrode structure. The first sacrificial layer is laterally etched based on the first via to form the first sacrificial structure surrounding the first via; each first conductive layer and each first electrode structure are partially exposed in the first sacrificial structure. Based on the first via, a second sacrificial layer is deposited, and the second sacrificial layer conformally covers the first sacrificial structure, each layer of the first conductive layer and each layer of the first electrode structure; The second sacrificial layer is laterally etched based on the first via to form a second sacrificial structure that is disposed between the first via and the first sacrificial structure; each first conductive layer and each first electrode structure are partially exposed in the second sacrificial structure.
5. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The second sacrificial structure is made of the same material as the first dielectric layer.
6. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Based on the second via and the first trench, the first sacrificial structure and the second sacrificial structure are removed sequentially to expose the semiconductor material layer, including: Based on the second via and the first trench, the first sacrificial structure is removed by wet etching, and the second sacrificial structure is removed by dry etching, exposing the semiconductor material layer.
7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The wet etching rate of the first sacrificial structure is greater than that of the second sacrificial structure; The dry etching rate of the second sacrificial structure is greater than the dry etching rate of the semiconductor material layer.
8. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The second sacrificial structure is removed by dry etching, including: Dry etching is used to simultaneously remove the second sacrificial structure, the first dielectric layer exposed by the first trench, and the first dielectric layer exposed by the second via.
9. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Also includes: A conformal second dielectric layer and a second electrode structure are sequentially deposited within the second via. The second dielectric layer fills the opening of the first electrode structure and covers the inner sidewall of the second via. The second electrode structure covers the second dielectric layer and fills the second via. The first electrode structure, the second dielectric layer, and the second electrode structure form a capacitor.
10. A semiconductor device, characterized in that, include: A semiconductor stacked structure is disposed on a substrate; The semiconductor stacked structure has a first trench spaced along a first direction, a row of first vias and a row of second vias, the first trenches extending along a second direction; the first direction intersects the second direction and is parallel to the substrate; The first via is provided with a gate layer extending in a direction perpendicular to the substrate and a plurality of gate insulating structures and a plurality of semiconductor structures sequentially and spaced around the periphery of the gate layer. The plurality of semiconductor structures, the plurality of gate insulating structures and the gate layer are used to form a multilayer transistor spaced apart in a direction perpendicular to the substrate. The first trench has multiple first conductive layers on both sides that are connected to the semiconductor structure of the multilayer transistor. The outer periphery of the second via is provided with a multilayer first electrode structure that is connected to the semiconductor structure of the multilayer transistor. On a plane parallel to the substrate, the semiconductor structure has the same dimensions in the first direction and the second direction.
11. The semiconductor device according to claim 10, characterized in that, The first conductive layer extends along the second direction and is connected along the first direction to the semiconductor structure of the adjacent transistor.
12. The semiconductor device according to claim 10, characterized in that, The semiconductor stacked structure further includes: The capacitor includes the first electrode structure, a second dielectric layer located within the second via, and a second electrode structure. The first electrode structure has an opening facing the second via; The second dielectric layer fills the opening of the first electrode structure and covers the inner wall of the second via; The second electrode structure covers the second dielectric layer and fills the second via.
13. An electronic device, characterized in that, include: A semiconductor device manufactured by the manufacturing method of any of the semiconductor devices described in claims 1-9 above, or a semiconductor device described in any of the semiconductor devices described in claims 10-12 above.