Method for manufacturing nord flash memory device
By forming an isolation layer and sidewall structure on the sidewall of the hard mask layer in the NORD flash memory device, the chip failure problem caused by floating gate short circuit is solved, ensuring stable device performance and avoiding the negative impact of reduced floating gate lithography window.
Patent Information
- Application Number
- CN202610773464.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-05-29
- Publication Date
- 2026-08-25
AI Technical Summary
In existing NORD flash memory devices, reducing the size of the floating gate opening or the size of the H-type active region to avoid short-circuiting of the floating gate can easily lead to residue at the floating gate connection or misalignment of ion implantation in the N-type doped region, causing chip failure.
Without reducing the exposure window of the floating gate lithography process, an isolation layer is formed on the sidewall of the hard mask layer, and combined with the sidewall structure, the short circuit of the floating gate is avoided. This includes forming an isolation layer and sidewalls on the sidewall of the hard mask layer, defining the window and etching the floating gate polysilicon layer to form a word line structure.
This effectively avoids short circuits in the floating gate, prevents chip failure, maintains the exposure window of the floating gate photolithography process, and ensures stable device performance.
Smart Images
Figure CN122641016A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a NORD flash memory device. Background Technology
[0002] NORD flash memory devices, with their advantages of low cost, low power consumption, and fast access speed, have occupied an increasingly important position in the field of non-volatile memory. With the development of technology, the application of data storage media has also shifted from some traditional non-volatile memories to flash memory. High-capacity solid-state storage devices with flash memory as the main storage medium have become one of the mainstream solutions for data storage today.
[0003] In the F95H process, the Bin51 PGM failed during CP1 testing. The cause of failure was a short circuit (FG short) between the two floating gates at the shared contact hole (share CT). Figure 1 and Figure 2 As shown. The most direct way to solve this failure is to reduce the aperture size of the FG, and etch away the shorting FG during the control gate contact via (CGCT) etching; or reduce the critical dimension of the H-type active region (H-ACT line CD), such as... Figure 4 and Figure 5 As shown, during the etching of the shallow trench isolation structure (STI), the shorting point FG is etched open.
[0004] However, directly reducing the opening size of the FG will cause scum to appear at the FG strap connection, such as... Figure 3 As shown; directly reducing the width of the ACT "H" dimension will cause dislocation after ion implantation (NPLUSIMP) of the N-type doped region at H-ACT, resulting in failure of CP1 Bin631 MPT, such as Figure 6 As shown. Summary of the Invention
[0005] The purpose of this invention is to provide a method for manufacturing a NORD flash memory device, which aims to avoid short circuits between adjacent floating gates at H-ACT without reducing the exposure window of the floating gate photolithography process.
[0006] To achieve the above objectives, the present invention provides a method for manufacturing a NORD flash memory device, comprising:
[0007] A semiconductor structure is provided, the semiconductor structure including a substrate, a gate stack on the substrate and a hard mask layer on the gate stack, the gate stack including a floating gate polysilicon layer, an inter-gate dielectric layer and a control gate polysilicon layer from bottom to top;
[0008] Pattern the hard mask layer to define a first window;
[0009] An isolation layer and a first sidewall located on the sidewall of the hard mask layer are formed within the first window, defining a second window;
[0010] Etch the control gate polysilicon layer and the inter-gate dielectric layer along the second window;
[0011] A second sidewall and a third sidewall are formed sequentially, wherein the second sidewall at least covers the sidewalls of the control gate polysilicon layer and the inter-gate dielectric layer, and the third sidewall at least covers the second sidewall; and...
[0012] The floating gate polysilicon layer is etched to define the word line window.
[0013] Optionally, the formation of the isolation layer includes:
[0014] An isolation material layer is formed on the substrate, the isolation material layer covering the bottom and sidewalls of the first window and extending to cover the surface of the hard mask layer;
[0015] The isolation material layer is etched to form an isolation layer on the sidewall of the hard mask layer.
[0016] Optionally, the isolation layer includes a nitrided layer.
[0017] Optionally, the thickness of the isolation layer is 100 angstroms to 200 angstroms.
[0018] Optionally, the isolation layer is a silicon nitride layer, and the thickness of the isolation layer is 150 angstroms.
[0019] Optionally, a gate oxide layer is formed on the substrate, and the gate stack is located on the gate oxide layer.
[0020] Optionally, the inter-gate dielectric layer includes an ONO structure consisting of a first oxide layer, a nitride layer, and a second oxide layer stacked from bottom to top.
[0021] Optionally, after etching the floating gate polysilicon layer, the process further includes:
[0022] A tunneling oxide layer is formed on the sidewall of the character line window;
[0023] A polysilicon layer for word lines is filled into the word line window;
[0024] The polysilicon layer for the word lines is subjected to chemical mechanical polishing and etch-back.
[0025] An oxide layer is formed on the polysilicon layer of the word line to form a word line structure.
[0026] Optionally, after forming the character line structure, the following may also be included:
[0027] Remove the hard mask layer and the isolation layer;
[0028] The gate stack is etched to form a gate structure.
[0029] Optionally, the isolation layer material and the hard mask layer material are the same, and the hard mask layer and the isolation layer are removed in the same process step.
[0030] Optionally, the first sidewall includes an oxide layer, the second sidewall includes an oxide layer, and the third sidewall includes a nitrided layer.
[0031] In summary, this invention provides a method for fabricating a NORD flash memory device. A patterned hard mask layer forms a first window, and an isolation layer is formed on the sidewall of the hard mask layer within the first window. The isolation layer is made of the same material as the hard mask layer and is removed together with the hard mask layer during removal. This method for fabricating a NORD flash memory device avoids floating gate short circuits at the H-ACT location without reducing the exposure window of the floating gate lithography process, thereby preventing chip failure caused by floating gate short circuits. Attached Figure Description
[0032] Figures 1 to 6 The image shown is an electron microscope image of a NORD flash memory device, in which... Figure 1 :FG short top view; Figure 2 :FGshort cross section; Figure 3 :FG scum; Figure 4 H-ACT; Figure 5 H-cell top view: Figure 6 :ACTdislocation;
[0033] Figure 7 A schematic flowchart illustrating the fabrication method of a NORD flash memory device provided in an embodiment of the present invention;
[0034] Figures 8A to 8H This is a schematic diagram of the structure corresponding to each step in the fabrication method of a NORD flash memory device according to an embodiment of the present invention.
[0035] The attached figures are labeled as follows:
[0036] 100 - Substrate; 101 - Gate oxide layer; 102 - Floating gate polysilicon layer; 103a - First oxide layer; 103b - Nitride layer; 103c - Second oxide layer; 104 - Control gate polysilicon layer; 105 - Hard mask layer; 106' - Isolation material layer; 106 - Isolation layer; 107 - First sidewall; 108 - Second sidewall; 109 - Third sidewall; 111 - Tunneling oxide layer; 112 - Word line polysilicon layer; 113 - Oxide layer; 110 - First window; 120 - Second window; 130 - Word line window. Detailed Implementation
[0037] To make the content of this invention clearer and easier to understand, the following description, in conjunction with the accompanying drawings, further illustrates the invention. Of course, this invention is not limited to this specific embodiment, and common substitutions well-known to those skilled in the art are also covered within the scope of protection of this invention.
[0038] Secondly, the present invention is described in detail using schematic diagrams. When describing the examples of the present invention in detail, for ease of explanation, the schematic diagrams are not enlarged to a certain extent according to the general proportions, and this should not be regarded as a limitation of the present invention.
[0039] For ease of description, some embodiments of the present invention may use spatially relative terms such as “above,” “below,” “top,” and “under” to describe the relationship between one element or component and another (or more) elements or components as shown in the accompanying drawings of the embodiments. It should be understood that, in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device during use or operation. For example, if the device in the drawings is flipped, it is described as an element or component “below” or “under” other elements or components, and will subsequently be positioned “above” or “on” other elements or components. The terms “first,” “second,” etc., used below are used to distinguish between similar elements and are not necessarily used to describe a particular order or temporal sequence.
[0040] Figure 7 This is a schematic flowchart illustrating a method for fabricating a NORD flash memory device according to an embodiment of the present invention, as shown below. Figure 7 As shown, the method for manufacturing a NORD flash memory device provided in this embodiment includes the following steps:
[0041] Step S01: Provide a semiconductor structure, the semiconductor structure including a substrate, a gate stack on the substrate and a hard mask layer on the gate stack, the gate stack including a floating gate polysilicon layer, an inter-gate dielectric layer and a control gate polysilicon layer from bottom to top;
[0042] Step S02: Pattern the hard mask layer and define the first window;
[0043] Step S03: An isolation layer and a first sidewall located on the sidewall of the hard mask layer are formed within the first window to define the second window;
[0044] Step S04: Etch the control gate polysilicon layer and the inter-gate dielectric layer along the second window;
[0045] Step S05: Sequentially form a second sidewall and a third sidewall, wherein the second sidewall at least covers the sidewall of the control gate polysilicon layer, and the third sidewall covers the second sidewall;
[0046] as well as,
[0047] Step S06: Etch the floating gate polysilicon layer to define the word line window.
[0048] Figures 8A to 8H This is a schematic diagram showing the structural steps corresponding to each step in the fabrication method of a NORD flash memory device according to an embodiment of the present invention. Please refer to... Figure 7 As shown, and in combination Figures 8A to 8H This invention provides a detailed description of the method for manufacturing the NORD flash memory device.
[0049] First, refer to Figure 8A As shown, steps S01 and S02 are performed to provide a semiconductor structure, which includes a substrate 100, a gate stack on the substrate 100, and a hard mask layer 105 on the gate stack. The gate stack includes, from bottom to top, a floating gate polysilicon layer 102, an inter-gate dielectric layer, and a control gate polysilicon layer 104. The hard mask layer 105 (FGSN_ET) is patterned, and a first window 110 is defined.
[0050] Specifically, the substrate 100 can be a silicon substrate, and the inter-gate dielectric layer includes an ONO structure composed of a first oxide layer 103a, a nitride layer 103b, and a second oxide layer 103c stacked from bottom to top. For example, the first oxide layer 103a and the second oxide layer 103c are silicon oxide layers, and the nitride layer 103b is a silicon nitride layer. The hard mask layer 105 is located on the control gate polysilicon layer 104, and the material of the hard mask layer 105 is at least one of silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbide nitride, and silicon oxynitride.
[0051] A gate oxide layer 101 is formed on the substrate 100, and the gate stack is located on the gate oxide layer 101. The gate oxide layer 101 can be formed by methods such as low-pressure chemical vapor deposition, atomic layer deposition, thermal oxidation, or molecular beam epitaxy. The gate oxide layer 101 is made of silicon oxide to enhance interlayer adhesion. For example, the gate oxide layer 101 has a thickness of 90 angstroms, the floating gate polysilicon layer 102 has a thickness of 300 angstroms, the control gate polysilicon layer 103 has a thickness of 600 angstroms, and the patterned hard mask layer 105 has a thickness of 3300 angstroms.
[0052] Next, refer to Figure 8B , Figure 8C and Figure 8D As shown, in step S03, an isolation layer 106 and a first sidewall 107 located on the sidewall of the hard mask layer 105 are formed in the first window 10, thereby defining the second window 120.
[0053] Specifically, the formation of the isolation layer 106 includes:
[0054] An isolation material layer 106' is formed on the substrate, the isolation material layer 106' covering the bottom and sidewalls of the first window 110, and extending to cover the surface of the hard mask layer 105, such as... Figure 8B As shown;
[0055] Etch the isolation material layer 106' to form an isolation layer 106 on the sidewall of the hard mask layer 105, such as... Figure 8C As shown.
[0056] The isolation layer 106 is located on the sidewall of the hard mask layer 105, exposing the control gate polysilicon layer 104 within the first window 110. The first sidewall 107 is located on the sidewall of the isolation layer 106 and covers part of the exposed control gate polysilicon layer 104. Figure 8D As shown.
[0057] In this embodiment, the isolation layer 106 includes a nitride layer, for example, the isolation layer is a silicon nitride layer, the first sidewall 107 includes an oxide layer, and the thickness of the isolation layer 106 is 100 angstroms to 200 angstroms, for example, the thickness of the isolation layer 106 is 150 angstroms.
[0058] In this embodiment, the first window 110 formed by the patterned hard mask layer 105 (FGSN_ET) corresponds to the opening size of the floating gate. The exposure window of the floating gate is not changed in the floating gate photolithography process. Instead, an isolation layer 106 is formed on the sidewall of the hard mask layer 105 within the first window, which avoids the problem of short circuit (FG short) between the two floating gates sharing the contact hole in the subsequent gate structure formation.
[0059] Next, refer to Figure 8E As shown, steps S04 and S05 are performed, etching is performed along the second window 120 of the control gate polysilicon layer 104 and the inter-gate dielectric layer until the floating gate polysilicon layer 102 is exposed; a second sidewall 108 and a third sidewall 109 are sequentially formed, wherein the second sidewall 108 at least covers the sidewalls of the control gate polysilicon layer 104 and the inter-gate dielectric layer, and the third sidewall 109 at least covers the second sidewall 108. The second sidewall 108 includes an oxide layer, and the third sidewall 109 includes a nitride layer.
[0060] Next, continue to refer to Figure 8E As shown, step S06 is executed to etch the floating gate polysilicon layer 102 and define the word line window 130.
[0061] Furthermore, the fabrication method of the NORD flash memory device provided in this embodiment of the invention further includes: after etching the floating gate polysilicon layer 102, forming a tunneling oxide layer 111 on the sidewall of the word line window 130; filling the word line window 130 with a word line polysilicon layer 112; and performing chemical mechanical polishing and etch-back on the word line polysilicon layer 112; forming an oxide layer 113 on the word line polysilicon layer 112 to form a word line structure, such as... Figure 8F As shown.
[0062] Furthermore, the method for fabricating the NORD flash memory device provided in this embodiment of the invention further includes: after forming the word line structure, removing the hard mask layer 105 and the isolation layer 106, as shown below. Figure 8G As shown, furthermore, the material of the isolation layer 106 is the same as that of the hard mask layer 105, and the hard mask layer 105 and the isolation layer 106 are removed in the same process step; the gate stack is etched to form a gate structure, as shown. Figure 8H As shown. In this embodiment, the isolation layer 106 and the hard mask layer 105 formed in step S03 are removed before the etching process of the gate stack, without affecting the structure of the Nord flash memory device.
[0063] In summary, this invention provides a method for fabricating a NORD flash memory device. A patterned hard mask layer forms a first window, and an isolation layer is formed on the sidewall of the hard mask layer within the first window. The isolation layer is made of the same material as the hard mask layer and is removed together with the hard mask layer during removal. This method for fabricating a NORD flash memory device avoids floating gate short circuits at the H-ACT region without reducing the exposure window of the floating gate lithography process, thereby preventing chip failure caused by floating gate short circuits.
[0064] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.
Claims
1. A method for fabricating a NORD flash memory device, characterized in that, include: A semiconductor structure is provided, the semiconductor structure including a substrate, a gate stack on the substrate and a hard mask layer on the gate stack, the gate stack including a floating gate polysilicon layer, an inter-gate dielectric layer and a control gate polysilicon layer from bottom to top; Pattern the hard mask layer to define a first window; An isolation layer and a first sidewall located on the sidewall of the hard mask layer are formed within the first window, defining a second window; Etch the control gate polysilicon layer and the inter-gate dielectric layer along the second window; A second sidewall and a third sidewall are formed sequentially, wherein the second sidewall at least covers the sidewalls of the control gate polysilicon layer and the inter-gate dielectric layer, and the third sidewall at least covers the second sidewall; and... The floating gate polysilicon layer is etched to define the word line window.
2. The method for fabricating a NORD flash memory device according to claim 1, characterized in that, The formation of the isolation layer includes: An isolation material layer is formed on the substrate, the isolation material layer covering the bottom and sidewalls of the first window and extending to cover the surface of the hard mask layer; The isolation material layer is etched to form an isolation layer on the sidewall of the hard mask layer.
3. The method for fabricating a NORD flash memory device according to claim 1, characterized in that, The isolation layer includes a nitrided layer.
4. The method for fabricating a NORD flash memory device according to claim 3, characterized in that, The thickness of the isolation layer is 100 angstroms to 200 angstroms.
5. The method for fabricating a NORD flash memory device according to claim 4, characterized in that, The isolation layer is a silicon nitride layer, and the thickness of the isolation layer is 150 angstroms.
6. The method for manufacturing a NORD flash memory device according to claim 1, characterized in that, A gate oxide layer is formed on the substrate, and the gate stack is located on the gate oxide layer.
7. The method for fabricating a NORD flash memory device according to claim 1, characterized in that, The inter-gate dielectric layer comprises an ONO structure consisting of a first oxide layer, a nitride layer, and a second oxide layer stacked from bottom to top.
8. The method for manufacturing a NORD flash memory device according to claim 1, characterized in that, After etching the floating gate polysilicon layer, the process further includes: A tunneling oxide layer is formed on the sidewall of the character line window; A polysilicon layer for word lines is filled into the word line window; The polysilicon layer for the word lines is subjected to chemical mechanical polishing and etch-back. An oxide layer is formed on the polysilicon layer of the word line to form a word line structure.
9. The method for fabricating a NORD flash memory device according to claim 8, characterized in that, After forming the character line structure, it also includes: Remove the hard mask layer and the isolation layer; The gate stack is etched to form a gate structure.
10. The method for fabricating a NORD flash memory device according to claim 9, characterized in that, The isolation layer material is the same as the hard mask layer material, and the hard mask layer and the isolation layer are removed in the same process step.
11. The method for manufacturing a NORD flash memory device according to claim 1, characterized in that, The first sidewall includes an oxide layer, the second sidewall includes an oxide layer, and the third sidewall includes a nitrided layer.