Display device and electronic device having the same

Abstract

The present disclosure provides a display device and an electronic device including the same. The display device includes a substrate including a display area and a non-display area surrounding the display area; a pixel circuit overlapping the display area and including a first thin film transistor including a first semiconductor layer and a first gate electrode; and a driving circuit connected to the pixel circuit, overlapping the non-display area, and including a second thin film transistor including a second semiconductor layer and a second gate electrode. The first semiconductor layer includes a first oxide semiconductor material, the second semiconductor layer includes a second oxide semiconductor material, and an electron mobility of the second thin film transistor is higher than an electron mobility of the first thin film transistor.

Description

[0001] This application claims priority and all benefits arising therefrom to Korean Patent Application No. 10-2025-0024092, filed on February 25, 2025, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] One or more embodiments relate to a display device and an electronic device including a display device. Background Technology

[0003] Among display devices, organic light-emitting diode (OLED) displays have attracted attention as a next-generation display with advantages such as wide viewing angle, excellent contrast ratio, and fast response speed.

[0004] Typically, thin-film transistors and organic light-emitting diodes (OLEDs), which serve as display elements, are formed on a substrate, and the OLEDs emit light to operate the organic light-emitting display device. These organic light-emitting display devices can be used as display units in small products such as mobile phones, as well as as display units in large products such as televisions. Summary of the Invention

[0005] The purpose of one or more embodiments is to provide a display device with excellent component characteristics and display quality, as well as an electronic device including the display device.

[0006] Other aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practice of the embodiments presented in this disclosure.

[0007] According to one or more embodiments, a display device is provided, comprising: a substrate including a display area and a non-display area surrounding the display area; a pixel circuit overlapping the display area and including a first thin-film transistor, the first thin-film transistor including a first semiconductor layer and a first gate electrode; and a driving circuit connected to the pixel circuit, overlapping the non-display area, and including a second thin-film transistor, the second thin-film transistor including a second semiconductor layer and a second gate electrode, wherein the first semiconductor layer includes a first oxide semiconductor material, the second semiconductor layer includes a second oxide semiconductor material, and the electron mobility of the second thin-film transistor is higher than that of the first thin-film transistor.

[0008] In one embodiment, the first semiconductor layer may include a crystalline oxide semiconductor material, and the second semiconductor layer may include an amorphous oxide semiconductor material.

[0009] In this embodiment, the first semiconductor layer and the second semiconductor layer can be arranged in the same layer.

[0010] In some embodiments, the first thin-film transistor may further include a third semiconductor layer disposed on the first semiconductor layer.

[0011] In this embodiment, the third semiconductor layer and the second semiconductor layer may comprise the same material.

[0012] In an embodiment, the third semiconductor layer may include an amorphous oxide semiconductor material, and the first semiconductor layer may include a crystalline oxide semiconductor material.

[0013] In an implementation, the third semiconductor layer may overlap with the first semiconductor layer.

[0014] In an implementation, the width of the third semiconductor layer may be smaller than the width of the first semiconductor layer.

[0015] In this implementation, the thickness of the third semiconductor layer and the thickness of the first semiconductor layer can be equal to each other.

[0016] In an implementation, the thickness of the third semiconductor layer and the thickness of the second semiconductor layer can be equal to each other, and the thickness of the second semiconductor layer can be less than the thickness of the first semiconductor layer.

[0017] In an implementation, the width of the third semiconductor layer may be smaller than the width of the first semiconductor layer but larger than the width of the first gate electrode.

[0018] In one implementation, the first thin-film transistor may be a driving transistor of a pixel circuit.

[0019] In an implementation, each of the first semiconductor layer and the second semiconductor layer may include indium, and the indium content of the first semiconductor layer may be greater than the indium content of the second semiconductor layer.

[0020] According to one or more embodiments, a display device is provided, comprising: a substrate including a display area and a non-display area surrounding the display area; a pixel circuit overlapping the display area; and a light-emitting element electrically connected to the pixel circuit and generating light, wherein the pixel circuit includes: a driving transistor including a drain electrode connected to a first node, a gate electrode connected to a second node, and a source electrode connected to a third node; a switching transistor applying a data signal to the first node in response to a scan signal; and an initialization transistor applying an initialization voltage to the second node in response to an initialization control signal, and the driving transistor including a first semiconductor layer comprising a crystalline oxide semiconductor material.

[0021] In an embodiment, the first semiconductor layer may include indium, and the indium content of the first semiconductor layer may be greater than or equal to 80 at.

[0022] In an embodiment, the driving transistor may further include a third semiconductor layer disposed on the first semiconductor layer, and the third semiconductor layer may include an amorphous oxide semiconductor material.

[0023] In this implementation, the thickness of the third semiconductor layer and the thickness of the first semiconductor layer can be equal to each other.

[0024] In this implementation, the thickness of the third semiconductor layer may be less than the thickness of the first semiconductor layer.

[0025] In an implementation, the width of the third semiconductor layer may be smaller than the width of the first semiconductor layer.

[0026] In an embodiment, the display device may further include a driving circuit that overlaps with the non-display area and includes an output transistor, wherein the output transistor may include a second semiconductor layer comprising an amorphous oxide semiconductor material.

[0027] According to one or more embodiments, an electronic device including a display device is provided, wherein the display device includes: a substrate including a display area and a non-display area surrounding the display area; a pixel circuit overlapping the display area and including a first thin-film transistor, the first thin-film transistor including a first semiconductor layer and a first gate electrode; and a driving circuit connected to the pixel circuit, overlapping the non-display area, and including a second thin-film transistor, the second thin-film transistor including a second semiconductor layer and a second gate electrode, wherein the first semiconductor layer includes a first oxide semiconductor material, the second semiconductor layer includes a second oxide semiconductor material, and the electron mobility of the second thin-film transistor is higher than that of the first thin-film transistor.

[0028] In one embodiment, the first semiconductor layer may include a crystalline oxide semiconductor material, and the second semiconductor layer may include an amorphous oxide semiconductor material.

[0029] According to one or more embodiments, an electronic device including a display device is provided, wherein the display device includes: a substrate including a display area and a non-display area surrounding the display area; a pixel circuit overlapping the display area; and a light-emitting element electrically connected to the pixel circuit and generating light. The pixel circuit includes: a driving transistor including a drain electrode connected to a first node, a gate electrode connected to a second node, and a source electrode connected to a third node; a switching transistor applying a data signal to the first node in response to a scan signal; and an initialization transistor applying an initialization voltage to the second node in response to an initialization control signal, wherein the driving transistor includes a first semiconductor layer comprising a crystalline oxide semiconductor material. Attached Figure Description

[0030] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings.

[0031] Figure 1 This is a schematic plan view of a display device according to an embodiment.

[0032] Figure 2 This is a schematic diagram of the equivalent circuit of a pixel according to an implementation method.

[0033] Figure 3A and Figure 3B It shows that they are respectively along Figure 1 A cross-sectional view of an example plane cut by lines A-A' and B-B'.

[0034] Figure 4A and Figure 4B This is a cross-sectional view of a display device according to another embodiment.

[0035] Figure 5A and Figure 5B This is a cross-sectional view of a display device according to another embodiment.

[0036] Figure 6A and Figure 6B This is a cross-sectional view of a display device according to another embodiment.

[0037] Figure 7A and Figure 7B This is a cross-sectional view of a display device according to another embodiment.

[0038] Figures 8A to 8H This is a cross-sectional view showing a method for manufacturing a display device according to an embodiment.

[0039] Figure 9 This is a block diagram of an electronic device according to an embodiment.

[0040] Figure 10 These are schematic diagrams of electronic devices according to various embodiments. Detailed Implementation

[0041] This disclosure can have various modifications and implementations, and specific embodiments are shown in the accompanying drawings and described in detail in the detailed description. The effects and features of this disclosure, as well as the methods for implementing them, will become apparent from the embodiments described in detail herein in conjunction with the accompanying drawings. However, this disclosure is not limited to the embodiments disclosed below and can be implemented in various forms.

[0042] In the following implementation, terms such as “first” or “second” are not used in a limiting sense, but rather to distinguish one component from another.

[0043] In the following implementation, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0044] In the following implementation, terms such as “comprising” or “having” mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0045] In the following embodiments, when various components such as layers, films, regions, and plates are referred to as being “on” or “above” other components, this includes not only cases where they are “directly” above other components, but also cases where other components are inserted between them.

[0046] To be understood, the features described in this article using relative terms such as “high” or “low” can refer to features that satisfy (e.g., greater than, less than, etc.) a threshold associated with the feature, or they can refer to the relative level of the feature.

[0047] In the examples below, unless the context clearly indicates otherwise, terms such as connection or combination do not necessarily mean a direct connection or combination and / or a fixed connection or combination of two components, and do not exclude the presence of another component between the two components.

[0048] In the accompanying drawings, the dimensions of the components may be exaggerated or reduced for ease of explanation. For example, the dimensions and / or thickness of each component shown in the drawings are arbitrarily shown for ease of explanation, and therefore this disclosure is not necessarily limited to what is shown.

[0049] In some implementations, a particular sequence of processes may be performed in a different order than that described, provided that implementation is otherwise feasible. For example, two processes described in sequence may be performed substantially simultaneously, or they may be performed in the reverse order of their description.

[0050] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In examples described with reference to the drawings, the same or corresponding parts are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0051] Figure 1 This is a schematic plan view of the display device 10 according to the embodiment.

[0052] refer to Figure 1The display device 10 can be applied to various electronic devices, such as small and medium-sized electronic devices (e.g., tablet PCs, smartphones, car navigation units, cameras, central information displays (CIDs) installed in vehicles, watch-type electronic devices, personal digital assistants (PDAs), portable multimedia players (PMPs), game consoles), medium and large electronic devices (e.g., televisions, billboards, monitors, personal computers, laptops), etc. However, these are presented as exemplary embodiments, and it is obvious that they can be employed in other electronic devices without departing from the concept of the invention.

[0053] The display device 10 includes a display panel that provides a display image. The display panel may include an inorganic light-emitting diode (LED) display panel, an organic light-emitting diode (OLED) display panel, a quantum dot (QD) light-emitting diode (QND) display panel, a plasma display panel, a field emission display panel, etc. Hereinafter, an organic light-emitting diode (OLED) display panel is used as an embodiment of the display panel, but the embodiments disclosed herein are not limited to this, and other display panels may be used as embodiments if the same technical concept applies.

[0054] The display device 10 may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA is the area where an image can be displayed, and the non-display area NDA is the area where no image is displayed, and components and / or wires for generating and / or transmitting various signals applied to the display area DA are disposed therein. Figure 1 In the diagram, the area within the boundary line of the square indicated by the dashed line corresponds to the display area DA, and the area outside the boundary line corresponds to the non-display area NDA. The display area DA can typically occupy the center of the display device 10.

[0055] The display area DA may include multiple pixels PX. The multiple pixels PX may be arranged in a matrix orientation on the substrate 100. The shape of each pixel PX may be rectangular or square in a plane, but is not limited to this, and may also be a rhombus with each side tilted in one direction. Each pixel PX may be arranged alternately in a strip or pentile pattern. In some aspects, each of the pixels PX may display a specific color by including one or more light-emitting components that emit light of a specific wavelength.

[0056] In the display area DA, signal lines such as scan lines (also called gate lines) SL, emit control lines ECL, data lines DL, and drive voltage lines PL are also arranged on the substrate 100. The scan lines SL and ECL may extend primarily along a first direction D1, while the data lines DL and PL may extend along a second direction D2 intersecting the first direction D1. Each pixel PX is connected to the scan lines SL, ECL, DL, and PL, and can receive scan signals (also called gate signals), emit control signals, data signals, and drive voltages ELVDD from these signal lines, respectively.

[0057] In the non-display area NDA, a pad portion PP, including pads (not shown) for receiving signals from the outside of the display device 10, is located on the substrate 100. As shown, the pad portion PP may be located at the lower end of the display device 10, but is not limited thereto. The pads of the pad portion PP are electrically connected to wires arranged in the non-display area NDA. A flexible printed circuit film (not shown) capable of transmitting signals and voltages received from the outside may be attached to the pad portion PP.

[0058] Driving means for generating and / or processing various signals for driving pixels PX in display area DA can be located in non-display area NDA and can be located on a flexible printed circuit film bonded to pad portion PP. The driving means may include a data driver for applying data signals to data line DL; a scan driver for applying scan signals to scan line SL; a transmit driver for applying transmit control signals to transmit control line ECL; and a signal controller for controlling the data driver, scan driver, and transmit driver.

[0059] The scan driver and transmit driver are integrated as drive circuits DCa and DCb in the non-display area NDA of the display device 10. Drive circuits DCa and DCb may include drive circuit DCa located to the left of display area DA and drive circuit DCb located to the right of display area DA, and may extend in a second direction D2. Each of drive circuits DCa and DCb may include a scan driver and / or a transmit driver. In addition to or as an alternative to the examples shown, drive circuits DCa and DCb may be located on a single side of display area DA. Drive circuits DCa and DCb may be electrically connected to the scan line SL and the transmit control line ECL. Drive circuits DCa and DCb may include shift registers comprising dependently connected cascaded stages, each stage including multiple transistors and at least one capacitor. Each stage may receive drive circuit signals and generate and output gate signals and / or transmit control signals.

[0060] The data driver and signal controller can be configured as an integrated circuit chip. The integrated circuit chip can be electrically connected to the display device 10 or mounted on the display device 10 in a tape-mount package (TCP). The data driver and signal controller can be formed as a single chip or as separate chips.

[0061] Drive signal lines DSLa and DSLb, which transmit drive circuit signals for operating drive circuits DCa and DCb, are located in the non-display area NDA. Drive signal lines DSLa and DSLb may include drive signal line DSLa located to the left of display area DA and drive signal line DSLb located to the right of display area DA. To avoid complicating the figures, drive signal lines DSLa and DSLb are... Figure 1 While depicted as a single line, the drive signal lines DSLa and DSLb may include multiple signal lines corresponding to multiple signals applied to the drive circuits DCa and DCb, or may include more or fewer signal lines. The drive signal lines DSLa and DSLb are electrically connected to the pad portion PP and may extend in a second direction D2 parallel to the drive circuits DCa and DCb between the drive circuits DCa and DCb and the display area DA.

[0062] The drive circuit signals transmitted from the pad portion PP to the drive circuits DCa and DCb via drive signal lines DSLa and DSLb may include a scan clock signal, a transmit clock signal, a gate low voltage, a gate high voltage, a scan frame signal (also known as a vertical start signal), and a transmit frame signal. The scan clock signal, gate low voltage, and gate high voltage can be transmitted to the scan drivers of the drive circuits DCa and DCb and used to generate scan signals. The transmit clock signal, gate low voltage, and gate high voltage can be transmitted to the transmit drivers of the drive circuits DCa and DCb and used to generate transmit control signals. The scan frame signal can be transmitted to the scan drivers to command the start of a frame used to input scan signals to the display area DA, and the transmit frame signal can be transmitted to the transmit drivers to command the start of a frame used to input transmit control signals to the display area DA.

[0063] A common voltage transmission line (CTL) supplying a common voltage ELVSS to pixel PX is located in the non-display area NDA. The CTL transmits a certain level of the common voltage ELVSS supplied through the pad portion PP to the common electrode of pixel PX. The CTL can be electrically connected to the pad portion PP at both ends and can be configured to surround the display area DA. On the left and right sides of the display area DA, the CTL can be located between the drive circuits DCa and DCb and the drive signal lines DSLa and DSLb.

[0064] The drive voltage transmission line DTL, which supplies the drive voltage ELVDD to pixel PX, is located in the non-display area NDA. The drive voltage transmission line DTL can be electrically connected to the pad portion PP and the drive voltage line PL, and can be located below the display area DA. The drive voltage ELVDD input through the pad portion PP can be applied to pixel PX through the drive voltage transmission line DTL and the drive voltage line PL.

[0065] The non-display area NDA may include a sealing area SR. The sealing area SR may be separate from the display area DA. A sealant 50 may be disposed in the sealing area SR. The sealant 50 may be formed to completely surround the display area DA. The sealant 50 may at least partially overlap with the driving circuits DCa and DCb. In the case where the sealant 50 overlaps with the driving circuits DCa and DCb, the area of ​​the non-display area NDA on the left and right sides of the display area DA can be reduced, thereby reducing the width of the left and right bezels of the display device 10. The portions of the substrate 100 located outside the sealing area SR at the left, right, and top edges of the display area DA may eventually be cut off.

[0066] Each pixel PX of the display device 10 includes a pixel circuit. The wires described above may pass through or surround each pixel PX to apply a drive signal to each pixel circuit. The pixel circuit may include transistors and capacitors, and the transistors may be thin-film transistors. The number of transistors and capacitors in each pixel circuit may vary. A 7T1C structure comprising 7 transistors and 1 capacitor is used below as an example to describe a pixel circuit, but the device is not limited to this, and various other modified pixel PX structures, such as 2T1C, 3T1C, and 6T2C structures, can be applied.

[0067] Figure 2 This is a schematic diagram of the equivalent circuit of a pixel PX according to an implementation method.

[0068] refer to Figure 2 The pixel PX located in the display area DA of the display device 10 according to the embodiment includes thin film transistors T1 to T7, a sustaining capacitor Cst and an organic light-emitting diode OLED, which are connected to display signal lines SL, SL2, ECL, BCL, DL, PL and VIL.

[0069] Thin-film transistors T1 to T7 may include a driving transistor T1, a switching transistor T2, a compensation transistor T3, an initialization transistor T4, an operation control transistor T5, a light emission control transistor T6, and a bypass transistor T7.

[0070] The display signal lines SL, SL2, ECL, BCL, DL, PL, and VIL may include the scan line SL, the front scan line SL2, the transmit control line ECL, the bypass control line BCL, the data line DL, the drive voltage line PL, and the initialization voltage line VIL. The scan line SL and the front scan line SL2 are connected to the scan drivers of the drive circuits DCa and DCb, and can receive the scan signal Sn and the front scan signal Sn-1, respectively. The transmit control line ECL is connected to the transmit drivers of the drive circuits DCa and DCb, and can receive the transmit control signal EM.

[0071] The front scan line SL2 transmits the front scan signal Sn-1 to the initialization transistor T4, the emission control line ECL transmits the emission control signal EM to the operation control transistor T5 and the light emission control transistor T6, and the bypass control line BCL transmits the bypass signal BP to the bypass transistor T7.

[0072] The data line DL can receive the data signal Dm, the drive voltage line PL can receive the drive voltage ELVDD, and the initialization voltage line VIL can receive the initialization voltage VINT. The initialization voltage VINT initializes the drive transistor T1.

[0073] The gate electrode of the driving transistor T1 is connected to the first terminal Cst1 of the sustaining capacitor Cst. The drain electrode of the driving transistor T1 is connected to the driving voltage line PL via the operation control transistor T5. The source electrode of the driving transistor T1 is connected to the anode of the organic light-emitting diode (OLED) via the light-emitting control transistor T6. The driving transistor T1 controls the driving current supplied to the OLED in response to the potential of the second node N2.

[0074] The gate electrode of switching transistor T2 is connected to the scan line SL. One of the source and drain electrodes of switching transistor T2 is connected to the data line DL. The other of the source and drain electrodes of switching transistor T2 is connected to the drain electrode of driving transistor T1 and is connected to the drive voltage line PL via operation control transistor T5. Switching transistor T2 is turned on by the scan signal Sn applied to the scan line SL and provides the data signal Dm applied to the data line DL to the first node N1.

[0075] The gate electrode of compensation transistor T3 is connected to scan line SL. One of the source and drain electrodes of compensation transistor T3 is connected to the source electrode of driving transistor T1 and is connected to the anode of organic light-emitting diode OLED via light emission control transistor T6. The other of the source and drain electrodes of compensation transistor T3 is connected to the source or drain electrode of initialization transistor T4, the first terminal Cst1 of sustaining capacitor Cst, and the gate electrode of driving transistor T1.

[0076] The gate electrode of initialization transistor T4 is connected to the previous scan line SL2. One of the source and drain electrodes of initialization transistor T4 is connected to the initialization voltage line VIL. The other of the source and drain electrodes of initialization transistor T4 is connected to the first terminal Cst1 of the sustaining capacitor Cst and the gate electrode of the driving transistor T1 via compensation transistor T3. Initialization transistor T4 applies an initialization voltage VINT to the second node N2 in response to an initialization control signal. For example, initialization transistor T4 turns on in response to a previous scan signal Sn-1 applied to the previous scan line SL2 and provides the initialization voltage VINT to the second node N2. The second node N2 is initialized by the initialization voltage VINT.

[0077] The gate electrode of the operating control transistor T5 is connected to the emitter control line ECL. One of the source and drain electrodes of the operating control transistor T5 is connected to the drive voltage line PL. The other of the source and drain electrodes of the operating control transistor T5 is connected to the drain electrode of the drive transistor T1, and also to either the source or drain electrode of the switching transistor T2.

[0078] The gate electrode of the light emission control transistor T6 is connected to the emission control line ECL. One of the source and drain electrodes of the light emission control transistor T6 is connected to the source electrode of the driving transistor T1 and to either the source or drain electrode of the compensation transistor T3. The other of the source and drain electrodes of the light emission control transistor T6 is connected to the anode of the organic light-emitting diode (OLED).

[0079] The gate electrode of bypass transistor T7 is connected to the bypass control line BCL. One of the source and drain electrodes of bypass transistor T7 is connected to the source or drain electrode of light emission control transistor T6, and is also connected to the anode of organic light-emitting diode (OLED). The other of the source and drain electrodes of bypass transistor T7 is connected to the initialization voltage line VIL, and is also connected to the source or drain electrode of initialization transistor T4.

[0080] The second terminal, Cst2, of the holding capacitor Cst is connected to the drive voltage line PL. The cathode of the organic light-emitting diode (OLED) is connected to the common voltage transmission line VSL, which transmits the common voltage ELVSS. The common voltage transmission line VSL or the cathode receives the common voltage ELVSS.

[0081] The circuit structure of a pixel (PX) is not limited to Figure 2 The structure shown can be modified to change the number of transistors, the number of capacitors, and the connections between them.

[0082] In some embodiments, thin-film transistors T1 to T7 may comprise an oxide semiconductor material. In some embodiments, thin-film transistors T1 to T7 may all be n-channel MOSFETs (NMOS) comprising an oxide semiconductor material. However, embodiments of this disclosure are not limited thereto, and some of the thin-film transistors T1 to T7 may be n-channel MOSFETs (NMOS), while the remainder may be p-channel MOSFETs (PMOS).

[0083] In the case of oxide semiconductors, carrier mobility is high and leakage current is low, so the voltage drop is not large even with long operating times. That is, in the case of oxide semiconductors, even at low frequency driving, the color change of the image due to voltage drop is not large, so low frequency driving is possible. Therefore, a display device that prevents leakage current and reduces power consumption can be realized by making thin film transistors T1 to T7 include oxide semiconductor materials.

[0084] In some embodiments, the oxide semiconductor is photosensitive, causing fluctuations in current due to external light. Therefore, it is advisable to place a metal layer beneath the oxide semiconductor to absorb or reflect light from the outside. When viewed in a direction perpendicular to the upper surface of the substrate 100 (perpendicular to the first direction D1 and the second direction D2), the metal layer beneath the oxide semiconductor can overlap with the oxide semiconductor.

[0085] Below, for reference Figure 3A and Figure 3B The stacked structure of the display device 10 is described in detail.

[0086] Figure 3A and Figure 3B It shows that they are respectively along Figure 1 A cross-sectional view of an example plane cut by lines A-A' and B-B'.

[0087] Each of the pixel PX in the display area DA and the driving circuit DCa in the non-display area NDA includes multiple thin-film transistors (TFTs). One TFT TRp and one TFT TRd from the plurality of TFTs included in the pixel PX will be described and explained. For convenience, the TFT TRp of the pixel PX is referred to as the first TFT, and the TFT TRd of the driving circuit DCa is referred to as the second TFT. The first TFT TRp shown may be either the driving transistor T1 or the light emission control transistor T6 of the pixel PX, and the second TFT TRd may be an output transistor (also called a buffer transistor) that outputs the scan signal or emission control signal in this stage.

[0088] The substrate 100 may be an insulating substrate including glass, plastic, quartz, ceramic, etc. In the case where the substrate 100 includes plastic, the substrate 100 may include polyimide, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polycarbonate (PC).

[0089] The lower metal layer (BML) can be disposed on the substrate 100. The lower metal layer (BML) may include a material with light-blocking properties. For example, the lower metal layer (BML) may be formed as a single layer or multiple layers, including one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). The lower metal layer (BML) can protect the semiconductor layer by blocking light incident from the outside.

[0090] In one embodiment, the lower metal layer BML may be electrically conductive. The lower metal layer BML may be electrically connected to one of the first source electrode 153p and the first drain electrode 154p of the first thin-film transistor TRp. The lower metal layer BML may be omitted.

[0091] A buffer layer 111 can be placed on the lower metal layer BML. The buffer layer 111 can cover the substrate 100 and the lower metal layer BML. The buffer layer 111 can block impurities that may diffuse from the substrate 100 to the semiconductor layer during the semiconductor layer formation process and reduce the stress applied to the substrate 100. The buffer layer 111 can increase the adhesion of the semiconductor layer. The buffer layer 111 is an insulating layer, but it is referred to as a buffer layer for its functional aspects. The buffer layer 111 may include materials such as silicon oxide (SiO2). x ) or silicon nitride (SiN) x Inorganic insulating materials such as buffer layer 111. For example, buffer layer 111 can be formed as a multilayer film in which multiple inorganic films are alternately stacked. Buffer layer 111 can be omitted.

[0092] The first thin-film transistor TRp and the second thin-film transistor TRd can be disposed on the buffer layer 111. The first thin-film transistor TRp can be formed in the display area DA, and the second thin-film transistor TRd can be formed in the non-display area NDA. The first thin-film transistor TRp may include a first semiconductor layer 120p, a first gate electrode 140p, a first source electrode 153p, and a first drain electrode 154p.

[0093] The first semiconductor layer 120p can be formed on the buffer layer 111. The thickness of the first semiconductor layer 120p can be in the range of 100 Å to 350 Å, preferably in the range of 150 Å to 300 Å.

[0094] The first semiconductor layer 120p may include an oxide semiconductor material. The first semiconductor layer 120p may include a crystalline oxide semiconductor material. For example, the oxide semiconductor material included in the first semiconductor layer 120p may include at least one of the following: InZnO-based oxide semiconductor material (IZO), InGaO-based oxide semiconductor material (IGO), InGaZnO-based oxide semiconductor material (IGZO), InSnO-based oxide semiconductor material (ITO), InGaZnSnO-based oxide semiconductor material (IGZTO), InSnZnO-based oxide semiconductor material (ITZO), ZnO-based oxide semiconductor material, and FeInZnO-based oxide semiconductor material (FIZO). However, embodiments of this disclosure are not limited thereto, and the first semiconductor layer 120p may include other oxide semiconductor materials having high crystallinity and high mobility.

[0095] In an embodiment, the first semiconductor layer 120p may comprise an indium-based oxide semiconductor material having an indium (In) content of 60 atomic percent (at%) or more among all metal elements, and may preferably comprise an indium-based oxide semiconductor material having an indium (In) content of 80 at% or more. For example, the first semiconductor layer 120p may comprise at least one of an InGaO (IGO)-based oxide semiconductor material, an InZnO (IZO)-based oxide semiconductor material, an InGaZnO (IGZO)-based oxide semiconductor material, and an InSnO (ITO)-based oxide semiconductor material, each having an indium (In) content of 80 at% or higher.

[0096] The first channel region 121p can have high mobility characteristics because the first semiconductor layer 120p includes a high concentration of indium (In). Because the first semiconductor layer 120p has high mobility characteristics, the first thin-film transistor TRp can have excellent electrical characteristics.

[0097] The first semiconductor layer 120p can be crystallized by a thermal processing process. Specifically, the first semiconductor layer 120p can be formed by deposition and patterning, followed by thermal processing for crystallization. In an embodiment, the first semiconductor layer 120p may include a crystallization control element that facilitates patterning by preventing crystallization during the deposition process and allowing the first semiconductor layer 120p to crystallize through a subsequent thermal processing process. The crystallization control element is a component with a strong affinity for oxygen and may include at least one of, for example, beryllium (Be), boron (B), carbon (C), aluminum (Al), silicon (Si), iron (Fe), calcium (Ca), tin (Sn), titanium (Ti), tantalum (Ta), vanadium (V), yttrium (Y), zirconium (Zr), hafnium (Hf), lanthanum (La), and germanium (Ge).

[0098] The first semiconductor layer 120p may include a first channel region 121p, a first source region 122p connected to one side of the first channel region 121p, and a first drain region 123p connected to the other side of the first channel region 121p. The first source region 122p and the first drain region 123p may be formed using the selective conductivity of a crystalline oxide semiconductor material. The first channel region 121p may be a non-conductive portion. The first channel region 121p may overlap with the first gate electrode 140p and may overlap with the lower metal layer BML. The first source region 122p and the first drain region 123p may not overlap with the first gate electrode 140p.

[0099] The first channel region 121p may have a crystalline structure and may be non-conductive because the first semiconductor layer 120p comprises a crystalline oxide semiconductor material. For example, the first channel region 121p may comprise at least one of the following crystal structures: cubic crystal structure, bixbyite crystal structure, cubic bixbyite crystal structure, spinel crystal structure, hexagonal crystal structure, and wurtzite crystal structure.

[0100] By having a crystal structure, the first channel region 121p can possess excellent physical and chemical stability. That is, it can prevent the first channel region 121p from being damaged or its properties from being deformed during the manufacturing process and use of the display device 10. Therefore, the first thin-film transistor TRp, as the driving transistor of the pixel circuit, can stably control the driving current supplied to the organic light-emitting diode OLED, and the display device 10 including the first thin-film transistor TRp has excellent driving stability.

[0101] A first gate insulating layer 112p may be disposed on the first semiconductor layer 120p. The first gate insulating layer 112p is an insulating layer comprising an insulating material and may include at least one of silicon oxide, silicon nitride, and metal oxide. For example, the first gate insulating layer 112p may include an inorganic insulating layer such as silicon oxide, silicon nitride, silicon nitride, aluminum oxide, etc. The first gate insulating layer 112p may have a single-film structure or a multilayer film structure.

[0102] The first gate insulating layer 112p can be patterned into a shape corresponding to the first gate electrode 140p. The first gate insulating layer 112p does not cover the first source region 122p and the first drain region 123p, so that the interlayer insulating layer 113 can directly contact the first source region 122p and the first drain region 123p. Therefore, the first source region 122p and the first drain region 123p can become conductive through hydrogen diffusion from the interlayer insulating layer 113.

[0103] However, the embodiments of this disclosure are not limited thereto, and a first gate insulating layer 112p may be formed to cover the buffer layer 111 and the first semiconductor layer 120p.

[0104] The first gate electrode 140p may be disposed on the first gate insulating layer 112p. The first gate electrode 140p may overlap with the first channel region 121p of the first semiconductor layer 120p. The first gate electrode 140p may include at least one of an aluminum-based metal (such as aluminum (Al) or an aluminum alloy), a silver-based metal (such as silver (Ag) or a silver alloy), a copper-based metal (such as copper (Cu) or a copper alloy), a molybdenum-based metal (such as molybdenum (Mo) or a molybdenum alloy), chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The first gate electrode 140p may have a multilayer film structure comprising at least two conductive films with different physical properties.

[0105] Interlayer insulating layer 113 covers the first semiconductor layer 120p and the first gate electrode 140p, and may be disposed on buffer layer 111 or substrate 100. For example, interlayer insulating layer 113 may comprise an inorganic insulating material such as silicon oxide, silicon nitride, silicon nitride, or aluminum oxide.

[0106] The first source electrode 153p and the first drain electrode 154p can be disposed on the interlayer insulating layer 113. Each of the first source electrode 153p and the first drain electrode 154p may include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof. Each of the first source electrode 153p and the first drain electrode 154p may be formed from a single layer comprising a metal or a metal alloy, or may be formed from a multilayer comprising two or more layers.

[0107] Each of the first source electrode 153p and the first drain electrode 154p can be connected to the first semiconductor layer 120p through a contact hole. Specifically, the first source electrode 153p and the first drain electrode 154p can be spaced apart from each other and are respectively connected to the first source region 122p and the first drain region 123p of the first semiconductor layer 120p. The first source electrode 153p and the first drain electrode 154p can transmit electrical signals to the first channel region 121p. In an embodiment, the first source electrode 153p or the first drain electrode 154p can be connected to the lower metal layer BML through a contact hole.

[0108] In the embodiments and accompanying drawings, for ease of explanation, the first source electrode 153p and the first drain electrode 154p are distinguished, and the first source electrode 153p and the first drain electrode 154p are not limited to the accompanying drawings and the above explanation. The first source electrode 153p and the first drain electrode 154p can be interchanged.

[0109] The planarization layer 114 can be positioned on the interlayer insulating layer 113 by covering the first source electrode 153p and the first drain electrode 154p. The planarization layer 114 can eliminate and planarize steps to improve the luminous efficiency of the organic light-emitting diode (OLED) formed thereon. The planarization layer 114 may include an organic insulating material. For example, the planarization layer 114 may include polyimide, polyamide, polyacrylate, polyphenylene ether, polyphenylene sulfide, unsaturated polyester, epoxy resin, phenolic resin, etc.

[0110] An organic light-emitting diode (OLED) can be disposed on a planarization layer 114. The OLED may include a pixel electrode 210, an intermediate layer 220 including a light-emitting layer, and a counter electrode 230. Here, the pixel electrode 210 may be an anode, which is a hole injection electrode, and the counter electrode 230 may be a cathode, which is an electron injection electrode. As another example, the pixel electrode 210 may be a cathode, and the counter electrode 230 may be an anode.

[0111] Pixel electrode 210 can be a (semi-)transparent electrode or a reflective electrode. For example, pixel electrode 210 may include a reflective layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr and their compounds, and a transparent or semi-transparent electrode layer located on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). For example, pixel electrode 210 may have a three-layer structure of ITO / Ag / ITO.

[0112] Pixel defining layer 115 can be disposed on planarization layer 114. Pixel defining layer 115 can prevent arcing at the edge of pixel electrode 210 by increasing the distance between the edge of pixel electrode 210 and the counter electrode 230 above pixel electrode 210. Pixel defining layer 115 comprises one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin, and can be formed by methods such as spin coating.

[0113] At least a portion of the intermediate layer 220 of the organic light-emitting diode (OLED) may be located within an opening formed by the pixel defining layer 115. The light-emitting area of ​​the OLED may be defined by the opening.

[0114] The intermediate layer 220 may include a light-emitting layer. The light-emitting layer may include an organic material containing a fluorescent or phosphorescent material that emits red, green, blue, or white light. The light-emitting layer may be a low-molecular-weight organic material or a high-molecular-weight organic material, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) may optionally be arranged below and above the light-emitting layer.

[0115] The light-emitting layer may have a patterned shape corresponding to each of the pixel electrodes 210. The layers included in the intermediate layer 220 other than the light-emitting layer may be modified in various ways, such as being integrally formed across the multiple pixel electrodes 210.

[0116] The counter electrode 230 can be a transparent electrode or a reflective electrode. For example, the counter electrode 230 can be a transparent or translucent electrode and can include a metal thin film with a low work function, including Li, Ca, LiF, Al, Ag, Mg, and their compounds. In some aspects, the counter electrode 230 may also include a transparent conductive oxide (TCO) film such as ITO, IZO, ZnO, or In2O3 located on the metal thin film. The counter electrode 230 is integrally formed on the entire surface of the display area DA and can be disposed above the intermediate layer 220 and the pixel defining layer 115.

[0117] The second thin-film transistor TRd is disposed in the non-display area NDA and may include a second semiconductor layer 130d, a second gate electrode 140d, a second source electrode 151d, and a second drain electrode 152d.

[0118] The second semiconductor layer 130d can be formed in the same layer as the first semiconductor layer 120p of the first thin-film transistor TRp. For example, both the first semiconductor layer 120p and the second semiconductor layer 130d can be formed on the buffer layer 111. The thickness of the second semiconductor layer 130d can be in the range of 50 Å to 300 Å, preferably in the range of 100 Å to 250 Å.

[0119] The second semiconductor layer 130d may include a second channel region 131d, a second source region 132d connected to one side of the second channel region 131d, and a second drain region 133d connected to the other side of the second channel region 131d. The second source region 132d and the second drain region 133d may be formed using the selective conductivity of the semiconductor material, and the second channel region 131d may be a non-conductive portion. The second channel region 131d may overlap with the second gate electrode 140d, and the second source region 132d and the second drain region 133d may not overlap with the second gate electrode 140d. The second channel region 131d may overlap with the lower metal layer BML. The electron mobility of the second channel region 131d may be higher than the electron mobility of the first channel region 121p of the first semiconductor layer 120p.

[0120] The second semiconductor layer 130d may include an oxide semiconductor material. For example, the second semiconductor layer 130d may include at least one of the following: InZnO-based oxide semiconductor material (IZO), InGaO-based oxide semiconductor material (IGO), InGaZnO-based oxide semiconductor material (IGZO), InSnO-based oxide semiconductor material (ITO), InGaZnSnO-based oxide semiconductor material (IGZTO), InSnZnO-based oxide semiconductor material (ITZO), ZnO-based oxide semiconductor material, and FeInZnO-based oxide semiconductor material (FIZO).

[0121] The second semiconductor layer 130d may include an oxide semiconductor material different from that of the first semiconductor layer 120p. For example, the first semiconductor layer 120p may include an InGaO (IGO) based oxide semiconductor material, and the second semiconductor layer 130d may include an InGaZnSnO (IGZTO) based oxide semiconductor material.

[0122] The second semiconductor layer 130d may comprise an indium-based oxide semiconductor material having an indium (In) content of 50 at% or higher. Preferably, the indium (In) content of the second semiconductor layer 130d may be 60 at% or higher. In an embodiment, the indium (In) content of the total metal elements in the second semiconductor layer 130d may be lower than the indium (In) content of the first semiconductor layer 120p.

[0123] The second semiconductor layer 130d may comprise an amorphous oxide semiconductor material. That is, the second channel region 131d of the second semiconductor layer 130d may be amorphous. Oxide semiconductors have oxygen vacancies and therefore exhibit high electron mobility even in the amorphous state. When the oxide semiconductor crystallizes, the number of oxygen vacancies decreases, and the electron mobility decreases. In other words, a semiconductor layer comprising a crystalline oxide semiconductor material has lower mobility characteristics than in the amorphous state.

[0124] In the display device 10, a second thin-film transistor TRd, including a second semiconductor layer 130d containing amorphous oxide semiconductor material, is disposed on the output transistor of the driving circuit DCa. A high output scan signal or transmit control signal EM can be provided by a thin-film transistor having a relatively high electron mobility compared to the driving transistor T1 of the pixel circuit, and the power consumption of the display device 10 can be reduced. In some aspects, the driving transistor T1 of the pixel circuit can improve the driving stability of the display device 10 by having excellent stability rather than a relatively low electron mobility.

[0125] The second gate insulating layer 112d can be disposed on the second semiconductor layer 130d. The second gate insulating layer 112d is an insulating layer comprising an insulating material, and may comprise at least one of silicon oxide, silicon nitride, and metal oxide. The second gate insulating layer 112d can be formed from the same material using the same manufacturing process as the first gate insulating layer 112p.

[0126] The second gate insulating layer 112d can be patterned into a shape corresponding to the second gate electrode 140d. In this case, the interlayer insulating layer 113 can directly contact the second source region 132d and the second drain region 133d, and the second source region 132d and the second drain region 133d can be conductive due to hydrogen diffusion from the interlayer insulating layer 113 adjacent to the second source region 132d and the second drain region 133d.

[0127] However, the embodiments disclosed herein are not limited thereto, and a second gate insulating layer 112d may be formed to cover both the buffer layer 111 and the second semiconductor layer 130d.

[0128] The second gate electrode 140d may be disposed on the second gate insulating layer 112d. The second gate electrode 140d may overlap with the second channel region 131d of the second semiconductor layer 130d. The second gate electrode 140d may include at least one of aluminum-based metals (such as aluminum (Al) or aluminum alloys), silver-based metals (such as silver (Ag) or silver alloys), copper-based metals (such as copper (Cu) or copper alloys), molybdenum-based metals (such as molybdenum (Mo) or molybdenum alloys), chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The second gate electrode 140d may have a multilayer film structure comprising at least two conductive films with different physical properties.

[0129] The interlayer insulating layer 113 covers the second semiconductor layer 130d and the second gate electrode 140d, and can be disposed on the buffer layer 111 or the substrate 100. The interlayer insulating layer 113 can be integrally formed throughout the display area DA and the non-display area NDA.

[0130] The second source electrode 151d and the second drain electrode 152d can be disposed on the interlayer insulating layer 113. Each of the second source electrode 151d and the second drain electrode 152d may include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

[0131] Each of the second source electrode 151d and the second drain electrode 152d can be connected to the second semiconductor layer 130d through a contact hole. For example, the second source electrode 151d and the second drain electrode 152d are spaced apart from each other and can be connected to the second source region 132d and the second drain region 133d of the second semiconductor layer 130d, respectively. The second source electrode 151d and the second drain electrode 152d can transmit electrical signals to the second channel region 131d.

[0132] In the following text, reference will be made to Figures 4A to 7B Variations of the display device 10 are described, and the same reference numerals will be used in the description and reference. Figures 1 to 3B The display device 10 described has the same configuration.

[0133] Figure 4A and Figure 4B This is a cross-sectional view of a display device 10 according to another embodiment. Figure 4B The first thin-film transistor TRp of the display device 10 and Figure 3B The first thin-film transistor TRp of the display device 10 is different. The differences mentioned above will be explained below, and any repeated explanations will be omitted.

[0134] refer to Figure 4BThe first thin-film transistor TRp may include a first semiconductor layer 120p, a first gate electrode 140p, a first source electrode 153p, a first drain electrode 154p, and a third semiconductor layer 130p.

[0135] The third semiconductor layer 130p can be formed on the first semiconductor layer 120p. The third semiconductor layer 130p can include an oxide semiconductor material. The third semiconductor layer 130p can be formed amorphously. In an embodiment, the third semiconductor layer 130p can be formed of the same material as the second semiconductor layer 130d of the second thin-film transistor TRd. The second semiconductor layer 130d and the third semiconductor layer 130p can be formed of the same material using the same process. The thickness of the third semiconductor layer 130p can be formed to be the same as the thickness of the first semiconductor layer 120p, but is not limited thereto.

[0136] The third semiconductor layer 130p may overlap with the first channel region 121p of the first semiconductor layer 120p. The width of the third semiconductor layer 130p may be formed to correspond to the first channel region 121p of the first semiconductor layer 120p. Here, the width is the length of a cross-section cut along a direction perpendicular to the upper surface of the substrate 100 (perpendicular to the first direction D1 and the second direction D2). That is, in the direction parallel to the upper surface of the substrate 100, the area of ​​the third semiconductor layer 130p may be smaller than the area of ​​the first semiconductor layer 120p.

[0137] The width of the third semiconductor layer 130p can be less than the width of the first semiconductor layer 120p and greater than the width of the first gate electrode 140p. When the side surface of the third semiconductor layer 130p is tapered, the width d2 of the lower surface of the third semiconductor layer 130p can be less than the width of the upper surface of the first semiconductor layer 120p that contacts the lower surface of the third semiconductor layer 130p, and greater than or equal to the width of the upper surface of the first channel region 121p. The width d1 of the upper surface of the third semiconductor layer 130p can be greater than or equal to the width of the first gate electrode 140p. The third semiconductor layer 130p may not overlap with the first source electrode 153p and the first drain electrode 154p.

[0138] The third semiconductor layer 130p can act as a protective layer for the first channel region 121p of the first semiconductor layer 120p, because the width of the third semiconductor layer 130p is formed to correspond to the first channel region 121p of the first semiconductor layer 120p. For example, when the first gate insulating layer 112p is formed, the third semiconductor layer 130p can prevent hydrogen from flowing directly into the first channel region 121p of the first semiconductor layer 120p.

[0139] In some aspects, in the case of the display device 10, it is possible to prevent the length or width of the first channel region 121p of the first semiconductor layer 120p from being formed differently from what is desired, because the side surface of the third semiconductor layer 130p has an inclined surface corresponding to the side surface of the first gate electrode 140p, and the lower surface of the third semiconductor layer 130p is larger than the first channel region 121p.

[0140] In some aspects, in the case of display device 10, the first gate insulating layer 112p may be disposed between the third semiconductor layer 130p and the first gate electrode 140p. The first gate insulating layer 112p may be patterned in a shape corresponding to the first gate electrode 140p, but is not limited thereto, and the first gate insulating layer 112p may also be formed to cover all of the buffer layer 111, the first semiconductor layer 120p and the third semiconductor layer 130p.

[0141] Figure 5A and Figure 5B This is a cross-sectional view of a display device 10 according to another embodiment. Figure 5B The first thin-film transistor TRp of the display device 10 and Figure 3B The first thin-film transistor TRp of the display device 10 is different. The differences mentioned above will be explained below, and any repeated explanations will be omitted.

[0142] refer to Figure 5B The first thin-film transistor TRp may include a first semiconductor layer 120p, a first gate electrode 140p, a first source electrode 153p, a first drain electrode 154p, and a third semiconductor layer 130p.

[0143] The third semiconductor layer 130p can be formed on the first semiconductor layer 120p. The third semiconductor layer 130p may include an oxide semiconductor material. The third semiconductor layer 130p may be formed amorphously. In an embodiment, the third semiconductor layer 130p may be formed of the same material as the second semiconductor layer 130d of the second thin-film transistor TRd. The second semiconductor layer 130d and the third semiconductor layer 130p may be formed of the same material using the same process.

[0144] The third semiconductor layer 130p can be formed to overlap with the first semiconductor layer 120p. In other words, the third semiconductor layer 130p can be formed on the first semiconductor layer 120p to cover the entire first semiconductor layer 120p.

[0145] The third semiconductor layer 130p may include a third channel region 131p, a third source region 132p connected to one side of the third channel region 131p, and a third drain region 133p connected to the other side of the third channel region 131p. The third source region 132p and the third drain region 133p may be formed by the selective conductivity of an amorphous oxide semiconductor material, and the third channel region 131p may be a non-conductive portion. The third channel region 131p may overlap with the first channel region 121p, and the third source region 132p and the third drain region 133p may overlap with the first source region 122p and the first drain region 123p, respectively.

[0146] The third channel region 131p of the third semiconductor layer 130p can have a higher carrier concentration than the first channel region 121p of the first semiconductor layer 120p.

[0147] The first gate electrode 140p can overlap with both the first channel region 121p and the third channel region 131p. The first source electrode 153p and the first drain electrode 154p can be connected to the third source region 132p and the third drain region 133p, respectively. The first source electrode 153p and the first drain electrode 154p can transmit electrical signals to the first channel region 121p and the third channel region 131p.

[0148] The first gate insulating layer 112p may be disposed between the third semiconductor layer 130p and the first gate electrode 140p. The first gate insulating layer 112p may be patterned in a shape corresponding to the first gate electrode 140p, but is not limited thereto, and the first gate insulating layer 112p may also be formed to cover all of the buffer layer 111, the first semiconductor layer 120p and the third semiconductor layer 130p.

[0149] Figure 6A and Figure 6B This is a cross-sectional view of a display device 10 according to another embodiment.

[0150] Figure 6A and Figure 6B The thickness of the third semiconductor layer 130p of the first thin-film transistor TRp and the thickness of the second semiconductor layer 130d of the second thin-film transistor TRd in the display device 10 are the same as those of the first thin-film transistor TRp and the second semiconductor layer 130d of the display device 10. Figure 5A and Figure 5B The differences are as follows: The above-mentioned differences will be explained below, and any repeated explanations will be omitted.

[0151] refer to Figure 6A and Figure 6BThe thickness t2 of the third semiconductor layer 130p can be less than the thickness t1 of the first semiconductor layer 120p. The third semiconductor layer 130p can be formed from the same material using the same process as the second semiconductor layer 130d, and the second semiconductor layer 130d and the third semiconductor layer 130p can have the same thickness. That is, when the second semiconductor layer 130d is formed in the same layer as the first semiconductor layer 120p (e.g., buffer layer 111), the thickness of the second semiconductor layer 130d is formed to be less than the thickness of the first semiconductor layer 120p, such that the thickness t2 of the third semiconductor layer 130p can be less than the thickness t1 of the first semiconductor layer 120p.

[0152] However, the embodiments disclosed herein are not limited thereto, and the thickness t2 of the third semiconductor layer 130p may be greater than the thickness t1 of the first semiconductor layer 120p.

[0153] Figure 7A and Figure 7B This is a cross-sectional view of a display device 10 according to another embodiment. Figure 7A and Figure 7B The gate insulating layer 112 of the display device 10 and Figure 4A and Figure 4B The gate insulating layers (i.e., the first gate insulating layer 112p and the second gate insulating layer 112d) of the display device 10 are different. The differences mentioned above will be explained below, and any repeated explanations will be omitted.

[0154] refer to Figure 7A and Figure 7B A gate insulating layer 112 can be formed to cover the first semiconductor layer 120p and the third semiconductor layer 130p of the first thin-film transistor TRp, and the second semiconductor layer 130d and the buffer layer 111 of the second thin-film transistor TRd. In this case, each of the first source electrode 153p, the first drain electrode 154p, the second source electrode 151d, and the second drain electrode 152d can penetrate the gate insulating layer 112 and be connected to the first semiconductor layer 120p or the second semiconductor layer 130d.

[0155] In the following text, reference will be made to Figures 8A to 8H A method for manufacturing a display device 10 according to an embodiment is described. Figures 8A to 8H The first region I in the diagram can be the region where the second thin-film transistor TRd is formed, and can correspond to... Figures 3A to 7A The non-display area NDA. The second area II can be the area forming the first thin-film transistor TRp, and can correspond to... Figures 3B to 7B The display area DA.

[0156] In the description of the methods and processes herein, operations may be performed in a different order than those shown and / or described, or in a different order or at different times. Some operations may also be omitted from the flowchart, one or more operations may be repeated, or additional operations may be added. According to the exemplary aspects described herein, descriptions of elements as "may be set," "may be formed," "may be patterned," etc., include methods, processes, and techniques for setting, forming, patterning elements, etc.

[0157] First, refer to Figure 8A In the method of manufacturing the display device 10 according to the embodiment, a first semiconductor material layer 120' is formed on a substrate 100 on which a lower metal layer BML and a buffer layer 111 are formed. The first semiconductor material layer 120' may be formed on the buffer layer 111 and may be formed in a first region I and a second region II.

[0158] The first semiconductor material layer 120' may include a crystalline oxide semiconductor material and may be formed as a thin film. The first semiconductor material layer 120' may be formed by sputtering or vapor deposition, such as pulsed laser deposition.

[0159] Next, as Figure 8B As shown, the first semiconductor material layer 120' is patterned to form a first semiconductor pattern 120p'. Patterning can be performed by wet etching using an acid solution such as a mixture of hydrochloric acid, nitric acid, dilute sulfuric acid, phosphoric acid, and acetic acid, and after forming a photoresist pattern on the first semiconductor material layer 120' corresponding to the portion where the first semiconductor layer 120p will be formed. Alternatively, dry etching or a combination of dry and wet etching can also be used.

[0160] Next, the first semiconductor pattern 120p' is heat-treated to transform it into a crystalline semiconductor pattern. The heat treatment of the first semiconductor pattern 120p' can use a temperature of 350°C or higher, and oxygen can be injected during the heat treatment process.

[0161] Next, as Figure 8C As shown, a second semiconductor material layer 130' is formed over the first semiconductor pattern 120p'. The second semiconductor material layer 130' can be formed in both the first region I and the second region II. That is, the second semiconductor material layer 130' can be formed on the buffer layer 111 in the first region I and stacked on the first semiconductor pattern 120p' in the second region II.

[0162] Next, as Figure 8DAs shown, the second semiconductor material layer 130' is patterned to form a second semiconductor pattern 130d' ​​and a third semiconductor pattern 130p'. The patterning of the second semiconductor material layer 130' can be performed by forming photoresist patterns corresponding to the portions where the second semiconductor layer 130d will be formed and the portions where the third semiconductor layer 130p will be formed, followed by an etching process. That is, the second semiconductor pattern 130d' ​​and the third semiconductor pattern 130p' can be formed simultaneously.

[0163] The patterning process of the second semiconductor material layer 130' can be performed after the crystallization of the first semiconductor pattern 120p'. Therefore, the first semiconductor pattern 120p' can be stably maintained even when the second semiconductor material layer 130' is patterned.

[0164] In an implementation, when the second semiconductor material layer 130' is patterned, the third semiconductor layer 130p can be avoided on the first semiconductor layer 120p by not forming the third semiconductor pattern 130p' corresponding to the third semiconductor layer 130p.

[0165] Next, as Figure 8E and Figure 8F As shown, a gate insulating material layer 112' and a gate electrode material layer 140' covering the first semiconductor pattern 120p', the second semiconductor pattern 130d' ​​and the third semiconductor pattern 130p' are formed on the buffer layer 111.

[0166] The gate insulating material layer 112' may include inorganic materials such as silicon oxide, silicon nitride and / or silicon nitride, and may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0167] The gate electrode material layer 140' may include molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may be formed as a single film or a multilayer film. The gate electrode material layer 140' may be formed by deposition methods such as, but not limited to, chemical vapor deposition, plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), physical vapor deposition (PVD), sputtering, and atomic layer deposition (ALD).

[0168] Next, as Figure 8GAs shown, the gate insulating material layer 112' and the gate electrode material layer 140' are patterned to form a first gate electrode 140p, a first gate insulating layer 112p, a second gate electrode 140d, and a second gate insulating layer 112d. In an embodiment, when the gate electrode material layer 140' is patterned, the gate insulating material layer 112' may not be patterned, and the gate insulating material layer 112' may form a gate insulating layer 112 spanning the first region I and the second region II (see [reference]). Figure 7A and Figure 7B ).

[0169] Next, impurities are doped into the first semiconductor pattern 120p' and the second semiconductor pattern 130d' ​​to form the first semiconductor layer 120p and the second semiconductor layer 130d. The first semiconductor layer 120p can be formed by implanting impurities into the first source region 122p and the first drain region 123p, excluding the first channel region 121p, and the second semiconductor layer 130d can be formed by implanting impurities into the second source region 132d and the second drain region 133d, excluding the second channel region 131d.

[0170] The third semiconductor pattern 130p' forms the third semiconductor layer 130p. In an embodiment, the width of the third semiconductor layer 130p may correspond to the width of the first channel region 121p. In this case, when the first semiconductor layer 120p is doped, the third semiconductor layer 130p can act as a mask to protect the first channel region 121p.

[0171] Next, as Figure 8H As shown, an interlayer insulating layer 113 is formed on the entire surface of the buffer layer 111 on the first gate electrode 140p and the second gate electrode 140d. A first via c1, exposing the first source region 122p of the first semiconductor layer 120p, a second via c2, exposing the first drain region 123p, a third via c3, exposing the second source region 132d of the second semiconductor layer 130d, and a fourth via c4, exposing the second drain region 133d, are formed through the interlayer insulating layer 113. The first source electrode 153p, the first drain electrode 154p, the second source electrode 151d, and the second drain electrode 152d are formed on the interlayer insulating layer 113.

[0172] The first source electrode 153p, the first drain electrode 154p, the second source electrode 151d, and the second drain electrode 152d can be formed into a conductive material layer by various deposition methods such as chemical vapor deposition, plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), physical vapor deposition (PVD), sputtering, and atomic layer deposition (ALD), and then formed by patterning the conductive material layer.

[0173] The display device 10 can be applied to various electronic devices. The electronic device according to the embodiments includes the display device 10 described herein, and may also include modules or devices with additional functions in addition to the display device 10.

[0174] Figure 9 This is a block diagram of the electronic device 1000 according to an embodiment. (See reference) Figure 9 The electronic device 1000 may include a display module 1100, a processor 1200, a memory 1300, and a power module 1400.

[0175] The processor 1200 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0176] The memory 1300 can store data information that supports the operation of the processor 1200 or the display module 1100. When the processor 1200 executes the application stored in the memory 1300, image data signals and / or input control signals are transmitted to the display module 1100, and the display module 1100 can process the received signals and output image information through the display screen.

[0177] The power module 1400 may include a power module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power module to generate power to support the operation of the electronic device 1000.

[0178] At least one of the components of the electronic device 1000 described herein may be included in the display device 10 according to the embodiments described herein. In some aspects, some of the individual modules that are functionally included in a single module may be included within the display device 10, and other modules may be disposed separately from the display device 10. For example, the display device 10 may include a display module 1100, while the processor 1200, memory 1300, and power module 1400 may be disposed in the form of other devices within the electronic device 1000 besides the display device 10.

[0179] Figure 10 These are schematic diagrams of electronic devices according to various embodiments.

[0180] refer to Figure 10The various electronic devices used in the display device 10 according to the embodiments may include not only electronic devices for displaying images (such as smartphones 1000.1a, tablet computers 1000.1b, laptop computers 1000.1c, televisions 1000.1d, and desktop monitors 1000.1e), but also wearable electronic devices including display modules (such as smart glasses 1000.2a, head-mounted displays 1000.2b, and smartwatches 1000.2c), and vehicle electronic devices 1000.3 including display modules (such as central information displays (CIDs) and interior mirror displays arranged on the dashboard, center console, and instrument panel of a car).

[0181] As described herein, in the case of the display device 10 and electronic device 1000 according to embodiments, a first thin-film transistor TRp, including a first semiconductor layer 120p (which includes a crystalline oxide semiconductor), is arranged in the pixel circuit to act as a driving transistor, and a second thin-film transistor TRd, including a second semiconductor layer 130d (which includes an amorphous oxide semiconductor), is arranged in the driving circuit to act as an output transistor, so that the characteristics of the driving transistor of the pixel circuit and the output transistor of the driving circuit can be selectively improved, and the electrical characteristics and driving stability can be improved.

[0182] In some respects, in the case of the display device 10 and electronic device 1000 according to the embodiments, process stability can be improved and process costs and time can be reduced.

[0183] The implementation can improve electrical characteristics and enhance the reliability of the manufacturing process by implementing the driving transistors of the pixel circuit and the buffer transistors of the driving circuit with different oxide semiconductor layers.

[0184] However, the effects are not limited to those described above, and can be extended in various ways without departing from the spirit and scope of the implementation.

[0185] Each of the embodiments described herein can be implemented independently, but it goes without saying that the structure of each embodiment can be applied in combination with other embodiments.

[0186] Although embodiments have been described with reference to the accompanying drawings, they are examples, and those skilled in the art will understand that various modifications and equivalent embodiments are possible. Therefore, the scope of protection of the embodiments should be determined by the technical concept of the appended claims.

[0187] The specific implementation described in the examples is an example and does not limit the scope of the examples in any way. Unless specifically mentioned that an element is "required" or "important," the element may not be a required component.

[0188] The term "described" and similar references used in this disclosure (particularly in the claims) may refer to both the singular and the plural. Where a scope is described in an embodiment, the invention is considered to include individual values ​​falling within that scope (unless otherwise stated) and identical to each individual value constituting that scope as described in the detailed description. Finally, unless the order or sequence of steps constituting the method according to an embodiment is explicitly described, the steps may be performed in any suitable order. Embodiments are not necessarily limited to the order in which the above steps are described. Any use of example or exemplary terminology in the embodiments is intended to exemplify embodiments and is not intended to limit the scope of embodiments unless otherwise defined by the claims. Furthermore, those skilled in the art will understand that various modifications, combinations, and variations can be made based on the design conditions and factors within the scope of the appended claims or their equivalents.

Claims

1. A display device, comprising: The substrate includes a display area and a non-display area surrounding the display area; A pixel circuit, overlapping the display area and including a first thin-film transistor, the first thin-film transistor including a first semiconductor layer and a first gate electrode; as well as A driving circuit, connected to the pixel circuit, overlaps with the non-display area and includes a second thin-film transistor, the second thin-film transistor including a second semiconductor layer and a second gate electrode. in: The first semiconductor layer comprises a first oxide semiconductor material. The second semiconductor layer includes a second oxide semiconductor material, and The electron mobility of the second thin-film transistor is higher than that of the first thin-film transistor.

2. The display device according to claim 1, wherein: The first semiconductor layer comprises a crystalline oxide semiconductor material, and The second semiconductor layer comprises an amorphous oxide semiconductor material.

3. The display device according to claim 1, wherein, The first semiconductor layer and the second semiconductor layer are arranged in the same layer.

4. The display device according to claim 1, wherein, The first thin-film transistor further includes a third semiconductor layer disposed on the first semiconductor layer.

5. The display device according to claim 4, wherein, The third semiconductor layer and the second semiconductor layer comprise the same material.

6. The display device according to claim 4, wherein: The third semiconductor layer comprises an amorphous oxide semiconductor material, and The first semiconductor layer comprises a crystalline oxide semiconductor material.

7. The display device according to claim 4, wherein, The third semiconductor layer overlaps with the first semiconductor layer.

8. The display device according to claim 4, wherein, The width of the third semiconductor layer is smaller than the width of the first semiconductor layer.

9. The display device according to claim 4, wherein, The thickness of the third semiconductor layer is equal to the thickness of the first semiconductor layer.

10. The display device according to claim 4, wherein: The thickness of the third semiconductor layer is equal to the thickness of the second semiconductor layer, and The thickness of the second semiconductor layer is less than the thickness of the first semiconductor layer.

11. The display device according to claim 4, wherein, The width of the third semiconductor layer is smaller than the width of the first semiconductor layer but larger than the width of the first gate electrode.

12. The display device according to claim 1, wherein, The first thin-film transistor is the driving transistor of the pixel circuit.

13. The display device according to claim 1, wherein: Each of the first semiconductor layer and the second semiconductor layer includes indium, and The indium content of the first semiconductor layer is greater than that of the second semiconductor layer.

14. A display device, comprising: The substrate includes a display area and a non-display area surrounding the display area; The pixel circuitry overlaps with the display area; as well as The light-emitting element is electrically connected to the pixel circuit and generates light. The pixel circuit includes: The driving transistor includes a drain electrode connected to a first node, a gate electrode connected to a second node, and a source electrode connected to a third node. A switching transistor, in response to a scan signal, applies a data signal to the first node; and Initialize the transistor, and in response to the initialization control signal, apply an initialization voltage to the second node. The driving transistor includes a first semiconductor layer, which comprises a crystalline oxide semiconductor material.

15. The display device according to claim 14, wherein: The first semiconductor layer includes indium, and The indium content of the first semiconductor layer is greater than or equal to 80 at.

16. The display device according to claim 14, wherein: The driving transistor further includes a third semiconductor layer disposed on the first semiconductor layer, and The third semiconductor layer comprises an amorphous oxide semiconductor material.

17. The display device according to claim 14, further comprising: A driving circuit, overlapping the non-display area and including an output transistor, and The output transistor includes a second semiconductor layer, which is composed of an amorphous oxide semiconductor material.

18. Electronic devices, including display devices, in, The display device includes: The substrate includes a display area and a non-display area surrounding the display area; Pixel circuitry, overlapping the display area and including a first thin-film transistor, the first thin-film transistor including a first semiconductor layer and a first gate electrode; and A driving circuit, connected to the pixel circuit, overlaps with the non-display area and includes a second thin-film transistor, the second thin-film transistor including a second semiconductor layer and a second gate electrode. in: The first semiconductor layer comprises a first oxide semiconductor material. The second semiconductor layer includes a second oxide semiconductor material, and The electron mobility of the second thin-film transistor is higher than that of the first thin-film transistor.

19. The electronic device according to claim 18, wherein: The first semiconductor layer comprises a crystalline oxide semiconductor material, and The second semiconductor layer comprises an amorphous oxide semiconductor material.

20. The electronic device according to claim 19, wherein, The first semiconductor layer and the second semiconductor layer are arranged in the same layer.

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