Method for regulating the resistance of a transistor

Abstract

The embodiment of the application provides a method for regulating resistance of a transistor, and relates to the technical field of semiconductor integrated circuit manufacturing, and aims to accurately regulate the average value and standard deviation value of the resistance of the transistor. The method comprises the following steps: forming a plurality of transistors on a substrate, the transistor comprising an ion implantation region and a gate, the ion implantation region comprising a source region and a drain region, and the material of the gate comprising polysilicon. According to a target resistance value, pre-adjusting process parameters of a plasma-enhanced chemical vapor deposition process, the process parameters comprising at least one of radio frequency power, vapor silicon source flow, oxidant gas flow or carrier gas flow. Using the plasma-enhanced chemical vapor deposition process, forming an oxide insulating layer on the side of the gate away from the substrate according to the process parameters, so that the resistance of the transistor reaches the target resistance value, the oxide insulating layer covering at least the source region, the drain region and the gate, and the material of the oxide insulating layer comprising silicon elements.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit manufacturing technology, and in particular to a method for adjusting the resistance of a transistor. Background Technology

[0002] In the past, the control of transistor resistance has mainly focused on changing the ion implantation conditions or subsequent rapid thermal annealing conditions, with very little consideration given to the contribution of the self-aligned barrier layer oxide to electrical performance. Changing the ion implantation conditions can improve the average resistance of the transistor, but it cannot solve the problem of poor in-plane uniformity. Changing the subsequent rapid thermal annealing conditions can improve the average resistance and standard deviation of the transistor, but it can easily change the film quality and affect the subsequent etching rate.

[0003] Therefore, how to precisely control the average value and standard deviation of the transistor's resistance without affecting the subsequent etching rate has become a problem to be solved in the field. Summary of the Invention

[0004] This application proposes a method for controlling the resistance of a transistor, which aims to precisely control the average value and standard deviation of the transistor's resistance, improve in-plane uniformity, and without affecting the subsequent etching rate.

[0005] To achieve the above objectives, embodiments of this application provide the following technical solutions: This application provides a method for controlling the resistance of a transistor. The method includes: forming a plurality of transistors on a substrate, each transistor including an ion-implanted region disposed within the substrate, and a gate insulating layer and a gate sequentially stacked on the substrate. The ion-implanted region includes a source region and a drain region, which are located on opposite sides of the gate along a first direction parallel to the substrate. The gate material includes polysilicon. Based on a target resistance value, process parameters of a plasma-enhanced chemical vapor deposition (PECVD) process are pre-adjusted. These process parameters include at least one of radio frequency power, vapor silicon source flow rate, oxidant gas flow rate, or carrier gas flow rate. Using the PECVD process, according to the process parameters, an oxide insulating layer is formed on the side of the gate away from the substrate to achieve the target resistance value. The oxide insulating layer at least covers the source region, drain region, and gate. The oxide insulating layer material includes silicon.

[0006] In the control method provided in the embodiments of this application, the gate material includes polycrystalline silicon, and the oxide insulating layer material includes silicon. During the formation of the oxide insulating layer using plasma-enhanced chemical vapor deposition (PECVD), the deposition conditions of the oxide insulating layer, i.e., the process parameters of the PECVD process, can be pre-adjusted to affect the silicon content in the oxide insulating layer, thereby affecting the number of silicon-hydrogen bonds in the oxide insulating layer. The number of silicon-hydrogen bonds can change the trap charge density in the oxide insulating layer. By adjusting the trap charge density, the diffusion suppression effect of the oxide insulating layer on ions can be controlled, thereby changing the overall resistance of the transistor. This allows for precise control of the average resistance of the transistor within a certain range and reduces the standard deviation, thus improving in-plane uniformity.

[0007] Furthermore, the control method provided in this application does not add any new process steps, that is, it does not require an additional annealing process, thereby avoiding the problem that the annealing process affects the subsequent etching rate, thus reducing the process difficulty and improving the feasibility of the process.

[0008] In some embodiments, pre-adjusting the process parameters further includes pre-adjusting the electrode spacing of the coating apparatus based on the resistance value of the target transistor. The electrode spacing is the distance between two electrodes of the coating apparatus. The resistances of multiple transistors have an average value and a standard deviation; as the electrode spacing decreases, the standard deviation decreases.

[0009] In some embodiments, pre-adjusting the process parameters further includes pre-adjusting the carrier gas flow rate. Specifically, when the electrode spacing is reduced, the standard deviation decreases as the carrier gas flow rate increases.

[0010] In some embodiments, pre-adjusting the process parameters further includes pre-adjusting the RF power. The resistances of the multiple transistors have an average value and a standard deviation. With an RF power range of 300W to 380W, the average value decreases and the standard deviation decreases as the RF power increases.

[0011] In some embodiments, pre-adjusting the process parameters further includes pre-adjusting both the carrier gas flow rate and the RF power. Specifically, when the RF power is greater than 380W, the average value and standard deviation decrease as both the RF power and the carrier gas flow rate increase.

[0012] In some embodiments, pre-adjusting the process parameters further includes pre-adjusting the oxidant gas flow rate. The resistance of the multiple transistors has an average value, which increases with increasing oxidant gas flow rate.

[0013] In some embodiments, pre-adjusting the process parameters further includes pre-adjusting the vapor silicon source flow rate. The resistances of the multiple transistors have an average value and a standard deviation; as the vapor silicon source flow rate increases, both the average value and the standard deviation decrease.

[0014] In some embodiments, pre-adjusting the process parameters further includes pre-adjusting both the oxidant gas flow rate and the vapor silicon source flow rate. The resistance of the multiple transistors has an average value, which decreases as the ratio of the oxidant gas flow rate to the vapor silicon source flow rate decreases.

[0015] In some embodiments, the material of the gaseous silicon source includes silane, the material of the oxidant gas includes nitrous oxide, and the material of the carrier gas includes nitrogen. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not actual dimensions of the products or actual processes of the methods involved in the embodiments of this application.

[0017] Figure 1 A flowchart illustrating a method for adjusting the resistance of a transistor as provided in an embodiment of this application; Figure 2 and Figure 3 A diagram illustrating the steps of a transistor resistance control method provided in an embodiment of this application. Detailed Implementation

[0018] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0019] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0020] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0021] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0022] This document describes exemplary embodiments with reference to cross-sectional views, which are intended as idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations caused, for example, by manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0023] In the past, the control of transistor resistance (HRP) has mainly focused on changing the ion implantation (IMP) conditions or subsequent rapid thermal annealing (RTA) conditions, with very little consideration given to the contribution of the self-aligned barrier layer oxide to the electrical performance. While changing the ion implantation conditions can directly control the average resistance of the transistor, it cannot solve the problem of poor in-plane uniformity. Changing the subsequent rapid thermal annealing conditions can effectively improve the average resistance and standard deviation of the transistor, but it easily alters the film quality, affecting the subsequent etching rate.

[0024] To address at least one of the above problems, embodiments of this application provide a method for adjusting the resistance of a transistor.

[0025] Embodiments of this application provide a method for adjusting the resistance of a transistor. Figure 1 A flowchart illustrating a method for adjusting the resistance of a transistor, provided as an embodiment of this application. Figure 2 and Figure 3 A diagram illustrating the steps of a transistor resistance control method provided in an embodiment of this application.

[0026] See Figure 1The control method includes the following steps S1 to S3: Step S1: See Figure 2 Multiple transistors 2 are formed on a substrate 1. Each transistor 2 includes an ion implantation region 3 disposed in the substrate 1, and a gate insulating layer 4 and a gate 5 sequentially stacked on the substrate 1. The ion implantation region 3 includes a source region 6 and a drain region 7. Along a first direction X parallel to the substrate, the source region 6 and the drain region 7 are located on opposite sides of the gate 5. The material of the gate 5 includes polysilicon.

[0027] Step S2: Based on the target resistance value, pre-adjust the process parameters of the plasma-enhanced chemical vapor deposition process. The process parameters include at least one of the following: radio frequency power, vapor silicon source flow rate, oxidant gas flow rate, or carrier gas flow rate.

[0028] Step S3: See Figure 3 Using a plasma-enhanced chemical vapor deposition process, an oxide insulating layer 8 is formed on the side of the gate 5 away from the substrate according to the process parameters, so that the resistance of the transistor 2 reaches the target resistance value. The oxide insulating layer 8 covers at least the source gate 5, the source region 6 and the drain region 7. The material of the oxide insulating layer 8 includes silicon.

[0029] For example, a high-frequency power supply (HF power) can provide plasma capability. By adjusting the radio frequency power of the HF power supply, the reactivity of the plasma can be affected, thereby changing the uniformity of the oxide insulating layer 8 film thickness. This allows the average resistance μ and standard deviation σ of the transistor 2 to be changed within a certain range. The average resistance μ is the sum of the resistance values ​​of the multiple transistors 2 divided by the number of transistors 2, and the standard deviation σ is the square root of the sum of the squares of the differences between the resistance values ​​of each transistor 2 and the average resistance μ, divided by the number of transistors 2.

[0030] The gaseous silicon source directly affects the silicon content in the oxide insulating layer 8. The oxidant gas can be used to regulate the degree of silicon oxidation. By synergistically regulating the gaseous silicon source flow rate and the oxidant gas flow rate, the silicon-to-oxygen ratio in the oxide insulating layer 8 can be affected, thereby controlling the average value μ. By regulating the carrier gas flow rate to stabilize the plasma, reaction stability is enhanced, thereby controlling the standard deviation σ.

[0031] It is understandable that during the formation of the oxide insulating layer 8, the silicon content in the oxide insulating layer 8 can be affected by pre-adjusting the deposition conditions of the oxide insulating layer 8, i.e., the process parameters of the plasma-enhanced chemical vapor deposition process, thereby affecting the number of silicon-hydrogen bonds in the oxide insulating layer 8. The number of silicon-hydrogen bonds can change the trap charge density in the oxide insulating layer 8. By adjusting the trap charge density, the diffusion suppression effect of the oxide insulating layer 8 on ions can be controlled, thereby changing the overall resistance of the transistor 2. This allows for precise control of the average resistance μ of the transistor 2 within a certain range, and a reduction in the standard deviation σ, thus improving in-plane uniformity. Furthermore, this control method does not add any new process steps, i.e., it does not require an additional annealing process, thus avoiding the problem of the annealing process affecting the subsequent etching rate, thereby reducing the process difficulty and improving the feasibility of the process.

[0032] In some embodiments, see Figure 3 The oxide insulating layer 8 can be made of silicon-rich oxide (SRO), the gaseous silicon source can be silane (SiH4), the oxidant gas can be nitrous oxide (N2O), and the carrier gas can be nitrogen (N2).

[0033] It is understandable that by setting the process materials of the plasma-enhanced chemical vapor deposition process to the aforementioned materials, combined with the pre-adjustment of process parameters and cooperation with SRO, the average resistance μ and standard deviation σ of transistor 2 can be further precisely controlled, thereby further improving in-plane uniformity.

[0034] In some embodiments, see Figure 3 The pre-adjustment of process parameters in step S2 above also includes pre-adjusting the electrode spacing (Spacing) d of the coating equipment 9 according to the target resistance value. Here, the electrode spacing d is the distance between the first electrode 10 and the second electrode 11 of the coating equipment 9. The transistor resistances of the multiple transistors 2 have an average value μ and a standard deviation σ; as the electrode spacing d decreases, the standard deviation σ decreases.

[0035] For example, for every 50 to 70 mil decrease in the electrode spacing d, the standard deviation σ decreases by approximately 0.2% to 0.8%.

[0036] It is understandable that as the electrode spacing d decreases, the difference in film thickness between the edge and center of the oxide insulating layer 8 decreases, making the film thickness of the oxide insulating layer 8 more uniform. Consequently, the distribution of silicon-hydrogen bonds in the oxide insulating layer 8 above different transistors 2 is also more uniform, which makes the average resistance μ of multiple transistors 2 closer to the target resistance, thereby reducing the standard deviation σ and improving in-plane uniformity.

[0037] In some embodiments, see Figure 3 The pre-adjustment of process parameters in step S2 above also includes pre-adjustment of carrier gas flow rate. Specifically, when the electrode spacing d decreases, the standard deviation σ decreases as the carrier gas flow rate increases.

[0038] For example, reducing the electrode spacing d from 400 mil to 350 mil and increasing the carrier gas flow rate from 2100 sccm to 2800 sccm reduces the standard deviation σ by 1% to 3%. Here, "sccm" refers to Standard Cubic Centimeter per Minute (sccm).

[0039] It is understandable that as the electrode spacing d decreases, the difference in film thickness between the edge and center of the oxide insulating layer 8 decreases, and as the carrier gas flow rate increases, the reactant partial pressure of the oxide insulating layer 8 decreases, further reducing the difference in film thickness between the edge and center of the oxide insulating layer 8. This makes the film thickness of the oxide insulating layer 8 more uniform, and the distribution of silicon-hydrogen bonds in the oxide insulating layer 8 above different transistors 2 is also more uniform. As a result, the average resistance μ of multiple transistors 2 is closer to the target resistance, thereby reducing the standard deviation σ.

[0040] In some embodiments, see Figure 3 The pre-adjustment of process parameters in step S2 above also includes pre-adjustment of RF power. The resistances of the multiple transistors 2 have an average value μ and a standard deviation σ. With an RF power range of 300W to 380W, as the RF power increases, both the average value μ and the standard deviation σ decrease.

[0041] For example, when the average resistance μ of transistor 2 is higher than the target resistance value, as the RF power increases by 20 to 80 W, the activity of silane (SiH4) in oxide insulating layer 8 increases, the silicon content of oxide insulating layer 8 increases, and the average resistance μ of transistor 2 decreases by about 3% to 5%.

[0042] For example, if it is necessary to reduce the average value μ and keep the standard deviation σ ≤ 2%, the RF power can be increased from 320W to 340W, while the carrier gas flow rate can be increased from 1500sccm to 1800sccm.

[0043] Understandably, when the average resistance μ of transistor 2 is higher than the target resistance value (i.e., when the resistance of transistor 2 is high), increasing the radio frequency power can increase the silicon content of the oxide insulating layer 8, thereby reducing the average resistance μ of transistor 2. This brings the average resistance μ closer to the target resistance value, thus lowering the standard deviation σ. Conversely, when the average resistance μ of transistor 2 is lower than the target resistance value (i.e., when the resistance of transistor 2 is low), decreasing the radio frequency power can decrease the silicon content of the oxide insulating layer 8, thereby increasing the average resistance μ of transistor 2. This brings the average resistance μ closer to the target resistance value, thus lowering the standard deviation σ.

[0044] In some embodiments, see Figure 3 The pre-adjustment of process parameters in step S2 above also includes pre-adjustment of both carrier gas flow rate and RF power. Specifically, when the RF power is greater than 380W, as the RF power and carrier gas flow rate increase, the average value μ decreases, and the standard deviation σ decreases.

[0045] Understandably, when it is necessary to reduce the average resistance μ while keeping the standard deviation σ within the target value, increasing the radio frequency power increases the silicon content of the oxide insulating layer 8, thereby reducing the average resistance μ of the transistor 2. Furthermore, increasing the carrier gas flow rate makes the plasma distribution in the oxide insulating layer 8 more uniform, improving the film uniformity of the oxide insulating layer 8. This results in a more uniform distribution of silicon-hydrogen bonds in the oxide insulating layer 8 above different transistors 2, making the average resistance μ of multiple transistors 2 closer to the target resistance, thus reducing the standard deviation σ. Through the coordinated adjustment of radio frequency power and carrier gas flow rate, both the average resistance μ and the standard deviation σ of the transistor 2 are reduced.

[0046] In some embodiments, see Figure 3 The pre-adjustment of process parameters in step S2 above also includes pre-adjustment of the oxidant gas flow rate. The resistance of the multiple transistors 2 has an average value μ, which increases with the increase of the oxidant gas flow rate.

[0047] For example, when the average resistance μ of transistor 2 is lower than the target resistance value, the average resistance μ of transistor 2 increases by 1% to 6% for every 40 sccm to 140 sccm increase in oxidant gas flow rate.

[0048] It is understandable that when the average resistance μ of transistor 2 is lower than the target resistance value, the oxidation degree of silicon in oxide insulating layer 8 can be enhanced by increasing the oxidant gas flow rate, thereby reducing the silicon content of oxide insulating layer 8 and increasing the average resistance μ of transistor 2.

[0049] In some embodiments, see Figure 3 The pre-adjustment of process parameters in step S2 above also includes pre-adjustment of the vapor silicon source flow rate. The resistances of the multiple transistors have an average value μ and a standard deviation σ. As the vapor silicon source flow rate increases, both the average value μ and the standard deviation σ decrease.

[0050] For example, when the average resistance μ of transistor 2 is higher than the target resistance value, for every 5 sccm to 25 sccm increase in the vapor phase silicon source flow rate, the average resistance μ of transistor 2 decreases by 1% to 8%.

[0051] Understandably, when the average resistance μ of transistor 2 is higher than the target resistance value (i.e., when the resistance of transistor 2 is high), increasing the flow rate of the vapor-phase silicon source increases the silicon content of the oxide insulating layer 8, thereby reducing the average resistance μ of transistor 2. This brings the average resistance μ closer to the target resistance value, thus lowering the standard deviation σ. Conversely, when the average resistance μ of transistor 2 is lower than the target resistance value (i.e., when the resistance of transistor 2 is low), decreasing the flow rate of the vapor-phase silicon source decreases the silicon content of the oxide insulating layer 8, thereby increasing the average resistance μ of transistor 2. This brings the average resistance μ closer to the target resistance value, thus lowering the standard deviation σ.

[0052] In some embodiments, see Figure 3 The pre-adjustment of process parameters in step S2 above also includes pre-adjusting the oxidant gas flow rate and the vapor silicon source flow rate. The resistance of the multiple transistors 2 has an average value μ, which decreases as the ratio of the oxidant gas flow rate to the vapor silicon source flow rate decreases.

[0053] For example, if a 10% reduction in the average value μ and a standard deviation σ ≤ 1.5% are required, the gas phase silicon source flow rate can be increased from 140 sccm to 180 sccm, and the oxidant gas flow rate can be decreased from 1600 sccm to 1200 sccm.

[0054] Understandably, when it is necessary to reduce the average resistance μ while keeping the standard deviation σ within the target value, increasing the flow rate of the vapor-phase silicon source increases the silicon content of the oxide insulating layer 8, thereby reducing the average resistance μ of the transistor 2. Furthermore, increasing the flow rate of the oxidant gas enhances the oxidation reaction of silicon in the oxide insulating layer 8, reducing its silicon content. This brings the silicon content and reaction rate of the oxide insulating layer 8 into equilibrium, thus reducing the standard deviation σ. Finally, reducing the ratio of the oxidant gas flow rate to the vapor-phase silicon source flow rate reduces both the average resistance μ and the standard deviation σ of the transistor 2.

[0055] For example, an embodiment of this application also provides an experiment on a method for controlling the resistance of a transistor, used to illustrate the control method in the above embodiments.

[0056] First, the target resistance value of transistor 2 is determined in this experiment. For example, the average value μ of the target resistance value can be set to 0.95kΩ~1.05kΩ, and the standard deviation σ can be set to σ≤2%. Then, the average value μ and standard deviation σ of the current resistance of transistor 2 in the initial state are determined. For example, in the initial state, the average value μ of the current resistance of transistor 2 is 1.2kΩ, and the standard deviation σ is 3.5%.

[0057] Then, the average resistance μ of transistor 2 is preferentially controlled. If the current average resistance μ of transistor 2 is too high, the process parameters are pre-adjusted. First, the flow rate of the vapor silicon source is increased proportionally, or the flow rate of the oxidant gas is decreased, and the RF power is slightly increased to reduce the average resistance μ. For example, SiH4 is increased by 10 sccm, or N2O is decreased by 80 sccm, and the RF power is increased by 30W, thereby reducing the average resistance μ of transistor 2. If the current average resistance μ of transistor 2 is too low, when pre-adjusting the process parameters, the flow rate of the vapor silicon source needs to be decreased proportionally, or the flow rate of the oxidant gas needs to be increased, and the RF power needs to be slightly decreased, thereby increasing the average resistance μ of transistor 2.

[0058] Next, the standard deviation σ of the resistance of transistor 2 is optimized. Since the current standard deviation σ of transistor 2's resistance is too high, process parameters are pre-adjusted by increasing the carrier gas flow rate or decreasing the electrode spacing d to reduce the standard deviation σ. For example, increasing the N2 flow rate by 600 sccm reduces μ to 1.05 kΩ and σ to 2.2%. The electrode spacing d is then adjusted again, decreasing by 30 mil, and the N2 flow rate is increased by another 200 sccm. Ultimately, μ = 1.05 kΩ and σ = 1.8%, meeting the target resistance value.

[0059] In the above experimental operation, after each round of process parameter adjustment, the average resistance μ and standard deviation σ of transistor 2 must be measured. If the target resistance value is not met, the above steps need to be repeated. It should be noted that when adjusting the process parameters in each round, the adjustment range of the process parameters must be controlled within ±10% of the base value of the process parameter. Furthermore, a quantitative model should be established based on the structure of each round of adjustment, and the direction and magnitude of the adjustment parameters can be directly determined based on this model in the future.

[0060] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for controlling the resistance of a transistor, characterized in that, include: Multiple transistors are formed on a substrate, the transistors including ion implantation regions disposed in the substrate, and gate insulating layers and gates sequentially stacked on the substrate; The ion implantation region includes a source region and a drain region, and along a first direction parallel to the substrate, the source region and the drain region are located on opposite sides of the gate; the gate material includes polycrystalline silicon; Based on the target resistance value, the process parameters of the plasma-enhanced chemical vapor deposition process are pre-adjusted; the process parameters include at least one of radio frequency power, vapor silicon source flow rate, oxidant gas flow rate, or carrier gas flow rate. Using a plasma-enhanced chemical vapor deposition process, according to the process parameters, an oxide insulating layer is formed on the side of the gate away from the substrate, so that the resistance of the transistor reaches the target resistance value; The oxide insulating layer at least covers the source region, the drain region, and the gate; the material of the oxide insulating layer includes silicon.

2. The control method according to claim 1, characterized in that, Pre-adjusting the process parameters further includes: The electrode spacing of the coating equipment is pre-adjusted according to the target resistance value; Wherein, the electrode spacing is the distance between two electrodes of the coating device; the resistance of the plurality of transistors has an average value and a standard deviation, and the standard deviation decreases as the electrode spacing decreases.

3. The control method according to claim 2, characterized in that, Pre-adjusting the process parameters further includes: The carrier gas flow rate is pre-adjusted; Specifically, when the electrode spacing decreases, the standard deviation decreases as the carrier gas flow rate increases.

4. The control method according to claim 1, characterized in that, Pre-adjusting the process parameters includes: The radio frequency power is pre-adjusted; The resistances of the plurality of transistors have an average value and a standard deviation; when the RF power ranges from 300W to 380W, the average value decreases and the standard deviation decreases as the RF power increases.

5. The control method according to claim 4, characterized in that, Pre-adjusting the process parameters further includes: Both the carrier gas flow rate and the radio frequency power are pre-adjusted; Specifically, when the RF power is greater than 380W, as the RF power and the carrier gas flow increase, the average value decreases and the standard deviation decreases.

6. The control method according to claim 1, characterized in that, Pre-adjusting the process parameters further includes: The flow rate of the oxidant gas is pre-adjusted; The resistance of the plurality of transistors has an average value, which increases as the flow rate of the oxidant gas increases.

7. The control method according to claim 1, characterized in that, Pre-adjusting the process parameters further includes: The flow rate of the gaseous silicon source is pre-adjusted; The resistances of the plurality of transistors have an average value and a standard deviation; as the flow rate of the vapor silicon source increases, the average value decreases, and the standard deviation decreases.

8. The control method according to claim 1, characterized in that, Pre-adjusting the process parameters further includes: The flow rates of both the oxidant gas and the gaseous silicon source are pre-adjusted; The resistance of the plurality of transistors has an average value; the average value decreases as the ratio of the oxidant gas flow rate to the gaseous silicon source flow rate decreases.

9. The control method according to any one of claims 1 to 8, characterized in that, The material of the gaseous silicon source includes silane; the material of the oxidant gas includes nitrous oxide; and the material of the carrier gas includes nitrogen.

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