Display substrate and display device

Abstract

The present disclosure provides a display substrate and a display device. The display substrate comprises a plurality of gate lines and a driving module arranged on a substrate; the driving module comprises a plurality of output control circuits and a plurality of driving circuits; n is a positive integer; the nth output control circuit controls the communication or disconnection between the nth gate line and the nth control clock signal line under the control of the nth output control signal; the nth output control terminal is the nth+m first node included in the nth+m driving circuit or the nth+m driving output terminal included in the nth+m driving circuit; m is a positive integer; the nth driving output terminal is electrically connected to the first end of the nth gate line, and the nth output control circuit is electrically connected to the second end of the nth gate line; the first end and the second end are opposite ends. In the embodiment of the present disclosure, the nth output control circuit is used to achieve the purpose of noise reduction for the far end of the nth gate line, reduce the delay of the far end of the nth gate line, and improve the display defects.

Description

Display substrate and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0002] The current trend in electronic product development is towards thinner and lighter designs and more diverse functions, which places increasing challenges on display product design. As customer demand for notebook products grows, there is a growing need for high performance at a lower cost to improve cost-effectiveness. IC (integrated circuit) costs constitute a significant portion of panel costs. Currently, using Dual Gate or Triple Gate designs can halve the number of ICs used in a panel, significantly reducing the overall panel cost. However, using Dual Gate or Triple Gate technologies doubles the number of gate lines, resulting in reduced GOA (Gate of Area) layout space on the left and right sides of the panel. For high PPI (pixel density) products, GOA layout is more difficult, necessitating the use of a dual-sided alternating drive design to further reduce layout space.

[0003] However, single-sided GOA driving results in significant signal delay at the far end of the gate lines, particularly a large falling edge delay in the drive signal provided by the gate lines. This can easily lead to display defects caused by mischarging of the far-end signal and differences in pixel voltage between near and far ends. To address this issue, a solution is needed. Summary of the Invention

[0004] In one aspect, embodiments of this disclosure provide a display substrate, including multiple rows of gate lines disposed on the substrate and a driving module; the driving module includes multiple output control circuits and multiple driving circuits;

[0005] The nth driving circuit includes an nth first node and an nth driving output terminal. The nth driving circuit is used to provide the nth driving signal to the nth row of gate lines through the nth driving output terminal; n is a positive integer.

[0006] The nth output control circuit is electrically connected to the nth output control terminal, the nth control clock signal line and the nth row of gate lines respectively, and is used to control the connection or disconnection between the nth row of gate lines and the nth control clock signal line under the control of the nth output control signal provided by the nth output control terminal.

[0007] The nth output control terminal is the (n+m)th first node included in the (n+m)th drive circuit or the (n+m)th drive output terminal included in the (n+m)th drive circuit; m is a positive integer.

[0008] The nth drive output terminal is electrically connected to the first end of the nth row of gate lines, and the nth output control circuit is electrically connected to the second end of the nth row of gate lines;

[0009] The first end and the second end are opposite ends.

[0010] Optionally, the nth driving circuit is located within the nth driving circuit region, the (n+m)th driving circuit is located within the (n+m)th driving circuit region, and the nth output control circuit is located within the (n+m)th driving circuit region.

[0011] Optionally, the nth output control terminal is the n+mth first node included in the n+mth driving circuit; the n+mth driving circuit includes the n+mth driving transistor for outputting the n+mth driving signal;

[0012] The gate of the (n+m)th driving transistor is electrically connected to the gate of the transistor included in the nth output control circuit via a connection portion, the connection portion having a cutout portion.

[0013] Optionally, the nth control clock signal line extends along a first direction, and the width of the cutout in the second direction is smaller than the width of the gate of the transistor included in the nth output control circuit in the second direction;

[0014] The first direction intersects with the second direction.

[0015] Optionally, the width of the gate of the (n+m)th driving transistor in the second direction is equal to the width of the gate of the transistor included in the nth output control circuit in the second direction;

[0016] The length of the gate of the transistor in the first direction of the nth output control circuit is less than the length of the gate of the (n+m)th driving transistor in the first direction.

[0017] Optionally, the first electrode of the transistor included in the nth output control circuit is electrically connected to the nth control clock signal line through a first connection line, and the second electrode of the transistor included in the nth output control circuit is electrically connected to the second end of the nth row gate line through a second connection line.

[0018] The virtual extension of the second connecting line in the second direction intersects with the first connecting line.

[0019] Optionally, the nth output control terminal is the n+mth first node included in the n+mth driving circuit; the n+mth driving circuit includes an n+mth pull-down reset circuit; the n+mth pull-down reset circuit is electrically connected to the n+mth first node and the n+mth second node respectively, and is used to reset the potential of the n+mth second node under the control of the potential of the n+mth first node;

[0020] The gate of the transistor included in the nth output control circuit is electrically connected to the gate of the transistor included in the (n+m)th pull-down reset circuit.

[0021] Optionally, the shortest distance between the gate of the transistor included in the nth output control circuit and the gate of the transistor included in the (n+m)th pull-down reset circuit is greater than or equal to 4 μm and less than 10 μm.

[0022] Optionally, the (n+m)th driving circuit includes an (n+m)th driving transistor for outputting the (n+m)th driving signal;

[0023] The ratio between the length of the active pattern of the (n+m)th driving transistor along the first direction and the length of the active pattern of the (n+m)th driving transistor along the second direction is greater than 1.

[0024] The first direction is the extension direction of the nth control clock signal line, and the second direction intersects with the first direction.

[0025] Optionally, the length of the active pattern of the (n+m)th driving transistor along the second direction is greater than or equal to 4 μm and less than 10 μm.

[0026] Optionally, the nth output control terminal is the (n+m)th drive output terminal;

[0027] The (n+m)th driving circuit includes an (n+m)th driving transistor for outputting the (n+m)th driving signal;

[0028] The second electrode of the (n+m)th driving transistor is electrically connected to the gate of the transistor included in the nth output control circuit;

[0029] The shortest distance between the gate of the (n+m)th driving transistor and the gate of the transistor included in the nth output control circuit is greater than or equal to 4 μm and less than 10 μm.

[0030] Optionally, the width of the gate of the transistor in the nth output control circuit along the second direction is smaller than the width of the gate of the (n+m)th driving transistor along the second direction.

[0031] The first direction is the extension direction of the nth control clock signal line, and the second direction intersects with the first direction.

[0032] Optionally, the second electrode of the (n+m)th driving transistor is electrically connected to the connection pattern via a via;

[0033] The connection pattern is electrically connected to the gate of the transistor included in the nth output control circuit, and the connection pattern and the gate of the transistor included in the nth output control circuit are disposed on the same layer.

[0034] Optionally, the nth driving circuit is electrically connected to the nth output clock signal line, and is used to control the connection between the nth driving output terminal and the nth output clock signal line under the control of the potential of the nth first node;

[0035] The clock signal connected to the nth output clock signal line is the same as the clock signal connected to the nth control clock signal line.

[0036] Optionally, the nth output control circuit includes an nth output control transistor;

[0037] The gate of the nth output control transistor is electrically connected to the nth output control terminal, the first electrode of the nth output control transistor is electrically connected to the nth control clock signal line, and the second electrode of the nth output control transistor is electrically connected to the second end of the nth row gate line.

[0038] Optionally, the drive module further includes redundant output control transistors;

[0039] The gate of the redundant output control transistor is electrically connected to the first node of the first driving circuit, the first electrode of the redundant output control transistor is electrically connected to the corresponding control clock signal line, and the second electrode of the redundant output control transistor is floating.

[0040] Optionally, the driving module further includes a first redundant driving circuit; the display substrate further includes a first redundant gate line; x is a positive integer;

[0041] The xth output control circuit included in the driving module is electrically connected to the first node included in the first redundant driving circuit and the last row of gate lines included in the display substrate. The xth output control circuit is used to control the driving signal on the last row of gate lines under the control of the potential of the first node included in the first redundant driving circuit.

[0042] The first redundant drive circuit and the xth output control circuit are located within the first redundant drive circuit region, and the first redundant drive circuit is electrically connected to one end of the first redundant gate line.

[0043] Optionally, the drive module further includes a second redundant drive circuit; the second redundant drive circuit is disposed within the second redundant drive circuit area;

[0044] The other end of the first redundant gate line is electrically connected to the second redundant drive circuit, and the first redundant drive circuit and the first drive circuit included in the drive module are located on the same side of the display substrate.

[0045] The drive module further includes a redundant output control circuit disposed in the second redundant drive circuit area; the output terminal of the redundant output control circuit is floating.

[0046] Optionally, the nth driving circuit includes an nth first node control circuit, an nth output circuit, an nth output reset circuit, an nth pull-down reset circuit, and an nth second node control circuit;

[0047] The nth first node control circuit is electrically connected to the input terminal, the reset terminal and the nth first node respectively, and is used to control the potential of the nth first node under the control of the input signal provided by the input terminal and the reset signal provided by the reset terminal;

[0048] The nth output circuit is electrically connected to the nth first node, the nth drive output terminal, and the nth output clock signal line, respectively, and is used to control the connection or disconnection between the nth drive output terminal and the nth output clock signal line under the control of the potential of the nth first node;

[0049] The nth output reset circuit is electrically connected to the nth second node and the nth drive output terminal respectively, and is used to reset the nth drive signal provided by the nth drive output terminal under the control of the potential of the nth second node;

[0050] The nth pull-down reset circuit is electrically connected to the nth first node and the nth second node respectively, and is used to reset the potential of the nth second node under the control of the potential of the nth first node;

[0051] The control circuit of the nth second node is electrically connected to the nth second node and is used to control the potential of the nth second node.

[0052] Optionally, the channel width-to-length ratio of the nth output control transistor is greater than or equal to 10 and less than or equal to 22.5.

[0053] Optionally, the channel length of the nth output control transistor is greater than or equal to 4 μm and less than or equal to 6 μm, and the channel width of the nth output control transistor is greater than or equal to 60 μm and less than or equal to 90 μm.

[0054] The display substrate of at least one embodiment of this disclosure includes a peripheral region and a display region; the peripheral region includes a first side region and a second side region; the first side region is disposed on a first side of the display region, and the second side region is disposed on a second side of the display region, wherein the first side and the second side are opposite sides;

[0055] The odd-numbered driving circuit of the driving module is disposed in the first side region, and the even-numbered driving circuit of the driving module is disposed in the second side region.

[0056] The driving module includes a 2a-1 driving circuit that is electrically connected to the first end of the 2a-1 row of gate lines, and is used to provide a 2a-1 driving signal to the 2a-1 row of gate lines;

[0057] The driving module includes a 2a driving circuit that is electrically connected to the second end of the 2a row gate line, and is used to provide a 2a driving signal to the 2a row gate line;

[0058] 'a' is a positive integer.

[0059] At least one embodiment of the present disclosure describes a display substrate including a multi-row, multi-column pixel circuit disposed in a display area; b is a positive integer;

[0060] The pixel circuit located in row b is electrically connected to the gate line in row 2b-1, and is used to access the corresponding data voltage under the control of the driving signal provided by the gate line in row 2b-1;

[0061] Another portion of the pixel circuit located in row b is electrically connected to the gate line in row 2b, and is used to receive the corresponding data voltage under the control of the 2b drive signal provided by the gate line in row 2b.

[0062] At least one embodiment of the present disclosure describes a display substrate including a multi-row, multi-column pixel circuit disposed in a display area; b is a positive integer;

[0063] The first color pixel circuit located in row 3b-2 is electrically connected to the gate line in row 3b-2, and is used to connect the corresponding data voltage under the control of the 3b-2 driving signal provided by the gate line in row 3b-2;

[0064] The second color pixel circuit located in row 3b-1 is electrically connected to the gate line in row 3b-1, and is used to connect the corresponding data voltage under the control of the driving signal provided by the gate line in row 3b-1;

[0065] The third color pixel circuit located in row 3b is electrically connected to the gate line in row 3b, and is used to connect the corresponding data voltage under the control of the third drive signal provided by the gate line in row 3b.

[0066] In a second aspect, embodiments of this disclosure provide a display device including the display substrate described above. Attached Figure Description

[0067] Figure 1 is a structural diagram of at least one embodiment of the nth driving circuit;

[0068] Figure 2 is a structural diagram of at least one embodiment of the nth driving circuit;

[0069] Figure 3A shows a circuit of at least one embodiment of the nth driving circuit;

[0070] Figure 3B is a timing diagram of at least one embodiment of the nth driving circuit shown in Figure 3A.

[0071] Figure 4 is a characteristic table of the (n-1)th output control transistor;

[0072] Figure 5 is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0073] Figure 6A is a layout diagram of the two driving circuits included in the driving module located to the left of the display area A0;

[0074] Figure 6B is a layout diagram of the gate metal layer in Figure 6A;

[0075] Figure 6C is a layout diagram of the semiconductor layer in Figure 6A;

[0076] Figure 6D is a layout diagram of the source and drain metal layers in Figure 6A;

[0077] Figure 6E is a stack-up diagram of the gate metal layer and semiconductor layer in Figure 6A;

[0078] Figure 6F is a layout diagram of the semiconductor layer and source / drain metal layers in Figure 6B;

[0079] Figure 6G is a layout diagram of the source and drain metal layers in Figure 6A;

[0080] Figure 7A is a layout diagram of the two driving circuits included in the driving module located to the right of the display area A0;

[0081] Figure 7B is a layout diagram of the gate metal layer in Figure 7A;

[0082] Figure 7C is a layout diagram of the semiconductor layer in Figure 7A;

[0083] Figure 7D is a layout diagram of the source and drain metal layers in Figure 7A;

[0084] Figure 7E is a stack-up diagram of the gate metal layer and semiconductor layer in Figure 7A;

[0085] Figure 7F is a layout diagram of the semiconductor layer and source / drain metal layers in Figure 7B;

[0086] Figure 7G is a layout diagram of a portion of the driving module located to the left of display area A0, including a driving circuit and a first redundant driving circuit.

[0087] Figure 8A is a layout diagram of the two driving circuits included in the driving module located to the left of the display area A0;

[0088] Figure 8B is a layout diagram of the gate metal layer in Figure 8A;

[0089] Figures 8C and 8G are layout diagrams of the semiconductor layer in Figure 8A;

[0090] Figure 8D is a layout diagram of the source and drain metal layers in Figure 8A;

[0091] Figure 8E is a stack-up diagram of the gate metal layer and semiconductor layer in Figure 8A;

[0092] Figure 8F is a layout diagram of the semiconductor layer and source / drain metal layers in Figure 8B;

[0093] Figure 9A is a layout diagram of the two driving circuits included in the driving module located to the right of the display area A0;

[0094] Figure 9B is a layout diagram of the gate metal layer in Figure 9A;

[0095] Figure 9C is a layout diagram of the semiconductor layer in Figure 9A;

[0096] Figure 9D is a layout diagram of the source and drain metal layers in Figure 9A;

[0097] Figure 9E is a stack-up diagram of the gate metal layer and semiconductor layer in Figure 9A;

[0098] Figure 9F is a layout diagram of the semiconductor layer and source / drain metal layers in Figure 9B;

[0099] Figure 10 is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0100] Figure 11 is a timing diagram of at least one embodiment of the display substrate shown in Figure 10 of this disclosure;

[0101] Figure 12 is a timing diagram of the operation of the display substrate according to at least one embodiment of the present disclosure when the display substrate includes 1080 driving circuits in at least one embodiment;

[0102] Figure 13A is a layout diagram of the two driving circuits included in the driving module located to the left of the display area A0;

[0103] Figure 13B is a layout diagram of the gate metal layer in Figure 13A;

[0104] Figure 13C is a layout diagram of the semiconductor layer in Figure 13A;

[0105] Figure 13D is a layout diagram of the source and drain metal layers in Figure 13A;

[0106] Figure 13E is a stack-up diagram of the gate metal layer and semiconductor layer in Figure 13A;

[0107] Figure 13F is a stack-up diagram of the semiconductor layer and source / drain metal layers in Figure 13A;

[0108] Figure 14A is a layout diagram of the two driving circuits included in the driving module located to the right of the display area A0;

[0109] Figure 14B is a layout diagram of the gate metal layer in Figure 14A;

[0110] Figure 14C is a layout diagram of the semiconductor layer in Figure 14A;

[0111] Figure 14D is a layout diagram of the source and drain metal layers in Figure 14A;

[0112] Figure 14E is a stack-up diagram of the gate metal layer and semiconductor layer in Figure 14A;

[0113] Figure 14F is a stack-up diagram of the semiconductor layer and source / drain metal layers in Figure 14A;

[0114] Figure 15 is a waveform diagram of the drive signal provided at the near and far ends of the gate line in the display substrate according to at least one embodiment of the present disclosure;

[0115] Figure 16 is a structural diagram of the pixel circuit in a display substrate according to at least one embodiment of the present disclosure;

[0116] Figure 17 is a structural diagram of the pixel circuit in a display substrate according to at least one embodiment of the present disclosure. Detailed Implementation

[0117] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0118] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two electrodes of the transistor other than the gate, one electrode is referred to as the first electrode and the other electrode as the second electrode.

[0119] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the source and the second electrode can be the drain; or, the first electrode can be the drain and the second electrode can be the source.

[0120] The display substrate described in this embodiment includes multiple rows of gate lines and a driving module disposed on a substrate; the driving module includes multiple output control circuits and multiple driving circuits;

[0121] The nth driving circuit includes an nth first node and an nth driving output terminal. The nth driving output terminal is electrically connected to the first end of the nth row of gate lines. The nth driving circuit is used to provide the nth driving signal to the nth row of gate lines through the nth driving output terminal; n is a positive integer.

[0122] The nth output control circuit is electrically connected to the second end of the nth row of gate lines, the nth output control terminal, and the nth control clock signal line, respectively, and is used to control the connection or disconnection between the nth row of gate lines and the nth control clock signal line under the control of the nth output control signal provided by the nth output control terminal.

[0123] The nth output control terminal is the (n+m)th first node included in the (n+m)th drive circuit or the (n+m)th drive output terminal included in the (n+m)th drive circuit; m is a positive integer.

[0124] The first end and the second end are opposite ends.

[0125] In the display substrate described in this embodiment, an nth output control circuit is used to control the second end of the nth row of gate lines to connect with the nth control clock signal line under the control of the potential of the n+mth first node or the n+mth drive signal provided by the n+mth drive output terminal. This achieves the purpose of noise reduction at the far end of the nth row of gate lines, reduces the delay at the far end of the nth row of gate lines, and improves display defects.

[0126] In at least one embodiment of this disclosure, the (n+m)th first node is the first node included in the (n+m)th driving circuit.

[0127] In at least one embodiment of this disclosure, an example of m equaling 1 is used for illustration.

[0128] In related technologies, the advantage of GOA (Gate On Array) double-sided cross-drive is that it can achieve narrow bezels and has low requirements for driver ICs (Integrated Circuits). The disadvantage is that single-sided GOA drive leads to large signal delay at the far end of the gate line, especially a large falling edge delay of the drive signal provided by the gate line, which can easily cause display defects due to mischarging of the far-end signal and differences in pixel voltage between near and far ends. To improve the display defects caused by large signal delay at the far end of the gate line in single-sided GOA drive, this disclosure embodiment achieves the technical effect of reducing far-end signal delay by designing an output control circuit at the far end of the gate line.

[0129] In related technologies, in order to meet the requirements of ultra-narrow bezels, a GOA design with dual-sided cross-drive is usually adopted.

[0130] The GOA design with dual-sided cross-drive can refer to a design where a first drive unit is set on the left side of the display area and a second drive unit is set on the right side of the display area; the first drive unit can be configured to provide drive signals to odd-numbered or even-numbered grid lines, and the second drive unit can be configured to provide drive signals to even-numbered or odd-numbered grid lines.

[0131] The driving module described in this disclosure can satisfy both narrow bezel requirements and ensure driving capability at the far end. Therefore, it can be applied to medium and large-sized display products (such as TVs / MNTs). Compared with the dual-side simultaneous driving GOA design commonly used in medium and large-sized products, it has the technical advantage of narrow bezels. The driving module described in this disclosure can also be applied to small-sized display products.

[0132] In at least one embodiment of this disclosure, when the first end is the left end, the second end can be the right end; when the first end is the left end, the second end can be the right end.

[0133] In at least one embodiment of this disclosure, the nth driving circuit is disposed in the nth driving circuit region, the (n+m)th driving circuit is disposed in the (n+m)th driving circuit region, and the nth output control circuit is disposed in the (n+m)th driving circuit region.

[0134] In a specific implementation, the nth output control circuit can be located within the (n+m)th drive circuit region.

[0135] In at least one embodiment of this disclosure, the nth output control terminal is the n+mth first node included in the n+mth driving circuit; the n+mth driving circuit includes the n+mth driving transistor for outputting the n+mth driving signal;

[0136] The gate of the (n+m)th driving transistor is electrically connected to the gate of the transistor included in the nth output control circuit via a connection portion, the connection portion having a cutout portion.

[0137] In practical implementation, when the nth output control terminal is the n+mth first node included in the n+mth driving circuit, the n+mth driving transistor and the transistor included in the nth output control circuit are placed in close proximity. Since the potential of the n+mth first node will self-boost, and at this time, the potential of the n+mth first node is more than twice the high voltage value, a cutout is provided between the gate of the n+mth driving transistor and the gate of the transistor included in the nth output control circuit to avoid overheating and burnout caused by excessive voltage. Simultaneously, it can reduce the area ratio of large metal blocks to avoid affecting the curing of the sealant after UV light transmittance.

[0138] In at least one embodiment of this disclosure, the nth control clock signal line extends along a first direction, and the width of the cutout portion in the second direction is smaller than the width of the gate of the transistor included in the nth output control circuit in the second direction.

[0139] The first direction intersects with the second direction.

[0140] Optionally, the first direction can be a vertical direction, the second direction can be a horizontal direction, the nth output control circuit can include an nth output control transistor, and the width of the cutout in the horizontal direction can be smaller than the width of the gate of the nth output control transistor in the horizontal direction.

[0141] In at least one embodiment of this disclosure, the width of the gate of the (n+m)th driving transistor in the second direction is equal to the width of the gate of the transistor included in the nth output control circuit in the second direction.

[0142] The length of the gate of the transistor in the first direction of the nth output control circuit is less than the length of the gate of the (n+m)th driving transistor in the first direction.

[0143] In a specific implementation, the width of the gate of the (n+m)th driving transistor in the horizontal direction can be equal to the width of the gate of the nth output control transistor in the horizontal direction; the length of the gate of the nth output control transistor in the vertical direction can be less than the length of the gate of the (n+m)th driving transistor in the vertical direction.

[0144] In at least one embodiment of this disclosure, the first electrode of the transistor included in the nth output control circuit is electrically connected to the nth control clock signal line via a first connection line, and the second electrode of the transistor included in the nth output control circuit is electrically connected to the second end of the nth row gate line via a second connection line.

[0145] The virtual extension of the second connecting line in the second direction intersects with the first connecting line.

[0146] In a specific implementation, the first electrode of the nth output control transistor can be electrically connected to the nth control clock signal line through the first connection line, and the second electrode of the nth output control transistor can be electrically connected to the second end of the nth row gate line through the second connection line. The virtual extension line of the second connection line in the horizontal direction can intersect with the first connection line.

[0147] In at least one embodiment of this disclosure, the nth output control transistor can be positioned using the space between vertically adjacent driving transistors to save vertical space.

[0148] In at least one embodiment of this disclosure, the driving module may further include a first redundant driving circuit; the display substrate may further include a first redundant gate line; x is a positive integer;

[0149] The xth output control circuit included in the driving module is electrically connected to the first node included in the first redundant driving circuit and the last row of gate lines included in the display substrate. The xth output control circuit is used to control the driving signal on the last row of gate lines under the control of the potential of the first node included in the first redundant driving circuit.

[0150] The first redundant drive circuit and the xth output control circuit are located within the first redundant drive circuit region, and the first redundant drive circuit is electrically connected to one end of the first redundant gate line.

[0151] In a specific implementation, at the rear end of the last driving circuit included in the driving module, the driving module may further include at least one redundant driving circuit. The xth output control circuit may be electrically connected to the first node included in the first redundant driving circuit and one end of the last row of gate lines included in the display substrate, respectively. Under the control of the potential of the first node included in the first redundant driving circuit, the driving signal on the last row of gate lines is controlled. The first redundant driving circuit and the xth output control circuit may be located in the same redundant driving circuit, and the first redundant driving circuit may be electrically connected to one end of the first redundant gate line.

[0152] In at least one embodiment of this disclosure, the last row of gate lines included in the display substrate refers to the last row of gate lines that has a control function on the corresponding transistors in the pixel circuit located in the display area, and does not include redundant gate lines.

[0153] In at least one embodiment of this disclosure, the drive module may further include a second redundant drive circuit; the second redundant drive circuit is disposed within the second redundant drive circuit region;

[0154] The other end of the first redundant gate line is electrically connected to the second redundant drive circuit, and the first redundant drive circuit and the first drive circuit included in the drive module are located on the same side of the display substrate.

[0155] The drive module further includes a redundant output control circuit disposed in the second redundant drive circuit area; the output terminal of the redundant output control circuit is floating.

[0156] In a specific implementation, the first redundant driving circuit can be disposed in the first side area, the second redundant driving circuit can be disposed in the second side area, and the first driving circuit included in the driving module can be located in the first side area.

[0157] The second redundant drive circuit can be set in the second redundant drive circuit region, and a redundant output control circuit can be set in the second redundant drive circuit region.

[0158] The second electrode of the transistor included in the redundant output control circuit (the output terminal of the redundant output control circuit can be the second electrode of the transistor included in the redundant output control circuit) can be floating.

[0159] For example, the first redundant driving circuit and the first driving circuit can both be located on the left side of the display area.

[0160] The display substrate described in at least one embodiment of this disclosure may further include at least one row of redundant gate lines;

[0161] The first end and the second end of the redundant gate line are respectively electrically connected to the corresponding redundant drive circuit.

[0162] In practice, the two ends of the redundant gate line can be electrically connected to different redundant drive circuits, using a bilateral drive method.

[0163] In at least one embodiment of this disclosure, the nth output control terminal is the n+mth first node included in the n+mth driving circuit; the n+mth driving circuit includes an n+mth pull-down reset circuit; the n+mth pull-down reset circuit is electrically connected to the n+mth first node and the n+mth second node respectively, and is used to reset the potential of the n+mth second node under the control of the potential of the n+mth first node;

[0164] The gate of the transistor included in the nth output control circuit is electrically connected to the gate of the transistor included in the (n+m)th pull-down reset circuit.

[0165] Optionally, the shortest distance between the gate of the transistor included in the nth output control circuit and the gate of the transistor included in the (n+m)th pull-down reset circuit is greater than or equal to 4 μm and less than 10 μm.

[0166] In specific implementation, when the nth output control terminal is the n+mth first node, the transistors included in the nth output control circuit and the transistors included in the n+mth pull-down reset circuit can be set close to each other to save space layout.

[0167] In at least one embodiment of this disclosure, the (n+m)th driving circuit includes an (n+m)th driving transistor for outputting an (n+m)th driving signal;

[0168] The ratio between the length of the active pattern of the (n+m)th driving transistor along the first direction and the length of the active pattern of the (n+m)th driving transistor along the second direction is greater than 1.

[0169] The first direction is the extension direction of the nth control clock signal line, and the second direction intersects with the first direction.

[0170] In specific implementation, when the nth output control terminal is the n+mth first node, by setting the transistors included in the nth output control circuit and the transistors included in the n+mth pull-down reset circuit to be close to each other, the length of the active pattern of the n+mth driving transistor along the first direction can be increased, and the length of the active pattern of the n+mth driving transistor along the second direction can be decreased, so as to achieve a narrow bezel without affecting the driving capability of the n+mth driving transistor.

[0171] Optionally, the length of the active pattern of the (n+m)th driving transistor along the second direction is greater than or equal to 4 μm and less than 10 μm.

[0172] In at least one embodiment of this disclosure, the first direction can be a vertical direction, and the second direction can be a horizontal direction.

[0173] In at least one embodiment of this disclosure, the nth output control terminal is the (n+m)th drive output terminal;

[0174] The (n+m)th driving circuit includes an (n+m)th driving transistor for outputting the (n+m)th driving signal;

[0175] The second electrode of the (n+m)th driving transistor is electrically connected to the gate of the transistor included in the nth output control circuit;

[0176] The shortest distance between the gate of the (n+m)th driving transistor and the gate of the transistor included in the nth output control circuit is greater than or equal to 4 μm and less than 10 μm.

[0177] In practical implementation, when the nth output control terminal is the n+mth drive output terminal, the n+mth drive transistor and the transistors included in the nth output control circuit can be placed close together to save space layout.

[0178] In at least one embodiment of this disclosure, the width of the gate of the transistor included in the nth output control circuit along the second direction is smaller than the width of the gate of the (n+m)th driving transistor along the second direction.

[0179] The first direction is the extension direction of the nth control clock signal line, and the second direction intersects with the first direction.

[0180] In a specific implementation, the nth output control circuit may include an nth output control transistor, and the width of the gate of the nth output control transistor in the horizontal direction may be smaller than the width of the gate of the (n+m)th driving transistor in the horizontal direction.

[0181] In at least one embodiment of this disclosure, the second electrode of the (n+m)th driving transistor is electrically connected to the connection pattern via a via;

[0182] The connection pattern is electrically connected to the gate of the transistor included in the nth output control circuit, and the connection pattern and the gate of the transistor included in the nth output control circuit are disposed on the same layer.

[0183] In a specific implementation, the second electrode of the (n+m)th driving transistor is formed on the source-drain metal layer, and the gate of the transistor included in the nth output control circuit is formed on the gate metal layer. Therefore, the second electrode of the (n+m)th driving transistor can be configured to be electrically connected to the connection pattern through a via, and the connection pattern is formed on the gate metal layer.

[0184] In at least one embodiment of this disclosure, the nth driving circuit is electrically connected to the nth output clock signal line, and is used to control the connection between the nth driving output terminal and the nth output clock signal line under the control of the potential of the nth first node;

[0185] The clock signal connected to the nth output clock signal line is the same as the clock signal connected to the nth control clock signal line.

[0186] In a specific implementation, the nth driving circuit, under the control of the potential of the nth first node, writes the nth output clock signal into the electrical connection of the nth driving output terminal, and the clock signal connected to the nth output clock signal line is the same as the clock signal connected to the nth control clock signal line.

[0187] In at least one embodiment of this disclosure, the nth output control circuit includes an nth output control transistor;

[0188] The gate of the nth output control transistor is electrically connected to the nth output control terminal, the first electrode of the nth output control transistor is electrically connected to the nth control clock signal line, and the second electrode of the nth output control transistor is electrically connected to the second end of the nth row gate line.

[0189] In at least one embodiment of this disclosure, the drive module further includes redundant output control transistors;

[0190] The gate of the redundant output control transistor is electrically connected to the first node of the first driving circuit, the first electrode of the redundant output control transistor is electrically connected to the corresponding control clock signal line, and the second electrode of the redundant output control transistor is floating.

[0191] In a specific implementation, a redundant output control transistor is provided in the first driving circuit region. The second electrode of the redundant output control transistor is floating and not electrically connected to the gate line.

[0192] In at least one embodiment of this disclosure, the nth driving circuit includes an nth first node control circuit, an nth output circuit, an nth output reset circuit, an nth pull-down reset circuit, and an nth second node control circuit;

[0193] The nth first node control circuit is electrically connected to the input terminal, the reset terminal and the nth first node respectively, and is used to control the potential of the nth first node under the control of the input signal provided by the input terminal and the reset signal provided by the reset terminal;

[0194] The nth output circuit is electrically connected to the nth first node, the nth drive output terminal, and the nth output clock signal line, respectively, and is used to control the connection or disconnection between the nth drive output terminal and the nth output clock signal line under the control of the potential of the nth first node;

[0195] The nth output reset circuit is electrically connected to the nth second node and the nth drive output terminal respectively, and is used to reset the nth drive signal provided by the nth drive output terminal under the control of the potential of the nth second node;

[0196] The nth pull-down reset circuit is electrically connected to the nth first node and the nth second node respectively, and is used to reset the potential of the nth second node under the control of the potential of the nth first node;

[0197] The control circuit of the nth second node is electrically connected to the nth second node and is used to control the potential of the nth second node.

[0198] In a specific implementation, the nth driving circuit may include an nth first node control circuit, an nth output circuit, an nth output reset circuit, an nth pull-down reset circuit, and an nth second node control circuit. The nth first node control circuit, under the control of the input signal and the reset signal, controls the potential of the nth first node. The nth output circuit, under the control of the potential of the nth first node, controls the connection or disconnection between the nth driving output terminal and the nth output clock signal line. The nth output reset circuit, under the control of the potential of the nth second node, resets the nth driving signal provided by the nth driving output terminal. The nth pull-down reset circuit, under the control of the potential of the nth first node, resets the potential of the nth second node. The nth second node control circuit controls the potential of the nth second node.

[0199] Optionally, the nth second node may include the nth first dropdown node and the nth second dropdown node.

[0200] Optionally, the channel width-to-length ratio of the nth output control transistor is greater than or equal to 10 and less than or equal to 22.5.

[0201] Optionally, the channel length of the nth output control transistor is greater than or equal to 4 μm and less than or equal to 6 μm, and the channel width of the nth output control transistor is greater than or equal to 60 μm and less than or equal to 90 μm.

[0202] In at least one embodiment of this disclosure, the channel length of the nth output control transistor can be greater than or equal to 60 μm and less than or equal to 90 μm;

[0203] The channel width of the nth output control transistor can be greater than or equal to 4 μm and less than or equal to 6 μm.

[0204] As shown in Figure 1, at least one embodiment of the nth driving circuit may include the nth first node control circuit 11, the nth output circuit 12, the nth output reset circuit 13, the nth pull-down reset circuit 14, and the nth second node control circuit 15.

[0205] The nth first node control circuit 11 is electrically connected to the input terminal I1, the reset terminal R1 and the nth first node PUn respectively, and is used to control the potential of the nth first node PUn under the control of the input signal provided by the input terminal I1 and the reset signal provided by the reset terminal R1;

[0206] The nth output circuit 12 is electrically connected to the nth first node PUn, the nth drive output terminal GTn, and the nth output clock signal line CKOn, respectively, and is used to control the connection or disconnection between the nth drive output terminal GTn and the nth output clock signal line CKOn under the control of the potential of the nth first node PUn.

[0207] The nth output reset circuit 13 is electrically connected to the nth first pull-down node PD1n, the nth second pull-down node PD2n and the nth drive output terminal GTn, respectively, and is used to reset the nth drive signal provided by the nth drive output terminal GTn under the control of the potential of the nth first pull-down node PD1n and the potential of the nth second pull-down node PD2n;

[0208] The nth pull-down reset circuit 14 is electrically connected to the nth first node PUn, the nth first pull-down node PD1n and the nth second pull-down node PD2n respectively, and is used to reset the potential of the nth first pull-down node PD1n and the potential of the nth second pull-down node PD2n under the control of the potential of the nth first node PUn;

[0209] The nth second node control circuit 14 is electrically connected to the nth first pull-down node PD1n and the nth second pull-down node PD2n respectively, and is used to control the potential of the nth first pull-down node PD1n and the nth second pull-down node PD2n.

[0210] In Figure 1, the one labeled 10 is the (n-1)th output drive circuit included in the (n-1)th drive circuit;

[0211] The (n-1)th output drive circuit 10 is electrically connected to the nth first node PUn, the (n-1)th control clock signal line CKCn-1, and the (n-1)th drive output terminal GTn-1, respectively, and is used to control the connection or disconnection between the (n-1)th drive output terminal GTn-1 and the (n-1)th control clock signal line CKCn-1 under the control of the potential of the nth first node PUn.

[0212] As shown in Figure 2, based on at least one embodiment of the driving circuit shown in Figure 1, the driving circuit described in at least one embodiment of this disclosure may further include an nth carry-out output circuit 15, an nth energy storage circuit 16, and an nth pull-down control circuit 17.

[0213] The nth first node control circuit 11 can also be electrically connected to the frame reset terminal TRST, the nth first pull-down node PD1n and the nth second pull-down node PD2n, and is used to control the potential of the nth first node PUn under the control of the frame reset signal provided by the frame reset terminal TRST, and to control the potential of the nth first node PUn under the control of the potential of the nth first pull-down node PD1n and the potential of the nth second pull-down node PD2n;

[0214] The nth output reset circuit 13 can also be electrically connected to the drive reset terminal GR, and is used to reset the nth drive signal provided by the nth drive output terminal GTn under the control of the drive reset signal provided by the drive reset terminal GR;

[0215] The drive reset terminal GR can be the (n+1)th drive output terminal;

[0216] The nth carry-out output circuit 15 is electrically connected to the nth first node PUn, the nth first pull-down node PD1n, the nth second pull-down node PD2n, the nth output clock signal line CKOn, and the nth carry-out output terminal OCn. It is used to control the connection or disconnection between the nth carry-out output terminal OCn and the nth output clock signal line CKOn under the control of the potential of the nth first node PUn, and to reset the nth carry-out signal provided by the nth carry-out output terminal OCn under the control of the potential of the nth first pull-down node PD1n and the nth second pull-down node PD2n.

[0217] The first end of the nth energy storage circuit 16 is electrically connected to the nth first node PUn, and the second end of the energy storage circuit 16 is electrically connected to the nth carry-out output terminal OCn. The energy storage circuit 16 is used to store electrical energy.

[0218] The nth pull-down control circuit 17 is electrically connected to the first control voltage terminal VDDO, the second control voltage terminal VDDE, the nth first pull-down node PD1n, the nth second pull-down node PD2n, and the input terminal I1, respectively. It is used to control the potential of PD1n under the control of the first control voltage provided by the first control voltage terminal VDDO, control the potential of PD2n under the control of the second control voltage provided by the second control voltage terminal VDDE, and reset the potentials of PD1n and PD2n under the control of the input signal provided by I1.

[0219] In at least one embodiment of this disclosure, the input terminal can be the (n-1)th carry-out output terminal, and the reset terminal can be the (n+1)th carry-out output terminal.

[0220] As shown in Figure 3A, based on at least one embodiment of the driving circuit shown in Figure 2, the (n-1)th output driving circuit may include the (n-1)th output control transistor MCn-1;

[0221] The nth first node control circuit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a fifth transistor M5;

[0222] The nth output circuit includes a driving transistor M6, and the nth output reset circuit includes a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9.

[0223] The nth pull-down reset circuit includes the tenth transistor M10 and the eleventh transistor M11;

[0224] The nth pull-down control circuit includes the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15;

[0225] The nth carry-out output circuit includes the sixteenth transistor M16, the seventeenth transistor M17, and the eighteenth transistor M18;

[0226] The nth energy storage circuit includes the nth storage capacitor C1n;

[0227] The gate of MCn-1 is electrically connected to PUn, the first electrode of MCn-1 is electrically connected to the clock signal line CLK, and the second electrode of MCn-1 is electrically connected to the (n-1)th drive output terminal GTn-1.

[0228] The gate and first electrode of M1 are both electrically connected to the input terminal I1, and the second electrode of M1 is electrically connected to PUn.

[0229] The gate of M2 is electrically connected to the reset terminal R1, the first electrode of M2 is electrically connected to PUn, and the second electrode of M2 is electrically connected to the first low voltage line LVGL.

[0230] The gate of M3 is electrically connected to PD1n, the first electrode of M3 is electrically connected to PUn, and the second electrode of M3 is electrically connected to the first low voltage line LVGL.

[0231] The gate of M4 is electrically connected to PD2n, the first electrode of M4 is electrically connected to PUn, and the second electrode of M4 is electrically connected to the first low voltage line LVGL.

[0232] The gate of M5 is electrically connected to TRST, the first electrode of M5 is electrically connected to PUn, and the second electrode of M5 is electrically connected to the first low voltage line LVGL.

[0233] The gate of M6 is electrically connected to PUn, the first electrode of M6 is electrically connected to CLK, and the second electrode of M6 is electrically connected to GTn.

[0234] The gate of M7 is electrically connected to PD1n, the first electrode of M7 is electrically connected to GTn, and the second electrode of M7 is electrically connected to the second low voltage line VGL.

[0235] The gate of M8 is electrically connected to PD2n, the first electrode of M8 is electrically connected to GTn, and the second electrode of M8 is electrically connected to the second low voltage line VGL.

[0236] The gate of M9 is electrically connected to GR, the first electrode of M9 is electrically connected to GTn, and the second electrode of M9 is electrically connected to the second low voltage line VGL.

[0237] The gate of M10 is electrically connected to PUn, the first electrode of M10 is electrically connected to PD1n, and the second electrode of M10 is electrically connected to the first low voltage line LVGL.

[0238] The gate of M11 is electrically connected to PUn, the first electrode of M11 is electrically connected to PD2n, and the second electrode of M11 is electrically connected to the first low voltage line LVGL.

[0239] The gate and first electrode of M12 are both electrically connected to VDDO, and the second electrode of M12 is electrically connected to PD1n.

[0240] The gate and the first electrode of M13 are both electrically connected to VDDE, and the second electrode of M13 is electrically connected to PD2n.

[0241] The gate of M14 is electrically connected to I1, the first electrode of M14 is electrically connected to PD1n, and the second electrode of M14 is electrically connected to the first low voltage line LVGL.

[0242] The gate of M15 is electrically connected to I1, the first electrode of M15 is electrically connected to PD2n, and the second electrode of M15 is electrically connected to the first low voltage line LVGL.

[0243] The gate of M16 is electrically connected to PUn, the first electrode of M16 is electrically connected to CLK, and the second electrode of M16 is electrically connected to the nth carry-out output terminal OCn.

[0244] The gate of M17 is electrically connected to PD1n, the first electrode of M17 is electrically connected to OCn, and the second electrode of M17 is electrically connected to the first low voltage line LVGL.

[0245] The gate of M18 is electrically connected to PD2n, the first electrode of M18 is electrically connected to OCn, and the second electrode of M18 is electrically connected to the first low voltage line LVGL.

[0246] The first plate of C1n is electrically connected to PUn, and the second plate of C1n is electrically connected to GTn.

[0247] In at least one embodiment shown in Figure 3A, all transistors may be n-type transistors.

[0248] As shown in Figure 3B, in at least one embodiment of the driving circuit shown in Figure 3A, when I1 provides a high voltage signal, M1 is turned on, the potential of PUn is high, MCn-1 is turned on, and the signal output by MCn-1 is as shown in Sn-1.

[0249] In at least one embodiment of this disclosure, regarding the selection of the size of the nth output control transistor, the near-end delay is specified when the near-end fall time Tf_near indicates the gate drive signal directly output by M3, and the far-end delay is specified when the far-end fall time Tf_far indicates the gate drive signal directly output by M3. After far-end compensation using each output control transistor, the absolute value of the difference between Tf_far and Tf_near needs to be controlled within 1% of the ratio between Tf_near and Tf_far. Tf_near and Tf_far can be obtained through software simulation during design, and can be obtained by measuring the waveform of the gate drive signal after the display product is produced. At the same time, the pixel voltage difference ΔVp corresponding to the near and far-end gate drive signals of the gate line needs to be less than or equal to 12mV, that is, within one gray level that the human eye can recognize. As shown in Figure 4, a scanning simulation was performed on the channel width W-MCn-1 of MCn-1 from 10 μs to 200 μs. The results showed that Tf_far decreased from 1.23 to 0.743 μs, and the difference between Tf_far and Tf_near decreased from 0.1652 to -0.042. Notably, when the channel width of MCn-1 was 70 μm, the optimal difference ΔTf between Tf_far and Tf_near was 0.05 μs. Based on the standard that the ratio of the absolute value of the difference between Tf_far and Tf_near to the value of Tf_near should be controlled within 1%, the channel width of each output control transistor is generally designed to be greater than or equal to 60 μm and less than or equal to 90 μm.

[0250] Simultaneously, voltage difference simulations were performed on the pixel circuits at the near and far ends of the gate line. It was found that when the channel width of the output control transistor is 70μm, ΔVp is optimal, at 0.0033V. According to the standard that ΔVp needs to be less than 12mV, the channel width of the output control transistor is generally designed to be greater than or equal to 50μm and less than or equal to 110μm. Combining this with the above standard requirement for ΔTf, the channel width of each output control transistor is generally designed to be greater than or equal to 60μm and less than or equal to 90μm.

[0251] The display substrate of at least one embodiment of this disclosure includes a peripheral region and a display region; the peripheral region includes a first side region and a second side region; the first side region is disposed on a first side of the display region, and the second side region is disposed on a second side of the display region, wherein the first side and the second side are opposite sides;

[0252] The drive module includes an odd number of drive circuits disposed in the first side region, and the drive module includes an even number of drive circuits disposed in the second side region.

[0253] The driving module includes a 2a-1 driving circuit that is electrically connected to the first end of the 2a-1 row of gate lines, and is used to provide a 2a-1 driving signal to the 2a-1 row of gate lines;

[0254] The driving module includes a 2a driving circuit that is electrically connected to the second end of the 2a row gate line, and is used to provide a 2a driving signal to the 2a row gate line;

[0255] 'a' is a positive integer.

[0256] As shown in Figure 5, CLK11 is the first clock signal line, CLK12 is the first second clock signal line, CLK13 is the first third clock signal line, CLK14 is the first fourth clock signal line, CLK15 is the first fifth clock signal line, CLK16 is the first sixth clock signal line, CLK17 is the first seventh clock signal line, and CLK18 is the first eighth clock signal line.

[0257] The line labeled CLK21 is the second first clock signal line, the line labeled CLK22 is the second second clock signal line, the line labeled CLK23 is the second third clock signal line, the line labeled CLK24 is the second fourth clock signal line, the line labeled CLK25 is the second fifth clock signal line, the line labeled CLK26 is the second sixth clock signal line, the line labeled CLK27 is the second seventh clock signal line, and the line labeled CLK28 is the second eighth clock signal line.

[0258] The circuit labeled GA1 is the first drive circuit included in the drive module, the circuit labeled GA2 is the second drive circuit included in the drive module, the circuit labeled GA3 is the third drive circuit included in the drive module, and the circuit labeled GA4 is the fourth drive circuit included in the drive module.

[0259] The circuit labeled GA5 is the fifth drive circuit included in the drive module; the circuit labeled GA6 is the sixth drive circuit included in the drive module; the circuit labeled GA7 is the seventh drive circuit included in the drive module; the circuit labeled GA8 is the eighth drive circuit included in the drive module; and the circuit labeled GA9 is the ninth drive circuit included in the drive module.

[0260] The first row of gate lines is labeled GL1, the second row is labeled GL2, the third row is labeled GL3, the fourth row is labeled GL4, the fifth row is labeled GL5, the sixth row is labeled GL6, the seventh row is labeled GL7, and the eighth row is labeled GL8.

[0261] CLK11, CLK12, CLK13, CLK14, CLK15, CLK16, CLK17, CLK18, GA1, GA3, GA5, GA7, and GA9 can be located in the first side area AC1; CLK11, CLK12, CLK13, CLK14, CLK15, CLK16, CLK17, and CLK18 all extend vertically.

[0262] CLK21, CLK22, CLK23, CLK24, CLK25, CLK26, CLK27, CLK28, GA2, GA4, GA6, and GA8 can be set in the second side area AC2; CLK21, CLK22, CLK23, CLK24, CLK25, CLK26, CLK27, and CLK28 all extend in the vertical direction;

[0263] CLK11 and CLK21 are both connected to the first clock signal, CLK12 and CLK22 are both connected to the second clock signal, CLK13 and CLK23 are both connected to the third clock signal, CLK14 and CLK24 are both connected to the fourth clock signal, CLK15 and CLK25 are both connected to the fifth clock signal, CLK16 and CLK26 are both connected to the sixth clock signal, CLK17 and CLK27 are both connected to the seventh clock signal, and CLK18 and CLK28 are both connected to the eighth clock signal.

[0264] The area labeled A0 is the display area;

[0265] The first side area AC1 is located on the left side of the display area A0, and the second side area AC2 is located on the right side of the display area A0.

[0266] As shown in Figure 5, the first drive output terminal of GA1 is electrically connected to the left side of G1, and the second drive output terminal of GA2 is electrically connected to the right side of G2.

[0267] The first drive output terminal of GA3 is electrically connected to the left side of G3, and the second drive output terminal of GA4 is electrically connected to the right side of G4.

[0268] The first drive output terminal of GA5 is electrically connected to the left side of G5, and the second drive output terminal of GA6 is electrically connected to the right side of G6.

[0269] The first drive output terminal of GA7 is electrically connected to the left side of G7, and the second drive output terminal of GA8 is electrically connected to the right side of G8.

[0270] The line labeled STV1 is the first starting voltage line, and the line labeled STV2 is the second starting voltage line.

[0271] In Figure 5, the transistor labeled MC1 is the first output control transistor, the transistor labeled MC2 is the second output control transistor, the transistor labeled MC3 is the third output control transistor, the transistor labeled MC4 is the fourth output control transistor, the transistor labeled MC5 is the fifth output control transistor, the transistor labeled MC6 is the sixth output control transistor, the transistor labeled MC7 is the seventh output control transistor, and the transistor labeled MC8 is the eighth output control transistor.

[0272] The gate of MC1 is electrically connected to the second first node of GA2, the first electrode of MC1 is electrically connected to CLK21, GA2 is electrically connected to CLK11, and the second electrode of MC1 is electrically connected to the right end of GL1.

[0273] The gate of MC2 is electrically connected to the third first node of GA3, the first electrode of MC2 is electrically connected to CLK12, the second electrode of MC2 is electrically connected to the left end of GL2; GA3 is electrically connected to CLK22.

[0274] The gate of MC3 is electrically connected to the fourth first node of GA4, the first electrode of MC3 is electrically connected to CLK23, GA3 is electrically connected to CLK13, and the second electrode of MC3 is electrically connected to the right end of GL3.

[0275] The gate of MC4 is electrically connected to the fifth first node of GA5, the first electrode of MC4 is electrically connected to CLK14, the second electrode of MC4 is electrically connected to the left end of GL4; GA5 is electrically connected to CLK24.

[0276] The gate of MC5 is electrically connected to the sixth first node of GA6, the first electrode of MC5 is electrically connected to CLK25, GA5 is electrically connected to CLK15, and the second electrode of MC5 is electrically connected to the right end of GL5.

[0277] The gate of MC6 is electrically connected to the seventh first node of GA7, the first electrode of MC6 is electrically connected to CLK16, the second electrode of MC6 is electrically connected to the left end of GL6; GA7 is electrically connected to CLK26.

[0278] The gate of MC7 is electrically connected to the eighth first node of GA8, the first electrode of MC7 is electrically connected to CLK27, GA7 is electrically connected to CLK17, and the second electrode of MC7 is electrically connected to the right end of GL7.

[0279] The gate of MC8 is electrically connected to the ninth first node of GA9, the first electrode of MC8 is electrically connected to CLK18, the second electrode of MC8 is electrically connected to the left end of GL8, and GA9 is electrically connected to CLK28.

[0280] In at least one embodiment of the display substrate shown in Figure 5, eight clock signal lines are provided on the left side of the display panel and eight clock signal lines are also provided on the right side of the display panel.

[0281] At least one embodiment of the display substrate shown in FIG5 of this disclosure, when in operation,

[0282] When the potential of the second first node included in GA2 is high, MC1 turns on and writes the first clock signal provided by CLK21 to the right end of GL1 to perform far-end compensation for GL1.

[0283] When the potential of the third first node included in GA3 is high, MC2 turns on and writes the second clock signal provided by CLK12 to the left end of GL2 to perform far-end compensation for GL2.

[0284] When the potential of the fourth first node included in GA4 is high, MC3 turns on and writes the third clock signal provided by CLK23 to the right end of GL3 to perform far-end compensation for GL3.

[0285] When the potential of the fifth first node included in GA5 is high, MC4 turns on and writes the fourth clock signal provided by CLK14 to the left end of GL4 to perform far-end compensation for GL4.

[0286] When the potential of the sixth first node included in GA6 is high, MC5 turns on and writes the fifth clock signal provided by CLK25 to the right end of GL5 to perform far-end compensation for GL5.

[0287] When the potential of the seventh first node included in GA7 is high, MC6 turns on and writes the sixth clock signal provided by CLK16 to the left end of GL6 to perform far-end compensation for GL6.

[0288] When the potential of the eighth first node included in GA8 is high, MC7 turns on and writes the seventh clock signal provided by CLK27 to the right end of GL7 to perform far-end compensation for GL7.

[0289] When the potential of the ninth first node included in GA9 is high, MC8 turns on and writes the eighth clock signal provided by CLK18 to the left end of GL8 to perform far-end compensation for GL8.

[0290] Figure 6A is a layout diagram of the two driving circuits included in the driving module located to the left of the display area A0.

[0291] In Figure 6A, the transistor labeled MC0 is the redundant output control transistor, and the transistor labeled MC2 is the second output control transistor.

[0292] M6-1 is the driving transistor in the first driving circuit, and M6-3 is the driving transistor in the third driving circuit; GT1 is the first driving output terminal, GT2 is the second driving output terminal, and GT3 is the third driving output terminal.

[0293] The gate of MC0 is electrically connected to the first node, the first electrode of MC0 is electrically connected to CLK18, and the second electrode of MC0 is floating.

[0294] MC0 and M6-1 are electrically connected via a first connecting part B1, which has a first hollow part L1.

[0295] MC2 and M6-3 are electrically connected via a second connecting part B2, which has a second hollow part L2.

[0296] In at least one embodiment of this disclosure, a redundant output control transistor MC0 may be provided in the first driving circuit, with the second electrode of MC0 floating to ensure process consistency.

[0297] As shown in Figure 6A, each clock signal line is located on the far left. MC0 and M6-1 are placed in close proximity, and the gates of MC0 and M6-1 are electrically connected to the first node. MC2 and M6-3 are placed in close proximity, and the gates of MC2 and M6-3 are electrically connected to the third node.

[0298] At the same time, because the potential of the first node will rise twice, the potential of the first node is more than twice the high voltage value VGH.

[0299] The first connecting part B1 has a first hollowed-out part L1, and the second connecting part B2 has a second hollowed-out part L2. The first connecting part B1 and the second connecting part B2 are hollowed out to avoid overheating and burnout caused by excessive voltage. At the same time, it can also reduce the proportion of the large metal side area, which affects the curing of the sealant after UV (laser) light transmittance.

[0300] As shown in Figure 6B, the width of the first cutout L1 in the horizontal direction is smaller than the width of the gate GC0 of MC0 in the horizontal direction.

[0301] The width of the second cutout L2 in the horizontal direction is smaller than the width of the gate GC2 of MC2 in the horizontal direction.

[0302] The width of GC0 in the horizontal direction is equal to the width of the gate G6-1 of M6-1 in the horizontal direction;

[0303] The width of GC2 in the horizontal direction is equal to the width of the gate G6-3 of M6-3 in the horizontal direction;

[0304] The vertical length of GC0 is less than the vertical length of the gate G6-1 of M6-1;

[0305] The vertical length of GC2 is less than the vertical length of the gate G6-3 of M6-3.

[0306] As shown in Figures 6A and 6D, the first electrode SC2 of MC2 is electrically connected to CLK12 through the first connecting line LX1, and the second electrode DC2 of MC2 is electrically connected to GT2 through the second connecting line LX2; both LX1 and LX2 are bent connecting lines.

[0307] In Figure 6G, the line labeled DY is a virtual extension line;

[0308] The virtual extension DY of the second connecting line L2 in the horizontal direction intersects with the first connecting line L1.

[0309] As shown in Figures 6A-6G, MC2 can be set up using the space between M6-1 and M6-3 to save vertical space.

[0310] In at least one embodiment shown in Figure 6A, in the first driving circuit, the gate of MC0 is electrically connected to the first first node, the first electrode of MC0 is electrically connected to CLK18, and the second electrode of MC0 is floating; the first electrode of M6-1 is electrically connected to CLK11, and the second electrode of M6-1 is electrically connected to GT1.

[0311] In the third driving circuit, the gate of MC2 is electrically connected to the third first node, the first electrode of MC2 is electrically connected to CLK12, and the second electrode of MC2 is electrically connected to GT2; the first electrode of M6-3 is electrically connected to CLK13, and the second electrode of M6-3 is electrically connected to GT3.

[0312] Figure 6B is a layout diagram of the gate metal layer in Figure 6A; Figure 6C is a layout diagram of the semiconductor layer in Figure 6A; Figures 6D and 6G are layout diagrams of the source and drain metal layers in Figure 6A.

[0313] Figure 6E is a stack-up diagram of the gate metal layer and semiconductor layer in Figure 6A, and Figure 6F is a layout diagram of the semiconductor layer and source / drain metal layer in Figure 6B.

[0314] In Figure 6B, the gate of MC0 is labeled GC0. As shown in Figure 6D, the first electrode of MC0 is labeled SC0, and the second electrode of MC0 is labeled DC0.

[0315] As shown in Figure 6B, GC2 is the gate of MC2. As shown in Figure 6D, SC2 is the first electrode of MC2, and DC2 is the second electrode of MC2.

[0316] As shown in Figure 6B, the gate labeled G6-1 is the gate of MC6-1, and the gate labeled G6-3 is the gate of MC6-3.

[0317] In Figure 6B, the part labeled B1 is the first connecting part, the part labeled L1 is the first hollow part, the part labeled B2 is the second connecting part, and the part labeled L2 is the second hollow part.

[0318] In Figure 6C, the active pattern labeled AC0 is MC0, the active pattern labeled AC2 is MC2, the active pattern labeled A6-1 is M6-1, and the active pattern labeled A6-3 is M6-3.

[0319] Figure 7A is a layout diagram of the two driving circuits included in the driving module located to the left of the display area A0.

[0320] In Figure 7A, the transistor labeled MC1 is the first output control transistor, and the transistor labeled MC4 is the third output control transistor.

[0321] M6-2 is the driving transistor in the second driving circuit, and M6-4 is the driving transistor in the fourth driving circuit; GT1 is the first driving output terminal, GT2 is the second driving output terminal, GT3 is the third driving output terminal, and GT4 is the fourth driving output terminal.

[0322] The gate of MC1 is electrically connected to the second first node, the first electrode of MC1 is electrically connected to CLK21, and the second electrode of MC1 is electrically connected to GT1.

[0323] MC1 and M6-2 are electrically connected via a third connecting part B3, wherein the third connecting part B3 has a third hollow part L3;

[0324] MC3 and M6-4 are electrically connected through a fourth connecting part B4, which has a fourth hollow part L4.

[0325] As shown in Figure 7A, each clock signal line is located on the far right. MC1 and M6-2 are placed in close proximity, and the gates of MC1 and M6-2 are electrically connected to the second first node. MC3 and M6-4 are placed in close proximity, and the gates of MC3 and M6-4 are electrically connected to the fourth first node.

[0326] At the same time, because the potential of the first node will rise twice, the potential of the first node is more than twice the high voltage value VGH.

[0327] The third connecting part B3 has a third hollow part L3, and the fourth connecting part B4 has a fourth hollow part L4. The third connecting part B3 and the fourth connecting part B4 are hollowed out to avoid overheating and burnout caused by excessive voltage. At the same time, it can also reduce the proportion of the large metal side area, which affects the curing of the sealant after UV (laser) light transmittance.

[0328] In at least one embodiment shown in FIG7A, in the second driving circuit, the gate of MC1 is electrically connected to the second first node, the first electrode of MC1 is electrically connected to CLK21, and the second electrode of MC1 is electrically connected to GT1; the first electrode of M6-2 is electrically connected to CLK22, and the second electrode of M6-2 is electrically connected to GT2.

[0329] In the fourth driving circuit, the gate of MC3 is electrically connected to the fourth first node, the first electrode of MC3 is electrically connected to CLK23, and the second electrode of MC3 is electrically connected to GT3; the first electrode of M6-4 is electrically connected to CLK24, and the second electrode of M6-4 is electrically connected to GT4.

[0330] Figure 7B is a layout diagram of the gate metal layer in Figure 7A; Figure 7C is a layout diagram of the semiconductor layer in Figure 7A; Figure 7D is a layout diagram of the source and drain metal layers in Figure 7A.

[0331] Figure 7E is a stack-up diagram of the gate metal layer and semiconductor layer in Figure 7A, and Figure 7F is a layout diagram of the semiconductor layer and source / drain metal layer in Figure 7B.

[0332] In Figure 7B, the gate of MC1 is labeled GC1. As shown in Figure 7D, the first electrode of MC1 is labeled SC1, and the second electrode of MC1 is labeled DC1.

[0333] As shown in Figure 7B, GC3 is the gate of MC3. As shown in Figure 7D, SC3 is the first electrode of MC3, and DC3 is the second electrode of MC3.

[0334] As shown in Figure 7B, the gate labeled G6-2 is the gate of MC6-2, and the gate labeled G6-4 is the gate of MC6-4.

[0335] In Figure 7B, the part labeled B3 is the third connecting part, the part labeled L3 is the third hollow part, the part labeled B4 is the fourth connecting part, and the part labeled L4 is the fourth hollow part.

[0336] In Figure 7C, the active pattern labeled AC1 is MC1, the active pattern labeled AC3 is MC3, the active pattern labeled A6-2 is M6-2, and the active pattern labeled A6-4 is M6-4.

[0337] Figure 7G is a layout diagram of a portion of the driving module located to the left of display area A0, including a driving circuit and a first redundant driving circuit.

[0338] In Figure 7G, the last driving circuit can be the 1080th driving circuit; the one labeled MC1080 is the 1080th output control transistor.

[0339] The terminal labeled GT1080 is the first 1080 drive output terminal, and GT1080 is electrically connected to the left end of the first 1080 row of gate lines included in the display substrate.

[0340] The terminal labeled GTM1 is the drive output terminal of the first redundant drive circuit; the terminals labeled M6-M1 are the drive transistors in the first redundant drive circuit.

[0341] GTM1 is electrically connected to the left end of the first row of redundant gate lines.

[0342] As shown in Figure 7G, the gate of MC1080 is electrically connected to the first node of the first redundant drive circuit included in the drive module. The potential of the first node of the first redundant drive circuit included in the drive module controls MC1080 to provide a corresponding drive signal to the left end of the first 1080 row gate line.

[0343] In at least one embodiment shown in Figure 7G, the MC1080 can be electrically connected to the corresponding clock signal line according to the actual situation, and the driving circuit and redundant driving circuit can also replace the clock signal line electrically connected to them according to the actual situation.

[0344] Figure 8A is a layout diagram of the two driving circuits included in the driving module located to the left of the display area A0.

[0345] In Figure 8A, MC0 is the redundant output control transistor, and MC2 is the second output control transistor; M6-1 is the driving transistor in the first driving circuit, and M6-3 is the driving transistor in the third driving circuit; M11-1 is the eleventh transistor in the first driving circuit, M10-1 is the tenth transistor in the first driving circuit, M11-3 is the eleventh transistor in the third driving circuit, and M10-3 is the tenth transistor in the third driving circuit; GT1 is the first driving output terminal, GT2 is the second driving output terminal, and GT3 is the third driving output terminal.

[0346] As shown in Figure 8A, MC0 and M6-1 are designed separately, and MC2 and M6-3 are designed separately.

[0347] Placing MC0 and M10-1 close together, and MC2 and M10-3 close together, allows MC0 and M10-1 to share the first node, and MC2 and M10-3 to share the third node, thus saving layout space.

[0348] In Figure 8A, M10-1 and M11-1 are transistors included in the pull-down reset circuit of the first driving circuit, and M10-3 and M11-3 are transistors included in the pull-down reset circuit of the third driving circuit.

[0349] As shown in Figure 8A, in the first driving circuit, the first electrode of MC0 is electrically connected to CLK18, and the second electrode of MC0 is floating; the first electrode of M6-1 is electrically connected to CLK11, and the second electrode of M6-1 is electrically connected to GT1.

[0350] In the third drive circuit, the first electrode of MC2 is electrically connected to CLK12, and the second electrode of MC2 is electrically connected to GT2; the first electrode of M6-3 is electrically connected to CLK13, and the second electrode of M6-3 is electrically connected to GT3.

[0351] By placing MC0 and M10-1 close together, and MC2 and M10-3 close together, the layout space of M6-1 and M6-3 can be increased. This allows for a 25% reduction in the horizontal space of the active graphic in M6-1 and an increase in the vertical space of the active graphic in M6-1, ensuring that the size of the active graphic in M6-1 remains unchanged. Similarly, by reducing the horizontal space of the active graphic in M6-3 by 25% and increasing the vertical space of the active graphic in M6-3, the size of the active graphic in M6-3 remains unchanged, thereby reducing the bezel of the entire display substrate.

[0352] Figure 8B is a layout diagram of the gate metal layer in Figure 8A; Figure 8C is a layout diagram of the semiconductor layer in Figure 8A; Figure 8D is a layout diagram of the source and drain metal layers in Figure 8A.

[0353] Figure 8E is a stack-up diagram of the gate metal layer and semiconductor layer in Figure 8A, and Figure 8F is a layout diagram of the semiconductor layer and source / drain metal layer in Figure 8B.

[0354] In Figure 8B, the gate labeled GC0 is the gate of MC0, the gate labeled GC2 is the gate of MC2; the gate labeled G6-1 is the gate of M6-1, and the gate labeled G6-3 is the gate of M6-3.

[0355] The first gate pattern is labeled GX1, and the third gate pattern is labeled GX3.

[0356] GX1 includes the gate of M10-1 and the gate of M11-1, and GX3 includes the gate of M10-3 and the gate of M11-3.

[0357] The minimum distance between GC0 and GX1 is 4µm;

[0358] The minimum distance between GC2 and GX3 is 4µm.

[0359] In at least one embodiment shown in Figures 8A-8F, the minimum distance between GC0 and the gate of the transistor included in the pull-down reset circuit in the first driving circuit is set to 4μm, and the minimum distance between GC2 and the gate of the transistor included in the pull-down reset circuit in the third driving circuit is set to 4μm, in order to save space layout.

[0360] In Figure 8C, the active pattern labeled AC0 is MC0, and the active pattern labeled AC2 is MC2.

[0361] The active graphic labeled A6-1 is M6-1, and the active graphic labeled A6-3 is M6-3.

[0362] In Figure 8G, LD1 represents the vertical length of A6-1, and LD2 represents the horizontal length of A6-1.

[0363] In Figure 8D, the electrode labeled SC0 is the first electrode of MC0, and the electrode labeled DC0 is the second electrode of MC0.

[0364] The electrode labeled SC2 is the first electrode of MC2, and the electrode labeled DC2 is the second electrode of MC2.

[0365] Figure 9A is a layout diagram of the two driving circuits included in the driving module located to the left of the display area A0.

[0366] In Figure 9A, MC1 is the first output control transistor, and MC3 is the third output control transistor; M6-2 is the driving transistor in the second driving circuit, and M6-4 is the driving transistor in the fourth driving circuit; M11-2 is the eleventh transistor in the second driving circuit, M10-2 is the tenth transistor in the second driving circuit, M11-4 is the eleventh transistor in the fourth driving circuit, and M10-4 is the tenth transistor in the fourth driving circuit; GT1 is the first driving output terminal, GT2 is the second driving output terminal, GT3 is the third driving output terminal, and GT4 is the fourth driving output terminal.

[0367] In Figure 9A, M10-1 and M11-1 are transistors included in the pull-down reset circuit of the first driving circuit, and M10-3 and M11-3 are transistors included in the pull-down reset circuit of the third driving circuit.

[0368] As shown in Figure 9A, MC1 and M6-2 are designed separately, and MC3 and M6-4 are designed separately.

[0369] Placing MC1 and M10-2 close together, and MC3 and M10-4 close together, allows MC1 and M10-2 to share the second first node, and MC3 and M10-4 to share the fourth first node, thus saving layout space.

[0370] As shown in Figure 9A, in the second driving circuit, the first electrode of MC1 is electrically connected to CLK21, and the second electrode of MC1 is electrically connected to GT1; the first electrode of M6-2 is electrically connected to CLK22, and the second electrode of M6-2 is electrically connected to GT2.

[0371] In the fourth drive circuit, the first electrode of MC3 is electrically connected to CLK23, and the second electrode of MC3 is electrically connected to GT3; the first electrode of M6-4 is electrically connected to CLK24, and the second electrode of M6-4 is electrically connected to GT4.

[0372] By placing MC1 and M10-2 close together, and MC3 and M10-4 close together, the layout space of M6-2 and M6-4 can be increased. This allows for a 25% reduction in the horizontal space of the active graphic in M6-2 and an increase in the vertical space of the active graphic in M6-2, ensuring that the size of the active graphic in M6-2 remains unchanged. Similarly, the horizontal space of the active graphic in M6-4 can be reduced by 25%, and the vertical space of the active graphic in M6-4 can be increased, ensuring that the size of the active graphic in M6-4 remains unchanged. This, in turn, reduces the bezel of the entire display substrate.

[0373] Figure 9B is a layout diagram of the gate metal layer in Figure 9A; Figure 9C is a layout diagram of the semiconductor layer in Figure 9A; Figure 9D is a layout diagram of the source and drain metal layers in Figure 9A.

[0374] Figure 9E is a stack-up diagram of the gate metal layer and semiconductor layer in Figure 9A, and Figure 9F is a layout diagram of the semiconductor layer and source / drain metal layer in Figure 9B.

[0375] In Figure 9B, the gate labeled GC1 is the gate of MC1, the gate labeled GC3 is the gate of MC3; the gate labeled G6-2 is the gate of M6-2, and the gate labeled G6-4 is the gate of M6-4.

[0376] The pattern labeled GX2 is the second gate pattern, and the pattern labeled GX4 is the fourth gate pattern;

[0377] GX2 includes the gate of M10-2 and the gate of M11-2, and GX4 includes the gate of M10-4 and the gate of M11-4.

[0378] The minimum distance between GC1 and GX2 is 4µm;

[0379] The minimum distance between GC3 and GX4 is 4µm.

[0380] In Figure 9C, the active pattern labeled AC1 is MC1, and the active pattern labeled AC3 is MC3.

[0381] The active graphic labeled A6-2 is M6-2, and the active graphic labeled A6-4 is M6-4.

[0382] In Figure 9D, the electrode labeled SC1 is the first electrode of MC1, and the electrode labeled DC1 is the second electrode of MC1.

[0383] The electrode labeled SC2 is the first electrode of MC2, and the electrode labeled DC2 is the second electrode of MC2.

[0384] As shown in Figure 10, CLK11 is the first clock signal line, CLK12 is the first second clock signal line, CLK13 is the first third clock signal line, CLK14 is the first fourth clock signal line, CLK15 is the first fifth clock signal line, CLK16 is the first sixth clock signal line, CLK17 is the first seventh clock signal line, and CLK18 is the first eighth clock signal line.

[0385] The line labeled CLK21 is the second first clock signal line, the line labeled CLK22 is the second second clock signal line, the line labeled CLK23 is the second third clock signal line, the line labeled CLK24 is the second fourth clock signal line, the line labeled CLK25 is the second fifth clock signal line, the line labeled CLK26 is the second sixth clock signal line, the line labeled CLK27 is the second seventh clock signal line, and the line labeled CLK28 is the second eighth clock signal line.

[0386] The circuit labeled GA1 is the first drive circuit included in the drive module, the circuit labeled GA2 is the second drive circuit included in the drive module, the circuit labeled GA3 is the third drive circuit included in the drive module, and the circuit labeled GA4 is the fourth drive circuit included in the drive module.

[0387] The circuit labeled GA5 is the fifth drive circuit included in the drive module; the circuit labeled GA6 is the sixth drive circuit included in the drive module; the circuit labeled GA7 is the seventh drive circuit included in the drive module; the circuit labeled GA8 is the eighth drive circuit included in the drive module; and the circuit labeled GA9 is the ninth drive circuit included in the drive module.

[0388] The first row of gate lines is labeled GL1, the second row is labeled GL2, the third row is labeled GL3, the fourth row is labeled GL4, the fifth row is labeled GL5, the sixth row is labeled GL6, the seventh row is labeled GL7, and the eighth row is labeled GL8.

[0389] CLK11, CLK12, CLK13, CLK14, CLK15, CLK16, CLK17, CLK18, GA1, GA3, GA5, GA7 and GA9 can be set in the first side area AC1;

[0390] CLK21, CLK22, CLK23, CLK24, CLK25, CLK26, CLK27, CLK28, GA2, GA4, GA6 and GA8 can be set in the second side area AC2;

[0391] CLK11 and CLK21 are both connected to the first clock signal, CLK12 and CLK22 are both connected to the second clock signal, CLK13 and CLK23 are both connected to the third clock signal, CLK14 and CLK24 are both connected to the fourth clock signal, CLK15 and CLK25 are both connected to the fifth clock signal, CLK16 and CLK26 are both connected to the sixth clock signal, CLK17 and CLK27 are both connected to the seventh clock signal, and CLK18 and CLK28 are both connected to the eighth clock signal.

[0392] The area labeled A0 is the display area;

[0393] The first side area AC1 is located on the left side of the display area A0, and the second side area AC2 is located on the right side of the display area A0.

[0394] As shown in Figure 10, the first drive output terminal of GA1 is electrically connected to the left side of G1, and the second drive output terminal of GA2 is electrically connected to the right side of G2.

[0395] The first drive output terminal of GA3 is electrically connected to the left side of G3, and the second drive output terminal of GA4 is electrically connected to the right side of G4.

[0396] The first drive output terminal of GA5 is electrically connected to the left side of G5, and the second drive output terminal of GA6 is electrically connected to the right side of G6.

[0397] The first drive output terminal of GA7 is electrically connected to the left side of G7, and the second drive output terminal of GA8 is electrically connected to the right side of G8.

[0398] The line labeled STV1 is the first starting voltage line, and the line labeled STV2 is the second starting voltage line.

[0399] In Figure 10, the transistor labeled MC1 is the first output control transistor, the transistor labeled MC2 is the second output control transistor, the transistor labeled MC3 is the third output control transistor, the transistor labeled MC4 is the fourth output control transistor, the transistor labeled MC5 is the fifth output control transistor, the transistor labeled MC6 is the sixth output control transistor, the transistor labeled MC7 is the seventh output control transistor, and the transistor labeled MC8 is the eighth output control transistor.

[0400] The gate of MC1 is electrically connected to the second drive output terminal of GA2, the first electrode of MC1 is electrically connected to CLK21, GA2 is electrically connected to CLK11, and the second electrode of MC1 is electrically connected to the right end of GL1.

[0401] The gate of MC2 is electrically connected to the third drive output terminal of GA3, the first electrode of MC2 is electrically connected to CLK12, the second electrode of MC2 is electrically connected to the left end of GL2; GA3 is electrically connected to CLK22.

[0402] The gate of MC3 is electrically connected to the fourth drive output terminal of GA4; the first electrode of MC3 is electrically connected to CLK23; GA3 is electrically connected to CLK13; and the second electrode of MC3 is electrically connected to the right end of GL3.

[0403] The gate of MC4 is electrically connected to the fifth drive output terminal of GA5, the first electrode of MC4 is electrically connected to CLK14, the second electrode of MC4 is electrically connected to the left end of GL4, and GA5 is electrically connected to CLK24.

[0404] The gate of MC5 is electrically connected to the sixth drive output terminal of GA6, the first electrode of MC5 is electrically connected to CLK25, GA5 is electrically connected to CLK15, and the second electrode of MC5 is electrically connected to the right end of GL5.

[0405] The gate of MC6 is electrically connected to the seventh drive output terminal of GA7, the first electrode of MC6 is electrically connected to CLK16, the second electrode of MC6 is electrically connected to the left end of GL6, and GA7 is electrically connected to CLK26.

[0406] The gate of MC7 is electrically connected to the eighth drive output terminal of GA8; the first electrode of MC7 is electrically connected to CLK27; GA7 is electrically connected to CLK17; and the second electrode of MC7 is electrically connected to the right end of GL7.

[0407] The gate of MC8 is electrically connected to the ninth drive output terminal of GA9, the first electrode of MC8 is electrically connected to CLK18, the second electrode of MC8 is electrically connected to the left end of GL8, and GA9 is electrically connected to CLK28.

[0408] In at least one embodiment of the display substrate shown in FIG10, eight clock signal lines are provided on the left side of the display panel and eight clock signal lines are also provided on the right side of the display panel.

[0409] At least one embodiment of the display substrate shown in FIG10 of this disclosure, when in operation,

[0410] When the second drive output terminal of GA2 outputs a high voltage signal, MC1 turns on and writes the first clock signal provided by CLK21 to the right end of GL1 to perform far-end compensation on GL1.

[0411] When the third drive output terminal of GA3 outputs a high voltage signal, MC2 turns on and writes the second clock signal provided by CLK12 to the left end of GL2 to perform far-end compensation for GL2.

[0412] When the fourth drive output terminal of GA4 outputs a high voltage signal, MC3 turns on and writes the third clock signal provided by CLK23 to the right end of GL3 to perform far-end compensation on GL3.

[0413] When the fifth drive output terminal of GA5 outputs a high voltage signal, MC4 turns on and writes the fourth clock signal provided by CLK14 to the left end of GL4 to perform far-end compensation on GL4.

[0414] When the sixth drive output terminal of GA6 outputs a high voltage signal, MC5 turns on and writes the fifth clock signal provided by CLK25 to the right end of GL5 to perform far-end compensation for GL5.

[0415] When the seventh drive output terminal of GA7 outputs a high voltage signal, MC6 turns on and writes the sixth clock signal provided by CLK16 to the left end of GL6 to perform far-end compensation for GL6.

[0416] When the eighth drive output terminal of GA8 outputs a high voltage signal, MC7 turns on and writes the seventh clock signal provided by CLK27 to the right end of GL7 to perform far-end compensation for GL7.

[0417] When the ninth drive output terminal of GA9 outputs a high voltage signal, MC8 turns on and writes the eighth clock signal provided by CLK18 to the left end of GL8 to perform far-end compensation on GL8.

[0418] As shown in Figure 11, when at least one embodiment of the display substrate shown in Figure 10 is in operation, when CLK22 provides a high voltage signal, the second drive output terminal GT2 of GA2 will output a high voltage signal, which will turn on MC1. Therefore, the high-level signal of CLK21 will be output to the right end of GL1 (CLK21 and CLK11 are the same clock signal), achieving the effect of remote noise reduction.

[0419] In Figure 11, S1 is the signal output by MC1.

[0420] Figure 12 is a timing diagram of the operation of the display substrate according to at least one embodiment of the present disclosure when the display substrate includes 1080 driving circuits in at least one embodiment.

[0421] In Figure 12, GT1 is the drive output terminal of the first drive circuit, GT2 is the drive output terminal of the second drive circuit, GT3 is the drive output terminal of the third drive circuit, GT4 is the drive output terminal of the fourth drive circuit, GT1080 is the drive output terminal of the 1080th drive circuit, GTM1 is the drive output terminal of the first redundant drive circuit, GTM2 is the drive output terminal of the second redundant drive circuit, GTM3 is the drive output terminal of the third redundant drive circuit, GTM4 is the drive output terminal of the fourth redundant drive circuit, and GTM5 is the drive output terminal of the fifth redundant drive circuit.

[0422] In at least one embodiment of this disclosure, each redundant drive circuit can be used to provide a reset signal for the last few drive circuits included in the drive module.

[0423] As shown in Figure 12, when the display substrate described in at least one embodiment of this disclosure is in operation,

[0424] First, during the 4H period, the frame reset signal provided by TRST is a high voltage signal, which reduces noise for the first node in advance;

[0425] After TRST provides a low voltage signal for 1H, STV provides a high voltage signal within 7H, turning on the first drive circuit, the second drive circuit, the third drive circuit, and the fourth drive circuit.

[0426] After STV provides high voltage signals 4H-7H, each clock signal line outputs its corresponding clock signal in sequence, and each drive circuit outputs its corresponding drive signal in sequence, thus ending one frame.

[0427] In at least one embodiment of this disclosure, the high-level duration of each clock signal can be 4H, and the (n+1)th clock signal can be delayed by 1H compared to the nth clock signal, where n is a positive integer.

[0428] In at least one embodiment of this disclosure, 1H can be equal to one frame time / N, where N is equal to the sum of the number of rows of the driving circuits included in the driving module and the number of buffer rows, and N is a positive integer; the number of buffer rows is generally 40-80 rows.

[0429] For example, when the display refresh rate is 60Hz, and the number of rows of the driving circuit included in the driving module is equal to 1600 and the number of buffer rows is equal to 60, 1H can be equal to 5.11μs.

[0430] Figure 13A is a layout diagram of the two driving circuits included in the driving module located to the left of the display area A0.

[0431] In Figure 13A, the transistor labeled MC0 is the redundant output control transistor, and the transistor labeled MC2 is the second output control transistor; the transistor labeled M6-1 is the drive transistor in the first drive circuit, and the transistor labeled M6-3 is the drive transistor in the third drive circuit; the transistor labeled GT1 is the first drive output terminal, the transistor labeled GT2 is the second drive output terminal, and the transistor labeled GT3 is the third drive output terminal.

[0432] As shown in Figure 13A, the clock signal lines are arranged on the far left. MC0 and M6-1 are placed close to each other, as are MC2 and MC6-3. The gate of MC0 is electrically connected to the second electrode of M6-1. The second electrode of M6-1 is used to output the first drive signal, and the gate of MC2 is electrically connected to the second electrode of M6-3. The second electrode of M6-3 is used to output the third drive signal. Typically, the second electrode of M6-1 is formed on the source / drain metal layer, and the gate of MC0 is formed on the gate metal layer. Therefore, the second electrode of M6-1 is electrically connected to the gate of MC0 through a first via H1, which can be a via penetrating the gate insulating layer. The second electrode of M6-3 is formed on the source / drain metal layer, and the gate of MC2 is formed on the gate metal layer. Therefore, the second electrode of M6-3 is electrically connected to the gate of MC2 through a second via H2, which can be a via penetrating the gate insulating layer.

[0433] Figure 13B is a layout diagram of the gate metal layer in Figure 13A, Figure 13C is a layout diagram of the semiconductor layer in Figure 13A, Figure 13D is a layout diagram of the source and drain metal layers in Figure 13A, Figure 13E is a stacked diagram of the gate metal layer and the semiconductor layer in Figure 13A, and Figure 13F is a stacked diagram of the semiconductor layer and the source and drain metal layers in Figure 13A.

[0434] In Figure 13B, the gate labeled GC0 is the gate of MC0, the gate labeled GC2 is the gate of MC2, the first connection pattern is labeled LX1, the second connection pattern is labeled LX2, the gate labeled G6-1 is the gate of M6-1, and the gate labeled G6-3 is the gate of M6-3.

[0435] In Figure 13B, the shortest distance between GC0 and G6-1 is greater than or equal to 4 μm and less than 10 μm, and the shortest distance between GC2 and G6-3 is greater than or equal to 4 μm and less than 10 μm.

[0436] In Figure 13C, the active pattern labeled AC0 is MC0, the active pattern labeled AC2 is MC2, the active pattern labeled A6-1 is M6-1, and the active pattern labeled A6-3 is M6-3.

[0437] In Figure 13D, the electrode labeled D6-1 is the second electrode of M6-1, and the electrode labeled D6-3 is the second electrode of M6-3.

[0438] In at least one embodiment shown in Figures 13A-13F, the width of the gate GC0 of MC0 in the horizontal direction is smaller than the width of the gate G6-1 of M6-1 in the horizontal direction.

[0439] The width of the gate GC2 of MC2 in the horizontal direction is smaller than the width of the gate G6-3 of M6-3 in the horizontal direction.

[0440] Figure 14A is a layout diagram of the two driving circuits included in the driving module located to the left of the display area A0.

[0441] In Figure 14A, MC1 is the first output control transistor, MC3 is the third output control transistor; M6-2 is the driving transistor in the second driving circuit, M6-4 is the driving transistor in the fourth driving circuit; GT1 is the first driving output terminal, GT2 is the second driving output terminal, GT3 is the third driving output terminal, and GT4 is the fourth driving output terminal.

[0442] As shown in Figure 14A, the clock signal lines are arranged on the far right. MC1 and M6-2 are placed close to each other, as are MC3 and MC6-4. The gate of MC1 is electrically connected to the second electrode of M6-2. The second electrode of M6-2 is used to output the second drive signal. The gate of MC3 is electrically connected to the second electrode of M6-4. The second electrode of M6-4 is used to output the fourth drive signal. Typically, the second electrode of M6-2 is formed on the source / drain metal layer, and the gate of MC1 is formed on the gate metal layer. Therefore, the second electrode of M6-2 is electrically connected to the gate of MC1 through a third via H3, which can be a via penetrating the gate insulating layer. The second electrode of M6-4 is formed on the source / drain metal layer, and the gate of MC3 is formed on the gate metal layer. Therefore, the second electrode of M6-4 is electrically connected to the gate of MC3 through a fourth via H4, which can also be a via penetrating the gate insulating layer.

[0443] Figure 14B is a layout diagram of the gate metal layer in Figure 14A, Figure 14C is a layout diagram of the semiconductor layer in Figure 14A, Figure 14D is a layout diagram of the source and drain metal layers in Figure 14A, Figure 14E is a stacked diagram of the gate metal layer and the semiconductor layer in Figure 14A, and Figure 14F is a stacked diagram of the semiconductor layer and the source and drain metal layers in Figure 14A.

[0444] In Figure 14B, the gate labeled GC1 is the gate of MC1, the gate labeled GC3 is the gate of MC3, the third connection pattern is labeled LX3, the fourth connection pattern is labeled LX4, the gate labeled G6-2 is the gate of M6-2, and the gate labeled G6-4 is the gate of M6-4.

[0445] In Figure 14B, the shortest distance between GC1 and G6-2 is greater than or equal to 4 μm and less than 10 μm, and the shortest distance between GC3 and G6-4 is greater than or equal to 4 μm and less than 10 μm.

[0446] In Figure 14C, the active pattern labeled AC1 is MC1, the active pattern labeled AC3 is MC3, the active pattern labeled A6-2 is M6-2, and the active pattern labeled A6-4 is M6-4.

[0447] In Figure 14D, the electrode labeled D6-2 is the second electrode of M6-2, and the electrode labeled D6-4 is the second electrode of M6-4.

[0448] As shown in Figure 15, when the driving module in the display substrate described in at least one embodiment of this disclosure is used, the addition of an output control transistor can reduce the Tf difference between the near and far ends of each row of gate lines from 0.29μs to 0.05μs, and reduce the pixel voltage difference ΔVp corresponding to the gate driving signal at the near and far ends of the gate lines from 31mV to 3.3mV, that is, reduce the difference from 2.5 gray levels to 0.3 gray levels, and the improvement effect is very obvious;

[0449] At least one embodiment of this disclosure can effectively reduce the difference in charging voltage between the near and far ends of the gate line, and completely solve the red and green color defects in Dual Gate display products and Triple Gate display products.

[0450] In at least one embodiment of this disclosure, only one transistor is added to a driving circuit, which does not occupy GOA (Gate On Array) layout space, making the design simple and effectively reducing the bezel of the display product.

[0451] At least one embodiment of this disclosure improves the display defects of display products without increasing costs or changing the process flow.

[0452] In Figure 15, the first curve LS1 is the waveform of the drive signal provided near the gate line, and the second curve LS2 is the waveform of the drive signal provided far from the gate line.

[0453] At least one embodiment of the present disclosure describes a display substrate including a multi-row, multi-column pixel circuit disposed in a display area; b is a positive integer;

[0454] The pixel circuit located in row b is electrically connected to the gate line in row 2b-1, and is used to access the corresponding data voltage under the control of the driving signal provided by the gate line in row 2b-1;

[0455] Another portion of the pixel circuit located in row b is electrically connected to the gate line in row 2b, and is used to receive the corresponding data voltage under the control of the 2b drive signal provided by the gate line in row 2b.

[0456] As shown in Figure 16, the red pixel circuit R11 in the first row and first column is electrically connected to the first row gate line GL1 and the first column data line DL1, respectively; the green pixel circuit G12 in the first row and second column is electrically connected to the second row gate line GL2 and the first column data line DL1, respectively.

[0457] The blue pixel circuit B13 in the first row and third column is electrically connected to the gate line GL2 in the second row and the data line DL2 in the second column, respectively; the red pixel circuit G14 in the first row and fourth column is electrically connected to the gate line GL1 in the first row and the data line DL2 in the second column, respectively.

[0458] The green pixel circuit G15 in the first row and fifth column is electrically connected to the gate line GL2 in the second row and the data line DL3 in the third column, respectively. The blue pixel circuit B16 in the first row and sixth column is electrically connected to the gate line GL2 in the first row and the data line DL3 in the third column, respectively.

[0459] The red pixel circuit R17 in the first row and seventh column is electrically connected to the first row gate line GL1 and the fourth column data line DL4, respectively. The green pixel circuit G18 in the first row and eighth column is electrically connected to the second row gate line GL2 and the fourth column data line DL4, respectively.

[0460] The blue pixel circuit B19 in the ninth column of the first row is electrically connected to the gate line GL2 in the second row and the data line DL5 in the fifth column; the red pixel circuit R110 in the tenth column of the first row is electrically connected to the gate line GL1 in the first row and the data line DL5 in the fifth column.

[0461] The green pixel circuit G111 in the first row and eleventh column is electrically connected to the gate line GL2 in the second row and the data line DL6 in the sixth column, respectively. The blue pixel circuit B112 in the first row and twelfth column is electrically connected to the gate line GL1 in the first row and the data line DL6 in the sixth column, respectively.

[0462] The red pixel circuit R113 in the first row and thirteenth column is electrically connected to the first row gate line GL1 and the seventh column data line DL7, respectively. The green pixel circuit G114 in the first row and fourteenth column is electrically connected to the second row gate line GL2 and the seventh column data line DL7, respectively.

[0463] The red pixel circuit R21 in the second row and first column is electrically connected to the gate line GL3 in the third row and the data line DL2 in the second column; the green pixel circuit G22 in the second row and second column is electrically connected to the gate line GL4 in the fourth row and the data line DL2 in the second column.

[0464] The blue pixel circuit B23 in the second row and third column is electrically connected to the gate line GL4 in the fourth row and the data line DL3 in the third column, respectively; the red pixel circuit R24 in the second row and fourth column is electrically connected to the gate line GL3 in the third row and the data line DL3 in the third column, respectively.

[0465] The green pixel circuit G25 in the second row and fifth column is electrically connected to the gate line GL4 in the fourth row and the data line DL4 in the fourth column, respectively. The blue pixel circuit B26 in the second row and sixth column is electrically connected to the gate line GL3 in the third row and the data line DL4 in the fourth column, respectively.

[0466] The red pixel circuit R27 in the second row and seventh column is electrically connected to the gate line GL3 in the third row and the data line DL5 in the fifth column, respectively. The green pixel circuit G28 in the second row and eighth column is electrically connected to the gate line GL4 in the fourth row and the data line DL5 in the fifth column, respectively.

[0467] The blue pixel circuit B29 in the second row and ninth column is electrically connected to the gate line GL4 in the fourth row and the data line DL6 in the sixth column, respectively; the red pixel circuit R210 in the second row and tenth column is electrically connected to the gate line GL3 in the third row and the data line DL5 in the sixth column, respectively.

[0468] The green pixel circuit G211 in the second row and eleventh column is electrically connected to the gate line GL4 in the fourth row and the data line DL7 in the seventh column, respectively. The blue pixel circuit B212 in the second row and twelfth column is electrically connected to the gate line GL3 in the third row and the data line DL7 in the seventh column, respectively.

[0469] The red pixel circuit R213 in the second row and thirteenth column is electrically connected to the gate line GL3 in the third row and the data line DL8 in the eighth column, respectively. The green pixel circuit G214 in the second row and fourteenth column is electrically connected to the gate line GL4 in the fourth row and the data line DL8 in the eighth column, respectively.

[0470] The red pixel circuit R31 in the third row and first column is electrically connected to the fifth row gate line GL5 and the first column data line DL1, respectively; the green pixel circuit G32 in the third row and second column is electrically connected to the sixth row gate line GL6 and the first column data line DL1, respectively.

[0471] The blue pixel circuit B33 in the third row and third column is electrically connected to the gate line GL6 in the sixth row and the data line DL2 in the second column, respectively; the red pixel circuit G34 in the third row and fourth column is electrically connected to the gate line GL5 in the fifth row and the data line DL2 in the second column, respectively.

[0472] The green pixel circuit G35 in the third row and fifth column is electrically connected to the gate line GL6 in the sixth row and the data line DL3 in the third column, respectively. The blue pixel circuit B36 in the third row and sixth column is electrically connected to the gate line GL5 in the fifth row and the data line DL3 in the third column, respectively.

[0473] The red pixel circuit R37 in the third row and seventh column is electrically connected to the fifth row gate line GL5 and the fourth column data line DL4, respectively. The green pixel circuit G38 in the third row and eighth column is electrically connected to the sixth row gate line GL6 and the fourth column data line DL4, respectively.

[0474] The blue pixel circuit B39 in the third row and ninth column is electrically connected to the gate line GL6 in the sixth row and the data line DL5 in the fifth column, respectively; the red pixel circuit R310 in the third row and tenth column is electrically connected to the gate line GL5 in the fifth row and the data line DL5 in the fifth column, respectively.

[0475] The green pixel circuit G311 in the third row and eleventh column is electrically connected to the gate line GL6 in the sixth row and the data line DL6 in the sixth column, respectively. The blue pixel circuit B312 in the third row and twelfth column is electrically connected to the gate line GL5 in the fifth row and the data line DL6 in the sixth column, respectively.

[0476] The red pixel circuit R313 in the third row and thirteenth column is electrically connected to the gate line GL5 in the fifth row and the data line DL7 in the seventh column, respectively. The green pixel circuit G314 in the third row and fourteenth column is electrically connected to the gate line GL6 in the sixth row and the data line DL7 in the seventh column, respectively.

[0477] The red pixel circuit R41 in the first column of the fourth row is electrically connected to the gate line GL7 in the seventh row and the data line DL2 in the second column; the green pixel circuit G42 in the second column of the fourth row is electrically connected to the gate line GL8 in the eighth row and the data line DL2 in the second column.

[0478] The blue pixel circuit B43 in the fourth row and third column is electrically connected to the gate line GL8 in the eighth row and the data line DL3 in the third column, respectively; the red pixel circuit R44 in the fourth row and fourth column is electrically connected to the gate line GL7 in the seventh row and the data line DL3 in the third column, respectively.

[0479] The green pixel circuit G45 in the fourth row and fifth column is electrically connected to the gate line GL8 in the eighth row and the data line DL4 in the fourth column, respectively. The blue pixel circuit B46 in the fourth row and sixth column is electrically connected to the gate line GL7 in the seventh row and the data line DL4 in the fourth column, respectively.

[0480] The red pixel circuit R47 in the fourth row and seventh column is electrically connected to the seventh row gate line GL7 and the fifth column data line DL5, respectively. The green pixel circuit G48 in the fourth row and eighth column is electrically connected to the eighth row gate line GL8 and the fifth column data line DL5, respectively.

[0481] The blue pixel circuit B49 in the fourth row and ninth column is electrically connected to the gate line GL8 in the eighth row and the data line DL6 in the sixth column, respectively; the red pixel circuit R410 in the fourth row and tenth column is electrically connected to the gate line GL7 in the seventh row and the data line DL5 in the sixth column, respectively.

[0482] The green pixel circuit G411 in the fourth row and eleventh column is electrically connected to the gate line GL8 in the eighth row and the data line DL7 in the seventh column, respectively. The blue pixel circuit B412 in the fourth row and twelfth column is electrically connected to the gate line GL7 in the seventh row and the data line DL7 in the seventh column, respectively.

[0483] The red pixel circuit R413 in the fourth row and thirteenth column is electrically connected to the gate line GL7 in the seventh row and the data line DL8 in the eighth column, respectively. The green pixel circuit G414 in the fourth row and fourteenth column is electrically connected to the gate line GL8 in the eighth row and the data line DL8 in the eighth column, respectively.

[0484] At least one embodiment of the present disclosure describes a display substrate including a multi-row, multi-column pixel circuit disposed in a display area; b is a positive integer;

[0485] The first color pixel circuit located in row 3b-2 is electrically connected to the gate line in row 3b-2, and is used to connect the corresponding data voltage under the control of the 3b-2 driving signal provided by the gate line in row 3b-2;

[0486] The second color pixel circuit located in row 3b-1 is electrically connected to the gate line in row 3b-1, and is used to connect the corresponding data voltage under the control of the driving signal provided by the gate line in row 3b-1;

[0487] The third color pixel circuit located in row 3b is electrically connected to the gate line in row 3b, and is used to connect the corresponding data voltage under the control of the third drive signal provided by the gate line in row 3b.

[0488] As shown in Figure 17, the red pixel circuit R11 in the first row and first column is electrically connected to the gate line GL1 in the first row, the red pixel circuit R12 in the first row and second column is electrically connected to the gate line GL1 in the first row, and the red pixel circuit R13 in the first row and third column is electrically connected to the gate line GL1 in the first row.

[0489] The green pixel circuit G21 in the first column of the second row is electrically connected to the gate line GL2 in the second row; the green pixel circuit G22 in the second column of the second row is electrically connected to the gate line GL2 in the second row; and the green pixel circuit G23 in the third column of the second row is electrically connected to the gate line GL2 in the second row.

[0490] The blue pixel circuit B31 in the first column of the third row is electrically connected to the gate line GL3 in the third row; the blue pixel circuit B32 in the second column of the third row is electrically connected to the gate line GL3 in the third row; and the blue pixel circuit B33 in the third column of the third row is electrically connected to the gate line GL3 in the third row.

[0491] The red pixel circuit R41 in the first column of the fourth row is electrically connected to the gate line GL4 in the fourth row; the red pixel circuit R42 in the second column of the fourth row is electrically connected to the gate line GL4 in the fourth row; and the red pixel circuit R43 in the third column of the fourth row is electrically connected to the gate line GL4 in the fourth row.

[0492] The green pixel circuit G51 in the first column of the fifth row is electrically connected to the gate line GL5 in the fifth row; the green pixel circuit G52 in the second column of the fifth row is electrically connected to the gate line GL5 in the fifth row; and the green pixel circuit G53 in the third column of the fifth row is electrically connected to the gate line GL5 in the fifth row.

[0493] The blue pixel circuit B61 in the first column of the sixth row is electrically connected to the gate line GL6 in the sixth row; the blue pixel circuit B62 in the second column of the sixth row is electrically connected to the gate line GL6 in the sixth row; and the blue pixel circuit B63 in the third column of the sixth row is electrically connected to the gate line GL6 in the sixth row.

[0494] R11, G21, B31, R41, G51 and B61 are all electrically connected to the first column of data lines DL1;

[0495] R12, G22, B32, R42, G52, and B62 are all electrically connected to the second column of data lines DL2;

[0496] R13, G23, B33, R43, G53, and B63 are all electrically connected to the third data line DL3.

[0497] The display device described in this disclosure includes the display substrate described above.

[0498] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A display substrate, comprising multiple rows of gate lines disposed on a substrate and a driving module; the driving module comprising multiple output control circuits and multiple driving circuits; The nth driving circuit includes an nth first node and an nth driving output terminal. The nth driving circuit is used to provide the nth driving signal to the nth row of gate lines through the nth driving output terminal; n is a positive integer. The nth output control circuit is electrically connected to the nth output control terminal, the nth control clock signal line and the nth row of gate lines respectively, and is used to control the connection or disconnection between the nth row of gate lines and the nth control clock signal line under the control of the nth output control signal provided by the nth output control terminal. The nth output control terminal is the n+mth first node included in the n+mth drive circuit or the n+mth drive output terminal included in the n+mth drive circuit. m is a positive integer; The nth drive output terminal is electrically connected to the first end of the nth row of gate lines, and the nth output control circuit is electrically connected to the second end of the nth row of gate lines; The first end and the second end are opposite ends.

2. The display substrate as claimed in claim 1, wherein, The nth driving circuit is located within the nth driving circuit region, the (n+m)th driving circuit is located within the (n+m)th driving circuit region, and the nth output control circuit is located within the (n+m)th driving circuit region.

3. The display substrate as described in claim 1, wherein, The nth output control terminal is the n+mth first node included in the n+mth driving circuit; the n+mth driving circuit includes the n+mth driving transistor for outputting the n+mth driving signal; The gate of the (n+m)th driving transistor is electrically connected to the gate of the transistor included in the nth output control circuit via a connection portion, the connection portion having a cutout portion.

4. The display substrate as described in claim 3, wherein, The nth control clock signal line extends along the first direction, and the width of the cutout portion in the second direction is smaller than the width of the gate of the transistor included in the nth output control circuit in the second direction. The first direction intersects with the second direction.

5. The display substrate as claimed in claim 4, wherein, The width of the gate of the (n+m)th driving transistor in the second direction is equal to the width of the gate of the transistor included in the nth output control circuit in the second direction. The length of the gate of the transistor in the first direction of the nth output control circuit is less than the length of the gate of the (n+m)th driving transistor in the first direction.

6. The display substrate as claimed in claim 4, wherein, The first electrode of the transistor included in the nth output control circuit is electrically connected to the nth control clock signal line through a first connection line, and the second electrode of the transistor included in the nth output control circuit is electrically connected to the second end of the nth row gate line through a second connection line. The virtual extension of the second connecting line in the second direction intersects with the first connecting line.

7. The display substrate as claimed in claim 1, wherein, The nth output control terminal is the n+mth first node included in the n+mth drive circuit; the n+mth drive circuit includes the n+mth pull-down reset circuit; The (n+m)th pull-down reset circuit is electrically connected to the (n+m)th first node and the (n+m)th second node respectively, and is used to reset the potential of the (n+m)th second node under the control of the potential of the (n+m)th first node; The gate of the transistor included in the nth output control circuit is electrically connected to the gate of the transistor included in the (n+m)th pull-down reset circuit.

8. The display substrate as claimed in claim 7, wherein, The shortest distance between the gate of the transistor included in the nth output control circuit and the gate of the transistor included in the (n+m)th pull-down reset circuit is greater than or equal to 4 μm and less than 10 μm.

9. The display substrate as claimed in claim 7, wherein, The (n+m)th driving circuit includes an (n+m)th driving transistor for outputting the (n+m)th driving signal; The ratio between the length of the active pattern of the (n+m)th driving transistor along the first direction and the length of the active pattern of the (n+m)th driving transistor along the second direction is greater than 1. The first direction is the extension direction of the nth control clock signal line, and the second direction intersects with the first direction.

10. The display substrate as claimed in claim 9, wherein, The active pattern of the (n+m)th driving transistor has a length along the second direction that is greater than or equal to 4 μm and less than 10 μm.

11. The display substrate as claimed in claim 1, wherein, The nth output control terminal is the (n+m)th drive output terminal; The (n+m)th driving circuit includes an (n+m)th driving transistor for outputting the (n+m)th driving signal; The second electrode of the (n+m)th driving transistor is electrically connected to the gate of the transistor included in the nth output control circuit; The shortest distance between the gate of the (n+m)th driving transistor and the gate of the transistor included in the nth output control circuit is greater than or equal to 4 μm and less than 10 μm.

12. The display substrate as claimed in claim 11, wherein, The width of the gate of the transistor in the nth output control circuit along the second direction is smaller than the width of the gate of the (n+m)th driving transistor along the second direction. The first direction is the extension direction of the nth control clock signal line, and the second direction intersects with the first direction.

13. The display substrate as claimed in claim 11, wherein, The second electrode of the (n+m)th driving transistor is electrically connected to the connection pattern through a via. The connection pattern is electrically connected to the gate of the transistor included in the nth output control circuit, and the connection pattern and the gate of the transistor included in the nth output control circuit are disposed on the same layer.

14. The display substrate as claimed in claim 1, wherein, The nth driving circuit is electrically connected to the nth output clock signal line and is used to control the connection between the nth driving output terminal and the nth output clock signal line under the control of the potential of the nth first node. The clock signal connected to the nth output clock signal line is the same as the clock signal connected to the nth control clock signal line.

15. The display substrate as claimed in claim 1, wherein, The nth output control circuit includes the nth output control transistor; The gate of the nth output control transistor is electrically connected to the nth output control terminal, the first electrode of the nth output control transistor is electrically connected to the nth control clock signal line, and the second electrode of the nth output control transistor is electrically connected to the second end of the nth row gate line.

16. The display substrate as claimed in claim 15, wherein, The drive module also includes redundant output control transistors; The gate of the redundant output control transistor is electrically connected to the first node of the first driving circuit, the first electrode of the redundant output control transistor is electrically connected to the corresponding control clock signal line, and the second electrode of the redundant output control transistor is floating.

17. The display substrate according to any one of claims 1 to 16, wherein, The driving module further includes a first redundant driving circuit; the display substrate further includes a first redundant gate line; x is a positive integer; The xth output control circuit included in the driving module is electrically connected to the first node included in the first redundant driving circuit and the last row of gate lines included in the display substrate. The xth output control circuit is used to control the driving signal on the last row of gate lines under the control of the potential of the first node included in the first redundant driving circuit. The first redundant drive circuit and the xth output control circuit are located within the first redundant drive circuit region, and the first redundant drive circuit is electrically connected to one end of the first redundant gate line.

18. The display substrate as claimed in claim 17, wherein, The drive module further includes a second redundant drive circuit; the second redundant drive circuit is disposed within the second redundant drive circuit area; The other end of the first redundant gate line is electrically connected to the second redundant drive circuit, and the first redundant drive circuit and the first drive circuit included in the drive module are located on the same side of the display substrate. The drive module further includes a redundant output control circuit disposed in the second redundant drive circuit area; the output terminal of the redundant output control circuit is floating.

19. The display substrate according to any one of claims 1 to 16, wherein, The nth driving circuit includes an nth first node control circuit, an nth output circuit, an nth output reset circuit, an nth pull-down reset circuit, and an nth second node control circuit; The nth first node control circuit is electrically connected to the input terminal, the reset terminal and the nth first node respectively, and is used to control the potential of the nth first node under the control of the input signal provided by the input terminal and the reset signal provided by the reset terminal; The nth output circuit is electrically connected to the nth first node, the nth drive output terminal, and the nth output clock signal line, respectively, and is used to control the connection or disconnection between the nth drive output terminal and the nth output clock signal line under the control of the potential of the nth first node; The nth output reset circuit is electrically connected to the nth second node and the nth drive output terminal respectively, and is used to reset the nth drive signal provided by the nth drive output terminal under the control of the potential of the nth second node; The nth pull-down reset circuit is electrically connected to the nth first node and the nth second node respectively, and is used to reset the potential of the nth second node under the control of the potential of the nth first node; The control circuit of the nth second node is electrically connected to the nth second node and is used to control the potential of the nth second node.

20. The display substrate as claimed in claim 15, wherein, The channel width-to-length ratio of the nth output control transistor is greater than or equal to 10 and less than or equal to 22.

5.

21. The display substrate as claimed in claim 15, wherein, The channel length of the nth output control transistor is greater than or equal to 4 μm and less than or equal to 6 μm, and the channel width of the nth output control transistor is greater than or equal to 60 μm and less than or equal to 90 μm.

22. The display substrate according to any one of claims 1 to 16, wherein, It includes a peripheral area and a display area; the peripheral area includes a first side area and a second side area; the first side area is located on the first side of the display area, and the second side area is located on the second side of the display area, the first side and the second side are opposite sides; The odd-numbered driving circuit of the driving module is disposed in the first side region, and the even-numbered driving circuit of the driving module is disposed in the second side region. The driving module includes a 2a-1 driving circuit that is electrically connected to the first end of the 2a-1 row of gate lines, and is used to provide a 2a-1 driving signal to the 2a-1 row of gate lines; The driving module includes a 2a driving circuit that is electrically connected to the second end of the 2a row gate line, and is used to provide a 2a driving signal to the 2a row gate line; 'a' is a positive integer.

23. The display substrate according to any one of claims 1 to 16, wherein, Includes multi-row, multi-column pixel circuitry located in the display area; b is a positive integer; The pixel circuit located in row b is electrically connected to the gate line in row 2b-1, and is used to access the corresponding data voltage under the control of the driving signal provided by the gate line in row 2b-1; Another portion of the pixel circuit located in row b is electrically connected to the gate line in row 2b, and is used to receive the corresponding data voltage under the control of the 2b drive signal provided by the gate line in row 2b.

24. The display substrate according to any one of claims 1 to 16, wherein, Includes multi-row, multi-column pixel circuitry located in the display area; b is a positive integer; The first color pixel circuit located in row 3b-2 is electrically connected to the gate line in row 3b-2, and is used to connect the corresponding data voltage under the control of the 3b-2 driving signal provided by the gate line in row 3b-2; The second color pixel circuit located in row 3b-1 is electrically connected to the gate line in row 3b-1, and is used to connect the corresponding data voltage under the control of the driving signal provided by the gate line in row 3b-1; The third color pixel circuit located in row 3b is electrically connected to the gate line in row 3b, and is used to connect the corresponding data voltage under the control of the third drive signal provided by the gate line in row 3b.

25. A display device comprising a display substrate as claimed in any one of claims 1 to 24.

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