Bandgap reference circuit, trimming method thereof and electronic device

Abstract

The application provides a band gap reference circuit, a trimming method thereof and an electronic device. A common-source common-gate current mirror module outputs a first bias current and a second bias current to a first bipolar transistor and a second bipolar transistor, so that a positive temperature coefficient resistor generates a positive temperature coefficient current to a temperature drift correction resistor, and first-order temperature drift correction of a reference voltage can be realized by adjusting only the size of the temperature drift correction resistor. When the ambient temperature reaches a starting temperature range, a second-order temperature drift correction module outputs a second-order correction current to the temperature drift correction resistor according to the first bias current, so that second-order temperature drift correction of the reference voltage is realized, and the temperature drift correction precision of the reference voltage is improved. An offset correction module outputs an offset compensation current that is not affected by temperature to the temperature drift correction resistor based on a control signal representing an offset value of the reference voltage, so that the offset of the reference voltage is corrected.

Description

Technical Field

[0001] This invention relates to the technical field of electronic circuits, and more particularly to a bandgap reference circuit, its adjustment method, and an electronic device thereof. Background Technology

[0002] Bandgap reference circuits are common and important modules in chips, used to provide reference voltages (or reference currents) with extremely low temperature drift. However, due to actual process variations, the temperature profile of the circuit's output voltage deviates from the design requirements. Therefore, after the chip is manufactured and shipped, it is usually necessary to perform first-order temperature drift correction on the output voltage of the bandgap reference circuit using calibration resistors.

[0003] However, even after first-order temperature drift correction, the reference voltage output by the bandgap reference circuit still has a large temperature coefficient, which cannot meet the requirements of high-precision applications. During the first-order temperature drift correction process, the output voltage also shifts, causing the overall output voltage to deviate from the target value. Summary of the Invention

[0004] The technical problem solved by this invention is how to correct the deviation of the reference voltage caused by temperature drift correction while improving the accuracy of temperature drift correction of the reference voltage.

[0005] To solve the above-mentioned technical problems, the present invention provides a bandgap reference circuit, comprising: A common-source cascode current mirror module is used to output a first bias current and a second bias current, wherein the first bias current is equal to the second bias current. A first bipolar transistor, a second bipolar transistor, and a positive temperature coefficient resistor are provided. The collector of the first bipolar transistor is connected to the first bias current, and the collector of the second bipolar transistor is connected to the second bias current. The base of the first bipolar transistor outputs a reference voltage and is connected to the base of the second bipolar transistor. The first and second ends of the positive temperature coefficient resistor are respectively connected to the emitter of the first bipolar transistor and the emitter of the second bipolar transistor. A temperature drift correction resistor, wherein the first end of the temperature drift correction resistor is connected to the second end of the positive temperature coefficient resistor, and the second end of the temperature drift correction resistor is connected to ground. The second-order temperature drift correction module outputs a second-order correction current to the temperature drift correction resistor according to the first bias current when the ambient temperature is greater than or equal to the starting temperature range. An offset correction module outputs an offset correction current to the temperature drift correction resistor and adjusts the magnitude of the offset correction current based on a control signal. The offset correction current is unaffected by temperature, and the control signal represents the offset value of the reference voltage.

[0006] Optionally, the second-order temperature drift correction module includes: a fifth cascode MOSFET, a sixth cascode MOSFET, a seventh cascode MOSFET, the third bipolar transistor, a first switching PMOS transistor, a second switching PMOS transistor, and the comparator resistor; The gates of the fifth, sixth, and seventh cascode MOSFETs are all connected to the first bias current. The sources of the fifth, sixth, and seventh cascode MOSFETs are all connected to the power supply voltage. The drain of the fifth cascode MOSFET serves as the first output terminal of the second cascode current mirror module. The drain of the sixth cascode MOSFET is connected to the source of the first and second switching PMOS transistors, respectively, and outputs a second-order correction initial current. The drain of the seventh cascode MOSFET is connected to the gate of the second switching PMOS transistor and the first terminal of the comparator resistor, respectively, and outputs a comparator current. The collector of the third bipolar transistor is connected to its own base, the first output terminal of the second common-source common-gate current mirror module, and the gate of the first switching PMOS transistor. The sources of the first and second switching PMOS transistors are both connected to the second-order correction initial current. The drain of the first switching PMOS transistor is connected to the first terminal of the temperature drift correction resistor. The gate of the second switching PMOS transistor is connected to the first terminal of the comparator resistor. The first terminal of the comparator resistor is connected to the comparator current. The second terminal of the comparator resistor, the drain of the second switching PMOS transistor, and the emitter of the third bipolar transistor are all connected to ground.

[0007] Optionally, the common-source common-gate current mirror module includes a first common-source common-gate MOSFET, a second common-source common-gate MOSFET, a third common-source common-gate MOSFET, a fourth common-source common-gate MOSFET, and a common-source common-gate resistor; the sources of the first and second common-source common-gate MOSFETs are both connected to the power supply voltage; the gate of the first common-source common-gate MOSFET is connected to the gate of the second common-source common-gate MOSFET and the first terminal of the common-source common-gate resistor; the drain of the first common-source common-gate MOSFET is connected to the source of the third common-source common-gate MOSFET; the drain of the second common-source common-gate MOSFET is connected to the source of the fourth common-source common-gate MOSFET; the gate of the third common-source common-gate MOSFET is connected to the gate of the fourth common-source common-gate MOSFET and the second terminal of the common-source common-gate resistor; the drain of the third common-source common-gate MOSFET is connected to the first terminal of the common-source common-gate resistor; the second terminal of the common-source common-gate resistor outputs the first bias current. The common-source common-gate current mirror module further includes a first Zener MOSFET and a second Zener MOSFET; the drain of the first Zener MOSFET is connected to the second terminal of the common-source common-gate resistor, the gate of the first Zener MOSFET is connected to the gate of the second Zener MOSFET, and the drain of the first Zener MOSFET is connected to the collector of the first bipolar transistor; the drain of the second Zener MOSFET is connected to the drain of the fourth Zener MOSFET and its own gate, and the source of the second Zener MOSFET is connected to the collector of the second bipolar transistor, and outputs the second bias current.

[0008] Optionally, the first common-source cascode MOSFET, the second common-source cascode MOSFET, the third common-source cascode MOSFET, the fourth common-source cascode MOSFET, the fifth common-source cascode MOSFET, the sixth common-source cascode MOSFET, and the seventh common-source cascode MOSFET are all PMOS transistors.

[0009] Optionally, the offset correction module includes an offset correction resistor, a first correction MOSFET, several second correction MOSFETs, and several correction switches; The source of the first correction MOS transistor is connected to the power supply voltage and is also connected to the source of the plurality of second correction MOS transistors. The gate of the first correction MOS transistor is also connected to the gate of the plurality of second correction MOS transistors. The drain of the first correction MOS transistor is connected to the first terminal of the offset correction resistor. The first end of the offset correction resistor is also connected to the base of the second bipolar transistor, and the second end of the offset correction resistor is connected to ground. The plurality of second correction MOS transistors and the plurality of correction switches correspond one-to-one. The drain of each second correction MOS transistor is coupled to the first end of the temperature drift correction resistor through the corresponding correction switch to output the offset correction current. The control signal is used to control the on / off state of the plurality of correction switches in order to adjust the magnitude of the offset correction current.

[0010] Optionally, the formula for the reference voltage is: Wherein, VBG represents the reference voltage; VBE2 represents the base-emitter voltage of the second bipolar transistor; R2 represents the resistance value of the temperature drift correction resistor; R1 represents the resistance value of the positive temperature coefficient resistor; VT represents the thermal voltage; n represents the size ratio of the first bipolar transistor and the second bipolar transistor; Icomp represents the second-order correction current; and Itrim represents the offset correction current.

[0011] Optionally, it also includes an output buffer MOSFET, the drain of which is connected to the drain of the first correction MOSFET, and the source of which is connected to the first terminal of the offset correction resistor.

[0012] The technical solution of the present invention also provides a method for adjusting a bandgap reference circuit. Based on the above-mentioned bandgap reference circuit, the adjustment method includes: The temperature curve of the reference voltage is detected. If the temperature curve of the reference voltage does not conform to the first preset temperature curve, the value of the temperature drift correction resistor is adjusted until the temperature curve of the reference voltage conforms to the first preset temperature curve. When the ambient temperature reaches the starting temperature range of the second-order temperature drift correction module outputting the second-order correction current, the second-order temperature drift correction module outputs the second-order correction current to the temperature drift correction resistor to correct the first preset temperature curve to the second preset temperature curve. The peak-to-valley difference of the second preset temperature curve is smaller than that of the first preset temperature curve. After the temperature curve of the reference voltage conforms to the second preset temperature curve, the offset value of the reference voltage is detected. Based on the offset value, the control signal is output to the offset correction module; The offset correction module adjusts the offset correction current flowing through the temperature drift correction resistor based on the control signal to compensate for the offset value of the reference voltage.

[0013] Optionally, before the temperature curve of the reference voltage conforms to the second preset temperature curve, the method further includes: controlling some of the correction switches among a plurality of correction switches to close, and controlling the remaining correction switches to open. The method by which the offset correction module adjusts the offset correction current based on the control signal specifically includes: the control signal changing the number of conducting switches among the plurality of correction switches.

[0014] The present invention also provides an electronic device, including the above-described bandgap reference circuit.

[0015] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: In the bandgap reference circuit provided by the technical solution of this invention, the common-source cascode current mirror module outputs the same first bias current and second bias current to ensure that the collector of the first bipolar transistor and the collector of the second bipolar transistor receive the same current. Since the base of the first bipolar transistor is connected to the base of the second bipolar transistor, and one end of the positive temperature coefficient resistor is connected to the emitter of the first bipolar transistor, and the other end of the positive temperature coefficient resistor is connected to the emitter of the second bipolar transistor, a base-emitter voltage difference is formed across the positive temperature coefficient resistor, thereby generating a positive temperature coefficient current. Since one end of the temperature drift correction resistor is connected to the emitter of the second bipolar transistor, and the other end of the temperature drift correction resistor is connected to ground, the positive temperature coefficient current flows through the temperature drift correction resistor to generate a positive temperature coefficient voltage.

[0016] Since the base output of the first bipolar transistor is a reference voltage, and based on circuit principles, the reference voltage is equal to the sum of the positive temperature coefficient voltage and the base-emitter voltage of the second bipolar transistor. Since the temperature coefficient of the base-emitter voltage of the second bipolar transistor is negative, the first-order temperature drift correction of the reference voltage can be achieved by adjusting the size of the temperature drift correction resistor.

[0017] When the ambient temperature does not reach the initial temperature range, only the reference voltage is subjected to first-order temperature drift correction. When the ambient temperature reaches or exceeds the initial temperature range, the second-order temperature drift correction module outputs a second-order correction current to the temperature drift correction resistor based on the first bias current to correct the temperature curve of the reference voltage, thereby realizing the second-order temperature drift correction of the reference voltage and improving the temperature drift correction accuracy of the reference voltage.

[0018] If the reference voltage deviates from the target value, the offset correction module outputs an offset correction current, which is unaffected by temperature, to the temperature drift correction resistor based on the control signal characterizing the offset value of the reference voltage, so as to generate an offset compensation voltage that is unaffected by temperature, thereby achieving offset correction of the reference voltage without affecting the temperature coefficient of the reference voltage.

[0019] In summary, the technical solution of the present invention improves the accuracy of temperature drift correction of the reference voltage and corrects the deviation of the reference voltage caused by temperature drift correction. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the circuit structure of the bandgap reference circuit provided in an embodiment of the present invention. Figure 1 ; Figure 2 This is a schematic diagram of the circuit structure of the bandgap reference circuit provided in an embodiment of the present invention. Figure 2 ; Figure 3 This is a waveform of the reference voltage varying with temperature in a bandgap reference circuit provided by an embodiment of the present invention. Figure 1 ; Figure 4 This is a waveform of the reference voltage varying with temperature in a bandgap reference circuit provided by an embodiment of the present invention. Figure 2 . Attached image description: 10-Common Source Common Gate Current Mirror Module; 20 - Offset correction module; 30-Second-order temperature drift correction module; Q1 - First bipolar transistor; Q2 - Second bipolar transistor; Q3 - Third bipolar transistor; R1 - Positive temperature coefficient resistor; R2 - Temperature drift correction resistor; R3 - Common source, common gate resistor; R4 - Offset correction resistor; R6 - Comparison resistor; I1 - First bias current; I2 - Second bias current; IPT - Second-order corrected initial current; Ib - Comparison current; Icomp - Second-order correction current; Itrim - Offset compensation current; VBG - Reference voltage; M1 - First common-source MOS transistor; M2 - Second common-source cascode MOSFET; M3 - Third common-source cascode MOSFET; M4 - Fourth common-source cascode MOSFET; M5 - First Zener MOSFET; M6 - Second Zener MOSFET; M7 - Output buffer MOSFET; M8 - First correction MOSFET; M9 - Second correction MOSFET; M10 - The fifth common-source cascode MOSFET; M11 - The sixth common-source MOS transistor; M12 - Seventh common-source MOS transistor; M13 - First switching PMOS transistor; M14 - Second switching PMOS transistor; X1 - First preset temperature curve; X2 - Second preset temperature curve; q1 - Calibration switch. Detailed Implementation

[0022] As described in the background section, even after first-order temperature drift correction, the reference voltage output by the bandgap reference circuit still has a large temperature coefficient, which cannot meet the requirements of high-precision applications. Furthermore, the output voltage also shifts during the first-order temperature drift correction process, causing the overall output voltage to deviate from the target value.

[0023] In view of this, the technical solution of the present invention provides a new bandgap reference circuit, including a common source cascode current mirror module, a first bipolar transistor, a second bipolar transistor, a positive temperature coefficient resistor, a temperature drift correction resistor, a second-order temperature drift correction module, and an offset correction module.

[0024] The common-source cascode current mirror module outputs a first bias current and a second bias current to the first bipolar transistor and the second bipolar transistor, causing the positive temperature coefficient resistor to generate a positive temperature coefficient current to the temperature drift correction resistor. This allows for first-order temperature drift correction of the reference voltage by simply adjusting the value of the temperature drift correction resistor. When the ambient temperature reaches the initial temperature range, the second-order temperature drift correction module outputs a second-order correction current to the temperature drift correction resistor based on the first bias current, achieving second-order temperature drift correction of the reference voltage and improving the accuracy of the reference voltage temperature drift correction. The offset correction module, based on a control signal characterizing the offset value of the reference voltage, outputs a temperature-independent offset compensation current to the temperature drift correction resistor, thereby correcting the offset of the reference voltage.

[0025] To make the above-mentioned objectives, features, and beneficial effects of the present invention more apparent and understandable, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus. Additionally, directional terms such as above, below, up, down, upward, downward, left, right, etc., are used relative to exemplary embodiments as they are shown in the figures, with upward or upper directions pointing towards the top of the corresponding figure and downward or lower directions pointing towards the bottom of the corresponding figure.

[0027] Please refer to Figure 1 This embodiment provides a bandgap reference circuit, specifically including: a common-source cascode current mirror module 10, a first bipolar transistor Q1, a second bipolar transistor Q2, a positive temperature coefficient resistor R1, a temperature drift correction resistor R2, a second-order temperature drift correction module 30, and an offset correction module 20.

[0028] In this embodiment, the common source cascode current mirror module 10 is used to output a first bias current I1 and a second bias current I2. The first bias current I1 and the second bias current I2 flow through two branches respectively, and the first bias current I1 is equal to the second bias current I2.

[0029] Please refer to Figure 2In this embodiment, the common-source common-gate current mirror module 10 includes a first common-source common-gate MOSFET M1, a second common-source common-gate MOSFET M2, a third common-source common-gate MOSFET M3, a fourth common-source common-gate MOSFET M4, and a common-source common-gate resistor R3. The sources of the first common-source common-gate MOSFET M1 and the second common-source common-gate MOSFET M2 are both connected to the power supply voltage VBAT. The gate of the first common-source common-gate MOSFET M1 is connected to the gate of the second common-source common-gate MOSFET M2 and the first terminal of the common-source common-gate resistor R3. The drain of the first common-source common-gate MOSFET M1 is connected to the source of the third common-source common-gate MOSFET M3. The drain of the second common-source common-gate MOSFET M2 is connected to the source of the fourth common-source common-gate MOSFET M4. The gate of the third cascode MOSFET M3 is connected to the gate of the fourth cascode MOSFET M4 and the second terminal of the cascode resistor R3, respectively. The drain of the third cascode MOSFET M3 is connected to the first terminal of the cascode resistor R3. The second terminal of the cascode resistor R3 outputs the first bias current I1.

[0030] Furthermore, the first common-source cascode MOS transistor M1, the second common-source cascode MOS transistor M2, the third common-source cascode MOS transistor M3, and the fourth common-source cascode MOS transistor M4 are all PMOS transistors.

[0031] Please continue to refer to this. Figure 2 In this embodiment, the common-source common-gate current mirror module 10 further includes a first Zener MOSFET M5 and a second Zener MOSFET M6; the drain of the first Zener MOSFET M5 is connected to the second terminal of the common-source common-gate resistor R3, the gate of the first Zener MOSFET M5 is connected to the gate of the second Zener MOSFET M6, and the drain of the first Zener MOSFET M5 is connected to the collector of the first bipolar transistor Q1; the drain of the second Zener MOSFET M6 is connected to the drain of the fourth common-source common-gate MOSFET M4 and its own gate, respectively, and the source of the second Zener MOSFET M6 is connected to the collector of the second bipolar transistor Q2, and outputs the second bias current I2.

[0032] Furthermore, both the first Zener MOSFET M5 and the second Zener MOSFET M6 are NMOS transistors.

[0033] Based on the above circuit structure, the working principle of the common source cascode current mirror module 10 is as follows: the first common source cascode MOSFET M1 and the second common source cascode MOSFET M2 form a current mirror structure and are combined with the common source cascode resistor R3 to generate the first bias current I1 flowing through the common source cascode resistor R3.

[0034] The third cascode MOSFET M3 and the fourth cascode MOSFET M4 serve as a cascode structure to improve the output impedance of the current mirror structure, thereby suppressing the influence of the MOSFET channel length modulation effect and significantly improving the accuracy and stability of the first bias current I1, thus providing a stable current for the first bipolar transistor Q1.

[0035] The first Zener MOSFET M5 and the second Zener MOSFET M6 form a current mirror structure to mirror the first bias current I1 flowing through the first Zener MOSFET M5 to the second Zener MOSFET M6, so as to output the second bias current I2, thereby providing a stable current for the second bipolar transistor Q2.

[0036] Please continue to refer to this. Figure 1 and Figure 2 The collector of the first bipolar transistor Q1 is connected to the source of the first Zener MOSFET M5 to receive the first bias current I1. The collector of the second bipolar transistor Q2 is connected to the emitter of the second Zener MOSFET M6 to receive the second bias current I2. The base of the first bipolar transistor Q1 outputs a reference voltage and is connected to the base of the second bipolar transistor Q2.

[0037] Since the first end of the positive temperature coefficient resistor R1 is connected to the emitter of the first bipolar transistor Q1, and the second end of the positive temperature coefficient resistor R1 is connected to the emitter of the second bipolar transistor Q2, a base-emitter voltage difference is formed across the two ends of the positive temperature coefficient resistor, thereby generating a positive temperature coefficient current.

[0038] Since one end of the temperature drift correction resistor is connected to the emitter of the second bipolar transistor and the other end is connected to ground, a positive temperature coefficient current flows through the temperature drift correction resistor to generate a positive temperature coefficient voltage.

[0039] Since the base output of the first bipolar transistor is a reference voltage, and based on circuit principles, the reference voltage is equal to the sum of the positive temperature coefficient voltage and the base-emitter voltage of the second bipolar transistor, the formula for the reference voltage is as follows: Formula (1) In the above formula (1), VBG represents the reference voltage; VBE2 represents the base-emitter voltage of the second bipolar transistor; R2 represents the resistance value of the temperature drift correction resistor; R1 represents the resistance value of the positive temperature coefficient resistor; VT represents the thermal voltage; and n represents the size ratio of the first bipolar transistor and the second bipolar transistor.

[0040] From the formula for the reference voltage, it can be seen that the reference voltage VBG is equal to the sum of the base-emitter voltage of the second bipolar transistor Q2 and the voltage across the temperature drift correction resistor R2. Because the base-emitter voltage of the second bipolar transistor Q2 has a negative temperature coefficient, and the voltage across the temperature drift correction resistor R2 has a positive temperature coefficient, the negative temperature coefficient of the base-emitter voltage can cancel out the positive temperature coefficient of the voltage across the temperature drift correction resistor R2. Therefore, at the design stage, the negative temperature coefficient of the base-emitter voltage and the positive temperature coefficient of the voltage across the temperature drift correction resistor R2 can be completely canceled out, so as to achieve a temperature coefficient of 0 for the reference voltage, thereby greatly suppressing the temperature drift of the reference voltage.

[0041] Please refer to Figure 3 However, the negative temperature coefficient of the base voltage and the positive temperature coefficient of the voltage across the temperature drift correction resistor R2 may not match the initial design values ​​due to process deviations or mismatches. Therefore, in this embodiment, the positive temperature coefficient of the voltage across the temperature drift correction resistor R2 can be adjusted by adjusting the resistance value of the temperature drift correction resistor R2, so that the reference voltage conforms to the first preset temperature curve X1. Figure 3 The solid line shown. And... Figure 3 The dashed lines shown are the temperature curves of the reference voltage obtained by increasing or decreasing the temperature drift correction resistor R2 corresponding to the first preset temperature curve X1. Since the peak-to-valley difference of the temperature curves obtained by increasing or decreasing the temperature drift correction resistor R2 corresponding to the first preset temperature curve X1 is greater than that of the preset temperature curve, the temperature drift of the reference voltage can be effectively suppressed by adjusting the resistance value of the temperature drift correction resistor R2.

[0042] However, conforming to the first preset temperature curve X1 is no longer sufficient to meet the high precision requirements of reference voltage in applications such as power supplies, analog circuits, ADCs / DACs, precision measurements, or sensor signal acquisition. Therefore, it is necessary to further reduce the peak-to-valley difference of the reference voltage's temperature curve to further improve the temperature drift correction accuracy of the reference voltage.

[0043] Please continue to refer to this. Figure 1 In view of this, when the ambient temperature is greater than or equal to the starting temperature range, the second-order temperature drift correction module 30 of this embodiment outputs a second-order correction current Icomp to the temperature drift correction resistor R2 according to the first bias current I1 to correct the temperature curve of the reference voltage VBG, thereby realizing the second-order temperature drift correction of the reference voltage VBG and improving the temperature drift correction accuracy of the reference voltage VBG.

[0044] Please continue to refer to this. Figure 2In this embodiment, the second-order temperature drift correction module 30 includes a fifth common-source MOSFET M10, a sixth common-source MOSFET M11, a seventh common-source MOSFET M12, a third bipolar transistor Q3, a first switching PMOS transistor M13, a second switching PMOS transistor M14, and a comparator resistor R6.

[0045] The gates of the fifth cascode MOSFET M10, the sixth cascode MOSFET M11, and the seventh cascode MOSFET M12 are all connected to the first bias current I1. The sources of the fifth cascode MOSFET M10, the sixth cascode MOSFET M11, and the seventh cascode MOSFET M12 are all connected to the power supply voltage. The drain of the fifth cascode MOSFET M10 serves as the first output terminal of the second cascode current mirror module. The drain of the sixth cascode MOSFET M11 is connected to the source of the first switching PMOS transistor M13 and the source of the second switching PMOS transistor M14, and outputs a second-order correction initial current IPT. The drain of the seventh cascode MOSFET is connected to the gate of the second switching PMOS transistor M14 and the first terminal of the comparator resistor R6, and outputs a comparator current Ib.

[0046] In this embodiment, the fifth cascode MOSFET M10, the sixth cascode MOSFET M11, and the seventh cascode MOSFET M12 are all PMOS transistors.

[0047] The gates of the fifth cascode MOSFET M10, the sixth cascode MOSFET M11, and the seventh cascode MOSFET M12 form a current mirror structure to mirror the first bias current I1, and to make the drain of the sixth cascode MOSFET M11 output a second-order correction initial current IPT and the drain of the seventh cascode MOSFET M12 output a comparison current Ib.

[0048] The collector of the third bipolar transistor Q3 is connected to its own base, the first output terminal of the second common-source common-gate current mirror module, and the gate of the first switching PMOS transistor M13. The sources of the first switching PMOS transistor M13 and the second switching PMOS transistor M14 are both connected to the second-order correction initial current IPT. The drain of the first switching PMOS transistor M13 is connected to the first terminal of the temperature drift correction resistor R2. The gate of the second switching PMOS transistor M14 is connected to the first terminal of the comparator resistor R6. The first terminal of the comparator resistor R6 is connected to the comparator current Ib. The second terminal of the comparator resistor R6, the drain of the second switching PMOS transistor M14, and the emitter of the third bipolar transistor Q3 are all connected to ground.

[0049] The first PMOS transistor M13 and the second PMOS transistor M14 can be equivalent to a comparator. The gate of the first PMOS transistor M13 is connected to the base-emitter voltage of the third bipolar transistor Q3 as the first input terminal. The gate of the second PMOS transistor M14 is connected to the product of the comparison current Ib and the comparison resistor R6 as the second input terminal, which is the second-order temperature drift correction initial voltage.

[0050] When the base-emitter voltage of the third bipolar transistor Q3 is greater than or equal to the initial voltage for second-order temperature drift correction, the first switching PMOS transistor M13 is turned off, and the second switching PMOS transistor M14 is turned on. Therefore, the initial second-order correction current IPT flows from the second switching PMOS transistor M14 to ground. Since the comparator current Ib is a mirror image of the first bias current I1, i.e., the comparator current Ib has a positive temperature coefficient, and the comparator resistor R6 has a negative temperature coefficient, the voltage applied to the gate of the second switching PMOS transistor M14 by the comparator resistor R6, i.e., the initial voltage for second-order temperature drift correction, remains essentially constant with temperature. Furthermore, since the base-emitter voltage of the third bipolar transistor Q3 has a negative temperature coefficient, it decreases as the ambient temperature rises. Therefore, the ambient temperature corresponding to when the base-emitter voltage of the third bipolar transistor Q3 equals the initial voltage for second-order temperature drift correction can be considered as the starting temperature range. The size of this starting temperature range can be adjusted by adjusting the value of the comparator resistor R6, and is not limited here.

[0051] Please refer to Figure 4 When the base-emitter voltage of the third bipolar transistor Q3 is greater than or equal to the initial voltage of the second-order temperature drift correction, it indicates that the ambient temperature is less than or equal to the starting temperature range. Since the first preset temperature curve X1 of the reference voltage VBG in this stage meets the high-precision requirements, there is no need to output the second-order correction current Icomp to the temperature drift correction resistor R2 to perform the second-order temperature drift correction of the reference voltage VBG.

[0052] When the base-emitter voltage of the third bipolar transistor Q3 is less than the initial voltage for second-order temperature drift correction, based on the above description, the ambient temperature is greater than the starting temperature range, and second-order temperature drift correction is required for the reference voltage VBG. Therefore, the first switching PMOS transistor M13 is turned on, and the second switching PMOS transistor M14 is turned off, so that the initial second-order correction current IPT flows into the first switching PMOS transistor M13, and the second-order correction current Icomp is output from the drain of the first switching PMOS transistor M13 to the temperature drift correction resistor R2.

[0053] After applying second-order temperature drift correction to the reference voltage VBG using the second-order correction current Icomp, the formula for the reference voltage VBG is modified as follows: Formula (2) In the above formula (2), Icomp represents the second-order correction current Icomp.

[0054] The formula for the second-order correction current Icomp is as follows: Formula (3) In the above formula (3), IPT represents the second-order correction initial current; VBE3 represents the base-emitter voltage of the third bipolar transistor Q3; Ib represents the comparison current; R6 represents the comparison resistor; and gm represents the transconductance of the first switching PMOS transistor M13.

[0055] Please continue to refer to this. Figure 4 When the ambient temperature is higher than the initial temperature range, after the drain output of the first switching PMOS transistor M13 carries a second-order correction current Icomp to the temperature drift correction resistor R2, the temperature curve of the reference current is corrected to the second preset temperature curve X2. In this embodiment, compared to the original peak-to-valley difference of 3.4mV for the first preset temperature curve X1, the peak-to-valley difference of the corrected first preset temperature curve X1 is only 1mV, thereby further improving the temperature drift correction accuracy of the reference voltage VBG and enhancing the practicality of the bandgap reference circuit in high-precision applications.

[0056] Changing the value of the temperature drift correction resistor R2 will not only change the positive temperature coefficient of the voltage across the resistor R2, but also change the value of the voltage across the resistor R2, thus causing the reference voltage to shift relative to the preset voltage.

[0057] Therefore, this embodiment additionally provides an offset correction module 20, which outputs an offset compensation current Itrim to the temperature drift correction resistor R2. Since the control signal represents the offset value of the reference voltage and the offset compensation current Itrim is not affected by temperature, the offset compensation of the reference voltage is achieved by adjusting the magnitude of the offset compensation current Itrim based on the control signal.

[0058] Please continue to refer to this. Figure 1 and Figure 2 The offset correction module 20 includes an offset correction resistor R4, a first correction MOSFET M8, several second correction MOSFETs M9, and several correction switches q1.

[0059] The source of the first correction MOS transistor M8 is connected to the power supply voltage VBAT and is also connected to the source of the plurality of second correction MOS transistors M9. The gate of the first correction MOS transistor M8 is connected to the gate of the plurality of second correction MOS transistors M9. The drain of the first correction MOS transistor M8 is connected to the first terminal of the offset correction resistor R4.

[0060] The first end of the offset correction resistor R4 is also connected to the base of the second bipolar transistor Q2, and the second end of the offset correction resistor R4 is connected to ground.

[0061] The plurality of second correction MOS transistors M9 and the plurality of correction switches q1 correspond one-to-one. The drain of each second correction MOS transistor M9 is coupled to the first end of the temperature drift correction resistor R2 through the corresponding correction switch q1 to output the offset compensation current Itrim.

[0062] The control signal is used to control the on / off state of the plurality of correction switches q1, so as to adjust the magnitude of the offset compensation current Itrim.

[0063] In this embodiment, the first correction MOS transistor M8 and several second correction MOS transistors M9 are all PMOS transistors.

[0064] The offset correction resistor R4 generates an initial offset compensation current Itrim flowing through the first correction MOSFET M8 based on the power supply voltage VBAT. Since the first correction MOSFET M8 and several second correction MOSFETs M9 all form a current mirror structure, the initial offset compensation current Itrim flowing through the first correction MOSFET M8 will be mirrored onto several second correction MOSFETs M9. Furthermore, since several correction switches q1 correspond one-to-one with several second correction MOSFETs M9, and the drain of each second correction MOSFET M9 is coupled to the first terminal of the temperature drift correction resistor R2 through the corresponding correction switch q1, the magnitude of the offset compensation current Itrim is equal to the product of the number of correction switches q1 that are turned on and the initial offset compensation current.

[0065] After offset correction of the reference voltage using the offset compensation current Itrim, the formula for the reference voltage is changed as follows: Formula (4) In the above formula (4), Itrim represents the offset compensation current.

[0066] Since the offset compensation voltage does not change with temperature, when the reference voltage shifts due to temperature drift correction, the magnitude of the reference voltage can be adjusted by changing the number of conducting transistors of the second correction MOSFET M9 to achieve offset correction of the reference voltage.

[0067] It should be noted that in this embodiment, the temperature drift correction resistor R2 is a single, complete resistor. In other embodiments, the temperature drift correction resistor R2 can also be replaced by a resistor network composed of several resistors connected in series and parallel. The offset compensation current Itrim output by the offset correction module 20 can flow directly through the entire resistor network, or it can be input into the resistor network through a node in the resistor network. The resistance value of the offset compensation current Itrim flowing through the resistor network is only one-half or one-third of the total resistance value of the resistor network. The specific value depends on the ratio of the impedance to ground of the input node to the total resistance value of the resistor network, and is not limited here.

[0068] Please continue to refer to this. Figure 2 In this embodiment, the bandgap reference circuit further includes an output buffer MOSFET M7. The drain of the output buffer MOSFET M7 is connected to the drain of the first correction MOSFET M8, and the source of the output buffer MOSFET M7 is connected to the first terminal of the offset correction resistor R4. The output buffer MOSFET M7 acts as a source follower to buffer and amplify the reference voltage and isolate the bandgap reference circuit from the external load, so as to ensure that the reference voltage can still be output stably when the load changes.

[0069] This embodiment also provides a method for adjusting a bandgap reference circuit, which specifically includes the following steps: The temperature curve of the reference voltage is detected. If the temperature curve of the reference voltage does not conform to the first preset temperature curve, the value of the temperature drift correction resistor is adjusted until the temperature curve of the reference voltage conforms to the first preset temperature curve.

[0070] When the ambient temperature reaches the starting temperature range of the second-order correction current output by the second-order temperature drift correction module, the second-order temperature drift correction module outputs a second-order correction current to the temperature drift correction resistor to correct the first preset temperature curve to the second preset temperature curve. The peak-to-valley difference of the second preset temperature curve is smaller than that of the first preset temperature curve.

[0071] After the temperature curve of the reference voltage conforms to the second preset temperature curve, the offset value of the reference voltage is detected.

[0072] Based on the offset value, the control signal is output to the offset correction module.

[0073] The offset correction module adjusts the offset correction current flowing through the temperature drift correction resistor based on the control signal to compensate for the offset value of the reference voltage.

[0074] In this embodiment, before the temperature curve of the reference voltage conforms to the second preset temperature curve, the method further includes: controlling some of the correction switches among a plurality of correction switches to close, and controlling the remaining correction switches to open.

[0075] The method for adjusting the offset correction current based on the control signal by the offset correction module specifically includes: the control signal changing the number of conducting switches among the plurality of correction switches, thereby adjusting the magnitude of the offset compensation current.

[0076] For example, in one embodiment, the number of the second calibration MOSFET and the calibration switch are both set to 6. Before detecting the temperature curve of the reference voltage, 3 calibration switches are controlled to be turned on and 3 calibration switches are controlled to be turned off.

[0077] When an increase in the reference voltage offset is detected, the control signal controls one or more of the three conducting correction switches to turn off, thereby reducing the magnitude of the offset compensation current, that is, reducing the magnitude of the offset compensation voltage, thereby reducing the magnitude of the reference voltage, and thus realizing the offset correction of the reference voltage.

[0078] When the reference voltage offset is detected to decrease, the control signal controls one or more of the three off correction switches to turn on, thereby increasing the magnitude of the offset compensation current, that is, increasing the magnitude of the offset compensation voltage, thereby increasing the magnitude of the reference voltage, and thus realizing the offset correction of the reference voltage.

[0079] In other embodiments, an electronic device is also provided, including the bandgap reference circuit described in the above embodiments.

[0080] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A bandgap reference circuit, characterized in that, include: A common-source cascode current mirror module is used to output a first bias current and a second bias current, wherein the first bias current is equal to the second bias current. A first bipolar transistor, a second bipolar transistor, and a positive temperature coefficient resistor are provided. The collector of the first bipolar transistor is connected to the first bias current, and the collector of the second bipolar transistor is connected to the second bias current. The base of the first bipolar transistor outputs a reference voltage and is connected to the base of the second bipolar transistor. The first and second ends of the positive temperature coefficient resistor are respectively connected to the emitter of the first bipolar transistor and the emitter of the second bipolar transistor. A temperature drift correction resistor, wherein the first end of the temperature drift correction resistor is connected to the second end of the positive temperature coefficient resistor, and the second end of the temperature drift correction resistor is connected to ground. The second-order temperature drift correction module outputs a second-order correction current to the temperature drift correction resistor according to the first bias current when the ambient temperature is greater than or equal to the starting temperature range. An offset correction module outputs an offset correction current to the temperature drift correction resistor and adjusts the magnitude of the offset correction current based on a control signal. The offset correction current is unaffected by temperature, and the control signal represents the offset value of the reference voltage.

2. The bandgap reference circuit according to claim 1, characterized in that, The second-order temperature drift correction module includes: a fifth common-source cascode MOSFET, a sixth common-source cascode MOSFET, a seventh common-source cascode MOSFET, a third bipolar transistor, a first switching PMOS transistor, a second switching PMOS transistor, and a comparator resistor; The gates of the fifth, sixth, and seventh cascode MOSFETs are all connected to the first bias current. The sources of the fifth, sixth, and seventh cascode MOSFETs are all connected to the power supply voltage. The drain of the fifth cascode MOSFET serves as the first output terminal of the second cascode current mirror module. The drain of the sixth cascode MOSFET is connected to the source of the first and second switching PMOS transistors, respectively, and outputs a second-order correction initial current. The drain of the seventh cascode MOSFET is connected to the gate of the second switching PMOS transistor and the first terminal of the comparator resistor, respectively, and outputs a comparator current. The collector of the third bipolar transistor is connected to its own base, the first output terminal of the second common-source common-gate current mirror module, and the gate of the first switching PMOS transistor. The sources of the first and second switching PMOS transistors are both connected to the second-order correction initial current. The drain of the first switching PMOS transistor is connected to the first terminal of the temperature drift correction resistor. The gate of the second switching PMOS transistor is connected to the first terminal of the comparator resistor. The first terminal of the comparator resistor is connected to the comparator current. The second terminal of the comparator resistor, the drain of the second switching PMOS transistor, and the emitter of the third bipolar transistor are all connected to ground.

3. The bandgap reference circuit according to claim 2, characterized in that, The common-source common-gate current mirror module includes a first common-source common-gate MOSFET, a second common-source common-gate MOSFET, a third common-source common-gate MOSFET, a fourth common-source common-gate MOSFET, and a common-source common-gate resistor. The sources of the first and second common-source common-gate MOSFETs are both connected to a power supply voltage. The gate of the first common-source common-gate MOSFET is connected to the gate of the second common-source common-gate MOSFET and the first terminal of the common-source common-gate resistor. The drain of the first common-source common-gate MOSFET is connected to the source of the third common-source common-gate MOSFET. The drain of the second common-source common-gate MOSFET is connected to the source of the fourth common-source common-gate MOSFET. The gate of the third common-source common-gate MOSFET is connected to the gate of the fourth common-source common-gate MOSFET and the second terminal of the common-source common-gate resistor. The drain of the third common-source common-gate MOSFET is connected to the first terminal of the common-source common-gate resistor. The second terminal of the common-source common-gate resistor outputs the first bias current. The common-source common-gate current mirror module further includes a first Zener MOSFET and a second Zener MOSFET; the drain of the first Zener MOSFET is connected to the second terminal of the common-source common-gate resistor, the gate of the first Zener MOSFET is connected to the gate of the second Zener MOSFET, and the drain of the first Zener MOSFET is connected to the collector of the first bipolar transistor; the drain of the second Zener MOSFET is connected to the drain of the fourth Zener MOSFET and its own gate, and the source of the second Zener MOSFET is connected to the collector of the second bipolar transistor, and outputs the second bias current.

4. The bandgap reference circuit according to claim 3, characterized in that, The first common-source common-gate MOSFET, the second common-source common-gate MOSFET, the third common-source common-gate MOSFET, the fourth common-source common-gate MOSFET, the fifth common-source common-gate MOSFET, the sixth common-source common-gate MOSFET, and the seventh common-source common-gate MOSFET are all PMOS transistors.

5. The bandgap reference circuit according to claim 1, characterized in that, The offset correction module includes an offset correction resistor, a first correction MOSFET, several second correction MOSFETs, and several correction switches; The source of the first correction MOS transistor is connected to the power supply voltage and is also connected to the source of the plurality of second correction MOS transistors. The gate of the first correction MOS transistor is also connected to the gate of the plurality of second correction MOS transistors. The drain of the first correction MOS transistor is connected to the first terminal of the offset correction resistor. The first end of the offset correction resistor is also connected to the base of the second bipolar transistor, and the second end of the offset correction resistor is connected to ground. The plurality of second correction MOS transistors and the plurality of correction switches correspond one-to-one. The drain of each second correction MOS transistor is coupled to the first end of the temperature drift correction resistor through the corresponding correction switch to output the offset correction current. The control signal is used to control the on / off state of the plurality of correction switches in order to adjust the magnitude of the offset correction current.

6. The bandgap reference circuit according to claim 5, characterized in that, The formula for the reference voltage is: Wherein, VBG represents the reference voltage; VBE2 represents the base-emitter voltage of the second bipolar transistor; R2 represents the resistance value of the temperature drift correction resistor; R1 represents the resistance value of the positive temperature coefficient resistor; VT represents the thermal voltage; n represents the size ratio of the first bipolar transistor and the second bipolar transistor; Icomp represents the second-order correction current; and Itrim represents the offset correction current.

7. The bandgap reference circuit according to claim 1, characterized in that, It also includes an output buffer MOSFET, the drain of which is connected to the drain of the first correction MOSFET, and the source of which is connected to the first terminal of the offset correction resistor.

8. A method for adjusting a bandgap reference circuit, characterized in that, Based on the bandgap reference circuit according to any one of claims 1 to 7, the adjustment method includes: The temperature curve of the reference voltage is detected. If the temperature curve of the reference voltage does not conform to the first preset temperature curve, the value of the temperature drift correction resistor is adjusted until the temperature curve of the reference voltage conforms to the first preset temperature curve. When the ambient temperature reaches the starting temperature range of the second-order temperature drift correction module outputting the second-order correction current, the second-order temperature drift correction module outputs the second-order correction current to the temperature drift correction resistor to correct the first preset temperature curve to the second preset temperature curve. The peak-to-valley difference of the second preset temperature curve is smaller than that of the first preset temperature curve. After the temperature curve of the reference voltage conforms to the second preset temperature curve, the offset value of the reference voltage is detected. Based on the offset value, the control signal is output to the offset correction module; The offset correction module adjusts the offset correction current flowing through the temperature drift correction resistor based on the control signal to compensate for the offset value of the reference voltage.

9. The method for adjusting the bandgap reference circuit according to claim 8, characterized in that, Before the temperature curve of the reference voltage conforms to the second preset temperature curve, the method further includes: controlling some of the correction switches among a plurality of correction switches to close, and controlling the remaining correction switches to open. The method by which the offset correction module adjusts the offset correction current based on the control signal specifically includes: the control signal changing the number of conducting switches among the plurality of correction switches.

10. An electronic device, characterized in that, Includes the bandgap reference circuit as described in any one of claims 1 to 9.

Images