Flash memory device and method of manufacturing the same
Patent Information
- Application Number
- CN202610771114.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-05-29
- Publication Date
- 2026-08-28
AI Technical Summary
[0006]本发明的目的在于提供一种闪存器件及其制备方法，以解决现有的闪存器件中，源线与浮栅的耦合方式容易削弱闪存器件的数据保持能力与耐久度、结电容随电压/温度容易产生漂移造成耦合系数不稳定导致浮栅电位失控等问题中的至少一个问题
[0033] In summary, this invention provides a flash memory device and its fabrication method. In the fabrication method, after forming trenches in a hard mask layer, a sacrificial dielectric layer, and a floating gate material layer, an ONO sidewall structure is formed on the sidewalls and part of the bottom wall of the trench. Then, the floating gate material layer at the bottom of the trench not covered by the ONO sidewall structure is etched. Subsequently, the silicon nitride layer in the ONO sidewall structure is etched back to form a lateral opening between a first silicon oxide layer and a second silicon oxide layer above the floating gate material layer in the trench. Next, an isolation dielectric layer is formed covering the exposed floating gate material layer and the inner wall of the lateral opening. Finally, the lateral opening and the trench are filled with source line polysilicon. This application, by forming an ONO sidewall structure on the trench sidewalls and etching back the silicon nitride layer in the ONO sidewall structure to form a lateral opening, and finally filling the lateral opening and the trench with source line polysilicon, increases the overlap area between the source line polysilicon and the floating gate, improves the coupling efficiency between the source line and the floating gate, and thus improves the programming efficiency of the flash memory device.
Smart Images
Figure CN122662230A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a flash memory device and its fabrication method. Background Technology
[0002] refer to Figure 1 , Figure 1 This is a basic structural diagram of the existing Super flash memory structure. The basic principle of flash memory programming is channel hot electron injection (CHE). The voltage difference between the source terminal 2 and the drain terminal 3 generates channel hot electrons. The coupling voltage of the floating gate 5 draws the channel hot electrons into the floating gate through the gate oxide layer 4. The hot electrons accumulate in the floating gate, completing the programming.
[0003] The coupling voltage (equivalent voltage) of the floating gate 5 mainly comes from three aspects: word line 8 coupling voltage, substrate coupling voltage and source line 7 coupling voltage.
[0004] Specifically, the formula for calculating the equivalent voltage of floating gate 5 is: VFG≈QFG / CTOT+α1VWL+α2VSL, where VFG is the equivalent voltage of the floating gate, QFG is the charge accumulated in the floating gate, CTOT is the total equivalent capacitance of the floating gate to all surrounding electrodes, α1 is the word line-floating gate coupling coefficient, VWL is the word line voltage, α2 is the source line-floating gate coupling coefficient, and VSL is the source line voltage. It can be seen that increasing the equivalent voltage of the floating gate can be achieved by maximizing α1 and / or α2.
[0005] In existing flash memory structures, the coupling between the source line (SL) 7 and the floating gate (FG) 5 is mainly achieved by forming a PN junction through ion implantation in the substrate at the bottom of the polysilicon source line 7. However, the PN junction is prone to leakage current, which weakens the data retention capability and endurance. Furthermore, the junction capacitance drifts with voltage / temperature, causing the coupling coefficient to be unstable and leading to the uncontrolled floating gate potential. Summary of the Invention
[0006] The purpose of this invention is to provide a flash memory device and its fabrication method, in order to solve at least one of the following problems in existing flash memory devices: the coupling method between the source line and the floating gate easily weakens the data retention capability and durability of the flash memory device; the junction capacitance easily drifts with voltage / temperature, causing the coupling coefficient to be unstable and leading to the uncontrolled floating gate potential.
[0007] To address the aforementioned technical problems, in one aspect, the present invention provides a method for fabricating a flash memory device, comprising:
[0008] A substrate is provided on which a gate oxide layer, a floating gate material layer, a sacrificial dielectric layer and a hard mask layer are sequentially formed, wherein trenches are formed in the hard mask layer, the sacrificial dielectric layer and a portion of the thickness of the floating gate material layer;
[0009] An ONO sidewall structure is formed on the sidewall and part of the bottom wall of the trench, wherein the ONO sidewall includes: an L-shaped first silicon oxide layer covering the sidewall and part of the bottom wall of the trench, an L-shaped silicon nitride layer covering the first silicon oxide layer, and an arc-shaped second silicon oxide layer located on the silicon nitride layer.
[0010] Continue etching the floating gate material layer under the trench bottom wall not covered by the ONO sidewall structure and stop at the surface of the gate oxide layer;
[0011] The silicon nitride layer is etched back from the upper and lower ends of the L-shaped silicon nitride layer to remove at least a portion of the silicon nitride layer on the bottom wall of the trench and a portion of the silicon nitride layer on the side wall of the trench, so as to form a lateral opening between the first silicon oxide layer and the second silicon oxide layer above the floating gate material layer in the trench.
[0012] An isolation dielectric layer is formed, which at least covers the inner wall of the lateral opening between the exposed floating gate material layer, the first silicon oxide layer, and the second silicon oxide layer in the trench;
[0013] A source line polysilicon is formed, which covers the hard mask layer and fills the lateral opening and the trench;
[0014] The hard mask layer and the source polysilicon beyond the surface of the sacrificial dielectric layer are removed by grinding.
[0015] Optionally, in the method for fabricating the flash memory device, a wet etching process is used to etch the silicon nitride layer from the upper end and the lower end of the L-shaped silicon nitride layer to remove at least a portion of the silicon nitride layer on the bottom wall of the trench and a portion of the silicon nitride layer on the side wall of the trench.
[0016] Optionally, in the method for fabricating the flash memory device, a wet etching process is used. During the process of etching back the silicon nitride layer from the upper and lower ends of the L-shaped silicon nitride layer, the wet solution used is phosphoric acid.
[0017] Optionally, in the method for fabricating the flash memory device, the lateral dimension of the lateral opening does not exceed the maximum lateral dimension of the second silicon oxide layer.
[0018] Optionally, in the method for fabricating the flash memory device, in the ONO sidewall, the thickness of the first silicon oxide layer is 250 angstroms to 350 angstroms; the thickness of the silicon nitride layer is 1150 angstroms to 1250 angstroms; and the thickness of the second silicon oxide layer is 550 angstroms to 650 angstroms.
[0019] Optionally, in the fabrication method of the flash memory device, a chemical vapor deposition process is used to form the isolation dielectric layer.
[0020] Optionally, in the method for fabricating the flash memory device, the material of the isolation dielectric layer is silicon dioxide.
[0021] Optionally, in the method for fabricating the flash memory device, the thickness of the isolation dielectric layer is 450 angstroms to 550 angstroms.
[0022] Optionally, in the method for fabricating the flash memory device, the method further includes:
[0023] A source line protection layer is formed, which covers the source line polysilicon;
[0024] Remove the sacrificial dielectric layer and a portion of the floating gate material layer at the bottom of the sacrificial dielectric layer to obtain the final floating gate;
[0025] A tunneling oxide layer is formed, which covers the outer surface of the floating gate;
[0026] Word line polysilicon is formed, which is located on the gate oxide layer outside the ONO sidewall structure and covers the outer surface of the ONO sidewall structure and the tunneling oxide layer.
[0027] A sidewall isolation layer is formed, which is located on the gate oxide layer outside the word line polysilicon and covers a portion of the outer surface of the word line polysilicon.
[0028] On the other hand, the present invention also provides a flash memory device, comprising:
[0029] A substrate on which a gate oxide layer, a floating gate material layer and a sacrificial dielectric layer are sequentially formed, wherein trenches are formed in the sacrificial dielectric layer and the floating gate material layer, wherein the inner surface of the floating gate material layer extends beyond the inner surface of the sacrificial dielectric layer in the trenches, so that the trenches are inverted convex shapes.
[0030] The ONO sidewall structure is located on the exposed floating gate material layer in the trench and covers the inner surface of the sacrificial dielectric layer. The ONO sidewall includes: an L-shaped first silicon oxide layer covering the inner surface of the sacrificial dielectric layer on the trench sidewall and the exposed upper surface of the floating gate material layer; a silicon nitride layer on the first silicon oxide layer; and an arc-shaped second silicon oxide layer on the silicon nitride layer. The lower end of the first silicon oxide layer near the floating gate material layer and the inner surface of the second silicon oxide layer extend beyond the lower end of the silicon nitride layer, forming a lateral opening between the first silicon oxide layer and the second silicon oxide layer above the floating gate material layer.
[0031] An isolation dielectric layer, the isolation dielectric layer at least covering the inner wall of the lateral opening between the exposed floating gate material layer, the first silicon oxide layer and the second silicon oxide layer in the trench;
[0032] Source line polysilicon, the source line polysilicon filling the lateral opening and the trench.
[0033] In summary, this invention provides a flash memory device and its fabrication method. In the fabrication method, after forming trenches in a hard mask layer, a sacrificial dielectric layer, and a floating gate material layer, an ONO sidewall structure is formed on the sidewalls and part of the bottom wall of the trench. Then, the floating gate material layer at the bottom of the trench not covered by the ONO sidewall structure is etched. Subsequently, the silicon nitride layer in the ONO sidewall structure is etched back to form a lateral opening between a first silicon oxide layer and a second silicon oxide layer above the floating gate material layer in the trench. Next, an isolation dielectric layer is formed covering the exposed floating gate material layer and the inner wall of the lateral opening. Finally, the lateral opening and the trench are filled with source line polysilicon. This application, by forming an ONO sidewall structure on the trench sidewalls and etching back the silicon nitride layer in the ONO sidewall structure to form a lateral opening, and finally filling the lateral opening and the trench with source line polysilicon, increases the overlap area between the source line polysilicon and the floating gate, improves the coupling efficiency between the source line and the floating gate, and thus improves the programming efficiency of the flash memory device. Attached Figure Description
[0034] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention.
[0035] Figure 1 This is a basic structural diagram of the existing Super flash memory architecture;
[0036] Figure 2 This is a flowchart of a method for fabricating a flash memory device according to an embodiment of the present invention;
[0037] Figures 3-12 This is a schematic diagram of the semiconductor structure in each process step of fabricating a flash memory device according to an embodiment of the present invention;
[0038] The reference numerals in the attached figures are explained as follows:
[0039] 1-Substrate, 2-Source terminal, 3-Drain terminal, 4-Gate oxide layer, 5-Floating gate, 6-Dielectric layer, 7-Source line (source line polysilicon), 8-Word line (word line polysilicon), 11-First sidewall, 12-Second sidewall, 13-Third sidewall;
[0040] 10-Substrate, 20-Gate oxide layer, 30-Floating gate material layer, 31-Final floating gate, 40-Sacrificial oxide layer, 50-Hard mask layer, 51-Trench, 52-Side opening, 61-First silicon oxide layer, 62-Silicon nitride layer, 63-Second silicon oxide layer, 70-Isolation dielectric layer, 81-Source line polysilicon, 82-Source line protection layer, 83-Tunneling oxide layer, 90-Word line polysilicon, 91-Sidewall isolation layer. Detailed Implementation
[0041] To make the objectives, advantages, and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clearly illustrate the objectives of the embodiments of the present invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and sometimes use different scales. It should also be understood that, unless specifically stated or indicated, the terms "first," "second," "third," etc., in the specification are only used to distinguish the various components, elements, steps, etc., in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.
[0042] This invention provides a method for fabricating a flash memory device, with reference to... Figure 2 , Figure 2 This is a flowchart of a method for fabricating a flash memory device according to an embodiment of the present invention. The method for fabricating the flash memory device includes:
[0043] First, perform step S1: Refer to Figure 3 , Figure 3 This is a schematic diagram of the semiconductor structure after trench formation according to an embodiment of this application. A substrate 10 is provided, on which a gate oxide layer 20, a floating gate material layer 30, a sacrificial dielectric layer 40 and a hard mask layer 50 are sequentially formed. Trench 51 is formed in the hard mask layer 50, the sacrificial dielectric layer 40 and a portion of the thickness of the floating gate material layer 30.
[0044] The substrate 10 can be one of monocrystalline silicon, polycrystalline silicon, or amorphous silicon. The substrate 10 can also have a silicon-on-insulator or silicon-on-epitaxy layer structure. The substrate 10 can also be other semiconductor materials, which will not be listed here.
[0045] Preferably, the sacrificial dielectric layer 40 is made of silicon nitride.
[0046] Preferably, the hard mask layer 50 is made of silicon dioxide.
[0047] Then, proceed to step S2: (Refer to...) Figure 4 , Figure 4 This is a schematic diagram of the semiconductor structure after the formation of the ONO sidewall structure according to an embodiment of this application. The ONO sidewall structure is formed on the sidewall and part of the bottom wall of the trench. The ONO sidewall includes: an L-shaped first silicon oxide layer 61 covering the sidewall and part of the bottom wall of the trench, an L-shaped silicon nitride layer 62 covering the first silicon oxide layer 61, and an arc-shaped second silicon oxide layer 63 located on the silicon nitride layer 62.
[0048] Preferably, in the ONO sidewall, the thickness of the first silicon oxide layer 61 is 250 angstroms to 350 angstroms; the thickness of the silicon nitride layer 62 is 1150 angstroms to 1250 angstroms; and the thickness of the second silicon oxide layer 63 is 550 angstroms to 650 angstroms.
[0049] Next, proceed to step S3: (Refer to...) Figure 5 , Figure 5 This is a schematic diagram of the semiconductor structure after the floating gate material layer under the trench bottom wall not covered by the ONO sidewall structure is further etched according to an embodiment of this application. The etching of the floating gate material layer 30 under the trench 51 bottom wall not covered by the ONO sidewall structure continues and stops on the surface of the gate oxide layer 20.
[0050] Further, proceed to step S4: Refer to Figure 6 , Figure 6 This is a schematic diagram of the semiconductor structure after the formation of the lateral opening in an embodiment of this application. The silicon nitride layer 62, which is L-shaped, is etched back from the upper and lower ends to remove at least a portion of the silicon nitride layer 62 on the bottom wall of the trench 51 and a portion of the silicon nitride layer 62 at the top of the trench sidewall, so as to form a lateral opening 52 between the first silicon oxide layer 61 and the second silicon oxide layer 63 above the floating gate material layer 30 in the trench 51.
[0051] The flash memory structure provided in this application embodiment is based on the source line polysilicon as the axis of symmetry, and all films / structures on both sides of the axis of symmetry are symmetrical.
[0052] Preferred, Reference Figure 6 The lateral dimension (dimension along the X direction) d1 of the lateral opening 52 does not exceed (is less than or equal to) the maximum lateral dimension (dimension along the X direction) d2 of the second silicon oxide layer 63. This can prevent the portion of the second silicon oxide layer 63 covering the upper surface of the first silicon oxide layer 61 from being completely etched to the point that the side surface of the first silicon oxide layer 61 is exposed during the formation of the lateral opening 52. That is, it can prevent the silicon nitride layer 62 from being excessively scooped out during the wet etching process to the point that the side surface of the first silicon oxide layer 61 is exposed.
[0053] Wherein, the maximum lateral dimension (dimension along the X direction) d2 of the arc-shaped second silicon oxide layer 63 is the lateral dimension of the bottom end of the second silicon oxide layer 63.
[0054] In this embodiment, the lateral dimension (dimension along the X direction) d1 of the lateral opening 52 is smaller than the lateral dimension (dimension along the X direction) d2 of the second silicon oxide layer 63.
[0055] In other embodiments, the lateral dimension (dimension along the X direction) d1 of the lateral opening 52 does not exceed (is less than or equal to) the maximum lateral dimension (dimension along the X direction) of the silicon nitride layer 62.
[0056] Preferably, the dimension of the lateral opening 52 along the Y direction is equal to the thickness of the silicon nitride layer 62.
[0057] Preferably, a wet etching process is used to etch the silicon nitride layer 62 from the upper and lower ends of the L-shaped silicon nitride layer 62 to remove at least a portion of the silicon nitride layer 62 on the bottom wall of the trench 51 and a portion of the silicon nitride layer 62 at the top of the trench sidewall.
[0058] In this embodiment, a wet etching process is used to etch the silicon nitride layer 62 from the upper and lower ends of the L-shaped silicon nitride layer 62. The wet solution used is phosphoric acid.
[0059] Next, proceed to step S5: (Refer to...) Figure 7 , Figure 7 This is a schematic diagram of the semiconductor structure after the formation of the isolation dielectric layer according to an embodiment of this application. The isolation dielectric layer 70 is formed, and the isolation dielectric layer 70 at least covers the inner wall of the lateral opening 52 between the floating gate material layer 30, the first silicon oxide layer 61 and the second silicon oxide layer 62 exposed in the trench 51.
[0060] The isolation dielectric layer 70 serves to isolate the floating gate material layer 30 from the subsequently deposited source line polysilicon 81.
[0061] Preferably, the isolation medium layer 70 is formed by chemical vapor deposition.
[0062] In this embodiment, the material of the isolation dielectric layer 70 is silicon dioxide.
[0063] Preferably, the thickness of the insulating medium layer 70 is 450 angstroms to 550 angstroms.
[0064] In this embodiment, before performing step S6 (forming source line polysilicon 81), ion implantation is performed on the substrate 10 at the bottom of the trench 51 to form a source line ion implantation region (not shown) at the bottom of the trench 51.
[0065] Further, proceed to step S6: Refer to Figure 8 , Figure 8 This is a schematic diagram of the semiconductor structure after the hard mask layer and the source polysilicon beyond the surface of the sacrificial dielectric layer are removed by grinding according to an embodiment of this application, forming a source polysilicon 81, which covers the hard mask layer 50 and fills the lateral opening 52 and the trench 51.
[0066] Preferably, the source line polycrystalline silicon 81 is formed using a CVD (chemical vapor deposition) process.
[0067] Finally, proceed to step S7: Continue to refer to Figure 8 The hard mask layer 50 and the source polysilicon 81 extending beyond the surface of the sacrificial dielectric layer 40 are removed by CMP (chemical mechanical polishing) process, and the first silicon oxide layer 61, the silicon nitride layer 62 and the second silicon oxide layer 63 extending beyond the surface of the sacrificial dielectric layer 40 are also removed by CMP process.
[0068] Furthermore, the method for fabricating the flash memory device may further include:
[0069] Step S8: Reference Figure 9 , Figure 9 This is a schematic diagram of the semiconductor structure after the formation of the source line protection layer in an embodiment of this application. The source line protection layer 82 is formed by thermal oxidation process, and the source line protection layer 82 covers the source line polysilicon 81.
[0070] In this embodiment, the source line protection layer 82 is made of silicon dioxide.
[0071] Step S9: Reference Figure 10 , Figure 10 This is a schematic diagram of the semiconductor structure after removing the sacrificial dielectric layer and a portion of the floating gate material layer at the bottom of the sacrificial dielectric layer according to an embodiment of this application. The sacrificial dielectric layer 40 and a portion of the floating gate material layer 30 at the bottom of the sacrificial dielectric layer 40 are removed to obtain the final floating gate 31.
[0072] Step S10: Reference Figure 11 , Figure 11 This is a schematic diagram of the semiconductor structure after the formation of polysilicon word lines in an embodiment of this application. A tunneling oxide layer 83 is formed using a CVD (chemical vapor deposition) process, and the tunneling oxide layer 83 covers the outer surface of the floating gate 31.
[0073] Step S11: Continue to refer to Figure 11 The word line polysilicon 90 is formed by using CVD (chemical vapor deposition) process. The word line polysilicon 90 is located on the gate oxide layer 20 outside the ONO sidewall structure and covers the outer surface of the ONO sidewall structure (first silicon oxide layer 61) and the tunneling oxide layer 83.
[0074] Step S12: Reference Figure 12 , Figure 12 This is a schematic diagram of the semiconductor structure after the formation of the sidewall isolation layer in an embodiment of this application. The sidewall isolation layer 91 is formed by CVD (chemical vapor deposition) process. The sidewall isolation layer 91 is located on the gate oxide layer 20 outside the word line polysilicon 90 and covers part of the outer surface of the word line polysilicon 90.
[0075] In this embodiment, the sidewall isolation layer 91 is made of silicon dioxide.
[0076] Furthermore, after forming the sidewall isolation layer 91, the method for fabricating the flash memory device may further include: performing ion implantation on the substrate 10 outside the sidewall isolation layer 91 to form a drain electrode (not shown) in the substrate 10 outside the sidewall isolation layer 91.
[0077] In this application, by forming an ONO sidewall structure on the trench sidewall and etching back the silicon nitride layer in the ONO sidewall structure to form a lateral opening, and finally filling the lateral opening and trench with source line polysilicon, the overlap area of the source line polysilicon and the floating gate can be increased, the coupling efficiency of the source line and the floating gate can be improved, thereby improving the programming efficiency of the flash memory device.
[0078] Based on the same inventive concept, the present invention also provides a flash memory device, see reference. Figure 8 The flash memory device includes:
[0079] A substrate 10, on which a gate oxide layer 20, a floating gate material layer 30 and a sacrificial dielectric layer 40 are sequentially formed, wherein a trench 51 is formed in the sacrificial dielectric layer 40 and the floating gate material layer 30, wherein, in the trench 51, the inner surface of the floating gate material layer 30 extends beyond the inner surface of the sacrificial dielectric layer 40 in the direction of the central axis of the trench, so that the trench 51 is inverted convex shape;
[0080] The ONO sidewall structure is located on the exposed floating gate material layer 30 in the trench 51 and covers the inner surface of the sacrificial dielectric layer 40. The ONO sidewall includes: an L-shaped first silicon oxide layer 61 covering the inner surface of the sacrificial dielectric layer 40 on the sidewall of the trench 51 and the exposed upper surface of the floating gate material layer 30; a silicon nitride layer 62 on the first silicon oxide layer 61; and an arc-shaped second silicon oxide layer 63 on the silicon nitride layer 62. In the direction of the central axis of the trench, the lower end of the first silicon oxide layer 61 and the inner surface of the second silicon oxide layer 63 near the floating gate material layer 30 extend beyond the lower end of the silicon nitride layer 62, so that a lateral opening 52 is formed between the first silicon oxide layer 61 and the second silicon oxide layer 63 above the floating gate material layer 30.
[0081] An isolation dielectric layer 70, which at least covers the inner wall of the lateral opening 52 between the exposed floating grid material layer 30, the first silicon oxide layer 61 and the second silicon oxide layer 63 in the trench;
[0082] Source line polysilicon 81, which fills the lateral opening 52 and the trench 51.
[0083] In the flash memory device provided in this application, an ONO sidewall structure covering the trench sidewall is formed on the floating gate material layer, and the lower end of the first silicon oxide layer and the inner surface of the second silicon oxide layer near the floating gate material layer extend beyond the lower end of the silicon nitride layer, so that a lateral opening is formed between the first silicon oxide layer and the second silicon oxide layer above the floating gate material layer. In this way, the subsequent source line polysilicon not only fills the trench, but also fills the lateral opening, thereby increasing the overlap area of the source line polysilicon and the floating gate, improving the coupling efficiency of the source line and the floating gate, and thus improving the programming efficiency of the flash memory device.
[0084] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.
Claims
1. A method for fabricating a flash memory device, characterized in that, include: A substrate is provided on which a gate oxide layer, a floating gate material layer, a sacrificial dielectric layer and a hard mask layer are sequentially formed, wherein trenches are formed in the hard mask layer, the sacrificial dielectric layer and a portion of the thickness of the floating gate material layer; An ONO sidewall structure is formed on the sidewall and part of the bottom wall of the trench, wherein the ONO sidewall includes: an L-shaped first silicon oxide layer covering the sidewall and part of the bottom wall of the trench, an L-shaped silicon nitride layer covering the first silicon oxide layer, and an arc-shaped second silicon oxide layer located on the silicon nitride layer. Continue etching the floating gate material layer under the trench bottom wall not covered by the ONO sidewall structure and stop at the surface of the gate oxide layer; The silicon nitride layer is etched back from the upper and lower ends of the L-shaped silicon nitride layer to remove at least a portion of the silicon nitride layer on the bottom wall of the trench and a portion of the silicon nitride layer on the side wall of the trench, so as to form a lateral opening between the first silicon oxide layer and the second silicon oxide layer above the floating gate material layer in the trench. An isolation dielectric layer is formed, which at least covers the inner wall of the lateral opening between the exposed floating gate material layer, the first silicon oxide layer, and the second silicon oxide layer in the trench; A source line polysilicon is formed, which covers the hard mask layer and fills the lateral opening and the trench; The hard mask layer and the source polysilicon beyond the surface of the sacrificial dielectric layer are removed by grinding.
2. The method for fabricating a flash memory device according to claim 1, characterized in that, A wet etching process is used to etch back the silicon nitride layer from the top and bottom ends of the L-shaped silicon nitride layer to remove at least a portion of the silicon nitride layer on the bottom wall of the trench and a portion of the silicon nitride layer on the sidewall of the trench.
3. The method for fabricating a flash memory device according to claim 1, characterized in that, In the process of etching back the silicon nitride layer from the top and bottom of the L-shaped layer using a wet etching process, phosphoric acid is used as the wet solution.
4. The method for fabricating a flash memory device according to claim 1, characterized in that, The lateral dimension of the lateral opening does not exceed the maximum lateral dimension of the second silicon oxide layer.
5. The method for fabricating a flash memory device according to claim 1, characterized in that, In the ONO sidewall, the thickness of the first silicon oxide layer is 250 angstroms to 350 angstroms; the thickness of the silicon nitride layer is 1150 angstroms to 1250 angstroms; and the thickness of the second silicon oxide layer is 550 angstroms to 650 angstroms.
6. The method for fabricating a flash memory device according to claim 1, characterized in that, The isolation medium layer is formed using a chemical vapor deposition process.
7. The method for fabricating a flash memory device according to claim 1, characterized in that, The material of the isolation medium layer is silicon dioxide.
8. The method for fabricating a flash memory device according to claim 1, characterized in that, The thickness of the isolation medium layer is 450 angstroms to 550 angstroms.
9. The method for fabricating a flash memory device according to claim 1, characterized in that, The method for fabricating the flash memory device further includes: A source line protection layer is formed, which covers the source line polysilicon; Remove the sacrificial dielectric layer and a portion of the floating gate material layer at the bottom of the sacrificial dielectric layer to obtain the final floating gate; A tunneling oxide layer is formed, which covers the outer surface of the floating gate; Word line polysilicon is formed, which is located on the gate oxide layer outside the ONO sidewall structure and covers the outer surface of the ONO sidewall structure and the tunneling oxide layer. A sidewall isolation layer is formed, which is located on the gate oxide layer outside the word line polysilicon and covers a portion of the outer surface of the word line polysilicon.
10. A flash memory device, characterized in that, include: A substrate on which a gate oxide layer, a floating gate material layer and a sacrificial dielectric layer are sequentially formed, wherein trenches are formed in the sacrificial dielectric layer and the floating gate material layer, wherein the inner surface of the floating gate material layer extends beyond the inner surface of the sacrificial dielectric layer in the trenches, so that the trenches are inverted convex shapes. The ONO sidewall structure is located on the exposed floating gate material layer in the trench and covers the inner surface of the sacrificial dielectric layer. The ONO sidewall includes: an L-shaped first silicon oxide layer covering the inner surface of the sacrificial dielectric layer on the trench sidewall and the exposed upper surface of the floating gate material layer; a silicon nitride layer on the first silicon oxide layer; and an arc-shaped second silicon oxide layer on the silicon nitride layer. The lower end of the first silicon oxide layer near the floating gate material layer and the inner surface of the second silicon oxide layer extend beyond the lower end of the silicon nitride layer, forming a lateral opening between the first silicon oxide layer and the second silicon oxide layer above the floating gate material layer. An isolation dielectric layer, the isolation dielectric layer at least covering the inner wall of the lateral opening between the exposed floating gate material layer, the first silicon oxide layer and the second silicon oxide layer in the trench; Source line polysilicon, the source line polysilicon filling the lateral opening and the trench.