Display panel and driving method thereof

Abstract

The application discloses a display panel and a driving method thereof, and belongs to the technical field of display. The display panel comprises a plurality of sub-pixels, each of which comprises a light-emitting unit and a pixel circuit. The display panel further comprises a silicon-based driving substrate comprising a plurality of substrate patterns and a plurality of pixel circuits; a dielectric layer located on one side of the silicon-based driving substrate and comprising a plurality of dielectric patterns; a first electrode layer located on the side of the dielectric layer away from the silicon-based driving substrate and comprising a plurality of first electrode patterns; and a second electrode layer located on the side of the silicon-based driving substrate away from the dielectric layer and comprising a plurality of second electrode patterns. The light-emitting unit comprises the first electrode pattern, the dielectric pattern, the substrate pattern and the second electrode pattern which are mutually overlapped. The first electrode pattern and the second electrode pattern are electrically connected to the pixel circuit corresponding to the light-emitting unit respectively. The light-emitting unit is used for emitting light under the reverse bias voltage driving applied by the pixel circuit. The reverse bias voltage is directed from the second electrode pattern to the first electrode pattern.

Description

Technical Field

[0001] This application belongs to the field of display technology, specifically relating to a display panel and its driving method. Background Technology

[0002] Currently, most silicon-based display panels achieve light emission by bonding silicon-based III-V compound semiconductors (such as indium gallium arsenide (InGaAs) and gallium nitride (GaN)) to a silicon-based driving backplane. However, the lattice mismatch and thermal expansion coefficients between silicon-based III-V compound semiconductors and silicon-based driving backplanes are quite different, requiring high-precision bonding technology. This process is difficult, has a low yield, and results in high mass production costs. Summary of the Invention

[0003] The purpose of this application is to provide a display panel and its driving method, which can solve the problems of low yield and high cost of display panels formed by bonding silicon-based III-V compound with silicon-based driving backplane.

[0004] In a first aspect, embodiments of this application provide a display panel including a plurality of sub-pixels, each sub-pixel including a light-emitting unit and a pixel circuit, and the display panel further including: A silicon-based driving substrate, comprising multiple substrate patterns and multiple pixel circuits; The dielectric layer, located on one side of the silicon-based driving substrate, includes multiple dielectric patterns; The first electrode layer, located on the side of the dielectric layer away from the silicon-based driving substrate, includes multiple first electrode patterns; The second electrode layer is located on the side of the silicon-based driving substrate away from the dielectric layer and includes multiple second electrode patterns. The light-emitting unit includes overlapping first electrode patterns, dielectric patterns, substrate patterns and second electrode patterns. The first electrode patterns and second electrode patterns are electrically connected to the pixel circuits corresponding to the light-emitting units. The light-emitting units are used to emit light under the reverse bias voltage applied by the pixel circuits. The reverse bias voltage is directed from the second electrode pattern to the first electrode pattern.

[0005] Optionally, the display panel may also include: The protective layer is located on the side of the first electrode layer away from the dielectric layer, and includes multiple first protective patterns and multiple second protective patterns. The first protective patterns are projected onto the silicon-based driving substrate and cover the projected onto the silicon-based driving substrate. The second protective patterns do not overlap with the projected onto the silicon-based driving substrate. A second protective pattern is provided between two adjacent sub-pixels.

[0006] Optionally, multiple second electrode patterns are connected as one unit, and the orthographic projections of the second electrode patterns and pixel circuits on the silicon-based driving substrate do not overlap.

[0007] Optionally, the display panel may also include: The color conversion layer is located on the side of the first electrode layer away from the dielectric layer. It includes multiple color conversion patterns. The color conversion patterns overlap with the orthographic projection of the light-emitting unit on the silicon-based driving substrate. The color conversion patterns are used to convert the light emitted by the light-emitting unit into light of a first color, and the first color and the second color are different.

[0008] Optionally, the multiple sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel; The first sub-pixel includes a first light-emitting unit and a first color conversion pattern. The first color conversion pattern overlaps with the orthographic projection of the first light-emitting unit onto the silicon-based driving substrate. The first color conversion pattern is used to convert the light of the first color emitted by the first light-emitting unit into red light. The second sub-pixel includes a second light-emitting unit and a second color conversion pattern. The second color conversion pattern overlaps with the orthographic projection of the second light-emitting unit onto the silicon-based driving substrate. The second color conversion pattern is used to convert the light of the first color emitted by the second light-emitting unit into green light. The third sub-pixel includes a third light-emitting unit and a third color conversion pattern. The third color conversion pattern overlaps with the orthographic projection of the third light-emitting unit onto the silicon-based driving substrate. The third color conversion pattern is used to convert the light of the first color emitted by the third light-emitting unit into blue light.

[0009] Optionally, the pixel circuit includes a first control module, a second control module, a first driving transistor, a second driving transistor, a third driving transistor, and a fourth driving transistor; The first and second driving transistors have opposite transistor types, the third and fourth driving transistors have opposite transistor types, the second and third driving transistors have the same transistor type, and the channel width-to-length ratios of the first, second, third, and fourth driving transistors are different from each other. The first terminal of the first driving transistor, the first terminal of the second driving transistor, the first terminal of the third driving transistor, and the first terminal of the fourth driving transistor are respectively electrically connected to the light-emitting unit corresponding to the pixel circuit. The input terminal of the first control module is electrically connected to the first data line, the control terminal is electrically connected to the first control line, and the output terminal is electrically connected to the control electrode of the first driving transistor and the control electrode of the second driving transistor, respectively. The input terminal of the second control module is electrically connected to the second data line, the control terminal is electrically connected to the second control line, and the output terminal is electrically connected to the control electrode of the third drive transistor and the control electrode of the fourth drive transistor, respectively.

[0010] Optionally, the pixel circuit further includes a third control module, a fourth control module, a first light-emitting control transistor, a second light-emitting control transistor, a third light-emitting control transistor, and a fourth light-emitting control transistor; the first light-emitting control transistor and the second light-emitting control transistor have the same transistor type, and the third light-emitting control transistor and the fourth light-emitting control transistor have the same transistor type. The second electrode of the first driving transistor is electrically connected to the first electrode of the first light-emitting control transistor, the second electrode of the second driving transistor is electrically connected to the first electrode of the second light-emitting control transistor, the second electrode of the third driving transistor is electrically connected to the first electrode of the third light-emitting control transistor, and the second electrode of the fourth driving transistor is electrically connected to the first electrode of the fourth light-emitting control transistor. The input terminal of the third control module is electrically connected to the first light-emitting control line, the control terminal is electrically connected to the third data line, and the output terminal is electrically connected to the control electrode of the first light-emitting control tube and the control electrode of the second light-emitting control tube, respectively. The input terminal of the fourth control module is electrically connected to the second light-emitting control line, the control terminal is electrically connected to the fourth data line Data4, and the output terminal is electrically connected to the control electrode of the third light-emitting control tube and the control electrode of the fourth light-emitting control tube, respectively.

[0011] Secondly, embodiments of this application provide a driving method for a display panel, used to drive the display panel as described in the first aspect, the driving method comprising: Based on the target grayscale value of the current display frame, determine the first voltage value corresponding to each subframe within the current display frame; wherein, the current display frame includes at least one subframe; Within a subframe, the pixel circuit controlling the display panel applies a reverse bias voltage of a first voltage value to the light-emitting unit of the display panel, driving the light-emitting unit to emit light.

[0012] Optionally, the current display frame includes multiple subframes; within each subframe, the pixel circuit controlling the display panel applies a reverse bias voltage of a first voltage value to the light-emitting unit, driving the light-emitting unit of the display panel to emit light, including: Within a subframe, a first control signal is sent to the first control line of the pixel circuit according to the first voltage value, a first data signal is sent to the first data line to control the first driving transistor or the second driving transistor to turn on, and a second control signal is sent to the second control line of the pixel circuit and a second data signal is sent to the second data line to control the third driving transistor or the fourth driving transistor to turn on, thereby providing the light-emitting unit with a driving current corresponding to the first voltage value.

[0013] Optionally, the driving method also includes: Within a subframe, a first light emission control signal is sent to the first light emission control line of the pixel circuit, a third data signal is sent to the third data line of the pixel circuit to control the first and second light emission control transistors to turn on, a second light emission control signal is sent to the second light emission control line of the pixel circuit, and a fourth data signal is sent to the fourth data line of the pixel circuit to control the third and fourth light emission control transistors to turn on; wherein, the effective level duration of the first and second light emission control signals is different.

[0014] In this embodiment, the display panel includes multiple sub-pixels, each sub-pixel including a light-emitting unit and a pixel circuit. The display panel also includes a silicon-based driving substrate, a dielectric layer, a first electrode layer, and a second electrode layer. The silicon-based driving substrate includes multiple substrate patterns and multiple pixel circuits. The dielectric layer is located on one side of the silicon-based driving substrate and includes multiple dielectric patterns. The first electrode layer is located on the side of the dielectric layer away from the silicon-based driving substrate and includes multiple first electrode patterns. The second electrode layer is located on the side of the silicon-based driving substrate away from the dielectric layer and includes multiple second electrode patterns. Each light-emitting unit includes overlapping first electrode patterns, dielectric patterns, substrate patterns, and second electrode patterns. The first electrode patterns and second electrode patterns are electrically connected to the pixel circuits corresponding to the light-emitting units. The light-emitting units emit light under a reverse bias applied by the pixel circuits, with the reverse bias pointing from the second electrode pattern to the first electrode pattern. Because the light-emitting units utilize the substrate patterns of the silicon-based driving substrate, compared to bonding silicon-based III-V compounds to the CMOS backplane, the light-emitting units in this embodiment are compatible with the fabrication process of the silicon-based driving substrate, which can improve production yield and reduce manufacturing costs.

[0015] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, specific embodiments of this application are given below. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is one of the structural schematic diagrams of a display panel provided in the embodiments of this application; Figure 2 This is a schematic diagram of the light-emitting principle of a light-emitting unit in a display panel provided in an embodiment of this application; Figure 3 This is a second schematic diagram of the structure of a display panel provided in an embodiment of this application; Figure 4 This is the third schematic diagram of the structure of a display panel provided in the embodiments of this application; Figure 5 This is the fourth schematic diagram of the structure of a display panel provided in the embodiments of this application; Figure 6 This is the fifth schematic diagram of the structure of a display panel provided in the embodiments of this application; Figure 7 This is a manufacturing process diagram of a display panel provided in an embodiment of this application; Figure 8 This is one of the schematic diagrams of a pixel circuit in a display panel provided in the embodiments of this application; Figure 9 This is a second schematic diagram of the structure of a pixel circuit in a display panel provided in an embodiment of this application; Figure 10 This is the third schematic diagram of the pixel circuit structure in a display panel provided in this application embodiment; Figure 11 This application provides a schematic diagram of the steps of a display panel driving method according to an embodiment; Figure 12 This is one of the timing diagrams of a driving method provided in an embodiment of this application; Figure 13 This is a second timing diagram of a driving method provided in an embodiment of this application; Figure 14 This is the third timing diagram of a driving method provided in the embodiments of this application; Figure 15 This is the fourth timing diagram of a driving method provided in the embodiments of this application; Figure 16 This is the fifth timing diagram of a driving method provided in the embodiments of this application. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0020] Additionally, it should be noted that when describing the elements and embodiments thereof in this application, the articles “a,” “an,” “the,” and “the” are intended to indicate the presence of one or more elements; unless otherwise stated, “multiple” means two or more; the terms “comprising,” “including,” “containing,” and “having” are intended to be inclusive and indicate that additional elements may exist besides those listed; the terms “first,” “second,” “third,” etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or order of formation.

[0021] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this application based on the specific circumstances.

[0022] Currently, most silicon-based display panels achieve light emission by bonding silicon-based III-V group compounds (such as InGaAs and GaN) to a CMOS backplane. This technology combines III-V group light-emitting materials with silicon-based driving circuits through heterogeneous integration, achieving both high luminous efficiency and high integration density. However, the bonding process is complex and costly. The significant differences in lattice mismatch and thermal expansion coefficients between III-V group compounds and silicon-based CMOS necessitate high-precision bonding techniques (such as hybrid bonding and metal bonding), resulting in high process difficulty, low yield, and consequently, high mass production costs.

[0023] Figure 1 This is one of the structural schematic diagrams of a display panel 10 provided in the embodiments of this application, such as... Figure 1 As shown, the display panel 10 includes a plurality of sub-pixels, each sub-pixel including a light-emitting unit 101 and a pixel circuit 102. The display panel 10 also includes: The silicon-based driving substrate 11 includes multiple substrate patterns 111 and multiple pixel circuits 102; The dielectric layer 12 is located on one side of the silicon-based driving substrate 11 and includes multiple dielectric patterns 121; The first electrode layer 13 is located on the side of the dielectric layer 12 away from the silicon-based driving substrate 11, and includes a plurality of first electrode patterns 131. The second electrode layer 14 is located on the side of the silicon-based driving substrate 11 away from the dielectric layer 12, and includes a plurality of second electrode patterns 141. The light-emitting unit 101 includes a first electrode pattern 131, a dielectric pattern 121, a substrate pattern 111, and a second electrode pattern 141 that overlap each other. The first electrode pattern 131 and the second electrode pattern 141 are electrically connected to the pixel circuit 102 corresponding to the light-emitting unit 101. The light-emitting unit 101 is used to emit light under the reverse bias voltage applied by the pixel circuit 102. The reverse bias voltage is directed from the second electrode pattern 141 to the first electrode pattern 131.

[0024] In some embodiments, multiple sub-pixels of the display panel 10 can emit light of the same color, or the multiple sub-pixels can include red sub-pixels, green sub-pixels, and blue sub-pixels to achieve full-color red, green, and blue display. Each sub-pixel includes a light-emitting unit 101 and a pixel circuit 102, with the pixel circuit 102 electrically connected to the light-emitting unit 101. In this embodiment, the light-emitting unit 101 uses a silicon-based solid-state incandescent light-emitting device.

[0025] like Figure 2 As shown, the silicon-based solid-state incandescent light-emitting device comprises a first electrode pattern 131 (top electrode), a dielectric pattern 121 with a high dielectric constant (K), a substrate pattern 111 (P-type silicon substrate), and a second electrode pattern 141 (bottom electrode). The first electrode pattern 131 is a transparent electrode pattern and can be fabricated using transparent electrode materials such as indium tin oxide (ITO), aluminum-zinc oxide (AZO), or indium-zinc oxide (IZO). The dielectric pattern 121 can be fabricated using materials with a high dielectric constant (K), such as hafnium dioxide (HfO2), hafnium titanium oxide (HfTiO), or hafnium tantalum titanium oxide (HfTaTiO). The second electrode pattern 141 can be fabricated using metallic conductive materials such as molybdenum (Mo) or copper (Cu), or it can employ a Mo / Cu bilayer structure. This is merely an example, and the embodiments in this application are not intended to limit the scope of the application.

[0026] like Figure 2As shown, when a reverse bias voltage (from the bottom electrode to the top electrode) is applied to both ends of a silicon-based solid-state incandescent light-emitting device (SSI-LED), the high dielectric constant (K) dielectric pattern 121 inside undergoes dielectric breakdown, forming a nanometer-sized conductive channel. When current flows through the conductive channel, it excites white light with a spectral range of 350–1000 nanometers (nm). The dielectric breakdown voltage is relatively large, ultimately resulting in a large current (mA level) flowing through the device. Unlike incandescent lamps, which are also thermoluminescent, SSI-LEDs have a dielectric layer 12 protecting the channels formed by dielectric breakdown.

[0027] For example, in the light-emitting unit 101, the first electrode pattern 131 is an ITO electrode pattern 131, the dielectric pattern 121 is an HfO2 dielectric pattern 121, the substrate is a p-type silicon (Si), and the second electrode pattern 141 is a Mo substrate electrode. Holes accumulated in the p-type silicon (Si) substrate are continuously injected into the HfO2 dielectric pattern 121 under the action of the electric field formed by the reverse bias voltage, forming defects in the HfO2 dielectric pattern 121. As the applied bias voltage gradually increases, the defects become more and more dense. When the applied bias voltage reaches a threshold, these defects will interconnect and combine to form a conductive channel that only allows hole carriers to pass through and will not disappear as the applied bias voltage decreases. When current flows through the conductive channel, the light-emitting unit 101 begins to emit light thermally.

[0028] The display panel 10 provided in this embodiment is applied to the field of silicon-based micro-display. Based on the silicon-based solid-state incandescent light-emitting principle, the silicon-based solid-state incandescent light-emitting device is pixelated and driven by a silicon-based driving circuit to achieve pixel grayscale display.

[0029] In some embodiments, the display panel 10 includes a second electrode layer 14, a silicon-based driving substrate 11, a dielectric layer 12, and a first electrode layer 13 stacked sequentially. In this embodiment, for example, the silicon-based driving substrate 11 forms a P-type Si substrate (substrate pattern 111) for the light-emitting unit 101, and multiple sub-pixels are formed by patterning the second electrode layer 14, the dielectric layer 12, and the first electrode layer 13, respectively. Each sub-pixel includes a light-emitting unit 101 and a pixel circuit 102 electrically connected to the light-emitting unit 101. For example, Figure 1 A cross-sectional view along the A-A' direction is shown in the display panel 10, with the ITO electrode pattern 131 and the HfO2 dielectric pattern 121 pixelated.

[0030] The display panel 10 provided in this embodiment adopts a single silicon-based solution and utilizes the thermoluminescence principle of silicon-based solid-state incandescent light-emitting devices. It has a wide emission spectrum range, and its luminous brightness and spectrum are almost unaffected by the external environment. It has high stability and does not require special packaging.

[0031] In some embodiments, such as Figure 1 As shown, the sub-pixel includes a first electrode pattern 131, a dielectric pattern 121, a substrate pattern 111, and a second electrode pattern 141. The first electrode pattern 131, the dielectric pattern 121, the substrate pattern 111, and the second electrode pattern 141 overlap in their orthogonal projections onto the silicon-based driving substrate 11, forming the light-emitting unit 101 of the sub-pixel. Figure 1 The intermediate substrate pattern 111 is the overlapping area of ​​the projection of the first electrode pattern 131 / dielectric pattern 121 and the silicon-based driving substrate 11. The second electrode layer 14 can be a full-surface grid pattern, that is, multiple second electrode patterns 141 are connected as one unit. Figure 1 The second electrode pattern 141 is the overlapping area of ​​the projection of the first electrode pattern 131 / dielectric pattern 121 and the silicon-based driving substrate 11.

[0032] In some embodiments, the first electrode pattern 131 and the second electrode pattern 141 in the light-emitting unit 101 are electrically connected to the pixel circuit 102 corresponding to the light-emitting unit 101, and a reverse bias voltage is applied to the light-emitting unit 101 by the pixel circuit 102, such as... Figure 2 As shown, the reverse bias voltage is directed from the second electrode pattern 141 (bottom electrode) to the first electrode pattern 131 (top electrode). In this way, the dielectric pattern 121 in the light-emitting unit 101 undergoes dielectric breakdown, forming a nanoscale conductive channel. When current passes through the conductive channel, it can excite the light-emitting unit 101 to emit white light.

[0033] In this embodiment, the display panel 10 includes a plurality of sub-pixels, each sub-pixel including a light-emitting unit 101 and a pixel circuit 102. The display panel 10 also includes a silicon-based driving substrate 11, a dielectric layer 12, a first electrode layer 13, and a second electrode layer 14. The silicon-based driving substrate 11 includes a plurality of substrate patterns 111 and a plurality of pixel circuits 102. The dielectric layer 12 is located on one side of the silicon-based driving substrate 11 and includes a plurality of dielectric patterns 121. The first electrode layer 13 is located on the side of the dielectric layer 12 away from the silicon-based driving substrate 11 and includes a plurality of first electrode patterns 131. The second electrode layer 14... The electrode layer 14 is located on the side of the silicon-based driving substrate 11 away from the dielectric layer 12, and includes a plurality of second electrode patterns 141. The light-emitting unit 101 includes overlapping first electrode patterns 131, dielectric patterns 121, substrate patterns 111, and second electrode patterns 141. The first electrode patterns 131 and second electrode patterns 141 are electrically connected to the pixel circuit 102 corresponding to the light-emitting unit 101. The light-emitting unit 101 emits light under a reverse bias voltage applied by the pixel circuit 102, with the reverse bias voltage pointing from the second electrode pattern 141 to the first electrode pattern 131. Since the light-emitting unit 101 utilizes the substrate pattern 111 of the silicon-based driving substrate 11, compared to bonding silicon-based III-V compound nanomaterials to the CMOS backplane, the light-emitting unit 101 in this embodiment is compatible with the fabrication process of the silicon-based driving substrate 11, which can improve production yield and reduce fabrication costs.

[0034] Optionally, the display panel 10 also includes: The protective layer 15 is located on the side of the first electrode layer 13 away from the dielectric layer 12, and includes a plurality of first protective patterns 151 and a plurality of second protective patterns 152. The orthographic projection of the first protective pattern 151 on the silicon-based driving substrate 11 covers the orthographic projection of the light-emitting unit 101 on the silicon-based driving substrate 11. The second protective pattern 152 does not overlap with the orthographic projection of the light-emitting unit 101 on the silicon-based driving substrate 11. A second protective pattern 152 is disposed between two adjacent sub-pixels.

[0035] In some embodiments, such as Figure 3 As shown, a protective layer 15 is deposited on the side of the first electrode layer 13 away from the dielectric layer 12, and the protective layer 15 covers the light-emitting unit 101. Figure 3 In the process, the overlapping area of ​​the projection of the protective layer 15 and the light-emitting unit 101 on the silicon-based driving substrate 11 is the first protective pattern 151, that is, the orthogonal projection of the first protective pattern 151 on the silicon-based driving substrate 11 covers the orthogonal projection of the light-emitting unit 101 on the silicon-based driving substrate 11.

[0036] In some embodiments, such as Figure 3As shown, the protective layer 15 is also used to define pixel regions, that is, a second protective pattern 152 is provided between two adjacent sub-pixels, and the second protective pattern 152 does not overlap with the orthographic projection of the light-emitting unit 101 on the silicon-based driving substrate 11. In this way, the protective layer 15 can prevent short circuits or leakage between the electrodes of adjacent sub-pixels, thus playing a role in electrical isolation. Furthermore, the protective layer 15 can fill the gaps between sub-pixels, serving as a barrier to protect the sidewalls of the dielectric pattern 121 and the first electrode pattern 131.

[0037] Optionally, multiple second electrode patterns 141 are connected as one unit, and the orthographic projections of the second electrode patterns 141 and the pixel circuit 102 on the silicon-based driving substrate 11 do not overlap.

[0038] In some embodiments, the second electrode layer 14 can be fabricated as a single surface, meaning that multiple second electrode patterns 141 are connected as a single unit, allowing the second electrode layer 14 to act as a bottom electrode and provide a constant voltage to the multiple light-emitting units 101. Furthermore, to avoid interference between the second electrode layer 14 and the pixel circuit 102, the second electrode patterns 141 and the orthographic projections of the pixel circuit 102 onto the silicon-based driving substrate 11 do not overlap. For example, as... Figure 4 As shown, the second electrode layer 14 is connected by a grid, and the pixel circuit 102 is located in the gap of the second electrode layer 14. The orthographic projection of the pixel circuit 102 and the second electrode pattern 141 do not overlap.

[0039] In this way, the second electrode layer 14 can be integrally formed, reducing process complexity, thereby reducing manufacturing costs and time. Furthermore, the second electrode layer 14 can provide a constant voltage, avoiding uneven brightness between different light-emitting units 101 due to voltage differences, and improving the display effect of the display panel 10.

[0040] Optionally, the display panel 10 also includes: The color conversion layer 16 is located on the side of the first electrode layer 13 away from the dielectric layer 12, and includes a plurality of color conversion patterns 161. The color conversion patterns 161 overlap with the orthographic projection of the light-emitting unit 101 on the silicon-based driving substrate 11. The color conversion patterns 161 are used to convert the light of the first color emitted by the light-emitting unit 101 into light of the second color. The first color and the second color are different.

[0041] In some embodiments, since the display panel 10 provided in this embodiment is based on the silicon-based solid-state incandescent light-emitting principle, the light-emitting unit 101 emits white light, that is, the first color is white. In order to enable the sub-pixels to emit light of the second color, the display panel 10 also includes a color conversion layer 16, so that the display panel 10 displays a color image.

[0042] like Figure 5As shown, the color conversion layer 16 is pixelated, meaning that the color conversion layer 16 includes multiple color conversion patterns 161, and each sub-pixel includes a color conversion pattern 161. The color conversion pattern 161 overlaps with the orthographic projection of the light-emitting unit 101 onto the silicon-based driving substrate 11, so that the white light emitted by the light-emitting unit 101 is converted into a second color light after passing through the color conversion pattern 161. The second color includes one of red, green, and blue.

[0043] Optionally, the multiple sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel; The first sub-pixel includes a first light-emitting unit 1011 and a first color conversion pattern 1611. The first color conversion pattern 1611 overlaps with the first light-emitting unit 1011 in the orthographic projection on the silicon-based driving substrate 11. The first color conversion pattern 1611 is used to convert the light of the first color emitted by the first light-emitting unit 1011 into red light. The second sub-pixel includes a second light-emitting unit 1012 and a second color conversion pattern 1612. The second color conversion pattern 1612 overlaps with the second light-emitting unit 1012 in the orthographic projection on the silicon-based driving substrate 11. The second color conversion pattern 1612 is used to convert the light of the first color emitted by the second light-emitting unit 1012 into green light. The third sub-pixel includes a third light-emitting unit 1013 and a third color conversion pattern 1613. The third color conversion pattern 1613 overlaps with the third light-emitting unit 1013 in the orthographic projection on the silicon-based driving substrate 11. The third color conversion pattern 1613 is used to convert the light of the first color emitted by the third light-emitting unit 1013 into blue light.

[0044] In some embodiments, the light-emitting unit 101 emits white light, i.e., the first color is white. The display panel 10 includes red sub-pixels (R), green sub-pixels (G), and blue sub-pixels (B), thereby achieving full-color display of the display panel 10 through the color conversion layer 16, wherein the color conversion layer 16 can be an RGB color film.

[0045] like Figure 6 As shown, the first sub-pixel is a red sub-pixel (R). Because the first color conversion pattern 1611 and the first light-emitting unit 1011 overlap in their orthographic projections onto the silicon-based driving substrate 11, the white light emitted by the first light-emitting unit 1011 is converted into red light after passing through the first color conversion pattern 1611. Figure 6 As shown, the second sub-pixel is a green sub-pixel (G). Since the second color conversion pattern 1612 and the second light-emitting unit 1012 overlap in the orthographic projection on the silicon-based driving substrate 11, the white light emitted by the second light-emitting unit 1012 is converted into green light after passing through the second color conversion pattern 1612.

[0046] like Figure 6As shown, the third sub-pixel is a blue sub-pixel (B). Because the third color conversion pattern 1613 overlaps with the orthographic projection of the third light-emitting unit 1013 onto the silicon-based driving substrate 11, the white light emitted by the third light-emitting unit 1013 is converted into green light after passing through the third color conversion pattern 1613. Furthermore, as... Figure 6 As shown, the display panel 10 also includes a black matrix (BM) layer, which can eliminate light crosstalk between different sub-pixels and improve the contrast of the display panel 10.

[0047] In some embodiments, RGB full-color display can also be achieved through grating beam splitting or resonant cavities. Specifically, grating beam splitting refers to integrating subwavelength gratings (SWGs) on the surface of subpixels. SWGs include gratings with different periods / duty cycles, transmitting / reflecting only a single R / G / B band. Resonant cavities utilize the wavelength-selective resonance of an optical resonant cavity, embedding a microcavity structure (two mirrors) in the output path. Only specific wavelengths (R / G / B) satisfy the resonance condition, resulting in constructive interference that enhances the output, while other wavelengths are suppressed. Typically, a high-reflectivity layer is placed at the bottom of the light source, while the top of the light source is semi-transparent and semi-reflective.

[0048] In some embodiments, such as Figure 7 As shown, the process flow of the display panel 10 provided in this embodiment includes: a first step of fabricating a silicon-based driving substrate 11 (including pixel circuit 102); a second step of depositing a dielectric layer 12 and a first electrode layer 13 on one side of the silicon-based driving substrate 11, for example, depositing an HfO2 dielectric layer 12 and an ITO electrode layer 13 by magnetron sputtering, wherein the thickness of the HfO2 dielectric layer 12 is 10-100 nm and the thickness of the ITO electrode layer 13 is 5-50 nm; and a third step of pixelating the dielectric layer 12 and the first electrode layer 13. For example, etching HfO2 dielectric pattern 121 and ITO electrode pattern 131; the fourth step is to deposit a protective layer 15, the material of which is, for example, SiO2; the fifth step is to prepare a second electrode layer 14, for example, by depositing a Mo electrode layer 14 by magnetron sputtering, the thickness of which is 50-200nm; the sixth step is to pixelate the second electrode layer 14, for example, by etching Mo electrode pattern 141; the seventh step is to prepare a color conversion layer 16, for example, by depositing and photolithography of an RGB color film; the eighth step is to prepare a BM (deposition and photolithography).

[0049] Optionally, such as Figure 8 As shown, the pixel circuit 102 includes a first control module 1021, a second control module 1022, a first driving transistor T2, a second driving transistor T11, a third driving transistor T12, and a fourth driving transistor T10. The first driving transistor T2 and the second driving transistor T11 have opposite transistor types, the third driving transistor T12 and the fourth driving transistor T10 have opposite transistor types, the second driving transistor T11 and the third driving transistor T12 have the same transistor type, and the channel width-to-length ratios of the first driving transistor T2, the second driving transistor T11, the third driving transistor T12 and the fourth driving transistor T10 are different from each other. The first terminal of the first driving transistor T2, the first terminal of the second driving transistor T11, the first terminal of the third driving transistor T12, and the first terminal of the fourth driving transistor T10 are respectively electrically connected to the light-emitting unit 101 corresponding to the pixel circuit 102. The input terminal of the first control module 1021 is electrically connected to the first data line Data1, the control terminal is electrically connected to the first control line Gate(n), and the output terminal is electrically connected to the control electrode of the first driving transistor T2 and the control electrode of the second driving transistor T11, respectively. The input terminal of the second control module 1022 is electrically connected to the second data line Data2, the control terminal is electrically connected to the second control line Gate(n), and the output terminal is electrically connected to the control electrode of the third driving transistor T12 and the control electrode of the fourth driving transistor T10, respectively.

[0050] In some embodiments, to achieve high-current driving, the pixel circuit 102 includes four driving current branches, each with a driving transistor. Therefore, the pixel circuit 102 includes a first driving transistor T2, a second driving transistor T11, a third driving transistor T12, and a fourth driving transistor T10, for a total of four driving transistors. Each pair of the four driving transistors is of the same type, consisting of two N-type transistors and two P-type transistors. However, the channel width-to-length ratio (W / L) of the four driving transistors is different, allowing the four current branches to provide different driving currents to the light-emitting unit 101.

[0051] For example, such as Figure 9 As shown, T1 to T10 are PMOS transistors, and T11 and T12 are NMOS transistors. That is, the first driving transistor T2 and the fourth driving transistor T10 are PMOS transistors, and the second driving transistor T11 and the third driving transistor T12 are NMOS transistors. The W / L ratio of the first driving transistor T2 is W0 / L0, the W / L ratio of the second driving transistor T11 is 4×W0 / L0, the W / L ratio of the third driving transistor T12 is 2×W0 / L0, and the W / L ratio of the fourth driving transistor T10 is 8×W0 / L0. Therefore, the magnitude of the driving current in the four driving current branches is mainly determined by the W / L ratios of the first driving transistor T2, the second driving transistor T11, the third driving transistor T12, and the fourth driving transistor T10.

[0052] In some embodiments, such as Figure 8As shown, the control electrode of the first driving transistor T2 and the control electrode of the second driving transistor T11 are both electrically connected to the first control module 1021, and the transistor types of the first driving transistor T2 and the second driving transistor T11 are opposite. Therefore, when the first control module 1021 is turned on under the action of the first control signal of the first control line Gate(n), the first data signal of the first data line Data1 is transmitted to the first driving transistor T2 and the second driving transistor T11, so that one of the first driving transistor T2 and the second driving transistor T11 is turned on, thereby outputting a driving current to the light-emitting unit 101.

[0053] In some embodiments, such as Figure 8 As shown, the control electrodes of the third driving transistor T12 and the fourth driving transistor T10 are both electrically connected to the second control module 1022. The transistor types of the third driving transistor T12 and the fourth driving transistor T10 are opposite. Therefore, when the second control module 1022 is turned on under the action of the second control signal of the second control line Gate(n), the second data signal of the second data line Data2 is transmitted to the third driving transistor T12 and the fourth driving transistor T10, so that one of the third driving transistor T12 and the fourth driving transistor T10 is turned on, thereby outputting a driving current to the light-emitting unit 101.

[0054] For example, such as Figure 9 As shown, the first control module 1021 includes a transistor T1 and a capacitor C1. The control electrode of transistor T1 is the gate and is electrically connected to the first control line Gate(n), the first electrode is the source and is electrically connected to the first data line Data1, and the second electrode is the drain and is electrically connected to the control electrode (gate) of the first driving transistor T2 and the second driving transistor T11. One end of capacitor C1 is electrically connected to transistor T1, and the other end is electrically connected to the Vss power supply terminal.

[0055] like Figure 9 As shown, the second control module 1022 includes transistor T9 and capacitor C2. The control electrode of transistor T9 is the gate and is electrically connected to the second control line Gate(n), the first electrode is the source and is electrically connected to the second data line Data2, and the second electrode is the drain and is electrically connected to the control electrode (gate) of the third driving transistor T12 and the fourth driving transistor T10. One end of capacitor C2 is electrically connected to transistor T9, and the other end is electrically connected to the Vss power supply terminal.

[0056] In this way, by controlling the conduction states of the first driving transistor T2, the second driving transistor T11, the third driving transistor T12 and the fourth driving transistor T10, different driving currents can be output to the light-emitting unit 101 to achieve different grayscale displays.

[0057] In some embodiments, the pixel circuit 102 further includes a third control module 1023, a first light-emitting control transistor T4, a second light-emitting control transistor T6, a third light-emitting control transistor T7, and a fourth light-emitting control transistor T8; the first light-emitting control transistor T4, the second light-emitting control transistor T6, the third light-emitting control transistor T7, and the fourth light-emitting control transistor T8 have the same transistor type; the second terminal of the first driving transistor T2 is electrically connected to the first terminal of the first light-emitting control transistor T4, the second terminal of the second driving transistor T11 is electrically connected to the first terminal of the second light-emitting control transistor T6, the second terminal of the third driving transistor T12 is electrically connected to the first terminal of the third light-emitting control transistor T7, and the second terminal of the fourth driving transistor T10 is electrically connected to the first terminal of the fourth light-emitting control transistor T8; the input terminal of the third control module 1023 is electrically connected to the light-emitting control line EM1(n), the control terminal is electrically connected to the third data line Data3, and the output terminal is electrically connected to the control terminals of the first light-emitting control transistor T4, the second light-emitting control transistor T6, the third light-emitting control transistor T7, and the fourth light-emitting control transistor T8, respectively.

[0058] In some embodiments, such as Figure 9 As shown, each drive current branch includes a drive transistor and a light-emitting control transistor connected in series. Specifically, the second terminal of the first drive transistor T2 is electrically connected to the first terminal of the first light-emitting control transistor T4, and the second terminal of the first light-emitting control transistor T4 is also electrically connected to the Vss power supply terminal, that is, the first drive transistor T2 and the first light-emitting control transistor T4 are connected in series. Similarly, the second drive transistor T11 is connected in series with the second light-emitting control transistor T6, the third drive transistor T12 is connected in series with the third light-emitting control transistor T7, and the fourth drive transistor T10 is connected in series with the fourth light-emitting control transistor T8.

[0059] In some embodiments, the first light-emitting control transistor T4, the second light-emitting control transistor T6, the third light-emitting control transistor T7, and the fourth light-emitting control transistor T8 are of the same transistor type, and the output terminal of the third control module 1023 is electrically connected to the control electrode of the first light-emitting control transistor T4, the control electrode of the second light-emitting control transistor T6, the control electrode of the third light-emitting control transistor T7, and the control electrode of the fourth light-emitting control transistor T8, respectively. That is, all four light-emitting control transistors are controlled by the third control module 1023. For example, as... Figure 9 As shown, the first light-emitting control transistor T4, the second light-emitting control transistor T6, the third light-emitting control transistor T7, and the fourth light-emitting control transistor T8 are all PMOS, meaning that the transistors of the four light-emitting control transistors are of the same type.

[0060] In some embodiments, when the third control module 1023 connects the light-emitting control line EM1(n) to the control electrode of each light-emitting control tube under the control of the third data signal of the third data line Data3, the light-emitting control tubes of the four drive current branches are simultaneously turned on or off under the action of the light-emitting control signal.

[0061] For example, such as Figure 9As shown, the third control module 1023 includes transistor T3, transistor T5, and capacitor C3. The gate of transistor T3 is electrically connected to the drain of transistor T5, the source is electrically connected to the light-emitting control line EM1(n), and the drain is electrically connected to the control electrode (gate) of the four light-emitting control transistors. The gate of transistor T5 is electrically connected to the third control line Gate(n), and the source is electrically connected to the third data line Data3. One end of capacitor C3 is electrically connected to the gate of transistor T3, and the other end is electrically connected to the Vss power supply terminal. Figure 9 In the example, the W / L ratio of transistors T4-T8 is 8×W0 / L0.

[0062] The first data line Data1, the second data line Data2, and the third data line Data3 have two levels: high level and low level. The third data line Data3 controls whether the pixel circuit 102 emits light in the current subframe, and the light-emitting unit 101 is driven to emit light in reverse.

[0063] Optionally, such as Figure 10 As shown, the pixel circuit 102 also includes a third control module 1023, a fourth control module 1024, a first light-emitting control transistor T4, a second light-emitting control transistor T6, a third light-emitting control transistor T7, and a fourth light-emitting control transistor T8; the first light-emitting control transistor T4 and the second light-emitting control transistor T6 have the same transistor type, and the third light-emitting control transistor T7 and the fourth light-emitting control transistor T8 have the same transistor type. The second electrode of the first driving transistor T2 is electrically connected to the first electrode of the first light-emitting control transistor T4; the second electrode of the second driving transistor T11 is electrically connected to the first electrode of the second light-emitting control transistor T6; the second electrode of the third driving transistor T12 is electrically connected to the first electrode of the third light-emitting control transistor T7; and the second electrode of the fourth driving transistor T10 is electrically connected to the first electrode of the fourth light-emitting control transistor T8. The input terminal of the third control module 1023 is electrically connected to the first light-emitting control line EM1(n), the control terminal is electrically connected to the third data line Data3, and the output terminal is electrically connected to the control electrode of the first light-emitting control tube T4 and the control electrode of the second light-emitting control tube T6 respectively. The input terminal of the fourth control module 1024 is electrically connected to the second light-emitting control line EM2(n), the control terminal is electrically connected to the fourth data line Data4, and the output terminal is electrically connected to the control electrode of the third light-emitting control tube T7 and the control electrode of the fourth light-emitting control tube T8, respectively.

[0064] In some embodiments, such as Figure 10As shown, each drive current branch includes a drive transistor and a light-emitting control transistor connected in series. Specifically, the second terminal of the first drive transistor T2 is electrically connected to the first terminal of the first light-emitting control transistor T4, and the second terminal of the first light-emitting control transistor T4 is also electrically connected to the Vss power supply terminal, that is, the first drive transistor T2 and the first light-emitting control transistor T4 are connected in series. Similarly, the second drive transistor T11 is connected in series with the second light-emitting control transistor T6, the third drive transistor T12 is connected in series with the third light-emitting control transistor T7, and the fourth drive transistor T10 is connected in series with the fourth light-emitting control transistor T8.

[0065] In some embodiments, the first light-emitting control transistor T4 and the second light-emitting control transistor T6 are of the same transistor type, and the output terminal of the third control module 1023 is electrically connected to the control electrode of the first light-emitting control transistor T4 and the control electrode of the second light-emitting control transistor T6, respectively. When the third control module 1023, under the control of the third data signal of the third data line Data3, connects the first light-emitting control line EM1(n) with the control electrodes of the first light-emitting control transistor T4 and the second light-emitting control transistor T6, the first light-emitting control transistor T4 and the second light-emitting control transistor T6 are simultaneously turned on or simultaneously turned off under the action of the first light-emitting control signal.

[0066] For example, such as Figure 10 As shown, both the first light-emitting control transistor T4 and the second light-emitting control transistor T6 are PMOS. The third control module 1023 includes transistor T3, transistor T5, and capacitor C3. The gate of transistor T3 is electrically connected to the drain of transistor T5, the source is electrically connected to the first light-emitting control line EM1(n), and the drain is electrically connected to the control electrode (gate) of the first light-emitting control transistor T4 and the second light-emitting control transistor T6. The gate of transistor T5 is electrically connected to the third control line Gate(n), and the source is electrically connected to the third data line Data3. One end of capacitor C3 is electrically connected to the gate of transistor T3, and the other end is electrically connected to the Vss power supply terminal.

[0067] In some embodiments, the third light-emitting control transistor T7 and the fourth light-emitting control transistor T8 are of the same transistor type, and the output terminal of the fourth control module 1024 is electrically connected to the control electrode of the third light-emitting control transistor T7 and the control electrode of the fourth light-emitting control transistor T8, respectively. When the fourth control module 1024, under the control of the fourth data signal of the fourth data line Data4, connects the second light-emitting control line EM2(n) with the control electrodes of the third light-emitting control transistor T7 and the fourth light-emitting control transistor T8, the third light-emitting control transistor T7 and the fourth light-emitting control transistor T8 are simultaneously turned on or simultaneously turned off under the action of the second light-emitting control signal.

[0068] For example, such as Figure 10As shown, both the third light-emitting control transistor T7 and the fourth light-emitting control transistor T8 are PMOS. The fourth control module 1024 includes transistor T13, transistor T14, and capacitor C4. The gate of transistor T13 is electrically connected to the drain of transistor T14, the source is electrically connected to the second light-emitting control line EM2(n), and the drain is electrically connected to the control electrode (gate) of the third light-emitting control transistor T7 and the fourth light-emitting control transistor T8. The gate of transistor T14 is electrically connected to the fourth control line, and the source is electrically connected to the fourth data line Data4. One end of capacitor C4 is electrically connected to the gate of transistor T8, and the other end is electrically connected to the Vss power supply terminal.

[0069] In this embodiment, by setting a third control module 1023 to control the first light-emitting control tube T4 and the second light-emitting control tube T6, and by setting a fourth control module 1024 to control the third light-emitting control tube T7 and the fourth light-emitting control tube T8, the four light-emitting control tubes can be turned on or off at different times, thus making the control method of the pixel circuit 102 more flexible.

[0070] This application embodiment also provides a driving method for a display panel 10, used to drive the display panel 10 of the aforementioned embodiments, such as... Figure 11 As shown, the driving method includes: Step S1: Determine the first voltage value corresponding to each subframe within the current display frame based on the target grayscale value of the current display frame; wherein, the current display frame includes at least one subframe. In step S2, within a subframe, the pixel circuit 102 of the control display panel 10 applies a reverse bias voltage of the first voltage value to the light-emitting unit 101 of the display panel 10, driving the light-emitting unit 101 to emit light.

[0071] In some embodiments, the pixel circuit 102 in the silicon-based driving substrate 11 can be employed as follows: Figure 9 or Figure 10 The pixel circuit 102 shown has three data lines: Data1, Data2, and Data3, each with a high / low voltage level. The different channel width-to-length ratios of the four driving transistors allow the four driving current branches to provide different amounts of driving current to the light-emitting unit 101, thus achieving different grayscale displays. Furthermore, each display frame is divided into multiple subframes. By controlling the driving current branches within each subframe, the driving current magnitude of the current subframe is changed, allowing different display frames to display images with different grayscale levels.

[0072] In some embodiments, the pixel circuit 102 in the silicon-based driving substrate 11 can also use existing pixel circuits such as 7T1C, and different grayscale displays can be achieved by controlling the magnitude of the driving current by writing data voltage to the data line. Furthermore, the display frame can include at least one subframe. When the display frame includes only one subframe, the pixel circuit outputs driving current to the light-emitting unit 101 by writing data voltage to the data line to display the grayscale image of the current display frame. The same principle applies to multiple subframes, which will not be elaborated further here.

[0073] In some embodiments, since the light-emitting unit 101 emits light under the reverse bias voltage applied by the pixel circuit 102, the reverse bias voltage points from the second electrode pattern 141 to the first electrode pattern 131, such as... Figure 9 or Figure 10 As shown, the light-emitting unit 101 is a light-emitting diode (LED). The cathode of the LED is electrically connected to the Vdd power supply terminal, and the anode of the LED is electrically connected to four driving current branches. In this embodiment, the second electrode pattern 141 of the light-emitting unit 101 is the cathode of the LED and is electrically connected to the Vdd power supply terminal to provide a constant voltage, while the first electrode pattern 131 of the light-emitting unit 101 is the anode of the LED.

[0074] Therefore, the first electrode of the driving transistor in the four driving current branches is electrically connected to the first electrode pattern 131 of the light-emitting unit 101. In this way, the light-emitting unit 101 receives the reverse bias voltage from the Vdd power supply terminal to the driving transistor, that is, the reverse bias voltage from the second electrode pattern 141 to the first electrode pattern 131.

[0075] In some embodiments, a first voltage value corresponding to each subframe within the current display frame is determined based on the target grayscale value of the current display frame. If the display frame includes only one subframe, the first voltage value is the data voltage corresponding to the current display frame. By writing the data voltage of the first voltage value to the pixel circuit 102, such as 7T1C, the pixel circuit 102 applies a reverse bias voltage of the first voltage value to the light-emitting unit 101, causing a conductive channel to be formed inside the light-emitting unit 101 and emitting white light.

[0076] In some embodiments, if the current display frame includes multiple sub-frames, the pixel circuit 102, as follows: Figure 9 or Figure 10 As shown, then first according to Figure 9 or Figure 10The resistance value of the driving current branch is determined to determine the current value that each driving current branch can provide, thereby obtaining the magnitude of the reverse bias voltage that each driving current branch can apply to the light-emitting unit 101. The total reverse bias voltage of the current display frame is determined based on the target grayscale value of the current display frame. Then, the magnitude of the reverse bias voltage (first voltage value) required for each sub-frame and the driving current branch that needs to be activated within each sub-frame are determined based on the number of sub-frames included in the current display frame. Finally, by controlling the activation of the corresponding driving current branch in the pixel circuit 102 within each sub-frame, a reverse bias voltage of the first voltage value corresponding to the current sub-frame is applied to the light-emitting unit 101, driving the light-emitting unit 101 to emit light.

[0077] In this embodiment of the application, by controlling the pixel circuit 102 of the display panel 10 to apply a reverse bias voltage of the first voltage value to the light-emitting unit 101 within the sub-frame of the current display frame, the light-emitting unit 101 is driven to emit light, so that the light-emitting unit 101 can display an image of the target grayscale value, thereby enabling the display panel 10 to achieve pixel grayscale display.

[0078] Optionally, the currently displayed frame includes multiple subframes; step S2 includes the following sub-steps: In sub-step A1, within the sub-frame, a first control signal is sent to the first control line Gate(n) of the pixel circuit 102 according to the first voltage value, a first data signal is sent to the first data line Data1 to control the first driving transistor T2 or the second driving transistor T11 to turn on, a second control signal is sent to the second control line Gate(n) of the pixel circuit 102, and a second data line signal is sent to the second data line Data2 to control the third driving transistor T12 or the fourth driving transistor T10 to turn on, and to provide the driving current corresponding to the first voltage value to the light-emitting unit 101.

[0079] In some embodiments, such as Figure 9 As shown, the first driving transistor T2 and the fourth driving transistor T10 are PMOS, and the second driving transistor T11 and the third driving transistor T12 are NMOS. The transistor types of the first driving transistor T2 and the second driving transistor T11 are opposite. In each subframe, the first control module 1021 controls one of the first driving transistor T2 and the second driving transistor T11 to turn on. The transistor types of the third driving transistor T12 and the fourth driving transistor T10 are also opposite. In each subframe, the second control module 1022 controls one of the third driving transistor T12 and the fourth driving transistor T10 to turn on.

[0080] Within each subframe, the on / off states of the four drive current branches can be categorized into four states. Specifically, such as... Figure 12 As shown, each subframe includes three phases: t1, t2, and t3. In phase t1, Gate(n) is high. Figure 9Transistors T1, T9, and T5 are all off. During stage t2, the Gate(n) signal of the first control line Gate(n), the second control line Gate(n), and the third control line Gate(n) becomes low, and transistors T1, T9, and T5 are all turned on. The high level of the first data line Data1 is written to the gates of the first driving transistor T2 and the second driving transistor T11 and charges capacitor C1. The low level of the second data line Data2 is written to the gates of the third driving transistor T12 and the fourth driving transistor T10 and charges capacitor C2. The low level of the third data line Data3 is written to the gate of transistor T3 and charges capacitor C3. During stage t3, the EM1(n) signal of the light-emitting control line EM1(n) becomes low, causing the four light-emitting control transistors to turn on. Then, in the four driving current branches, the branch containing the second driving transistor T11 and the fourth driving transistor T10 is turned on, providing the driving current corresponding to the first voltage value to the light-emitting unit 101.

[0081] like Figure 13 As shown, Gate(n) is high during stage t1. Figure 9 Transistors T1, T9, and T5 are all off. During stage t2, the Gate(n) signal of the first control line Gate(n), the second control line Gate(n), and the third control line Gate(n) becomes low, and transistors T1, T9, and T5 are all turned on. The low level of the first data line Data1 is written to the gates of the first driving transistor T2 and the second driving transistor T11 and charges capacitor C1. The low level of the second data line Data2 is written to the gates of the third driving transistor T12 and the fourth driving transistor T10 and charges capacitor C2. The low level of the third data line Data3 is written to the gate of transistor T3 and charges capacitor C3. During stage t3, the EM1(n) signal of the light-emitting control line EM1(n) becomes low, causing the four light-emitting control transistors to turn on. Then, in the four driving current branches, the branch containing the first driving transistor T2 and the fourth driving transistor T10 is turned on, providing the driving current corresponding to the first voltage value to the light-emitting unit 101.

[0082] like Figure 14 As shown, Gate(n) is high during stage t1. Figure 9Transistors T1, T9, and T5 are all off. During stage t2, the Gate(n) signal of the first control line Gate(n), the second control line Gate(n), and the third control line Gate(n) becomes low, and transistors T1, T9, and T5 are all turned on. The high level of the first data line Data1 is written to the gates of the first driving transistor T2 and the second driving transistor T11 and charges capacitor C1. The high level of the second data line Data2 is written to the gates of the third driving transistor T12 and the fourth driving transistor T10 and charges capacitor C2. The low level of the third data line Data3 is written to the gate of transistor T3 and charges capacitor C3. During stage t3, the EM1(n) signal of the light-emitting control line EM1(n) becomes low, causing the four light-emitting control transistors to turn on. Then, in the four driving current branches, the branch containing the second driving transistor T11 and the third driving transistor T12 is turned on, providing the driving current corresponding to the first voltage value to the light-emitting unit 101.

[0083] like Figure 15 As shown, Gate(n) is high during stage t1. Figure 9 Transistors T1, T9, and T5 are all off. During stage t2, the Gate(n) signal of the first control line Gate(n), the second control line Gate(n), and the third control line Gate(n) becomes low, and transistors T1, T9, and T5 are all turned on. The low level of the first data line Data1 is written to the gates of the first driving transistor T2 and the second driving transistor T11 and charges capacitor C1. The high level of the second data line Data2 is written to the gates of the third driving transistor T12 and the fourth driving transistor T10 and charges capacitor C2. The low level of the third data line Data3 is written to the gate of transistor T3 and charges capacitor C3. During stage t3, the EM1(n) signal of the light-emitting control line EM1(n) becomes low, causing the four light-emitting control transistors to turn on. Then, in the four driving current branches, the branch containing the first driving transistor T2 and the third driving transistor T12 is turned on, providing the driving current corresponding to the first voltage value to the light-emitting unit 101.

[0084] Therefore, each subframe driver has 4 states. If the current display frame includes 3 subframes, the current display frame can achieve 4×4×4+1=65 gray levels. The calculation method is 4 states × 3 subframes + 0 gray levels = 65 gray levels. Furthermore, increasing the number of subframes can achieve more gray level displays.

[0085] Optionally, the driving method also includes: In sub-step A2, within a subframe, a first light emission control signal is sent to the first light emission control line EM1(n) of the pixel circuit 102, a third data signal is sent to the third data line Data3 of the pixel circuit 102, controlling the first light emission control transistor T4 and the second light emission control transistor T6 to turn on, a second light emission control signal is sent to the second light emission control line EM2(n) of the pixel circuit 102, and a fourth data signal is sent to the fourth data line Data4 of the pixel circuit 102, controlling the third light emission control transistor T7 and the fourth light emission control transistor T8 to turn on; wherein, the effective level duration of the first light emission control signal and the second light emission control signal is different.

[0086] In some embodiments, such as Figure 10 As shown, both the first light-emitting control transistor T4 and the second light-emitting control transistor T6 are PMOS transistors, and the third control module 1023 controls the first light-emitting control transistor T4 and the second light-emitting control transistor T6 to be turned on or off simultaneously. Figure 10 As shown, the third light-emitting control transistor T7 and the fourth light-emitting control transistor T8 are both PMOS transistors, and the fourth control module 1024 controls the third light-emitting control transistor T7 and the fourth light-emitting control transistor T8 to be turned on or off at the same time.

[0087] In some embodiments, Figure 10 In the pixel circuit 102, the effective levels of both the first light-emitting control signal EM1(n) and the second light-emitting control signal EM2(n) are low. For example... Figure 16 As shown, during the t3 phase of the first subframe (Sub-frame1) and the second subframe (Sub-frame2), the low-level duration of the first light-emitting control line EM1(n) is greater than the low-level duration of the second light-emitting control signal EM2(n).

[0088] Within each subframe, there are four states: only the first light-emitting control transistor T4 is turned on, only the second light-emitting control transistor T6 is turned on, both the first and second light-emitting control transistors T4 are turned on, or neither is turned on. The four states of the driving transistors multiplied by the four states of the light-emitting control transistors constitute the display state of one subframe. For two subframes, the display states are 4×4×4×4, which can achieve 4×4×4×4=256 grayscale levels, enabling the display of more grayscale levels.

[0089] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0090] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0091] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A display panel, characterized in that, The display panel includes multiple sub-pixels, each sub-pixel comprising a light-emitting unit and a pixel circuit. The display panel also includes: A silicon-based driving substrate, comprising multiple substrate patterns and multiple pixel circuits; A dielectric layer, located on one side of the silicon-based driving substrate, includes multiple dielectric patterns; The first electrode layer is located on the side of the dielectric layer away from the silicon-based driving substrate and includes a plurality of first electrode patterns; The second electrode layer, located on the side of the silicon-based driving substrate away from the dielectric layer, includes a plurality of second electrode patterns; wherein, the light-emitting unit includes overlapping first electrode patterns, dielectric patterns, substrate patterns and second electrode patterns, the first electrode patterns and the second electrode patterns are respectively electrically connected to the pixel circuits corresponding to the light-emitting unit, and the light-emitting unit is used to emit light under the reverse bias voltage applied by the pixel circuit, the reverse bias voltage being directed from the second electrode pattern to the first electrode pattern.

2. The display panel according to claim 1, characterized in that, The display panel also includes: A protective layer is located on the side of the first electrode layer away from the dielectric layer, and includes a plurality of first protective patterns and a plurality of second protective patterns. The first protective patterns are projected onto the silicon-based driving substrate and cover the projected image of the light-emitting unit onto the silicon-based driving substrate. The second protective patterns do not overlap with the projected image of the light-emitting unit onto the silicon-based driving substrate, and the second protective patterns are disposed between two adjacent sub-pixels.

3. The display panel according to claim 1, characterized in that, The plurality of second electrode patterns are connected as one unit, and the orthographic projections of the second electrode patterns and the pixel circuits on the silicon-based driving substrate do not overlap.

4. The display panel according to claim 1, characterized in that, The display panel also includes: A color conversion layer is located on the side of the first electrode layer away from the dielectric layer, and includes multiple color conversion patterns. The color conversion patterns overlap with the orthographic projection of the light-emitting unit on the silicon-based driving substrate. The color conversion patterns are used to convert light of a first color emitted by the light-emitting unit into light of a second color, wherein the first color and the second color are different.

5. The display panel according to claim 4, characterized in that, The plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel; The first sub-pixel includes a first light-emitting unit and a first color conversion pattern. The first color conversion pattern overlaps with the orthographic projection of the first light-emitting unit onto the silicon-based driving substrate. The first color conversion pattern is used to convert the light of the first color emitted by the first light-emitting unit into red light. The second sub-pixel includes a second light-emitting unit and a second color conversion pattern. The second color conversion pattern overlaps with the orthographic projection of the second light-emitting unit onto the silicon-based driving substrate. The second color conversion pattern is used to convert the light of the first color emitted by the second light-emitting unit into green light. The third sub-pixel includes a third light-emitting unit and a third color conversion pattern. The third color conversion pattern overlaps with the orthographic projection of the third light-emitting unit onto the silicon-based driving substrate. The third color conversion pattern is used to convert the light of the first color emitted by the third light-emitting unit into blue light.

6. The display panel according to any one of claims 1-5, characterized in that, The pixel circuit includes a first control module, a second control module, a first driving transistor, a second driving transistor, a third driving transistor, and a fourth driving transistor; The first driving transistor and the second driving transistor have opposite transistor types, the third driving transistor and the fourth driving transistor have opposite transistor types, the second driving transistor and the third driving transistor have the same transistor type, and the channel width-to-length ratios of the first driving transistor, the second driving transistor, the third driving transistor and the fourth driving transistor are different from each other. The first terminal of the first driving transistor, the first terminal of the second driving transistor, the first terminal of the third driving transistor, and the first terminal of the fourth driving transistor are respectively electrically connected to the light-emitting unit corresponding to the pixel circuit; The input terminal of the first control module is electrically connected to the first data line, the control terminal is electrically connected to the first control line, and the output terminal is electrically connected to the control electrode of the first driving transistor and the control electrode of the second driving transistor, respectively. The input terminal of the second control module is electrically connected to the second data line, the control terminal is electrically connected to the second control line, and the output terminal is electrically connected to the control electrode of the third driving transistor and the control electrode of the fourth driving transistor, respectively.

7. The display panel according to claim 6, characterized in that, The pixel circuit further includes a third control module, a fourth control module, a first light-emitting control transistor, a second light-emitting control transistor, a third light-emitting control transistor, and a fourth light-emitting control transistor; the first light-emitting control transistor and the second light-emitting control transistor have the same transistor type, and the third light-emitting control transistor and the fourth light-emitting control transistor have the same transistor type. The second terminal of the first driving transistor is electrically connected to the first terminal of the first light-emitting control transistor, the second terminal of the second driving transistor is electrically connected to the first terminal of the second light-emitting control transistor, the second terminal of the third driving transistor is electrically connected to the first terminal of the third light-emitting control transistor, and the second terminal of the fourth driving transistor is electrically connected to the first terminal of the fourth light-emitting control transistor. The input terminal of the third control module is electrically connected to the first light-emitting control line, the control terminal is electrically connected to the third data line, and the output terminal is electrically connected to the control electrode of the first light-emitting control tube and the control electrode of the second light-emitting control tube, respectively. The input terminal of the fourth control module is electrically connected to the second light-emitting control line, the control terminal is electrically connected to the fourth data line, and the output terminal is electrically connected to the control electrode of the third light-emitting control tube and the control electrode of the fourth light-emitting control tube, respectively.

8. A driving method for a display panel, characterized in that, The driving method for driving a display panel as described in any one of claims 1-7 includes: Based on the target grayscale value of the current display frame, a first voltage value corresponding to each subframe within the current display frame is determined; wherein, the current display frame includes at least one subframe; Within the subframe, the pixel circuit controlling the display panel applies a reverse bias voltage of the first voltage value to the light-emitting unit of the display panel, driving the light-emitting unit to emit light.

9. The driving method according to claim 8, characterized in that, The current display frame includes multiple sub-frames; within each sub-frame, controlling the pixel circuit of the display panel to apply a reverse bias voltage of the first voltage value to the light-emitting unit, driving the light-emitting unit of the display panel to emit light, includes: Within the subframe, a first control signal is sent to the first control line of the pixel circuit according to the first voltage value, a first data signal is sent to the first data line to control the first driving transistor or the second driving transistor to turn on, a second control signal is sent to the second control line of the pixel circuit, and a second data signal is sent to the second data line to control the third driving transistor or the fourth driving transistor to turn on, thereby providing the light-emitting unit with a driving current corresponding to the first voltage value.

10. The driving method according to claim 9, characterized in that, The driving method further includes: Within the subframe, a first light emission control signal is sent to the first light emission control line of the pixel circuit, a third data signal is sent to the third data line of the pixel circuit to control the first and second light emission control transistors to turn on, a second light emission control signal is sent to the second light emission control line of the pixel circuit, and a fourth data signal is sent to the fourth data line of the pixel circuit to control the third and fourth light emission control transistors to turn on; wherein the effective level durations of the first and second light emission control signals are different.

Images