A non-ip all-optical fiber architecture-based zero-delay KVM seat collaboration system and method

Abstract

The application relates to the technical field of KVM seat cooperation and video data transmission, and discloses a zero-delay KVM seat cooperation system and method based on a non-IP all-optical fiber architecture, which comprises a host end, a central switching node and a seat end connected by optical fibers. The host end performs non-uniform compression on baseband video according to peripheral operation states, intercepts redundant characters during a baseband signal blanking period when a storage water level reaches an alarm line, and fills compression loads to physical time slots for issuing; the central switching node adopts a physical layer matrix switching mode, performs level stage mapping and transparent transmission on photoelectric signals without two-layer analysis; the seat end performs demultiplexing and video reconstruction, and adjusts the frequency of a voltage-controlled oscillator by using local line buffer water level feedback to realize clock synchronization. The application eliminates whole-frame network cache delay by using bottom blanking time slot backflow, dynamically balances link bandwidth, and guarantees accurate synchronous output of a video clock without protocol stack analysis.

Description

Technical Field

[0001] This invention relates to the field of KVM seat collaboration and video data transmission technology, specifically to a zero-latency KVM seat collaboration system and method based on a non-IP all-fiber architecture. Background Technology

[0002] KVM-based collaborative systems are primarily used in command centers and data centers to enable centralized cross-screen operation and signal scheduling across multiple hosts. Conventional KVM systems are typically built on an IP network architecture. Video signals and peripheral control commands from the host end must be encapsulated through the TCP / IP protocol stack, then routed and forwarded to the receiving end via network switching. This IP-based transmission mechanism involves data packet assembly, and to cope with network jitter, the receiving end usually needs to be configured with full-frame image buffering. These mechanisms inherently result in end-to-end transmission processing time, leading to noticeable image and operational delays in applications requiring high-frequency interactive operations.

[0003] To address latency issues arising from IP network transmission, KVM systems employing non-IP fiber optic transmission architectures have emerged in the industry. This architecture eliminates the network and transport layer protocol stacks, directly transmitting data at the underlying link level. However, in practical applications, as the video resolution of access devices increases, non-IP architectures face technical limitations in the transmission scheduling of the underlying physical links. Existing non-IP architectures often use static channel allocation methods to transmit video and control data. When high-resolution video streams and high-frequency peripheral operation data are generated simultaneously in large quantities, fixed transmission time slots are difficult to adapt to dynamically changing service data volumes. Due to the lack of coordinated and dynamic allocation capabilities for idle time slots at the physical layer, the system is prone to underlying link congestion and hardware buffer queue overflow when handling high-load data streams.

[0004] Meanwhile, because the standard IP network protocol stack is removed, non-IP architecture systems cannot rely on conventional network time protocols to synchronize the clocks of the transmitting and receiving devices. During prolonged baseband data pass-through, clock frequency drift occurs between the transmitting and receiving ends due to the physical characteristics of the crystal oscillators in the hardware devices. Without an underlying clock closed-loop adjustment mechanism, this frequency drift error gradually accumulates, causing deviations in the video reconstruction timing at the receiving end, which in turn leads to synchronization issues during image output at the display end, affecting the stability of the system's continuous operation. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a zero-latency KVM workstation collaboration system and method based on a non-IP all-fiber architecture. This solves the problem that conventional IP-based KVM (keyboard, video, mouse) systems, when processing high-resolution video and peripheral operation data, are limited by the packet encapsulation process of the TCP / IP protocol stack, multi-level routing table lookup of switching nodes, and whole-frame caching mechanisms, resulting in increased end-to-end transmission latency. While existing non-IP fiber KVM architectures reduce network layer latency, this invention also addresses the issue of latency.

[0006] To address the above problems, the present invention provides the following technical solution: The first aspect of this invention provides a zero-latency KVM agent collaboration system based on a non-IP all-fiber architecture, comprising: The host node is used to acquire the baseband video pixel stream of the video source and collect the operation data of the peripheral devices to generate ownership Boolean flag bits and discrete state flag codes; based on the ownership Boolean flag bits and discrete state flag codes, it performs non-uniform quantization and chroma physical folding on the baseband video pixel stream to generate compressed video payload and store it in the on-chip memory; it monitors the current water level value of the on-chip memory, and when the current water level value reaches the set hardware warning line, it intercepts the regular blanking synchronization character during the blanking period of the baseband signal of the video interface, inserts a custom data delimiter into the physical link, extracts the compressed video payload accumulated in the on-chip memory and fills it into the blanking period physical slot for distribution, generating a multiplexed data link layer frame sequence; The central switching node is connected to the host node via a physical link and operates in physical layer port matrix switching mode. It is used to directly map and transmit photoelectric signals containing multiplexed data link layer frame sequences from the input port to the target output port. The workstation node is connected to the central switching node via a physical link. It is used to receive the photoelectric signals transmitted by the central switching node, extract control messages and compressed video payloads through demultiplexing, perform inverse quantization and chroma upsampling on the compressed video payloads, and realize clock synchronization by combining the water level feedback mechanism of the local row buffer storage area, reconstruct the baseband video signal and output it to the display device.

[0007] In a preferred embodiment of the present invention, when the host node performs non-uniform quantization and chroma physical folding on the baseband video pixel stream based on the ownership Boolean flag and the discrete state flag, it specifically performs the following: when the ownership Boolean flag indicates that the current video pixel is located in the focal region, it allocates a minimum quantization step size to the current video pixel and maintains the full-sample chroma array structure at the source end; when the ownership Boolean flag indicates that the current video pixel is located in the non-focal region and the discrete state flag indicates that the peripheral is in a high-frequency displacement burst state, it adjusts the quantization step size of the luminance component of the current video pixel and converts the full-sample chroma array structure into a sub-sample array; wherein, when converting to a sub-sample array, adjacent pixel pairs or four neighboring pixel blocks are used as boundary units, the independent luminance component values ​​of each pixel are retained, and an arithmetic average operation is performed on the original chroma component values ​​to generate a shared chroma value and allocate it to the corresponding pixel.

[0008] In a preferred embodiment of the present invention, when the host node monitors the current water level value of the on-chip memory, and the current water level value reaches the set hardware warning line, the host node intercepts the regular blanking synchronization character during the blanking period of the video interface baseband signal. Specifically, the host node configures the on-chip memory as a circular buffer driven by the video compression pipeline clock for writing and driven by the transmission link clock for reading, and uses Gray code conversion logic to extract cross-clock domain synchronization of the read and write pointers; calculates the address difference between the synchronized write address pointer and the read address pointer, and performs a backtracking compensation calculation in combination with the preset total physical address depth value of the on-chip memory when the write action loops back, and extracts the real address difference as the current water level value; when the current water level value is greater than or equal to the hardware warning line, the host node extracts the core line and field synchronization pulse characters in the blanking interval in the physical coding control sublayer for transparent transmission, and at the same time blocks the transmission of redundant padding characters in the blanking interval to free up physical transmission time slots.

[0009] In a preferred embodiment of the present invention, when the host node inserts a custom data delimiter into the physical link, extracts the compressed video payload accumulated in the on-chip memory, and fills it into the physical slots of the blanking cycle for transmission, the specific steps are as follows: A custom data delimiter is generated by selecting a combination of control characters not occupied by the video interface standard at the physical coding layer, and sent to the physical link immediately following the core line and field synchronization pulse characters, instructing the communication protocol layer to switch to out-of-band data backflow mode; the number of remaining physical transmission slots in the current blanking cycle is calculated, and when it is confirmed that the number of remaining physical transmission slots is greater than a preset minimum slot threshold, the compressed video payload is extracted from the on-chip memory; character escaping processing is performed on the extracted compressed video payload at the physical coding sub-layer to prevent the data bit sequence from overlapping with the control delimiter of the physical link, and the escaped data is filled into the idle physical transmission slots for transmission; when the number of remaining physical transmission slots reaches a set critical buffer value, or the current water level value falls back to a preset safety line, the extraction operation is interrupted and a backflow end delimiter is inserted into the physical link.

[0010] In a preferred embodiment of the present invention, when the central switching node directly maps and transmits the photoelectric signal containing the multiplexed data link layer frame sequence from the input port to the target output port, it specifically performs the following: without extracting the media access control layer frame header of the data frame for Layer 2 lookup routing, and without performing content parsing and verification on the internal compressed video payload; based on the static port mapping table issued by the internal management control module, it directly maps and switches the received baseband electrical signal containing the multiplexed data link layer frame sequence to the target output port by means of physical replication at the level level using the internal hardware connection matrix.

[0011] In a preferred embodiment of the present invention, when the agent node extracts control messages and compressed video payloads through demultiplexing, it specifically performs the following: performs delimiter matching on the input serial bit stream through the internal low-level hardware state machine; when a custom data delimiter is detected, it switches to out-of-band data backflow mode and performs character inversion processing at the physical coding sub-layer to restore the multiplexed data link layer frame sequence; when the low-level hardware state machine detects a valid video start character or line synchronization character of the standard video timing in the out-of-band data backflow mode, it triggers the fault-tolerant reset logic to reset to the normal video timing reception state; extracts the payload type identifier field inside the data link layer frame, routes and separates the control message to the peripheral device control bus, and truncates the media access control layer frame header and alignment padding characters to extract the clean compressed video payload.

[0012] In a preferred embodiment of the present invention, when the workstation performs inverse quantization and chroma upsampling on the compressed video payload, it specifically performs the following: extracts the quantization parameter increment syntax element from the compressed video payload, calculates the local quantization step size actually applied to the current processed pixel block by combining the global basic quantization parameters; performs inverse scaling on the frequency domain coefficients using the local quantization step size, and restores the pixel component values ​​in the spatial domain through inverse transformation; when it is detected that the chroma format of the current pixel block is a subsampled array, it performs direct copying by reading the chroma component values ​​of the currently known pixels, or uses the arithmetic mean of the chroma component values ​​of adjacent known pixels as the interpolation of the missing pixels in the middle, and inversely restores to the full sampled chroma array.

[0013] In a preferred embodiment of the present invention, when the workstation reconstructs the baseband video signal and outputs it to the display device, it is specifically used to: read the extended display identifier data in the display device through the display data channel; parse the extended display identifier data to obtain the front shoulder time, back shoulder time and sync pulse width parameters physically supported by the display device; and, based on the core line and field sync pulse characters that are transparently retained in the receiving link, and the parsed front shoulder time, back shoulder time and sync pulse width parameters, insert blanking sync levels of corresponding length between the restored effective video lines and between fields to construct a standard video timing framework.

[0014] In a preferred embodiment of the present invention, when the workstation node achieves clock synchronization by combining the water level feedback mechanism of the local row buffer storage area, it is specifically used to: write the burst compressed video payload transmitted by backflow into the local row buffer storage area constructed by the static random access memory array; monitor the current read / write pointer water level of the local row buffer storage area, and when the water level is continuously higher than the upper limit of the preset water level threshold range, the water level feedback loop outputs a control voltage to increase the output frequency of the local voltage-controlled oscillator; when the water level is continuously lower than the lower limit of the preset water level threshold range, the water level feedback loop outputs a reverse control voltage to decrease the output frequency of the local voltage-controlled oscillator; and use the adjusted local voltage-controlled oscillator to drive the local crystal oscillator to generate the basic pixel clock, thereby completing the clock synchronization between the source and receiver.

[0015] A second aspect of this invention provides a zero-latency KVM agent collaboration method based on a non-IP all-fiber architecture, applicable to a system including host nodes, a central switching node, and agent nodes. The method includes: The host node acquires the baseband video pixel stream of the video source and collects the operation data of the peripheral devices to generate ownership Boolean flag bits and discrete state flag codes; Based on the ownership Boolean flag and discrete state flag, the host node performs non-uniform quantization and chroma physical folding on the baseband video pixel stream to generate a compressed video payload and store it in the on-chip memory. The host node monitors the current water level value of the on-chip memory. When the current water level value reaches the set hardware warning line, it intercepts the regular blanking synchronization character during the blanking period of the video interface baseband signal, inserts a custom data delimiter into the physical link, extracts the compressed video payload accumulated in the on-chip memory and fills it into the blanking period physical slot for distribution, generating a multiplexed data link layer frame sequence. The central switching node operates in physical layer port matrix switching mode, directly mapping and transmitting the photoelectric signal containing the multiplexed data link layer frame sequence from the input port to the target output port; The workstation receives the photoelectric signal transmitted through the central switching node, extracts the control message and compressed video payload through demultiplexing, performs inverse quantization and chroma upsampling on the compressed video payload, and achieves clock synchronization by combining the water level feedback mechanism of the local row buffer storage area, reconstructs the baseband video signal and outputs it to the display device.

[0016] This invention provides a zero-latency KVM agent collaboration system and method based on a non-IP all-fiber architecture. It offers the following advantages: 1. This invention monitors the on-chip memory level of the host computer, intercepts regular synchronization characters during the blanking period of the video baseband signal, and fills the compressed video payload into the empty physical blanking slots for transmission. This mechanism achieves time-slot multiplexing of video stream and peripheral data at the physical coding layer, eliminating the need for the system to perform packet encapsulation at the network layer and to drive the underlying transmission pipeline without waiting for a complete image frame buffer, thus reducing end-to-end data transmission latency.

[0017] 2. This invention generates identifier bits based on peripheral operation data and performs non-uniform quantization and chroma physical folding on the baseband video pixel stream. The system distinguishes between focused and non-focused regions according to the operation state, and increases the luminance quantization step size and converts the non-focused regions into chroma sub-sampling arrays when high-frequency interactive operations occur. This design dynamically adjusts the compression ratio of the video stream in conjunction with the interactive state, preventing transmission channel blockage caused by sudden high data volumes under a fixed underlying physical link bandwidth.

[0018] 3. The present invention utilizes a water level feedback mechanism in the local row buffer storage area at the workstation end. By monitoring the water level offset of the buffer queue read / write pointer, it outputs a control voltage to fine-tune the frequency of the local voltage-controlled oscillator. This mechanism achieves clock frequency synchronization between the source and receiver ends at the hardware level in a non-IP architecture that does not rely on standard network time protocols, compensates for the physical frequency offset of the crystal oscillator, and avoids buffer overflow or read-out problems caused by clock drift. Attached Figure Description

[0019] Figure 1 This is an architectural block diagram of a zero-latency KVM collaborative system according to an embodiment of the present invention; Figure 2This is a flowchart illustrating the workflow of a zero-latency KVM collaboration method according to an embodiment of the present invention. Figure 3 This is a flowchart illustrating the physical layer continuous synchronization and direct optical path establishment according to an embodiment of the present invention. Figure 4 This is a schematic diagram illustrating the peripheral interrupt extraction and vector calculation principle of one embodiment of the present invention; Figure 5 This is a schematic diagram illustrating the principle of interactive state dimensionality reduction mapping and feedforward encapsulation according to an embodiment of the present invention; Figure 6 A schematic diagram illustrating the principle of defining the scope of ownership for feedforward parameter analysis and processing according to an embodiment of the present invention; Figure 7 This is a schematic diagram illustrating the principle of non-uniform quantization and chromaticity physical folding mechanism according to an embodiment of the present invention. Figure 8 This is a schematic diagram illustrating the principle of on-chip cache level monitoring and blanking timing interception according to an embodiment of the present invention; Figure 9 This is a schematic diagram illustrating the principle of blanking zone out-of-band delimitation and data backflow drainage according to an embodiment of the present invention; Figure 10 This is a schematic diagram illustrating the principle of optoelectronic fully interconnected transparent transmission and service payload separation according to an embodiment of the present invention; Figure 11 This is a schematic diagram of adaptive reverse recovery and baseband timing reconstruction according to an embodiment of the present invention.

[0020] The components are as follows: 10. Host node; 11. Video acquisition module; 12. Parameter parsing module; 13. On-chip memory; 131. Raw video line buffer; 132. Compressed bitstream buffer; 14. Video compression module; 15. Frame blocking module; 16. First optoelectronic transceiver module; 17. Peripheral simulation module; 18. Display interface simulation logic; 20. Seat node; 21. Second optoelectronic transceiver module; 22. Demultiplexing module; 23. Peripheral interrupt module; 24. Video decoding module; 25. Video output interface; 30. Optical switching matrix; 31. Crossbar switch array; 32. Management and control module. Detailed Implementation

[0021] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] See attached document Figure 1 , Figure 1This is an architectural block diagram of a zero-latency KVM collaboration system according to an embodiment of the present invention. The present invention provides a zero-latency KVM collaboration system that may include: a host node 10, a workstation node 20, and an optical switching matrix 30.

[0023] The host node 10 is deployed on the computer side and is used to acquire source video signals and process reverse control logic. The host node 10 includes a video acquisition module 11, a parameter parsing module 12, an on-chip memory 13, a video compression module 14, a frame sealing module 15, a first optoelectronic transceiver module 16, a peripheral simulation module 17, and a display interface simulation logic 18.

[0024] The display interface emulation logic 18 connects to the display data channel of the video output interface of the external computer, and is used to provide the external computer with extended display identification data of the terminal display device. The display interface emulation logic 18 receives the extended display identification data returned by the agent node 20, and caches it as display capability information that can be read by the external computer, so that the external computer outputs video signals according to the resolution, refresh rate and synchronization timing supported by the agent terminal display device.

[0025] The peripheral simulation module 17 is physically connected to the peripheral interface of the external computer. It generates input reports conforming to the human-machine interface device protocol based on the reverse control frames parsed by the parameter parsing module 12, and feeds back keyboard, mouse, scroll wheel, or other peripheral interaction data to the external computer. The peripheral simulation module 17 includes device-side controller logic, report generation logic, and interrupt upload logic. The device-side controller logic enumerates keyboard, mouse, or composite human-machine interface devices on the external computer side. The report generation logic generates input reports based on key values, button states, scroll wheel increments, relative displacements, or absolute coordinates returned by the agent node 20. The interrupt upload logic submits the input report according to the polling cycle requested by the external computer. Thus, the human-machine interaction actions collected by the agent node 20 can be restored to local peripheral input events recognizable by the external computer via the reverse optical link.

[0026] The video acquisition module 11 is physically connected to an external computer to acquire raw baseband video data.

[0027] The video stream directly enters the raw video line buffer 131 of the on-chip memory 13. The on-chip memory 13 is logically divided into the raw video line buffer 131 and the compressed bitstream buffer 132. The raw video line buffer 131 maintains a line-level buffer depth to provide line-level read and write operations for subsequent encoding pipelines. The compressed bitstream buffer 132 is used to buffer the compressed video payload output by the video compression module 14 and provides a first-in-first-out read interface for the frame sealing module 15.

[0028] The video compression module 14 is coupled to the read port of the raw video line buffer 131 in the on-chip memory 13 and to the write port of the compressed bitstream buffer 132. The video compression module 14 performs source encoding processing driven by the video pixel clock.

[0029] The frame-sealing module 15 is used to reassemble the compressed video payload and related control signaling into a data link layer format.

[0030] The first optoelectronic transceiver module 16 is responsible for the electro-optical conversion and optoelectronic conversion of the underlying physical optical signals.

[0031] The workstation node 20 is deployed on the user operation side and is used to drive peripherals and restore baseband video signals. The workstation node 20 includes a second optoelectronic transceiver module 21, a demultiplexing module 22, a peripheral interrupt module 23, a video decoding module 24, and a video output interface 25.

[0032] The second optoelectronic transceiver module 21 is connected to the underlying optical fiber physical link and performs the transmission and reception processing of the underlying optical signals.

[0033] The demultiplexing module 22 is used to strip control messages and video compression payloads from the forward data stream.

[0034] The peripheral interrupt module 23 directly listens to the underlying interrupt signals of external input devices and extracts physical interaction action features.

[0035] The video decoding module 24 performs inverse quantization decoding and synchronization timing recovery operations.

[0036] The video output interface 25 outputs a standard level signal to the terminal display device.

[0037] The optical switching matrix 30 serves as the core physical layer hub, establishing full-duplex fiber optic physical connections with both the host node 10 and the agent node 20. The optical switching matrix 30 internally includes a crossbar switch array 31 and a management and control module 32.

[0038] The cross switch array 31 is a high-speed solid-state cross switch matrix with transparent pass-through at the physical layer. It is used to close or open the photoelectric channels between the input ports and the output ports, and to complete the bit stream mapping between ports without performing frame header parsing, content verification, routing table lookup or store-and-forward.

[0039] The management control module 32 is connected to the control bus of the cross switch array 31 and is used to issue port addressing and cross interconnection configuration register words.

[0040] The zero latency referred to in this invention means that, compared to traditional KVM systems that use network protocol stacks, store-and-forward, routing lookup tables, and operating system software protocol stacks, the additional waiting latency introduced by the above mechanisms is reduced or eliminated. It does not mean that the physical propagation time, photoelectric conversion time, encoding processing time, decoding processing time, and row-level buffering time are zero.

[0041] See attached document Figure 2 , Figure 2 This is a flowchart illustrating a zero-latency KVM collaboration method according to an embodiment of the present invention. The present invention provides a zero-latency KVM collaboration method, comprising the following steps: S10, the physical ports corresponding to the first optoelectronic transceiver module 16 of the host node 10 and the optical switching matrix 30, and the physical ports corresponding to the second optoelectronic transceiver module 21 of the seat node 20 and the optical switching matrix 30 respectively establish a clock continuous synchronization mechanism in the physical coding sublayer. The management and control module 32 scans the hardware address of each endpoint and drives the cross switch array 31 to complete the establishment of the physical layer transparent transmission channel between the host node 10 and the target seat node 20. S20, the peripheral interrupt module 23 of the seat node 20 listens for the interrupt request event of the human-computer interaction device, extracts the position vector of the input device in the coordinate system and calculates the current interaction frequency; S30, the hardware logic maps the collected motion features and displacement vectors into a limited number of status identification codes, and encapsulates the coordinate parameters, status identification codes, and human-machine interface device input report data into an out-of-band control frame, which is transmitted to the host node 10 via a reverse optical link; wherein, the human-machine interface device input report data includes at least one or more of the following: device type field, button key value field, button status field, scroll wheel increment field, relative displacement field, or absolute coordinate field; S40, the parameter parsing module 12 of the host node 10 extracts the out-of-band control frame feature parameters, and the video compression module 14 uses the feedback coordinate parameters as the origin and determines the processing scope of the current pixel row based on spatial distance; at the same time, the peripheral simulation module 17 generates a keyboard, mouse or composite peripheral input report that can be recognized by an external computer based on the human-machine interface device input report data in the out-of-band control frame, and submits the input report through the peripheral interface of the external computer; S50, the video compression module 14 performs minimum quantization processing on video pixels within the core area defined as the ownership scope and maintains the source end chroma sampling structure. When the status code indicates that there is a frequent displacement action, it performs chroma physical folding operation on video pixels outside the core area and downgrades the sampling structure array of color components at the hardware layer. S60, the frame blocking module 15 reads the data dwell capacity level value of the compressed bitstream buffer 132. When the data dwell capacity triggers the hardware preset level threshold, it identifies the redundant padding characters corresponding to the line blanking period or the field blanking period in the dedicated serial link format of this system, and retains the core line and field synchronization control characters. S70, the frame blocking module 15 inserts a custom data delimiter into the physical transmission time slot corresponding to the redundant padding character, and directly fills the valid video compressed data accumulated in the compressed bitstream buffer 132 into the physical transmission time slot for transmission. S80, the optical switching matrix 30 transmits the encapsulated optoelectronic data stream through the cross switch array 31 to the target seat end node 20, and the demultiplexing module 22 separates the video payload and sends it to the video decoding module 24. S90, the video decoding module 24 performs a reverse restoration operation on the regular frame payload. When a data delimiter is detected, the accompanying payload data is restored to the video line buffer storage area. The blanking synchronization level timing is reconstructed according to the local reference clock generator, and the video output interface 25 is driven to output the baseband video signal.

[0042] See attached document Figure 3 , Figure 3 This is a flowchart illustrating physical layer continuous synchronization and direct optical path establishment according to an embodiment of the present invention. In the aforementioned near-zero additional latency KVM collaboration method, the first optoelectronic transceiver module 16 of the host node 10, the second optoelectronic transceiver module 21 of the agent node 20, and the corresponding physical ports of the optical switching matrix 30 are powered on and initialized. The first optoelectronic transceiver module 16 establishes port-level continuous synchronization with the host-side physical port of the optical switching matrix 30, and the second optoelectronic transceiver module 21 establishes port-level continuous synchronization with the agent-side physical port of the optical switching matrix 30. The physical coding sublayers within the first optoelectronic transceiver module 16 and the second optoelectronic transceiver module 21 then initiate their coding logic. In this physical coding sublayer, data is converted into a line coding format suitable for transmission in the optical fiber medium. In specific implementations, common line coding formats may include 8b / 10b encoding or 64b / 66b encoding. For the specific encoding and scrambling mechanisms in the physical coding sublayer, those skilled in the art can refer to relevant communication standard protocols; the underlying hardware logic is well-known in the field and will not be elaborated here.

[0043] During the initial establishment of the optical link or in idle periods without effective service data transmission, the media access control layer hardware controllers of the first optoelectronic transceiver module 16 and the second optoelectronic transceiver module 21 are configured to continuously output coded idle characters. Typically, line coding mechanisms introduce redundant bits to ensure sufficient level transitions in the data stream. These coded idle characters are special alignment characters defined in the physical coding sublayer specification, such as the K28.5 character used in the 8b / 10b coding system. The continuous transmission of these special characters aims to maintain high-frequency transition edges on the optical signal in the fiber optic link. The clock and data recovery circuits within the receiver optical module rely on these transition edges to extract the synchronization clock. Continuously transmitting coded idle characters ensures that the phase-locked loop (PLL) within the receiver remains in a stable locked state. This continuous clock locking mechanism helps eliminate the millisecond-level re-handshake and re-locking time required by traditional network devices during sleep and wake-up transitions, thus providing the physical layer foundation for subsequent low-latency data pass-through.

[0044] The management and control module 32 inside the optical switching matrix 30 initiates the device probing process via the hardware backplane bus. The management and control module 32 bypasses the monitoring of the link establishment status of each physical port. Since the system does not use the common Ethernet Internet Protocol stack and address resolution protocol, the management and control module 32 cannot obtain network layer information by sending broadcast data packets. The management and control module 32 directly reads the physical hardware address embedded in the underlying hardware of the access node through an out-of-band management channel. In one feasible implementation, this out-of-band management channel can be established using the low-speed auxiliary pin of the underlying interface of the optoelectronic transceiver module. Each host node 10 and agent node 20 has a node identity register or non-volatile identity memory internally configured, which contains the node hardware address. For example, based on the module standard internal integrated circuit control bus interface, the management and control module 32 sends a low-speed polling command to each access port to obtain the node hardware address of the node corresponding to the inserted module; the node hardware address can be represented in the form of a media access control address or in the form of a system-defined embedded identity code. In this implementation, the low-speed auxiliary pin is not only used to read the optical module's own information, but is extended to a node management channel to read the fixed hardware address in the corresponding KVM node controller. After the management control module 32 extracts the hardware identifiers of the host node 10 and the agent node 20, it establishes a one-to-one correspondence between the physical port and the device node.

[0045] According to the system's preset seat allocation strategy, the management and control module 32 issues a cross-connect configuration register word to the cross switch array 31. The cross switch array 31 can be internally composed of a high-frequency solid-state multiplexer and demultiplexer. After receiving the configuration register word, the cross switch array 31 connects the specified input physical pins and output physical pins at the hardware level. A point-to-point physical layer transparent pass-through channel is established from the host node 10 to the seat node 20 through the above-described pass-through configuration method. In this optical path, the optoelectronic data stream passes through the optical switching matrix 30 in its original bit stream form. The forwarding process of the optoelectronic data stream does not involve packet header parsing, service content identification, complete frame buffer writing, or routing table lookup operations. The forwarding delay of the optical signal essentially depends on the internal hardware propagation delay of the cross switch array 31.

[0046] See attached document Figure 4 , Figure 4 This is a schematic diagram illustrating the peripheral interrupt extraction and vector calculation principle according to an embodiment of the present invention. In the aforementioned zero-latency KVM collaborative method, the peripheral interrupt module 23 of the agent node 20 performs polling probing of the communication endpoints of the human-computer interaction device at the underlying hardware level. In conventional computer architectures, the response to peripheral actions depends on the software-driven protocol stack processing of the operating system. In this embodiment, the agent node 20 is directly connected to the human-computer interaction device as an independent hardware node. The peripheral interrupt module 23 embeds Universal Serial Bus (USB) host controller logic and is configured to listen for level transitions and interrupt transmission data packets on the peripheral bus physical interface in an environment without operating system intervention. For the device enumeration and endpoint communication mechanism of the underlying protocol stack of the USB, those skilled in the art can refer to relevant bus specifications and standards; its underlying handshake logic is well-known in the field and will not be described in detail here.

[0047] During the device enumeration phase, the peripheral interrupt module 23 reads the device descriptor, interface descriptor, and HMI device report descriptor of the human-machine interface device, and establishes an input report parsing table based on the HMI device report descriptor. When a valid interrupt request data packet is detected from the human-machine interface device, the peripheral interrupt module 23 parses the input report payload carried in the interrupt request data packet at the data link layer according to the input report parsing table. The peripheral interrupt module 23 extracts the input device's position vector parameter, key status Boolean word, scroll wheel increment, keyboard key value, or other peripheral action fields from the payload. The position vector parameter represents the absolute spatial position of the input device mapped in the two-dimensional display screen coordinate system. The key status Boolean word contains multiple logic bits, corresponding to the closed or open levels of the left and right mouse buttons and keyboard function keys, respectively. When the data transmitted by the human-machine interface device is only a relative offset, the peripheral interrupt module 23 converts it into an absolute position vector parameter through a hardware accumulator based on the set screen resolution reference. To avoid logical dead zones caused by coordinate value overflow due to hardware accumulation, the peripheral interrupt module 23 has internal boundary clamping logic. This boundary clamping logic restricts the accumulated absolute position vector parameter to the maximum value range of the horizontal and vertical pixels defined by the current screen resolution. The aforementioned screen resolution reference can be automatically determined by reading the extended display identifier data of the terminal display device during the system power-on initialization phase. The agent node 20 reads the extended display identifier data of the terminal display device through the display data channel of the video output interface 25 and sends the extended display identifier data back to the host node 10 via the reverse control frame or management control channel. The host node 10 caches the received extended display identifier data in the on-chip register and provides the corresponding display capability information to the external computer through the display interface emulation logic, so that the external computer outputs a resolution and refresh rate that matches the terminal display device. The display interface emulation logic is connected to the display data channel of the video output interface of the external computer and is used to present the extended display identifier data sent back by the agent node 20 as display capability information that can be read by the external computer.

[0048] The peripheral interrupt module 23 is internally equipped with a crystal clock generator and a counter to record the timestamp information corresponding to two consecutive valid interrupt request events. The peripheral interrupt module 23 reads the position vector parameters of the current cycle and the position vector parameters of the previous cycle, and uses the hardware logic processing unit to calculate the two-dimensional planar linear displacement distance parameters generated by the input device in two adjacent sampling cycles.

[0049] The peripheral interrupt module 23 calculates the current instantaneous displacement rate parameter of the human-computer interaction device based on the obtained two-dimensional planar linear displacement distance parameter and the timestamp difference between two consecutive interrupt request events. This instantaneous displacement rate parameter constitutes the quantitative basis for subsequent classification of interactive action state categories. The peripheral interrupt module 23 monitors the number of high and low level toggles of the key state Boolean word using a set statistical window period to obtain the current interactive action frequency parameter. The relevant statistical window period length is configured and set by the system's underlying registers based on the physical debouncing delay time of conventional peripherals. In a feasible implementation, combined with the conventional polling interval of the universal serial bus device, the statistical window period length can be set to a range of tens to hundreds of milliseconds to support accurate capture of actions such as repeated clicks.

[0050] See attached document Figure 5 , Figure 5 This is a schematic diagram of interactive state dimensionality reduction mapping and feedforward encapsulation according to an embodiment of the present invention. In the above-described zero-latency KVM collaboration method, the peripheral interrupt module 23 of the agent node 20 is internally configured with a hardware state machine logic unit. This hardware state machine logic unit receives the instantaneous displacement rate parameter, key state Boolean word, and interactive action frequency parameter obtained from the preceding steps. Considering the high dimensionality of the data combination of peripheral operation parameters, in order to reduce the bandwidth overhead of the reverse control channel and simplify the decision logic of the host-side video encoding pipeline, the hardware state machine logic unit executes the action state dimensionality reduction rule, classifying and mapping continuous interactive actions into discrete state identifier codes within a finite set.

[0051] The hardware state machine logic unit compares the instantaneous displacement rate parameter with a preset rate threshold in the system hardware register and simultaneously detects the level holding characteristics of the key state Boolean word. This state machine logic executes the mapping based on the following complete branch conditions: First, when the instantaneous displacement rate parameter is lower than the rate threshold and the key state Boolean word has not undergone a level flip within the current sampling period, the hardware state machine logic unit determines that the input device is in a micro-motion hovering state and generates a first discrete state identifier code indicating this state, which is 00. Second, when the instantaneous displacement rate parameter is greater than or equal to the rate threshold and the key state Boolean word indicates that a specific trigger bit is at a continuously closed level, the system identifies operations such as dragging windows that easily trigger large-scale updates to the display screen. The hardware state machine logic unit determines that it is currently in a high-frequency dragging state and generates a second discrete state identifier code indicating this state, which is 01. Third, when the instantaneous displacement rate parameter is greater than or equal to the rate threshold, but the key state Boolean word does not indicate any closed level, it is determined to be a normal cursor movement state. In this case, the hardware state machine logic unit outputs the first discrete state identifier code mentioned above to maintain the normal encoding strategy.

[0052] The hardware state machine logic unit simultaneously performs threshold checks on the interaction frequency parameter. When the interaction frequency parameter exceeds the set frequency trigger threshold, it indicates that there are currently dense key clicks or high-frequency coordinate jitter operations. The hardware state machine logic unit determines that the input device is in a high-frequency burst state and generates a corresponding third discrete state identifier code, which is 10.

[0053] When the status code is 00, the video compression module 14 maintains the normal quantization parameters and full-sample chroma structure for both the focus processing range and the background processing range. When the status code is 01, the video compression module 14 enables a first-level background degradation strategy for the background processing range. When the status code is 10, the video compression module 14 enables a second-level background degradation strategy for the background processing range. The first-level background degradation strategy includes folding the chroma structure of the background area from 4:4:4 to 4:2:2, and the second-level background degradation strategy includes folding the chroma structure of the background area from 4:4:4 to 4:2:0 or further increasing the luminance component quantization step size.

[0054] In one feasible implementation, a logical priority mechanism is configured in the hardware to address potential overlap in decision-making during state machine branches. When both the frequency trigger condition and the displacement trigger condition are met simultaneously, the output priority of the third discrete state identifier code is higher than that of the second and first discrete state identifier codes. The aforementioned frequency trigger threshold can be set to a range of three to eight level toggles per second to match the characteristics of conventional physical button actions.

[0055] The peripheral interrupt module 23 merges the extracted screen absolute position vector parameters with the currently generated discrete status identifier code to construct a custom out-of-band control frame at the data link layer. This out-of-band control frame is composed of a frame header delimiter, payload type identifier, frame length field, frame sequence number field, device type field, coordinate data segment, button status field, key value field, scroll wheel increment field, displacement data field, status code data segment, timestamp field, and a cyclic redundancy check sequence, all concatenated with a fixed byte width. The device type field distinguishes between keyboard, mouse, touchpad, and composite input devices; the frame sequence number field detects lost or out-of-order reverse control frames; and the timestamp field aligns the host node 10's peripheral actions with the video frame processing timing.

[0056] The media access control layer hardware scheduler of the agent node 20 assigns the highest transmission priority to the assembled out-of-band control frame. Once the out-of-band control frame is ready, the hardware scheduler monitors the physical transmission status of the current reverse fiber optic link and, within the first interframe gap after the current transmission of a regular heartbeat message or low-priority data frame, controls the second optoelectronic transceiver module 21 to inject the out-of-band control frame into the reverse fiber optic link. Through this high-priority channel scheduling, signaling including coordinate parameters, button status, and peripheral input report data can be transmitted to the host node 10 with a microsecond delay, ensuring that the cross-node delivery of feedforward parameters is completed before the host node 10 acquires and processes the video frame data at the corresponding moment. Among them, the coordinate parameters and button status are sent immediately after a single interruption event occurs; the interaction action frequency parameter is updated periodically based on a sliding statistical window and the status identification code is successively corrected with subsequent out-of-band control frames.

[0057] See attached document Figure 6 , Figure 6 This is a schematic diagram illustrating the principle of feedforward parameter parsing and processing scope delineation according to an embodiment of the present invention. In the aforementioned zero-latency KVM collaboration method, the parameter parsing module 12 of the host node 10 monitors the underlying data receiving channel, identifies and extracts the out-of-band control frames returned in reverse. The parameter parsing module 12 parses the payload of the out-of-band control frame, extracting the screen absolute position vector parameter, the corresponding discrete status identifier code, and the human-machine interface device input report data. The screen absolute position vector parameter and the discrete status identifier code are sent to the video compression module 14 for region division and encoding strategy selection; the human-machine interface device input report data are sent to the peripheral simulation module 17 for generating peripheral input reports recognizable by an external computer. Considering that out-of-band control frames arrive asynchronously on the physical link, to avoid disrupting the integrity of the video processing timing, the parameter parsing module 12 preferentially writes the extracted screen absolute position vector parameter and discrete status identifier code into an on-chip temporary storage register, waiting for video timing alignment triggering.

[0058] The parameter parsing module 12 extracts the video timing signal output by the current video acquisition module 11. When a valid transition edge of the video source field synchronization signal is detected, the parameter parsing module 12 updates the parameters in the on-chip temporary storage register to the working register. This operation keeps the reference origin coordinates and status code locked throughout the entire video scanning cycle. Combining the horizontal and vertical synchronization signals of the video source, the parameter parsing module 12 constructs a two-dimensional planar coordinate reference system corresponding to the resolution of the current input video stream internally in hardware. If the coordinate reference returned by the feedforward is inconsistent with the effective resolution of the current video source, the parameter parsing module 12 performs hardware multiplication according to the set resolution scaling factor, mapping the received screen absolute position vector parameter to the actual position parameter in the current video source coordinate system, and using it as the reference origin for subsequent image region division. The parameter parsing module 12 uses the maximum effective horizontal and vertical pixel values ​​of the current video source to perform boundary verification and clamping operations on the reference origin coordinates. When the input reference origin coordinate value is greater than the maximum effective pixel value of the current video source, it is forcibly reset to the maximum effective pixel value. For the timing parsing mechanism of line synchronization and field synchronization of video signals, those skilled in the art can refer to the relevant video interface standards and specifications, which are well-known technologies in the field and will not be elaborated here.

[0059] Driven by the video pixel clock, baseband video pixels enter the processing pipeline of the video compression module 14 one by one. The hardware logic array in the parameter parsing module 12 synchronously tracks the coordinate position of the currently scanned video pixel. For each video pixel entering the pipeline, the hardware logic array calculates the difference between the horizontal and vertical coordinates of the pixel in the two-dimensional plane coordinate reference system and the horizontal and vertical coordinates of the reference origin. To avoid introducing high-latency square root operation units into the hardware pipeline, the hardware logic array calls internal multipliers and adders to obtain the sum of the multiplication results of the horizontal pixel difference and the vertical pixel difference. The parameter parsing module 12 uses this sum as a metric to measure the spatial distance between the current pixel and the reference origin.

[0060] The parameter parsing module 12 compares the calculated measurement parameter with the distance threshold reference value configured in the system register. This distance threshold reference value is equivalent to the self-multiplied value of a preset radius threshold. To adapt to the physical characteristics of display devices of different sizes and the actual distribution of the central visual acuity zone of the human eye, the management control module 32 can dynamically configure the preset radius threshold value through the underlying bus. In typical implementation scenarios, the preset radius threshold value, combined with the physical size of a typical display device, can be set to a range of 100 to 300 pixels. When the measurement parameter is less than or equal to the distance threshold reference value, the parameter parsing module 12 determines that the currently scanned pixel falls within the focus processing ownership range and generates a logic high-level ownership Boolean flag bit for that pixel.

[0061] When the metric parameter exceeds the distance threshold reference value, the parameter parsing module 12 determines that the currently scanned pixel is within the background processing ownership range of the non-focus area and generates a low-level ownership Boolean flag for that pixel. As the video pixel clock advances, the parameter parsing module 12 continuously outputs pixel-by-pixel ownership Boolean flags that are strictly aligned with the current video pixel. The parameter parsing module 12 synchronously transmits this flag sequence, along with the discrete state identifier code latched in the working register, to the video compression module 14 via the on-chip data bus, thereby providing a direct trigger condition for the video compression module 14 to perform non-uniform compression processing.

[0062] See attached document Figure 7 , Figure 7 This is a schematic diagram of a non-uniform quantization and chroma physical folding mechanism according to an embodiment of the present invention. The video compression module 14 internally houses a color space conversion logic array and a quantization control engine. Driven by the video pixel clock, the video compression module 14 synchronously receives the baseband video pixel stream and the pixel-by-pixel ownership Boolean flag and discrete state flag code transmitted from the parameter parsing module 12. When the input baseband video pixel stream uses a red-green-blue color space format, the color space conversion logic array uses a hardware multiplier-accumulator to convert it into a color space format containing independent luminance and chrominance components to support subsequent independent intervention on the chrominance channel. When the input baseband video pixel stream itself is in a format containing independent luminance and chrominance components (e.g., YCbCr format), the color space conversion logic array activates a bypass pass-through mode, directly outputting the pixel stream to the subsequent processing layer to avoid invalid redundant calculations. For the matrix conversion calculation logic between different color space formats, those skilled in the art can refer to relevant video image processing specifications, which are well-known technologies in the field and will not be elaborated here.

[0063] The quantization control engine checks the Boolean flags aligned with the current video pixel one by one. When a Boolean flag is detected to be at a logic high level, the video compression module 14 determines that the currently scanned video pixel is located within the core area of ​​the focus processing authority. For this core area, the quantization control engine assigns the minimum quantization step size supported by the system to the transform coefficients of the current pixel and performs lossless or near-lossless compression. At the same time, the hardware pipeline of the video compression module 14 locks the full-sampling chroma array structure (e.g., 4:4:4 chroma sampling format) at the source end, without discarding any chroma component data, thereby ensuring the visual edge sharpness of text and fine graphics within the user's field of vision.

[0064] When the ownership Boolean flag is detected to be at a low logic level, the video compression module 14 determines that the current pixel is located in a non-focus background area. The quantization control engine then reads the currently latched discrete state flag to determine the degradation strategy. When the discrete state flag is the aforementioned first discrete state flag, it indicates that the peripheral device is in a stable or slightly fluctuating state, and there is no risk of a large-area global refresh of the image. The quantization control engine maintains the normal quantization parameters and keeps the full-sample chroma array. When the discrete state flag is the aforementioned second or third discrete state flag, it indicates that the current peripheral device is in a high-frequency dragging or frequent displacement sudden action. This state tends to cause large-area changes in the video image and lead to a surge in the amount of instantaneous encoded data. At this time, the quantization control engine triggers the non-uniform quantization and chroma physical folding mechanism.

[0065] After triggering the chroma physical folding mechanism, the video compression module 14 adjusts the sampling structure array of color components for the background region within the current pixel scan line. Specifically, the hardware pipeline converts the original full-sample chroma array into a sub-sample array. In one specific implementation, if the source full-sample array is in 4:4:4 format, the hardware pipeline folds it down to a 4:2:2 or 4:2:0 format. To avoid color format misalignment at the decoding end due to sampling structure switching at arbitrary single-pixel boundaries, the video compression module 14 internally includes a pixel aggregation buffer. This buffer uses even-numbered pixel pairs or four-neighbor pixel blocks as the smallest operational boundary unit. When the chroma mode field indicates a 4:2:2 chroma structure, the video compression module 14 uses two horizontally adjacent pixels as the smallest folding unit; when the chroma mode field indicates a 4:2:0 chroma structure, the video compression module 14 uses a 2×2 pixel block formed by horizontal and vertical directions as the smallest folding unit. The boundaries of the focus processing area and the background processing area are forcibly aligned to the boundaries of these smallest folding units. Taking the 4:2:2 format as an example, the pixel aggregation buffer operates on two adjacent pixels as a unit in the horizontal scanning direction. It retains the independent luminance component values ​​of these two pixels, while simultaneously averaging the original chrominance component values ​​of the two pixels and distributing the calculated average chrominance value to both pixels, thus discarding redundant high-frequency chrominance sampling points. At the same time, the quantization control engine synchronously increases the quantization step size of the luminance component in this background region. This hardware-level dimensionality reduction truncation, combining spatial and spectral domains, can reduce the instantaneous physical bit width requirement of video pixels without affecting the core focus image quality, thereby suppressing bit rate spikes.

[0066] After completing the above processing, the video compression module 14 sends the video data, which has undergone adaptive quantization and chroma adjustment, to the entropy encoder for variable-length encoding to generate a compressed video payload. When generating the compressed video payload, the video compression module 14 writes a local encoding parameter field to the header of each encoding unit. This local encoding parameter field includes at least a region identifier field, a quantization parameter increment field, and a chroma mode field. The chroma mode field indicates the chroma sampling structure used by the current encoding unit, where 00 represents a 4:4:4 chroma structure, 01 represents a 4:2:2 chroma structure, and 10 represents a 4:2:0 chroma structure. The generated compressed video payload is continuously pushed to the compressed bitstream buffer 132 of the on-chip memory 13 according to a first-in, first-out principle, awaiting subsequent data link layer format reassembly and physical transmission scheduling by the frame-sealing module 15.

[0067] See attached document Figure 8 , Figure 8 This is a schematic diagram illustrating the principle of on-chip buffer level monitoring and blanking timing interception according to an embodiment of the present invention. The compressed bitstream buffer 132 in the on-chip memory 13 of the host node 10 receives the compressed video payload from the video compression module 14. To support continuous data stream throughput under a very shallow buffer architecture, the on-chip memory 13 is physically configured as a static random access memory array. The compressed bitstream buffer 132 is logically divided into a circular buffer. This circular buffer maintains a write address pointer driven by the video compression pipeline clock and a read address pointer driven by the transmission link clock of the frame blocking module 15. To avoid metastability issues caused by cross-clock domain read pointers, a synchronizer composed of multi-level flip-flops is used internally in the hardware, combined with Gray code conversion logic to perform cross-domain synchronization extraction of the read and write pointers. For specific cross-clock domain signal synchronization processing in digital circuits, those skilled in the art can refer to relevant integrated circuit design specifications, which are well-known technologies in the field and will not be elaborated here.

[0068] The frame-sealing module 15 integrates a compressed bitstream level monitoring circuit. Driven by the system sampling clock, the row-level resident capacity monitoring circuit acquires the synchronized write address pointer and read address pointer in real time and sends them to a hardware subtractor to calculate the address difference between the two. Considering the physical address space boundary of the circular buffer, when the value of the write address pointer is less than the value of the read address pointer, it indicates that the write operation has reached the upper limit of the address space and a wraparound has occurred. At this time, the row-level resident capacity monitoring circuit calls the compensation logic, adding the value of the write address pointer to the preset total physical address depth value of the on-chip memory 13, and then subtracting the value of the read address pointer to obtain the real address difference after wraparound compensation. The frame-sealing module 15 uses this real address difference as the current level value reflecting the amount of currently backlogged and unsent data in the compressed bitstream buffer 132.

[0069] The frame-sealing module 15 sends the real-time calculated current water level value to a digital comparator and compares it with the hardware warning threshold set in the internal system register clock cycle by clock cycle. The value of this hardware warning threshold is related to the number of bytes per line of data in the current video source. In a specific implementation, the management control module 32 dynamically sets the hardware warning threshold according to the parsed video source resolution as the difference between the total capacity of the compressed bitstream buffer 132 and two to three times the maximum resident amount of compressed video data per line. This setting aims to reserve necessary buffer margins to ensure that residual pixels still in the input pipeline will not cause physical overflow before the interception mechanism is triggered.

[0070] When the digital comparator outputs a low level, it indicates that the current water level is below the hardware warning threshold, and the capacity of the compressed bitstream buffer 132 is within a safe range. The frame sealing module 15 maintains the normal baseband video timing assembly and distribution. When the digital comparator outputs a high level, it indicates that the current water level has reached or exceeded the hardware warning threshold, and the system faces the risk of buffer overflow. The line-level resident capacity monitoring circuit then sends a trigger interception interrupt signal to the frame sealing module 15.

[0071] Upon receiving the trigger interception interrupt signal, the frame sealing module 15 initiates the blanking timing interception mechanism. The frame sealing module 15 parses the video interface baseband signal synchronously transmitted from the video acquisition module 11 and encodes the video line synchronization, field synchronization, effective video area, and blanking area into a preset control character sequence in the system's dedicated serial link format. In standard video timing, when the effective video line scan ends or the effective video field scan ends, the baseband signal specifies the transmission of regular line blanking synchronization characters or field blanking synchronization characters to fill idle time slots. In the system's dedicated serial link format, these line blanking synchronization characters or field blanking synchronization characters correspond to the blanking area control character sequence generated by the frame sealing module 15. To prevent screen tearing caused by the loss of synchronization reference at the remote device, the frame sealing module 15 internally activates a blanking timing protection mechanism. The frame sealing module 15 identifies and extracts the core line and field synchronization pulse characters within the blanking interval at the physical coding control sublayer for transparent transmission, while selectively blocking the transmission of redundant padding characters corresponding to the period between the front and back shoulders in the system's dedicated serial link format to the lower-level physical transmission link. This operation forces the corresponding physical transmission time slots to be freed up, thereby providing physical conditions for subsequently squeezing the backlog of compressed video payloads into these slots, ensuring the continuity and stability of the video transmission link.

[0072] See attached document Figure 9 , Figure 9This is a schematic diagram illustrating the principle of blanking out-of-band delimitation and data backflow drainage according to an embodiment of the present invention. After the blanking timing interception mechanism is activated, the frame sealing module 15 constructs a custom data delimiter for subsequent data backflow operations. In high-speed serial physical links, data streams typically rely on specific control characters to maintain byte alignment and clock recovery. The frame sealing module 15, at the physical coding layer, combines conventional underlying line coding rules such as 8b / 10b to select a specific combination of control characters that are not occupied by the video interface standard and have high Hamming distance characteristics to generate a custom data delimiter. This custom data delimiter differs from the valid video start delimiter or blanking start delimiter in conventional video timing. For the underlying coding rules and control character definitions in high-speed serial links, those skilled in the art can refer to the relevant physical layer transmission specifications; the underlying coding logic is well-known in the field and will not be elaborated here.

[0073] In the physical transmission pipeline, immediately following the preserved core line and field synchronization pulse characters, the frame-sealing module 15 sends the custom data delimiter constructed above to the first optoelectronic transceiver module 16. This custom data delimiter serves as a state switching flag at the communication protocol layer, indicating that the remote receiving node's current transmission channel has switched from the standard blanking idle state to out-of-band data backflow mode, reminding the receiving end to prepare for extracting non-standard video timing payloads.

[0074] To prevent backflowing compressed data from exceeding the limit and encroaching on the starting physical time slot of the next valid video line, thus causing downlink frame coordinate misalignment, the frame sealing module 15 is internally configured with time slot capacity calculation logic. This time slot capacity calculation logic calculates the number of safely available physical transmission slots within the current blanking period based on the duration of the currently blocked redundant front or back shoulder and the link transmission clock frequency. The aforementioned minimum time slot threshold required by a single data packet is jointly determined by the minimum data packet length configured internally by the system and the current transmission baud rate of the link, aiming to prevent data packets from being physically truncated at the end of the time slot. As the system transmission clock advances, this time slot capacity calculation logic continuously decreases and updates the number of remaining physical transmission slots.

[0075] After confirming that the number of remaining physical transmission slots is greater than the minimum slot threshold mentioned above, the frame sealing module 15 triggers the payload backfilling mechanism. Based on the read address pointer, the frame sealing module 15 extracts the backlogged valid video compressed data from the compressed bitstream buffer 132. The frame sealing module 15 packages the extracted valid video compressed data and performs character escaping processing on the packaged data at the physical coding sublayer. This escaping processing aims to prevent accidental overlap between the bit sequence within the valid video compressed data and the control delimiters of the physical link, thereby avoiding state machine parsing errors at the receiving end. After completing the escaping processing, the frame sealing module 15 fills the data into the currently idle blanking period physical slots and transmits it. Through this multiplexing operation, the system utilizes the idle capacity of the blanking area to empty the backlogged data in the compressed bitstream buffer 132 without increasing the additional physical channel bandwidth. When the frame sealing module 15 detects that the current level of the compressed bitstream buffer 132 is continuously higher than the hardware warning line, the frame sealing module 15 sends a congestion indication signal back to the video compression module 14. In response to the congestion indication signal, the video compression module 14 increases the quantization step size of the background region, expands the chroma folding ratio of the background region, or further folds the chroma structure of the background region from 4:2:2 to 4:2:0, so that the average bit rate output by the video compression module 14 does not exceed the effective payload transmission rate of the optical link.

[0076] During data backflow, the frame sealing module 15 synchronously monitors the number of remaining physical transmission slots and the current level of the compressed bitstream buffer 132. When the number of remaining physical transmission slots reaches a preset critical buffer value (which is statically set in the system register to be equal to the number of clock cycles required to send a backflow end delimiter), or when the current level of the on-chip memory 13 falls back to a preset safety line, the frame sealing module 15 interrupts the workflow of retrieving data from the on-chip memory 13. Subsequently, the frame sealing module 15 inserts a backflow end delimiter into the physical transmission pipeline and releases the timing interception restriction on the video interface baseband signal, so that the valid video start character of the next line can be sent normally according to the standard video timing, maintaining the consistency of the overall video scan rhythm.

[0077] See attached document Figure 10 , Figure 10 This is a schematic diagram illustrating the principle of optoelectronic fully interconnected transparent transmission and service payload separation according to an embodiment of the present invention. The optical switching matrix 30 is internally configured with a crossbar switch array 31. The input ports of the crossbar switch array 31 receive high-speed optical signals transmitted by the first optoelectronic transceiver module 16 of the host node 10 via an optical fiber link, and convert them into physical layer baseband electrical signals using a front-end photodetector. To meet the stringent timing requirements of a near-zero additional delay cooperative system, the crossbar switch array 31 operates in a pass-through forwarding mode in its hardware architecture.

[0078] In a KVM matrix system, if the central switching node uses a conventional Layer 2 packet switching mechanism, its underlying controller will identify non-standard timing data containing custom delimiters as illegal frames and discard them, thus causing the data backflow mechanism to fail. Therefore, in the pass-through forwarding mode of this embodiment, the crossbar switch array 31 is configured in physical layer port matrix switching mode. The crossbar switch array 31 does not extract the Media Access Control layer frame header of the data frame for table lookup routing, nor does it perform any deep content parsing or verification of the payload within the data. The crossbar switch array 31 directly uses the static port mapping table issued by the internal management control module 32 to map and copy the baseband electrical signal of the source port to the target port using a hardware connection matrix. Subsequently, the crossbar switch array 31 converts the baseband electrical signal back into an optical signal for transmission via the port laser driver. This physical-level pass-through avoids the queuing delay caused by the store-and-forward mechanism and ensures that the underlying bit stream containing non-standard blanking area multiplexing timing can penetrate the central switching node. For the specific circuit topology construction of the optoelectronic crossbar switch physical matrix, those skilled in the art can refer to relevant network switching standards and specifications, which are well-known technologies in the field and will not be elaborated here.

[0079] The second optoelectronic transceiver module 21 of the workstation node 20 receives the optical signal forwarded by the central switching node 30. The second optoelectronic transceiver module 21 performs optoelectronic conversion and clock data recovery operations, and sends the recovered serial bit stream to the internal demultiplexing module 22. The underlying hardware state machine of the demultiplexing module 22 performs continuous character boundary alignment and delimiter matching on the input serial bit stream. When the aforementioned custom data delimiter is detected, the demultiplexing module 22 determines that the current physical link is in out-of-band data backflow mode, and performs character inversion processing on subsequent data blocks in the physical coding sublayer to restore the original data link layer frame sequence of the transmitting end. To prevent transient errors in the physical link from causing the loss of the backflow end delimiter and thus triggering a state machine deadlock, the underlying hardware state machine of the demultiplexing module 22 is configured with fault-tolerant reset logic. When the state machine detects a valid video start character or line synchronization character of the standard video timing in out-of-band data backflow mode, regardless of whether a backflow end delimiter is received, the state machine is forcibly reset to the normal video timing reception state. When the demultiplexing module 22 detects a cyclic redundancy check sequence error, discontinuous frame number, character inversion failure, or out-of-band data backflow mode duration exceeding the preset maximum time slot length, the demultiplexing module 22 discards the current abnormal data block and outputs an indication signal to the video decoding module 24 indicating frame loss or repetition of the previous valid line, in order to prevent abnormal loads from continuing to enter the decoding pipeline.

[0080] The demultiplexing module 22 parses the restored data link layer frame, extracting the payload type identifier field inside its frame header to separate the mixed data streams for service. When the payload type identifier field indicates that the current data frame is a regular control message, the demultiplexing module 22 separates the data frame from the main data stream and routes it to the peripheral device control bus of the agent node 20 to maintain device heartbeat, synchronize peripheral enumeration status, or respond to system configuration parameters.

[0081] When the payload type identifier field indicates that the current data frame carries valid video data, the demultiplexing module 22 determines it to be a video compression payload. The demultiplexing module 22 strips the media access control layer header, cyclic redundancy check sequence, and underlying alignment padding characters from the data frame to extract the video compression bitstream. Whether the data is transmitted in a regular valid video time zone or extracted from the physical slots in the blanking zone, the demultiplexing module 22 writes it sequentially into the subsequent first-in-first-out buffer queue according to the physical timing of its arrival. The demultiplexing module 22 then pushes the reassembled continuous video compression bitstream to the input pipeline of the video decoding module 24 through this buffer queue. This separation and reassembly mechanism makes the underlying physical link multiplexing transparent to the upper-layer services, ensuring that the video decoding module 24 can obtain a continuous and compliant compressed bitstream.

[0082] See attached document Figure 11 , Figure 11 This is a schematic diagram of adaptive reverse recovery and baseband timing reconstruction according to an embodiment of the present invention. The demultiplexing module 22 of the workstation node 20 continuously pushes a continuous stream of compressed video bits to the input pipeline of the video decoding module 24. The video decoding module 24 is internally configured with a row buffer storage area constructed from a static random access memory array. For video payloads transmitted back during the blanking period at the transmitting end, due to their sudden and dense arrival on the physical link, the video decoding module 24, based on the receiving clock, uses direct memory access control logic to temporarily store these accompanying payload data in the row buffer storage area. This addresses the transient rate fluctuations caused by the sudden arrival of data in the blanking period, providing a stable data supply for subsequent decoding pipelines.

[0083] The entropy decoder and inverse quantization unit inside the video decoding module 24 extract compressed data from the line buffer storage area and perform inverse operations. In the inverse quantization stage, to cooperate with the non-uniform quantization mechanism introduced at the transmitting end, the video decoding module 24 extracts the quantization parameter increment syntax elements located at the macroblock header or coding tree unit header when parsing the video compressed bitstream. Based on these increment syntax elements and the basic quantization parameters at the image level, the video decoding module 24 calculates the local quantization step size actually applied to the currently processed pixel block. The video decoding module 24 uses this local quantization step size to perform fine or coarse inverse quantization on the current discrete cosine transform coefficients or wavelet coefficients, thereby restoring the frequency domain coefficients containing luminance and chrominance components, and further outputting the pixel component values ​​in the spatial domain through inverse transform. For the entropy decoding and inverse transform calculation logic in conventional video coding standards, those skilled in the art can refer to relevant image decoding specifications, which are well-known technologies in the field and will not be elaborated upon here.

[0084] The video decoding module 24 detects the chroma sampling format of the current macroblock or pixel group. Specifically, the video decoding module 24 obtains the current physical chroma structure by parsing the chroma mode field carried in the header of each coding unit in the bitstream. When the chroma mode field is 00, the video decoding module 24 directly outputs the chroma components according to the 4:4:4 structure; when the chroma mode field is 01, the video decoding module 24 performs chroma upsampling according to the path from 4:2:2 to 4:4:4; when the chroma mode field is 10, the video decoding module 24 performs chroma upsampling according to the path from 4:2:0 to 4:4:4.

[0085] When it is detected that the current pixel group has undergone non-uniform quantization and chroma physical folding mechanisms at the transmitting end, i.e., its format is a subsampled array (e.g., 4:2:2 or 4:2:0 format), the format resampling logic inside the video decoding module 24 is activated. The decoding logic performs chroma array upsampling on the subsampled array to inversely restore it to a full-sampled chroma array (e.g., 4:4:4 format). In the specific hardware implementation, to avoid introducing complex interpolation filters and increasing pipeline delay, the video decoding module 24 adopts a neighborhood copying strategy. Taking the restoration from 4:2:2 to 4:4:4 as an example, the hardware logic reads the chroma component value of the current even-numbered pixel and directly copies it to fill the chroma channel of the adjacent odd-numbered pixel. In an optional implementation, the video decoding module 24 calls its internal shift register and adder to calculate the arithmetic mean of the chroma values ​​of two adjacent known pixels, and uses this mean as the chroma interpolation for the missing pixels in the middle.

[0086] After completing the spatial domain reconstruction of the pixel components, the video decoding module 24 enters the baseband timing reconstruction stage. Considering that the conventional blanking timing at the transmitting end has been forcibly truncated and replaced with data backflow slots in previous steps, the video decoding module 24 uses its internal video timing generator to regenerate the baseband image required by the standard display interface specification. Before generating the timing, the video decoding module 24 actively reads the Extended Display Identifier (EDID) data of the display connected to the physical display interface through the Display Data Channel (DDC). The video decoding module 24 parses the EDID to obtain the front shoulder time, back shoulder time, and sync pulse width parameters precisely supported by the current display device. Subsequently, the video timing generator, based on the core line and field sync pulse characters passed through and retained by the demultiplexing module 22, combined with the parsed EDID timing parameters, drives the local crystal oscillator to generate the basic pixel clock and inserts blanking sync levels of corresponding lengths between valid video lines and fields.

[0087] To avoid buffer overflow or readout caused by the inherent frequency deviation of the physical crystal oscillators at both ends of the transmission and reception ends in an architecture without a full frame buffer, the video decoding module 24 integrates a voltage-controlled oscillator (VCO) and a level feedback loop. The video decoding module 24 monitors the current read / write pointer level of the line buffer storage area in real time. When the level continuously exceeds the upper limit of the preset level threshold range, it indicates that the write speed at the receiving end is greater than the local decoding consumption speed. The feedback loop outputs a control voltage to slightly adjust the output frequency of the VCO, thus accelerating the local pixel clock. When the level continuously falls below the lower limit of the preset level threshold range, the feedback loop outputs a reverse control voltage to slightly reduce the output frequency of the VCO. This preset level threshold range is typically statically set between 40% and 60% of the total capacity of the line buffer storage area. Through a dynamic clock tracking mechanism, the video decoding module 24 achieves physical synchronization with the source timing of the host node 10 when outputting the reconstructed baseband video signal, thereby outputting a continuous and stable baseband image to the external display.

[0088] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A zero-latency KVM workstation collaboration system based on a non-IP all-fiber architecture, characterized in that, include: The host node is used to acquire the baseband video pixel stream of the video source and collect the operation data of the peripheral devices to generate ownership Boolean flag bits and discrete state flag codes. Based on the ownership Boolean flag and the discrete state flag, non-uniform quantization and chroma physical folding are performed on the baseband video pixel stream to generate a compressed video payload and store it in the on-chip memory; the current water level value of the on-chip memory is monitored, and when the current water level value reaches the set hardware warning line, the regular blanking synchronization character is intercepted during the blanking period of the video interface baseband signal, and a custom data delimiter is inserted into the physical link. The compressed video payload accumulated in the on-chip memory is extracted and filled into the blanking period physical slot and sent down to generate a multiplexed data link layer frame sequence. The central switching node is connected to the host node via a physical link and operates in physical layer port matrix switching mode. It is used to directly map and transmit the photoelectric signal containing the multiplexed data link layer frame sequence from the input port to the target output port. The workstation node is connected to the central switching node via a physical link. It is used to receive the photoelectric signals transmitted by the central switching node, extract the control message and the compressed video payload through demultiplexing, perform inverse quantization and chroma upsampling on the compressed video payload, and realize clock synchronization by combining the water level feedback mechanism of the local row buffer storage area, reconstruct the baseband video signal and output it to the display device.

2. The zero-latency KVM workstation collaboration system based on a non-IP all-fiber architecture as described in claim 1, characterized in that, When the host node performs non-uniform quantization and physical chroma folding on the baseband video pixel stream based on the ownership Boolean flag and the discrete state flag, it is specifically used for: When the ownership Boolean flag indicates that the current video pixel is in the focus region, the minimum quantization step size is allocated to the current video pixel, and the full sampling chroma array structure at the source end is maintained; When the ownership Boolean flag indicates that the current video pixel is located in a non-focal region, and the discrete state flag indicates that the peripheral is in a high-frequency displacement burst state, the step size of the luminance component of the current video pixel is increased, and the full-sample chroma array structure is converted into a sub-sample array; wherein, when converting to the sub-sample array, adjacent pixel pairs or four neighboring pixel blocks are used as boundary units, the independent luminance component values ​​of each pixel are retained, and an arithmetic mean operation is performed on the original chroma component values ​​to generate a shared chroma value and allocate it to the corresponding pixel.

3. The zero-latency KVM workstation collaboration system based on a non-IP all-fiber architecture as described in claim 1, characterized in that, When the host node monitors the current water level value of the on-chip memory, and the current water level value reaches a set hardware warning threshold, it intercepts the regular blanking synchronization character during the blanking period of the video interface baseband signal. Specifically, this is used for: The on-chip memory is configured as a circular buffer driven by the video compression pipeline clock for writing and driven by the transmission link clock for reading, and Gray code conversion logic is used to extract the read and write pointers synchronously across clock domains. The address difference is calculated by obtaining the synchronized write address pointer and read address pointer, and when the write operation loops back, the loopback compensation calculation is performed in combination with the preset total physical address depth value of the on-chip memory, and the real address difference is extracted as the current water level value. When the current water level is greater than or equal to the hardware warning line, the core line and field synchronization pulse characters in the blanking interval are transmitted through the physical coding control sublayer, while the redundant padding characters in the blanking interval are blocked from being sent out, so as to force the physical transmission time slot to be freed up.

4. The zero-latency KVM workstation collaboration system based on a non-IP all-fiber architecture as described in claim 1, characterized in that, When the host node inserts a custom data delimiter into the physical link, extracts the compressed video payload accumulated in the on-chip memory, fills it into the blanking period physical slot, and then sends it out, it is specifically used for: In the physical coding layer, a combination of control characters not occupied by the video interface standard is selected to generate the custom data delimiter, which is then sent to the physical link following the core line and field synchronization pulse characters, instructing the communication protocol layer to switch to out-of-band data backflow mode. Calculate the number of remaining physical transmission slots in the current blanking period, and when it is confirmed that the number of remaining physical transmission slots is greater than the preset minimum slot threshold, extract the compressed video payload from the on-chip memory; In the physical coding sublayer, character escaping is performed on the extracted compressed video payload to prevent the data bit sequence from overlapping with the control delimiters of the physical link, and the escaped data is filled into the idle physical transmission slots for transmission. When the number of remaining physical transmission slots reaches the set critical buffer value, or when the current water level falls back to the preset safety line, the extraction operation is interrupted and a backflow end delimiter is inserted into the physical link.

5. A zero-latency KVM workstation collaboration system based on a non-IP all-fiber architecture as described in claim 1, characterized in that, When the central switching node directly maps and transmits the photoelectric signal containing the multiplexed data link layer frame sequence from the input port to the target output port, it is specifically used for: The media access control layer frame header of the data frame is not extracted for Layer 2 table lookup routing, and the content parsing and verification of the compressed video payload inside is not performed. Based on the static port mapping table issued by the internal management and control module, the baseband electrical signal containing the multiplexed data link layer frame sequence received is directly mapped and switched to the target output port by means of physical level copying using the internal hardware connection matrix.

6. A zero-latency KVM agent collaboration system based on a non-IP all-fiber architecture as described in claim 1, characterized in that, When the agent node extracts the control message and the compressed video payload through demultiplexing, it is specifically used for: The internal low-level hardware state machine performs delimiter matching on the input serial bit stream. When the custom data delimiter is detected, it switches to out-of-band data backflow mode and performs character inversion processing in the physical coding sub-layer to restore the multiplexed data link layer frame sequence. When the underlying hardware state machine detects a valid video start character or line synchronization character of the standard video timing in the out-of-band data backflow mode, it triggers the fault-tolerant reset logic to force a reset to the normal video timing reception state. Extract the payload type identifier field inside the data link layer frame, route the control message to the peripheral device control bus, and truncate the media access control layer frame header and alignment padding characters to extract the clean compressed video payload.

7. A zero-latency KVM workstation collaboration system based on a non-IP all-fiber architecture as described in claim 1, characterized in that, When the seat node performs inverse quantization and chroma upsampling on the compressed video payload, it is specifically used for: The incremental quantization parameter syntax element is extracted from the compressed video payload, and the local quantization step size of the current processed pixel block is calculated by combining it with the global basic quantization parameters. The frequency domain coefficients are inversely scaled using the local quantization step size, and the pixel component values ​​in the spatial domain are restored through inverse transformation. When the chroma format of the current pixel block is detected to be a subsampled array, the chroma component values ​​of the currently known pixels are read to perform direct copying, or the arithmetic mean of the chroma component values ​​of adjacent known pixels is used as the interpolation of the missing pixels in the middle to reverse restore the full sampled chroma array.

8. A zero-latency KVM workstation collaboration system based on a non-IP all-fiber architecture as described in claim 1, characterized in that, When the seat terminal node reconstructs the baseband video signal and outputs it to the display device, it is specifically used for: The extended display identifier data within the display device is read via the display data channel; Parse the extended display identifier data to obtain the front shoulder time, back shoulder time, and synchronization pulse width parameters physically supported by the display device; Based on the core line and field synchronization pulse characters that are transparently preserved in the receiving link, as well as the parsed front shoulder time, back shoulder time, and synchronization pulse width parameters, blanking synchronization levels of corresponding lengths are inserted between the restored effective video lines and fields to construct a standard video timing framework.

9. A zero-latency KVM workstation collaboration system based on a non-IP all-fiber architecture as described in claim 1, characterized in that, When the agent node uses the water level feedback mechanism of the local row buffer storage area to achieve clock synchronization, it is specifically used for: The burst compressed video payload transmitted via backflow is written into the local row buffer storage area constructed by the static random access memory array; The current read / write pointer level of the local row buffer storage area is monitored in real time. When the level is continuously higher than the upper limit of the preset level threshold range, the level feedback loop outputs a control voltage to slightly increase the output frequency of the local voltage-controlled oscillator. When the water level remains below the lower limit of the preset water level threshold range, the water level feedback loop outputs a reverse control voltage to slightly reduce the output frequency of the local voltage-controlled oscillator. The finely tuned local voltage-controlled oscillator is used to drive the local crystal oscillator to generate the basic pixel clock, thus completing the clock synchronization between the source and receiver.

10. A zero-latency KVM agent collaboration method based on a non-IP all-fiber architecture, used to execute the zero-latency KVM agent collaboration method based on a non-IP all-fiber architecture as described in any one of claims 1 to 9, characterized in that, The method includes: The host node acquires the baseband video pixel stream of the video source and collects the operation data of the peripheral devices to generate ownership Boolean flag bits and discrete state flag codes; The host node performs non-uniform quantization and chroma physical folding on the baseband video pixel stream based on the ownership Boolean flag and the discrete state flag, generates a compressed video payload and stores it in the on-chip memory. The host node monitors the current water level value of the on-chip memory. When the current water level value reaches the set hardware warning line, it intercepts the regular blanking synchronization character during the blanking period of the video interface baseband signal, inserts a custom data delimiter into the physical link, extracts the compressed video payload accumulated in the on-chip memory and fills it into the blanking period physical slot for distribution, generating a multiplexed data link layer frame sequence. The central switching node operates in physical layer port matrix switching mode, directly mapping and transmitting the photoelectric signal containing the multiplexed data link layer frame sequence from the input port to the target output port; The workstation receives the photoelectric signal transmitted by the central switching node, extracts the control message and the compressed video payload through demultiplexing, performs inverse quantization and chroma upsampling on the compressed video payload, and achieves clock synchronization by combining the water level feedback mechanism of the local row buffer storage area, reconstructs the baseband video signal and outputs it to the display device.

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