An inertial sensor interface circuit based on charge overlap rebalancing

Abstract

The application belongs to the field of micro electro mechanical system (MEMS) and analog integrated circuit design, and specifically provides an inertial sensor interface circuit based on charge overlap rebalancing, which is used to solve the inherent defects of the existing capacitance-voltage conversion interface circuit under the open loop architecture. The application comprises a charge balance dynamic biasing module, a programmable compensation capacitor array, a gating switch module, a first single-ended capacitance voltage conversion module, a second single-ended capacitance voltage conversion module, a clock generation module and a reference voltage generation module, wherein the two single-ended capacitance voltage conversion modules form symmetric branches, are alternately connected to the inertial sensor through the gating switch module, correspondingly obtain a differential output voltage, and are fed back to the charge balance dynamic biasing module to form a feedback loop, realize essential linearization through charge dynamic rebalancing, and effectively eliminate the influence of static and dynamic errors through the programmable compensation capacitor array and the correlated double sampling circuit.

Description

Technical Field

[0001] This invention belongs to the field of microelectromechanical systems (MEMS) and analog integrated circuit design, and relates to the capacitance-to-voltage conversion interface circuit of capacitive MEMS inertial sensors. Specifically, it provides an inertial sensor interface circuit based on charge overlap and rebalancing, which can be widely used in automotive-grade inertial navigation, high-end industrial measurement and control, aerospace and other scenarios with stringent requirements for measurement accuracy, temperature stability and long-term bias reliability. Background Technology

[0002] Capacitive MEMS inertial sensors (especially accelerometers and gyroscopes) have advantages such as low temperature coefficient, low power consumption, low noise, high sensitivity, and easy monolithic integration with CMOS technology, making them core devices in the field of high-precision inertial measurement. The signal readout of capacitive MEMS inertial sensors relies on a capacitance-to-voltage converter (CTC) interface circuit. This interface circuit is the only bridge connecting the MEMS inertial sensor to the back-end analog signal processing link, and its performance directly determines the sensor's measurement accuracy, linearity, temperature stability, and long-term zero-point drift characteristics.

[0003] Currently, capacitance-to-voltage conversion interface circuits primarily employ an open-loop architecture. Their core principle lies in directly converting the capacitance change of a MEMS inertial sensor into a voltage signal through switched capacitor sampling, without a closed-loop feedback control mechanism. However, in engineering applications, especially those requiring wide temperature ranges, strong interference, and high precision, such interface circuits suffer from insurmountable architectural flaws. Firstly, the open-loop architecture lacks error suppression capabilities and exhibits extremely high parasitic capacitance sensitivity. It cannot achieve dynamic charge balance, allowing the inherent parasitic capacitance of the MEMS inertial sensor to directly enter the signal. This parasitic capacitance is typically much larger than the effective sensing capacitance change in the fF range, introducing severe nonlinear errors and hindering accurate compensation across the entire temperature range. Secondly, inherent hyperbolic nonlinearity cannot be eliminated, limiting the dynamic range. An inherent hyperbolic function nonlinearity exists between the change in sensing capacitance and the input physical quantity (acceleration / angular velocity). The lack of feedback linearization in the open-loop architecture leads to severe measurement distortion with large signal inputs, restricting the sensor's dynamic range. Third, the analog ground (AGND) is highly dependent, and noise and temperature drift are amplified throughout the entire process. The signal detection reference of the open-loop architecture is completely bound to the analog ground. The inherent noise floor, temperature drift, and power coupling interference of the analog ground will be amplified throughout the signal chain, directly degrading the accuracy of low-frequency measurement and long-term bias stability, and failing to meet the zero-point stability requirements for long-cycle operation. Fourth, it has insufficient low-frequency noise suppression capability and a significant signal-to-noise ratio bottleneck. The open-loop architecture cannot build a full-link noise suppression system, and has limited means to suppress the inherent flicker noise of operational amplifiers. The in-band signal-to-noise ratio is difficult to break through 120dB, and it cannot distinguish weak capacitance changes at the fF level. Some methods suppress flicker noise through chopper stabilization technology, but at the same time, they worsen the white noise substrate, resulting in a contradiction between performance trade-offs. Fifth, it has poor wide-temperature adaptability and insufficient reliability. The open-loop architecture is extremely sensitive to the temperature drift of device parameters. In high-temperature environments above 40℃, offset drift and gain drift will deteriorate significantly, making it unsuitable for automotive-grade and industrial-grade high-temperature applications ranging from -50℃ to 175℃. At the same time, it lacks on-chip self-test and overflow protection functions, and is prone to runaway behavior under extreme conditions.

[0004] In summary, although some existing technologies have attempted basic charge balance approaches, they have not developed mature, engineerable closed-loop circuit architectures, nor have they developed closed-loop interface circuits based on the principle of charge overlap and rebalancing. Therefore, this invention proposes an inertial sensor interface circuit based on charge overlap and rebalancing, which achieves dynamic charge rebalancing through closed-loop negative feedback, thus completely solving the inherent defects of the aforementioned open-loop architecture. Summary of the Invention

[0005] The purpose of this invention is to provide a high-precision inertial sensor interface circuit based on charge overlap rebalancing, so as to solve the inherent defects of the existing capacitor-to-voltage conversion interface circuit under the open-loop architecture.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] An inertial sensor interface circuit based on charge overlap and rebalancing includes: a charge balance dynamic bias module, a programmable compensation capacitor array, a gating switch module, a first single-ended capacitor voltage conversion module, a second single-ended capacitor voltage conversion module, a clock generation module, and a reference voltage generation module. Its core idea is to: achieve differential output and common-mode interference cancellation through time interleaving and multiplexing of two symmetrical single-ended branches; maintain a dynamic charge balance state through closed-loop negative feedback to achieve high-linearity voltage output; and achieve static compensation for parasitic capacitance and process mismatch, and dynamic suppression of low-frequency noise and temperature drift through a programmable compensation capacitor array and a related dual-sampling circuit.

[0008] The first single-ended capacitor voltage conversion module and the second single-ended capacitor voltage conversion module form a symmetrical branch. The two are alternately connected to the common terminal of the differential sensing capacitor pair in the inertial sensor through a gating switch module to obtain the differential output voltage, which is then fed back to the charge balance dynamic bias module.

[0009] The charge balance dynamic bias module and the programmable compensation capacitor array are connected to the differential sensing capacitor pair in the inertial sensor. The charge balance dynamic bias module generates a bias voltage signal with complementary polarity according to the feedback voltage, and applies it to the differential sensing capacitor pair and the programmable compensation capacitor array in the inertial sensor, thereby realizing charge balance and parasitic capacitance cancellation.

[0010] The clock generation module is used to generate the master clock and all switch control signals for the inertial sensor interface circuit.

[0011] The reference voltage generation module is used to generate a reference voltage to provide a common-mode bias voltage for the first single-ended capacitor voltage conversion module and the second single-ended capacitor voltage conversion module.

[0012] Furthermore, the clock generation module generates switch control signals p1 to p6, wherein switch control signals p1, p2, p3, and p4 form a four-phase non-overlapping clock, and the high levels of the four-phase non-overlapping clock appear sequentially and do not overlap; switch control signals p5 and p6 form a two-phase non-overlapping clock, wherein switch control signal p5 is an OR signal of switch control signals p1 and p2, and switch control signal p6 is an OR signal of switch control signals p3 and p4.

[0013] Furthermore, the differential sensing capacitor pair in the inertial sensor is composed of sensing capacitor C. S1 With sensing capacitor C S2It is connected in series, with the two ends being the first sensing capacitor plate terminal CT and the second sensing capacitor plate terminal CB, and the series node being the common terminal M;

[0014] The charge balance dynamic bias module includes a first switch network and a second switch network, and the programmable compensation capacitor array consists of compensation capacitor C. C1 With compensation capacitor C C2 The capacitors are connected in series, with the first compensation capacitor plate end CcT and the second compensation capacitor plate end CcB at their two ends. The series node is connected to the common terminal M of the differential sensing capacitor pair. The first compensation capacitor plate end CcT and the first sensing capacitor plate end CT are connected to the first switching network, and the second compensation capacitor plate end CcB and the second sensing capacitor plate end CB are connected to the second switching network.

[0015] The first switch network and the second switch network are each composed of four sets of switches. According to the timing sequence, the first sensing capacitor plate terminal CT, the second sensing capacitor plate terminal CB, the first compensation capacitor plate terminal CcT, and the second compensation capacitor plate terminal CcB are connected to the power supply voltage VSS, the power supply voltage VDD, the output voltage Vout_p, and the output voltage Vout_n.

[0016] Furthermore, in the charge balance dynamic bias module:

[0017] When the switch control signal p1 is high, the first sensing capacitor plate terminal CT in the differential sensing capacitor pair is connected to the power supply voltage VDD, the second sensing capacitor plate terminal CB is connected to the power supply voltage VSS, and the first compensation capacitor plate terminal CcT and the second compensation capacitor plate terminal CcB in the programmable compensation capacitor array are both connected to the output voltage Vout_p.

[0018] When the switch control signal p2 is high, the first sensing capacitor plate terminal CT and the second sensing capacitor plate terminal CB in the differential sensing capacitor pair are both connected to the output voltage Vout_p. In the programmable compensation capacitor array, the first compensation capacitor plate terminal CcT is connected to the power supply voltage VDD, and the second compensation capacitor plate terminal CcB is connected to the power supply voltage VSS.

[0019] When the switch control signal p3 is high, the first sensing capacitor plate terminal CT in the differential sensing capacitor pair is connected to the power supply voltage VSS, the second sensing capacitor plate terminal CB is connected to the power supply voltage VDD, and the first compensation capacitor plate terminal CcT and the second compensation capacitor plate terminal CcB in the programmable compensation capacitor array are both connected to the output voltage Vout_n.

[0020] When the switch control signal p4 is high, the first sensing capacitor plate terminal CT and the second sensing capacitor plate terminal CB in the differential sensing capacitor pair are both connected to the output voltage Vout_n. In the programmable compensation capacitor array, the first compensation capacitor plate terminal CcT is connected to the power supply voltage VSS, and the second compensation capacitor plate terminal CcB is connected to the power supply voltage VDD.

[0021] Furthermore, the selection switch module consists of control switch s1 and control switch s2, and is controlled by switch control signal p5 and switch control signal p6. Control switch s1 is connected to the first single-ended capacitor voltage conversion module, and control switch s2 is connected to the second single-ended capacitor voltage conversion module.

[0022] Furthermore, the first single-ended capacitor voltage conversion module includes a first-stage integrator and a second-stage integrator, and each integrator is equipped with a CDS circuit.

[0023] The first-stage integrator includes: operational amplifier OPA1 and integrating capacitor C. i1 CDS capacitor C off1 And control switches S3 to S6; CDS capacitor C off1 The left end is connected to the input terminal of the first single-ended capacitor voltage conversion module, and the right end is connected to the inverting input terminal of the operational amplifier OPA1; the integrating capacitor C i1 The left end is connected to the input terminal of the first single-ended capacitor voltage conversion module via control switch S4, and the right end is connected to the output terminal of operational amplifier OPA1, with the integrating capacitor C... i1 A control switch s5 is set between the two ends; a control switch s6 is set between the output terminal and the inverting input terminal of operational amplifier OPA1; the non-inverting input terminal of operational amplifier OPA1 is connected to the output voltage Vout_p to form a feedback path; the input terminal of the first single-ended capacitor voltage conversion module is connected to the output voltage Vout_p through a control switch s3 to form a feedback path.

[0024] The second-stage integrator includes: sampling capacitor C ss1 Operational amplifier OPA2, integrating capacitor C i2 CDS capacitor C off2 and control switch S7~ control switch S 13 Among them, the sampling capacitor C ss1 and control switches S7, S8, S9, S 11 This constitutes a voltage sampling module, consisting of operational amplifier OPA2 and integrating capacitor C. i2 Constructing an integrator, CDS capacitor C off2 and control switch s 10 s 12 s 13 Constructing a CDS circuit; sampling capacitor C ss1The left end is connected to the output of the first-stage integrator via control switch S7, and simultaneously connected to the reference voltage AGND via control switch S8; sampling capacitor C ss1 The right end is controlled by switch S 11 Connect CDS capacitor C off2 The left end is simultaneously connected to the output voltage Vout_p via control switch s9, forming a feedback path; CDS capacitor C off2 The left end is controlled by switch s 10 Connect the reference voltage AGND and the CDS capacitor C. off2 The right end is connected to the inverting input of operational amplifier OPA2; integrating capacitor C i2 The left end is controlled by switch s 12 Connect CDS capacitor C off2 On the left end, simultaneously via control switch s 13 Connect the inverting input of operational amplifier OPA2; integrating capacitor C i2 The right end is connected to the output of operational amplifier OPA2. The non-inverting input of operational amplifier OPA2 is connected to the reference voltage AGND. The output of operational amplifier OPA2 serves as the output of the first single-ended capacitor voltage conversion module.

[0025] Furthermore, when the switch control signal p1 is high, control switches s3 and s6 are closed, and the CDS capacitor C... off1 The error signal of the sampling operational amplifier OPA1 is sampled. At the same time, the control switch S5 is closed, and the integrating capacitor C... i1 The circuit is short-circuited for discharge; when the switch control signal p2 is high, the control switch s4 closes, and the induced charge at the common terminal is input to the integrating capacitor C. i1 CDS capacitor C off1 CDS capacitor C off1 When the signal link is connected, the error signal is canceled out, and the induced charge is transferred by the integrating capacitor C. i1 The result is integrated and converted into a voltage change at the output of operational amplifier OPA1, which is then output to the second-stage integrator.

[0026] Furthermore, when the switch control signal p2 is high, switches s7 and s9 are closed, and the sampling capacitor C... ss1 The sampling operation amplifier OPA1 output voltage; when the switch control signal p1 is high, it controls switches s8 and s9. 11 Close, sampling capacitor C ss1 The sampled voltage is integrated by operational amplifier OPA2 to obtain the output voltage Vout_p; simultaneously, when the switch control signal p3 is high, the switch s is controlled. 10 s 13 Closed, CDS capacitor C off2The error signal of the sampling operational amplifier OPA2 is used to control switch s at the other times when the switch control signal p3 is low. 12 All closed, CDS capacitor C off2 Error cancellation is achieved by connecting to the signal link.

[0027] Furthermore, the reference voltage generation module employs a chopper-stabilized AGND generation circuit.

[0028] Based on the above technical solution, the beneficial effect of the present invention is that it provides an inertial sensor interface circuit based on charge overlap rebalancing, which has the following advantages:

[0029] 1) Adopting a closed-loop architecture eliminates inherent nonlinearity at its source;

[0030] This invention creatively proposes a closed-loop structure based on charge overlap balance loop (CSBL), which is completely different from the open-loop architecture in the prior art. It achieves essential linearization through dynamic charge rebalancing, which greatly expands the dynamic range of the sensor.

[0031] 2) Parasitic capacitance is fully compensated, achieving ultra-high robustness;

[0032] This invention precisely counteracts the effects of MEMS parasitic capacitance and process mismatch by using a programmable compensation capacitor array, completely eliminating the influence of parasitic capacitance from the transfer function and solving the most critical performance bottleneck in the open-loop architecture.

[0033] 3) Completely eliminates reference voltage dependence, significantly improving long-term stability;

[0034] This invention adopts a pseudo-differential closed-loop architecture, which fundamentally breaks the strong binding of signal detection to the reference voltage AGND, avoids the amplification effect of AGND noise and temperature drift, and reduces the long-term zero-point drift by more than an order of magnitude compared with the open-loop structure, meeting the high reliability requirements of long-cycle operation.

[0035] 4) End-to-end noise suppression achieves ultra-high signal-to-noise ratio;

[0036] This invention employs full-link CDS technology to reduce 1 / f flicker noise power by 10 times without worsening white noise, and can accurately distinguish weak capacitance changes at the fF level.

[0037] 5) Strong adaptability to a wide temperature range, covering extreme operating conditions;

[0038] This invention adopts a closed-loop wide temperature range design, which can work stably in the temperature range of -50℃ to 175℃, fully meeting the needs of automotive-grade and industrial-grade high-temperature application scenarios;

[0039] 6) High integration and high flexibility reduce engineering costs;

[0040] This invention can integrate a full range of functional modules, including an oscillator clock module, programmable gain, programmable bandwidth, on-chip self-test, and overflow protection, without the need for complex external components. It can be directly adapted to MEMS sensors and subsequent ADC devices with different ranges. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of an inertial sensor interface circuit based on charge overlap and rebalancing.

[0042] Figure 2 This is a circuit schematic of an inertial sensor interface circuit based on charge overlap and rebalancing.

[0043] Figure 3 This is a circuit timing diagram of an inertial sensor interface circuit based on charge overlap and rebalancing. Detailed Implementation

[0044] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0045] This embodiment provides an inertial sensor interface circuit based on charge swapping and rebalancing, abbreviated as CSBL (Charge Swap Balancing Loop) circuit, such as... Figure 1 and Figure 2 As shown, it includes: a charge balance dynamic bias module, a programmable compensation capacitor array, a gating switch module, a first single-ended capacitor voltage conversion module, a second single-ended capacitor voltage conversion module, a clock generation module, and a reference voltage generation module.

[0046] To achieve differential output, the first single-ended capacitor voltage conversion module and the second single-ended capacitor voltage conversion module form a symmetrical branch. The two are alternately connected to the common terminal of the differential sensing capacitor pair in the inertial sensor through a gating switch module to obtain the differential output voltage, which is then fed back to the charge balance dynamic bias module.

[0047] The charge balance dynamic bias module and the programmable compensation capacitor array are connected together to the differential sensing capacitor pair in the inertial sensor. The charge balance dynamic bias module establishes a controlled plate potential on the differential sensing capacitor pair based on the switching timing and feedback voltage to achieve charge balance. At the same time, it establishes a voltage drop condition with complementary polarity on the programmable compensation capacitor array to inject a charge change of opposite polarity into the common node to counteract the effects of parasitic capacitance, etc.

[0048] Furthermore, the clock generation module is used to generate the switching control signals for the inertial sensor interface circuit, generate the main clock of the CSBL circuit, and generate switching control signals p1 to p6, such as... Figure 3 As shown; to avoid charge sharing or short circuits caused by adjacent clock phases being active simultaneously, switch control signals p1, p2, p3, and p4 are configured as a four-phase clock with non-overlapping characteristics. Specifically, the period of each clock phase is the system master clock period T, and the high-level pulse width W satisfies the relationship: W = T / 4 - t no , t no The high levels of the four non-overlapping clocks appear sequentially and do not overlap; the switch control signal p5 and the switch control signal p6 form a two-phase non-overlapping clock. The switch control signal p5 is the OR signal of the switch control signal p1 and the switch control signal p2, and the switch control signal p6 is the OR signal of the switch control signal p3 and the switch control signal p4.

[0049] The reference voltage generation module is used to generate a reference voltage to provide a common-mode bias voltage for the first single-ended capacitor voltage conversion module and the second single-ended capacitor voltage conversion module. This module uses a chopper-stabilized AGND generation circuit to generate the reference voltage AGND, which provides a common-mode bias voltage for the operational amplifiers in the two single-ended capacitor voltage conversion modules, typically (VDD+VSS) / 2.

[0050] Furthermore, the charge balance dynamic bias module and the programmable compensation capacitor array are connected to the differential sensing capacitor pair of the external inertial sensor.

[0051] The differential sensing capacitor in the inertial sensor is controlled by the sensing capacitor C. S1 With sensing capacitor C S2 Series connection, sensing capacitor C S1 The upper plate serves as the first sensing capacitor plate terminal CT, and the sensing capacitor C S1 With sensing capacitor C S2 The series node is used as the common terminal M, and the sensing capacitor C S2 The lower electrode plate serves as the second sensing capacitor electrode plate end CB;

[0052] The charge balance dynamic bias module includes a first switch network and a second switch network, and the programmable compensation capacitor array consists of compensation capacitor C. C1 With compensation capacitor C C2 Series connection, compensation capacitor C C1 The upper-level board is the first compensation capacitor plate terminal CcT, and the compensation capacitor C C2 The lower stage board is the second compensation capacitor plate terminal CcB, and the compensation capacitor C C1 With compensation capacitor C C2The series node connects to the common terminal M of the differential sensing capacitor pair, and the output of the programmable compensation capacitor array is led out from this node to connect to the subsequent module; the first switch network is connected between the first compensation capacitor plate terminal CcT and the first sensing capacitor plate terminal CT, and the second switch network is connected between the second compensation capacitor plate terminal CcB and the second sensing capacitor plate terminal CB.

[0053] The first and second switch networks each consist of four sets of switches. According to the timing sequence, CT, CB, CcT, and CcB are connected to the power supply voltage VSS, the power supply voltage VDD, the output voltage Vout_p, and the output voltage Vout_n. The output voltage Vout_p and the output voltage Vout_n serve as feedback voltages to form a feedback loop.

[0054] When the switch control signal p1 is high, the differential sensing capacitor CT is connected to the power supply voltage VDD, and CB is connected to the power supply voltage VSS. In the programmable compensation capacitor array, CcT and CcB are both connected to the output voltage Vout_p.

[0055] When the switch control signal p2 is high, the differential sensing capacitor pair CT and CB are both connected to the output voltage Vout_p. In the programmable compensation capacitor array, CcT is connected to the power supply voltage VDD and CcB is connected to the power supply voltage VSS.

[0056] When the switch control signal p3 is high, the differential sensing capacitor CT is connected to the power supply voltage VSS, and CB is connected to the power supply voltage VDD. In the programmable compensation capacitor array, CcT and CcB are both connected to the output voltage Vout_n.

[0057] When the switch control signal p4 is high, the differential sensing capacitor pair CT and CB are both connected to the output voltage Vout_n. In the programmable compensation capacitor array, CcT is connected to the power supply voltage VSS, and CcB is connected to the power supply voltage VDD.

[0058] As can be seen from the above, in this embodiment, the differential output voltages Vout_p and Vout_n of the inertial sensor interface circuit are fed back to the charge balance dynamic bias module (the first switch network and the second switch network) to form a feedback loop. The output voltages Vout_p and Vout_n act on the first plate terminal CT and the second plate terminal CB of the differential sensing capacitor pair, dynamically adjusting the voltage between the plates of the differential sensing capacitor. Then, through the negative feedback loop, the net charge on the common terminal M of the differential sensing capacitor pair is adjusted to zero, and the charge balance state is re-entered, thereby achieving high linearity output of the interface circuit. At the same time, the voltage between the plates of the compensation capacitor in the programmable compensation capacitor array is also dynamically adjusted by the feedback loop, and the control timing is interleaved with the control timing of the sensing capacitor plate voltage. This allows the programmable compensation capacitor array to inject a counteracting charge of opposite polarity (compared to the charge injected by the differential sensing capacitor pair at the common terminal M). By adapting the programmable adjustment of the compensation capacitor value, the influence of static errors such as sensing capacitor mismatch and parallel parasitic capacitance can be offset at the sensing capacitor, achieving static calibration.

[0059] Furthermore, the selection switch module consists of control switch S1 and control switch S2, which are controlled by two complementary and non-overlapping switch control signals P5 and P6, respectively. This allows the induced charge accumulated at the common terminal M to be alternately input to the first single-ended capacitor voltage conversion module and the second single-ended capacitor voltage conversion module. One end of control switch S1 is connected to the common terminal M, and the other end is connected to the input terminal of the first single-ended capacitor voltage conversion module. One end of control switch S2 is connected to the common terminal M, and the other end is connected to the input terminal of the second single-ended capacitor voltage conversion module. During operation, when switch control signal P5 is high, the induced charge accumulated at the common terminal M is input to the first single-ended capacitor voltage conversion module through control switch S1; when switch control signal P6 is high, the induced charge accumulated at the common terminal M is input to the second single-ended capacitor voltage conversion module through control switch S2. This allows for the alternating selection of two completely symmetrical single-ended signal paths in time, achieving differential output.

[0060] Furthermore, the first single-ended capacitor voltage conversion module and the second single-ended capacitor voltage conversion module adopt a symmetrical structure, and the control clock phases are 180° apart.

[0061] The first single-ended capacitor voltage conversion module operates when the control switch s1 is turned on, corresponding to the first half of the control cycle: switch control signal p1 and switch control signal p2; specifically, it includes: a first-stage integrator and a second-stage integrator, and each integrator is equipped with a CDS circuit.

[0062] The first-stage integrator includes: operational amplifier OPA1 and integrating capacitor C. i1 CDS capacitor C off1And control switches s3 to s6, including operational amplifier OPA1 and integrating capacitor C. i1 Together with control switch S5, they form an integrator, and CDS capacitor C... off1 The control switches S3, S4, and S6 form a CDS circuit; the CDS capacitor C off1 The left end is connected to the input terminal of the first single-ended capacitor voltage conversion module, and the right end is connected to the inverting input terminal of the operational amplifier OPA1; the integrating capacitor C i1 The left end is connected to the input terminal of the first single-ended capacitor voltage conversion module via control switch S4, and the right end is connected to the output terminal of operational amplifier OPA1, with the integrating capacitor C... i1 A control switch s5 is set between the two ends; a control switch s6 is set between the output terminal and the inverting input terminal of operational amplifier OPA1; the non-inverting input terminal of operational amplifier OPA1 is connected to the output voltage Vout_p to form a feedback path; the input terminal of the first single-ended capacitor voltage conversion module is connected to the output voltage Vout_p through a control switch s3 to form a feedback path.

[0063] When the switch control signal p1 is high, control switches s3 and s6 are closed, and the CDS capacitor C... off1 The sampling operational amplifier OPA1 samples error signals such as offset voltage and 1 / f noise. Simultaneously, control switch S5 closes, and the integrating capacitor C... i1 The circuit is short-circuited for discharge; when the switch control signal p2 is high, the control switch s4 closes, and the induced charge output from the common terminal M is input to the integrating capacitor C. i1 CDS capacitor C off1 CDS capacitor C off1 When the signal link is connected, the error signal is canceled out, and the induced signal is controlled by the integrating capacitor C. i1 The result is integrated and converted into a voltage change at the output of operational amplifier OPA1, which is then output to the second-stage integrator.

[0064] The second-stage integrator includes: sampling capacitor C ss1 Operational amplifier OPA2, integrating capacitor C i2 CDS capacitor C off2 and control switch S7~ control switch S 13 Among them, the sampling capacitor C ss1 and control switches S7, S8, S9, S 11 This constitutes a voltage sampling module, consisting of operational amplifier OPA2 and integrating capacitor C. i2 Constructing an integrator, CDS capacitor C off2 and control switch s 10 s 12 s 13 Constructing a CDS circuit; sampling capacitor C ss1The left end is connected to the output of the first-stage integrator (i.e., the output of operational amplifier OPA1) via control switch S7, and simultaneously connected to the reference voltage AGND via control switch S8; sampling capacitor C ss1 The right end is controlled by switch S 11 Connect CDS capacitor C off2 The left end is simultaneously connected to the output voltage Vout_p via control switch s9, forming a feedback path; CDS capacitor C off2 The left end is controlled by switch s 10 Connect the reference voltage AGND and the CDS capacitor C. off2 The right end is connected to the inverting input of operational amplifier OPA2; integrating capacitor C i2 The left end is controlled by switch s 12 Connect CDS capacitor C off2 On the left end, simultaneously via control switch s 13 Connect the inverting input of operational amplifier OPA2; integrating capacitor C i2 The right end is connected to the output of operational amplifier OPA2. The non-inverting input of operational amplifier OPA2 is connected to the reference voltage AGND. The output of operational amplifier OPA2 serves as the output of the first single-ended capacitor voltage conversion module.

[0065] When the switch control signal p2 is high, the control switches s7 and s9 are closed, and the sampling capacitor C... ss1 The sampling operation amplifier OPA1 output voltage; when the switch control signal p1 is high, it controls switches s8 and s9. 11 Close, sampling capacitor C ss1 The sampled voltage is integrated by operational amplifier OPA2 to obtain the output voltage Vout_p; simultaneously, when the switch control signal p3 is high, the switch s is controlled. 10 s 13 Closed, CDS capacitor C off2 The sampling operational amplifier OPA2 samples error signals such as offset voltage and 1 / f noise. During the remaining times when the switch control signal p3 is low, the switch s is controlled. 12 All closed, CDS capacitor C off2 Error cancellation is achieved by connecting to the signal link.

[0066] Correspondingly, the second single-ended capacitor voltage conversion module operates when the control switch s2 is turned on, corresponding to the second half of the control cycle: switch control signal p3 and switch control signal p4; wherein, operational amplifier OPA3 and integrating capacitor C i3 CDS capacitor bank C off3 and control switch s 14 ~s 17 The first-stage integrator is constructed using sampling capacitor C.ss2 Operational amplifier OPA4, integrating capacitor C i4 CDS capacitor bank C off4 and control switch s 18 ~s 24 This forms the second-stage integrator; the circuit connection of the corresponding components is completely consistent with that of the first single-ended capacitor voltage conversion module, and the switch control signal p3 corresponds to the switch control signal p1, and the switch control signal p4 corresponds to the switch control signal p2.

[0067] As can be seen from the above circuit structure and control timing, when control switches s1 and s2 are respectively turned on, the polarities of the bias voltage signals applied to the plates of the sensing capacitor by the first switch network and the second switch network are complementary, that is, the driving polarities on the input sensing capacitor are opposite. Therefore, the signal connected to the input terminal of the second single-ended capacitor voltage conversion module is opposite in polarity to that of the first single-ended capacitor voltage conversion module. Thus, the output voltages obtained by the two single-ended capacitor voltage conversion modules constitute a differential output pair.

[0068] In summary, this invention provides an inertial sensor interface circuit based on charge overlap and rebalancing, where the differential sensing capacitor C of the external MEMS sensor... S1 C S2 The three circuit nodes (CT at the first sensing capacitor plate, CB at the second sensing capacitor plate, and the common terminal M) connect the charge balance dynamic bias module and the programmable compensation capacitor array. The charge balance dynamic bias module dynamically adjusts the voltage on the two plates of CT and CB through two switching networks, thereby achieving charge rebalancing through a negative feedback loop; at the same time, a programmable compensation capacitor C is introduced in series. C1 C C2 This is used to eliminate the influence of parasitic capacitance. Furthermore, the common terminal M is alternately connected to the input terminals of the first single-ended capacitor voltage conversion module and the second single-ended capacitor voltage conversion module through a gating switch module. The two single-ended capacitor voltage conversion modules are completely symmetrical in structure and each contains two stages of integrator circuits with CDS circuits. The output terminals of the two modules serve as the differential output terminals of the CSBL circuit, outputting differential voltage signals Vout_p and Vout_n. This differential output voltage serves as a feedback signal, feeding back to the charge balance dynamic bias and the first stage integrator of the single-ended capacitor voltage conversion module, forming a complete negative feedback loop to achieve high linearity voltage output.

[0069] The above description is merely a specific embodiment of the present invention. Any feature disclosed in this specification may be replaced by other equivalent or similar features unless otherwise specified. All disclosed features, or steps in all methods or processes, may be combined in any way except for mutually exclusive features and / or steps.

Claims

1. An inertial sensor interface circuit based on charge overlap and rebalancing, characterized in that, include: The system includes a charge balance dynamic bias module, a programmable compensation capacitor array, a gating switch module, a first single-ended capacitor voltage conversion module, a second single-ended capacitor voltage conversion module, a clock generation module, and a reference voltage generation module. The first single-ended capacitor voltage conversion module and the second single-ended capacitor voltage conversion module form a symmetrical branch. The two are alternately connected to the common terminal of the differential sensing capacitor pair in the inertial sensor through a gating switch module to obtain the differential output voltage, which is then fed back to the charge balance dynamic bias module. The charge balance dynamic bias module and the programmable compensation capacitor array are connected to the differential sensing capacitor pair in the inertial sensor. The charge balance dynamic bias module generates a bias voltage signal with complementary polarity according to the feedback voltage, and applies it to the differential sensing capacitor pair and the programmable compensation capacitor array in the inertial sensor, thereby realizing charge balance and parasitic capacitance cancellation. The clock generation module is used to generate the master clock and all switch control signals for the inertial sensor interface circuit. The reference voltage generation module is used to generate a reference voltage to provide a common-mode bias voltage for the first single-ended capacitor voltage conversion module and the second single-ended capacitor voltage conversion module. The clock generation module generates switch control signals p1 to p6. Switch control signals p1, p2, p3, and p4 form a four-phase non-overlapping clock, with the high levels of the four-phase non-overlapping clock appearing sequentially and without overlap. Switch control signals p5 and p6 form a two-phase non-overlapping clock. Switch control signal p5 is the OR signal of switch control signals p1 and p2, and switch control signal p6 is the OR signal of switch control signals p3 and p4. The differential sensing capacitor in the inertial sensor is controlled by the sensing capacitor C. S1 With sensing capacitor C S2 It is connected in series, with the two ends being the first sensing capacitor plate terminal CT and the second sensing capacitor plate terminal CB, and the series node being the common terminal M; The charge balance dynamic bias module includes a first switch network and a second switch network, and the programmable compensation capacitor array consists of compensation capacitor C. C1 With compensation capacitor C C2 The capacitors are connected in series, with the first compensation capacitor plate end CcT and the second compensation capacitor plate end CcB at their two ends. The series node is connected to the common terminal M of the differential sensing capacitor pair. The first compensation capacitor plate end CcT and the first sensing capacitor plate end CT are connected to the first switching network, and the second compensation capacitor plate end CcB and the second sensing capacitor plate end CB are connected to the second switching network. The first switch network and the second switch network are each composed of four sets of switches. According to the timing sequence, the first sensing capacitor plate terminal CT, the second sensing capacitor plate terminal CB, the first compensation capacitor plate terminal CcT, and the second compensation capacitor plate terminal CcB are connected to the power supply voltage VSS, the power supply voltage VDD, the output voltage Vout_p, and the output voltage Vout_n. In the charge balance dynamic bias module: When the switch control signal p1 is high, the first sensing capacitor plate terminal CT in the differential sensing capacitor pair is connected to the power supply voltage VDD, the second sensing capacitor plate terminal CB is connected to the power supply voltage VSS, and the first compensation capacitor plate terminal CcT and the second compensation capacitor plate terminal CcB in the programmable compensation capacitor array are both connected to the output voltage Vout_p. When the switch control signal p2 is high, the first sensing capacitor plate terminal CT and the second sensing capacitor plate terminal CB in the differential sensing capacitor pair are both connected to the output voltage Vout_p. In the programmable compensation capacitor array, the first compensation capacitor plate terminal CcT is connected to the power supply voltage VDD, and the second compensation capacitor plate terminal CcB is connected to the power supply voltage VSS. When the switch control signal p3 is high, the first sensing capacitor plate terminal CT in the differential sensing capacitor pair is connected to the power supply voltage VSS, the second sensing capacitor plate terminal CB is connected to the power supply voltage VDD, and the first compensation capacitor plate terminal CcT and the second compensation capacitor plate terminal CcB in the programmable compensation capacitor array are both connected to the output voltage Vout_n. When the switch control signal p4 is high, the first sensing capacitor plate terminal CT and the second sensing capacitor plate terminal CB in the differential sensing capacitor pair are both connected to the output voltage Vout_n. In the programmable compensation capacitor array, the first compensation capacitor plate terminal CcT is connected to the power supply voltage VSS, and the second compensation capacitor plate terminal CcB is connected to the power supply voltage VDD. The selection switch module consists of control switch s1 and control switch s2, and is controlled by switch control signal p5 and switch control signal p6. Control switch s1 is connected to the first single-ended capacitor voltage conversion module, and control switch s2 is connected to the second single-ended capacitor voltage conversion module.

2. The inertial sensor interface circuit based on charge overlap rebalancing according to claim 1, characterized in that, The first single-ended capacitor voltage conversion module includes a first-stage integrator and a second-stage integrator, and each integrator is equipped with a CDS circuit. The first-stage integrator includes: operational amplifier OPA1 and integrating capacitor C. i1 CDS capacitor C off1 And control switches S3 to S6; CDS capacitor C off1 The left end is connected to the input terminal of the first single-ended capacitor voltage conversion module, and the right end is connected to the inverting input terminal of the operational amplifier OPA1; the integrating capacitor C i1 The left end is connected to the input terminal of the first single-ended capacitor voltage conversion module via control switch S4, and the right end is connected to the output terminal of operational amplifier OPA1, with the integrating capacitor C... i1 A control switch s5 is set between the two ends; a control switch s6 is set between the output terminal and the inverting input terminal of operational amplifier OPA1; the non-inverting input terminal of operational amplifier OPA1 is connected to the output voltage Vout_p to form a feedback path; the input terminal of the first single-ended capacitor voltage conversion module is connected to the output voltage Vout_p through a control switch s3 to form a feedback path. The second-stage integrator includes: sampling capacitor C ss1 Operational amplifier OPA2, integrating capacitor C i2 CDS capacitor C off2 and control switch S7~ control switch S 13 Among them, the sampling capacitor C ss1 and control switches S7, S8, S9, S 11 This constitutes a voltage sampling module, consisting of operational amplifier OPA2 and integrating capacitor C. i2 Constructing an integrator, CDS capacitor C off2 and control switch s 10 s 12 s 13 Constructing a CDS circuit; sampling capacitor C ss1 The left end is connected to the output of the first-stage integrator via control switch S7, and simultaneously connected to the reference voltage AGND via control switch S8; sampling capacitor C ss1 The right end is controlled by switch s 11 Connect CDS capacitor C off2 The left end is simultaneously connected to the output voltage Vout_p via control switch s9, forming a feedback path; CDS capacitor C off2 The left end is controlled by switch s 10 Connect the reference voltage AGND and the CDS capacitor C. off2 The right end is connected to the inverting input of operational amplifier OPA2; integrating capacitor C i2 The left end is controlled by switch s 12 Connect CDS capacitor C off2 On the left end, simultaneously via control switch s 13 Connect the inverting input of operational amplifier OPA2; integrating capacitor C i2 The right end is connected to the output of operational amplifier OPA2. The non-inverting input of operational amplifier OPA2 is connected to the reference voltage AGND. The output of operational amplifier OPA2 serves as the output of the first single-ended capacitor voltage conversion module.

3. The inertial sensor interface circuit based on charge overlap rebalancing according to claim 2, characterized in that, When the switch control signal p1 is high, control switches s3 and s6 are closed, and the CDS capacitor C... off1 The error signal of the sampling operational amplifier OPA1 is measured, and at the same time, the control switch S5 is closed, and the integrating capacitor C... i1 Short-circuited discharge; when the switch control signal p2 is high, the control switch s4 closes, and the induced charge at the common terminal M is input to the integrating capacitor C. i1 CDS capacitor C off1 CDS capacitor C off1 Error cancellation is achieved by connecting to the signal link; the induced charge is controlled by the integrating capacitor C. i1 The result is integrated and converted into a voltage change at the output of operational amplifier OPA1, which is then output to the second-stage integrator.

4. The inertial sensor interface circuit based on charge overlap rebalancing according to claim 2, characterized in that, When the switch control signal p2 is high, the control switches s7 and s9 are closed, and the sampling capacitor C... ss1 The sampling operation amplifier OPA1 output voltage; when the switch control signal p1 is high, it controls switches s8 and s9. 11 Close, sampling capacitor C ss1 The sampled voltage is integrated by operational amplifier OPA2 to obtain the output voltage Vout_p; simultaneously, when the switch control signal p3 is high, the switch s is controlled. 10 s 13 Closed, CDS capacitor C off2 The error signal of the sampling operational amplifier OPA2 is used to control switch s at the other times when the switch control signal p3 is low. 12 All closed, CDS capacitor C off2 Error cancellation is achieved by connecting to the signal link.

5. The inertial sensor interface circuit based on charge overlap rebalancing according to claim 1, characterized in that, The reference voltage generation module uses a chopper-stabilized AGND generation circuit.

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