Transistor, display panel and display device

Abstract

This application provides a transistor, a display panel, and a display device. The transistor includes a source / drain electrode and an active portion. The active portion includes a first semiconductor layer and a second semiconductor layer stacked together. The second semiconductor layer is located on the side of the first semiconductor layer away from the source / drain electrode film. The first semiconductor layer includes a first crystalline oxide, and the second semiconductor layer includes a second crystalline oxide. The crystallinity of the first crystalline oxide is c1, and the crystallinity of the second crystalline oxide is c2, where 0 < c1 - c2 ≤ 30%. This design implies a small difference in crystallinity between the first and second semiconductor layers, which helps to enhance the induced growth effect of the crystalline oxide in the second semiconductor layer on the crystalline oxide in the first semiconductor layer. This further improves the overall stability of the active portion, thereby enabling the transistor to possess both high carrier mobility and high stability.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a transistor, a display panel, and a display device. Background Technology

[0002] To meet the requirements of high carrier mobility and high stability, current transistor designs commonly employ bilayer semiconductor structures formed by stacking low-mobility, high-stability amorphous oxide layers and high-mobility, low-stability amorphous oxide layers. With advancements in semiconductor materials research, crystalline oxide semiconductors have begun to exhibit higher carrier mobility, leading to increasing interest in replacing amorphous oxides with crystalline oxides for use in the aforementioned bilayer semiconductor structures.

[0003] However, compared to the bilayer amorphous oxide layer structure, the characteristic that the crystal states of the two crystalline oxide layers in the bilayer crystalline oxide layer structure can easily influence each other places higher demands on the bilayer oxide semiconductor structure. Summary of the Invention

[0004] This application provides a transistor, a display panel, and a display device to optimize the balance between the mutual influence of the crystal states between the two semiconductor layers within the transistor and the transistor performance.

[0005] In view of this, this application provides a transistor including a source and a drain and an active portion. The active portion includes a first semiconductor layer and a second semiconductor layer stacked together, and the second semiconductor layer is located on the side of the first semiconductor layer away from the film layer where the source and drain are located.

[0006] The first semiconductor layer comprises a first crystalline oxide, and the second semiconductor layer comprises a second crystalline oxide. The crystallinity of the first crystalline oxide is c1, and the crystallinity of the second crystalline oxide is c2, where 0 < c1 - c2 ≤ 30%.

[0007] Based on the same inventive concept, this application also provides a display panel including the aforementioned transistor.

[0008] Based on the same inventive concept, this application also provides a display device, including the above-mentioned display panel.

[0009] Compared with the prior art, the transistor, display panel, and display device provided by the present invention achieve at least the following beneficial effects: In this embodiment, the design of c1-c2 ≤ 30% implies a smaller difference in crystallinity between the first and second semiconductor layers. This helps to enhance the induced growth effect of the crystalline oxide in the second semiconductor layer on the crystalline oxide in the first semiconductor layer, which is beneficial to further improving the overall stability of the active part, thereby achieving a transistor with both high carrier mobility and high stability. Furthermore, the crystallinity of the crystalline oxide can affect the carrier mobility of the semiconductor layer to a certain extent. To meet the requirement of a difference in carrier mobility between the first and second semiconductor layers, this embodiment limits c1-c2 to > 0 to achieve a design where the carrier mobility of the first semiconductor layer is greater than that of the second semiconductor layer, thereby further improving the stability characteristics of the transistor. Attached Figure Description

[0010] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A schematic diagram of a transistor portion structure provided in this application; Figure 2 For preparation Figure 1 A schematic diagram of some steps in the transistor process shown; Figure 3 This is a schematic diagram illustrating the fabrication process of the first semiconductor layer and the second semiconductor layer; Figure 4 A schematic diagram of a partial structure of a display panel provided in this application; Figure 5 for Figure 4 The diagram shows a partial structure of the pixel circuitry within the display panel and the connection relationship between the light-emitting devices. Figure 6 for Figure 4 The diagram shows the equivalent circuit diagram of the pixel circuit within the display panel. Figure 7 This is a schematic diagram of a display device provided in this application. Detailed Implementation

[0012] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0013] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0014] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0015] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0016] In related technologies, amorphous oxide semiconductors (AOS) have become one of the candidate materials for fabricating high-performance semiconductor devices due to their high carrier mobility, low off-state current, excellent optical transparency, and low processing temperature requirements. To meet the functional requirements of both high carrier mobility and high stability, a double-layer semiconductor structure is often used to fabricate semiconductor devices. This double-layer structure consists of two stacked layers: a low-mobility, high-stability amorphous oxide film and a high-mobility, low-stability amorphous oxide film.

[0017] However, with the emergence of new industries (such as 5G communication, artificial intelligence, and virtual reality), the mobility of amorphous oxide semiconductor materials can no longer sustainably meet technological demands. Conversely, with the continuous progress in semiconductor material research, crystalline oxide semiconductor materials have begun to exhibit higher mobility characteristics. Therefore, using crystalline oxide semiconductor materials as the material basis for bilayer semiconductor structure designs has become an inevitable trend. It is important to note that the crystallization states of the two crystalline oxide semiconductor layers can easily interfere with each other, potentially interfering with the performance of semiconductor devices. Therefore, how to reduce the impact of crystallization state interference between the two crystalline oxide layers on semiconductor devices while achieving high mobility using crystalline oxide semiconductor materials has become one of the urgent problems to be solved.

[0018] Figure 1 This is a schematic diagram of a transistor portion structure provided in this application. Figure 2 For preparation Figure 1 The diagram shows a partial step of the transistor operation.

[0019] To address the aforementioned problems, this application provides a transistor 10, such as... Figure 1 As shown, transistor 10 includes source and drain terminals 01 and an active portion 02. The source and drain terminals 01 may include a first electrode 011 and a second electrode 012, which can be the source and drain of transistor 10, respectively. When transistor 10 is turned on, the first electrode 011 and the second electrode 012 are electrically connected through the active portion 02. Specifically, when the gate 03 of transistor 10 receives an enable signal, a channel can appear in the portion of the active portion 02 located between the first electrode 011 and the second electrode 012, allowing charge carriers to pass through, thereby achieving electrical connection between the source and drain. At this time, the carrier mobility of the components in the active portion 02 affects the conduction efficiency of transistor 10; that is, the higher the carrier mobility of the components in the active portion 02, the higher the efficiency of carrier migration between the first electrode 011 and the second electrode 012, and the better the conduction effect of transistor 10.

[0020] The active part 02 includes a first semiconductor layer 021 and a second semiconductor layer 022 stacked together. The second semiconductor layer 022 is located on the side of the first semiconductor layer 021 away from the film layer where the source and drain electrodes 01 are located. The first semiconductor layer 021 can contact the surface of the second semiconductor layer 022 away from the substrate 201.

[0021] Combination Figure 1 and Figure 2 In the actual fabrication process, the first semiconductor layer 021 can be set later than the second semiconductor layer 022. Therefore, the second semiconductor layer 022 can be considered as the substrate supporting the semiconductor material corresponding to the first semiconductor layer 021. In this case, the semiconductor material corresponding to the first semiconductor layer 021 can be epitaxially grown on the surface of the second semiconductor layer 022, ultimately forming the first semiconductor layer 021. During this process, some characteristics of the semiconductor material in the second semiconductor layer 022 (such as crystal structure orientation) can affect the corresponding characteristics of the semiconductor material in the first semiconductor layer 021. That is, the second semiconductor layer 022 can be considered as an "inducing template" affecting the formation of the first semiconductor layer 021.

[0022] In addition, such as Figure 1 As shown, the transistor 10 also includes a buffer layer 04 and a light shielding layer 05. The buffer layer 04 may be located on the side of the active part 02 near the substrate 201, and the light shielding layer 05 may be located between the buffer layer 04 and the substrate 201.

[0023] The first semiconductor layer 021 comprises a first crystalline oxide, and the second semiconductor layer 022 comprises a second crystalline oxide. In this case, both semiconductor layers included in the active portion 02 contain crystalline oxides. Based on the "inducing template" effect of the second semiconductor layer 022, the crystallization state of the crystalline oxides within the second semiconductor layer 022 (e.g., crystal structure orientation, grain arrangement sequence, etc.) can influence the crystallization state of the crystalline oxides within the first semiconductor layer 021. For example, if the grain growth in the second semiconductor layer 022 exhibits high order, the grains in the first semiconductor layer 021 can also exhibit high order under the influence of the second semiconductor layer 022.

[0024] It is important to note that the influence of the crystallization state of the crystalline oxide in the second semiconductor layer 022 on the crystallization state of the crystalline oxide in the first semiconductor layer 021 is related to the difference in crystallinity between the crystalline oxides included in the two semiconductor layers. Specifically, the smaller the difference in crystallinity between the first and second crystalline oxides, the stronger the "inducing template" effect of the second semiconductor layer 022 on the first semiconductor layer 021.

[0025] The crystallinity of the first crystalline oxide is c1, and the crystallinity of the second crystalline oxide is c2, where 0 < c1 - c2 ≤ 30%.

[0026] In this embodiment, the design of c1-c2 ≤ 30% means that the crystallinity difference between the first semiconductor layer 021 and the second semiconductor layer 022 is small. This helps to enhance the induced growth effect of the crystalline oxide in the second semiconductor layer 022 on the crystalline oxide in the first semiconductor layer 021, which is beneficial to further improve the overall stability of the active part 02, thereby enabling the transistor 10 to have both high carrier mobility and high stability. In addition, the crystallinity of the crystalline oxide can affect the carrier mobility of the semiconductor layer to a certain extent. In order to meet the requirement of the difference in carrier mobility between the first semiconductor layer 021 and the second semiconductor layer 022, this embodiment limits c1-c2 > 0 to achieve a design where the carrier mobility of the first semiconductor layer 021 is greater than that of the second semiconductor layer 022, thereby further improving the stability characteristics of the transistor 10.

[0027] Figure 3 This diagram illustrates the fabrication process of the first and second semiconductor layers.

[0028] In the actual fabrication process of transistor 10, the first semiconductor layer 021 can be fabricated using atomic layer deposition (ALD) technology, and the second semiconductor layer 022 can be fabricated using physical vapor deposition (PVD) technology. It should be noted that existing processes using these deposition techniques easily lead to oxygen defects in the semiconductor layer, which is detrimental to the overall performance of the transistor device. This application, by using the second semiconductor layer 022 as the growth substrate for the first semiconductor layer 021, allows oxygen defects 022a in the second semiconductor layer 022 to diffuse upwards into the first semiconductor layer 021 during the fabrication of the first semiconductor layer 021, thus helping to repair oxygen defects 021a caused by the atomic layer deposition process in the first semiconductor layer 021 (e.g., oxygen defects 022a). Figure 3 As shown in the figure, this helps to reduce the overall number of oxygen defects in the two semiconductor layers and improve the functional stability of transistor 10.

[0029] Figure 4 This is a schematic diagram of a partial structure of a display panel provided in this application. Figure 5 for Figure 4 The diagram shows a partial structure of the pixel circuitry within the display panel and the connection relationship between it and the light-emitting devices. Figure 6 for Figure 4 The diagram shows the equivalent circuit diagram of the pixel circuit within the display panel.

[0030] Combination Figure 1 , Figure 4 and Figure 5 Transistor 10 can be a device structure within the pixel circuit 21 of the display panel 20. Considering that the pixel circuit 21 can provide driving current to the light-emitting device 30, the high mobility of the active part 02 in transistor 10 helps to improve the power supply performance of the pixel circuit 21. It should be noted that... Figure 5 The light-emitting device 30 shown can be a micro light-emitting diode (LED). In addition, the light-emitting device 30 may also include a mini light-emitting diode (MID), an organic light-emitting diode (OLED), etc. The type of light-emitting device 30 shown in this application is only for illustrative purposes and does not mean that the type of light-emitting device 30 is limited to a certain type.

[0031] like Figure 6As shown, the pixel circuit 21 may include a data writing transistor T1, a first switching transistor T2, a driving transistor T3, a threshold grabbing transistor T4, a first reset transistor T5, a second switching transistor T6, and a second reset transistor T7. The connection relationship between the above transistor structures is as follows: Figure 5 As shown, further details will not be repeated here. The transistor 10 provided in this application can be any transistor structure in the pixel circuit 21.

[0032] For example, if transistor 10 can write data to transistor T1, the high carrier mobility of transistor 10 helps to improve the signal transmission efficiency of data writing to transistor T1, thereby improving the integrity of data voltage writing within a limited data writing period.

[0033] For example, if transistor 10 can be a driving transistor T3, then the high stability characteristics of transistor 10 help to enhance the stability of the light-emitting driving current output by driving transistor T3, thereby enhancing the light-emitting stability of light-emitting device 30.

[0034] In some embodiments of this application, both the first crystalline oxide and the second crystalline oxide contain a first-class element, namely the metallic element indium (In). In this application, using indium as a dopant element helps improve the carrier mobility characteristics of the crystalline oxide, thus meeting the high carrier mobility requirements for the first and second semiconductor layers. In this case, both the first and second crystalline oxides may contain indium oxide (InO). It should be noted that when the crystalline oxide contains InO, the crystal orientations of the first and second crystalline oxides can be the (2, 2, 2) plane of InO.

[0035] The atomic content x1 of the first type of element in the first crystalline oxide is greater than the atomic content x2 of the first type of element in the second crystalline oxide.

[0036] In this embodiment, it is known that the higher the atomic content of the first type of element, the higher the carrier mobility of the corresponding crystalline oxide can be. In this embodiment, by limiting x1 to x2, it is beneficial to achieve a higher carrier mobility of the first semiconductor layer 021 than that of the second semiconductor layer 022, thereby satisfying the carrier mobility difference between the two layers in the double semiconductor layer stack, which is beneficial to improving the overall stability of the transistor 10.

[0037] In some embodiments of this application, 80% < x1 ≤ 99%.

[0038] In this embodiment, the design of 80% < x1 ≤ 99% results in a large atomic content of indium in the first semiconductor layer 021, which means that the doping ratio of indium is large. This enables the first semiconductor layer 021 to have a high carrier mobility, which is beneficial to meeting the performance requirements of transistor 10.

[0039] In some embodiments of this application, the second crystalline oxide further contains a second type of element, including gallium and / or tin.

[0040] In one possible implementation, the second type of elements includes the metallic element gallium, in which case the second crystalline oxide may include indium gallium oxide (InGaO).

[0041] In one possible implementation, the second type of elements includes the metallic element tin, in which case the second crystalline oxide may include indium tin oxide (InSnO).

[0042] In one possible implementation, the second type of elements includes the metallic elements gallium and tin, in which case the second crystalline oxide may include indium gallium tin oxide (InGaSnO).

[0043] The atomic content x3 of the second type of element in the second crystalline oxide satisfies: 15 at.% ≤ x3 ≤ 30 at.%.

[0044] In this embodiment, since the size of In atoms doped in the multi-component system is similar to that of Ga and Sn atoms, using gallium and tin as second-class elements helps suppress the formation of oxygen vacancy defects in the second crystalline oxide, thus improving the stability of the second semiconductor layer O22 composed of the second crystalline oxide. Furthermore, the design of 15 at.% ≤ x3 ≤ 30 at.% in this embodiment implies a small amount of doping of the second-class elements in the second crystalline oxide, which helps reduce the impact on the crystallization state of the second crystalline oxide.

[0045] In some embodiments of this application, the second type of elements includes the metallic elements gallium and tin. In this case, the second crystalline oxide may include indium tin oxide (InSnO).

[0046] In the second crystalline oxide, the atomic ratio f between the metal elements gallium and tin satisfies: 1 ≤ f ≤ 5.

[0047] In this embodiment, when f=1, it can be considered that the atomic proportions of gallium and tin in the second crystalline oxide are equal. Adding gallium and tin in equal proportions to the second crystalline oxide helps to reduce the adverse effects on its crystallization state. Furthermore, the design of 1 < f ≤ 5 helps to further reduce the number of oxygen defects in the second semiconductor layer 022, thereby helping the second semiconductor layer 022 to guide the crystallization state in the first semiconductor layer 021, reducing the number of oxygen defects in the first semiconductor layer 021, and enhancing stability.

[0048] In some embodiments of this application, the composition of the first crystalline oxide is the same as that of the second crystalline oxide.

[0049] In the embodiments of this application, the crystalline oxides included in the first semiconductor layer 021 and the second semiconductor layer 022 can be the same, for example, both can be InGaO, or both can be InSnO, or both can be InGaSnO. This design helps to enhance the affinity between the first semiconductor layer 021 and the second semiconductor layer 022, strengthen the guiding effect of the oxide in the second semiconductor layer 022 on the growth of the oxide in the first semiconductor layer 021, and fully utilize the inducing substrate effect of the second semiconductor layer 022.

[0050] In some embodiments of this application, the average grain diameter m1 of the first semiconductor layer 021 is greater than the average grain diameter m2 of the second semiconductor layer 022.

[0051] In this embodiment, a larger grain size of the semiconductor material is more conducive to the orderliness of crystallinity within the semiconductor layer, which helps to further improve the carrier mobility of the semiconductor material. The design of m1 > m2 in this embodiment is beneficial for further increasing the carrier mobility of the first semiconductor layer 021 based on the doping process (adding metal elements such as In). This facilitates the realization of a dual-semiconductor layer stack design combining a high-carrier-mobility semiconductor layer (first semiconductor layer 021) and a low-carrier-mobility semiconductor layer (second semiconductor layer 022), which helps optimize the performance of the transistor 10 itself.

[0052] In some embodiments of this application, 5nm≤m1≤20nm, 4nm≤m2≤10nm.

[0053] In this embodiment, the grain size m1 of the first semiconductor layer 021 can satisfy: 5nm ≤ m1 ≤ 20nm. The grain size m2 of the second semiconductor layer 022 can satisfy: 4nm ≤ m2 ≤ 10nm.

[0054] In some embodiments of this application, 1.25 ≤ m1 / m2 ≤ 5.

[0055] In this embodiment, under the premise that m1 > m2, the minimum value of m1 can be 5nm and the maximum value can be 20nm. This design helps to maximize the carrier mobility of the crystalline oxide in the first semiconductor layer 021 and fully utilize the inducing substrate effect of the second semiconductor layer 022.

[0056] In some embodiments of this application, the thickness of the first semiconductor layer 021 is h1, the thickness of the second semiconductor layer 022 is h2, and 1.5≤h2 / h1≤20.

[0057] In this embodiment, the thickness h1 of the first semiconductor layer 021 satisfies: 2nm ≤ h1 ≤ 10nm. The thickness h2 of the second semiconductor layer 022 satisfies: 15nm ≤ h2 ≤ 40nm. In this embodiment, the design of h1 < h2 means that the thickness of the first semiconductor layer 021 is smaller than that of the second semiconductor layer 022. This thickness design helps to optimize the crystallization state of the first semiconductor layer 021, making it easier to form larger grains, thereby improving the carrier mobility of the crystalline oxide within the first semiconductor layer 021.

[0058] In some embodiments of this application, the thickness of the first semiconductor layer is h1, where 2 nm ≤ h1 ≤ 10 nm; The grain size m1 of the first semiconductor layer increases with the increase of the thickness h1 of the first semiconductor layer.

[0059] In this embodiment, the grain size that can be formed in the first semiconductor layer is positively correlated with the thickness h1 of the first semiconductor layer. The larger the thickness h1 of the first semiconductor layer, the larger the maximum value of the grain size m1 formed therein. This design means that by adjusting the thickness h1 of the first semiconductor layer, grains with larger diameters can be formed as much as possible, thereby enabling the first semiconductor layer to have high mobility characteristics, which is beneficial to improving the performance of the transistor 10 itself.

[0060] In some embodiments of this application, the carrier mobility of the first semiconductor layer 021 is y1, the carrier mobility of the second semiconductor layer 022 is y2, and 3.5≤y1 / y2≤10.

[0061] In this embodiment, the design of y1 / y2 ≥ 3.5 satisfies the condition of a large carrier mobility in the first semiconductor layer 021 and ensures a certain mobility difference between the upper and lower semiconductor layers. This mobility difference is beneficial for achieving the overall stability of the double-layer semiconductor structure. Furthermore, this embodiment also limits y1 / y2 to ≤ 10 to avoid an excessively large difference in carrier mobility between the first semiconductor layer 021 and the second semiconductor layer 022. This ensures the affinity between the corresponding crystalline oxides of the upper and lower semiconductor layers and helps to leverage the induced growth effect of the second semiconductor layer 022 on the first crystalline oxide within the first semiconductor layer 021.

[0062] This application provides a display panel 20, combined with Figure 4 and Figure 5 The display panel 20 includes the aforementioned transistor 10.

[0063] In the display panel 20 provided in this application embodiment, the carrier mobility and overall stability of the active part 02 in the transistor 10 are effectively improved, and the performance of the transistor 10 is further optimized.

[0064] Figure 7 This is a schematic diagram of a display device provided in this application.

[0065] This application provides a display device 40, such as... Figure 7 As shown, the display device 40 may include the aforementioned display panel 20. The display device may be a mobile phone, or it may be an electronic device such as a computer or television.

[0066] When the display device 40 provided in this application uses the aforementioned display panel 20 for display, the screen display effect is improved and enhanced.

[0067] The same or similar parts between the various embodiments in this specification can be referred to mutually. In particular, the device embodiments and terminal embodiments are basically similar to the method embodiments, so the description is relatively simple, and the relevant parts can be referred to the description in the method embodiments.

Claims

1. A transistor, characterized in that, It includes a source and a drain and an active portion. The active portion includes a first semiconductor layer and a second semiconductor layer stacked together. The second semiconductor layer is located on the side of the first semiconductor layer away from the film layer where the source and drain are located. The first semiconductor layer comprises a first crystalline oxide, and the second semiconductor layer comprises a second crystalline oxide. The crystallinity of the first crystalline oxide is c1, and the crystallinity of the second crystalline oxide is c2, where 0 < c1 - c2 ≤ 30%.

2. The transistor according to claim 1, characterized in that, Both the first crystalline oxide and the second crystalline oxide contain a first-class element, which is the metallic element indium. The atomic content x1 of the first type of element in the first crystalline oxide is greater than the atomic content x2 of the first type of element in the second crystalline oxide.

3. The transistor according to claim 2, characterized in that, 80%＜x1≤99%。 4. The transistor according to claim 2, characterized in that, The second crystalline oxide also contains a second type of element, including gallium and / or tin. The atomic content x3 of the second type of element in the second crystalline oxide satisfies: 15 at.% ≤ x3 ≤ 30 at.%.

5. The transistor according to claim 4, characterized in that, The second category of elements includes the metallic elements gallium and tin; In the second crystalline oxide, the atomic ratio f between the metal element gallium and the metal element tin satisfies: 1≤f≤5.

6. The transistor according to claim 5, characterized in that, The composition of the first crystalline oxide is the same as that of the second crystalline oxide.

7. The transistor according to claim 1, characterized in that, The grain size m1 of the first semiconductor layer is larger than the grain size m2 of the second semiconductor layer.

8. The transistor according to claim 7, characterized in that, 5nm≤m1≤20nm, 4nm≤m2≤10nm.

9. The transistor according to claim 8, characterized in that, 1.25≤m1 / m2≤5.

10. The transistor according to claim 1, characterized in that, The thickness of the first semiconductor layer is h1, the thickness of the second semiconductor layer is h2, and 1.5 ≤ h2 / h1 ≤ 20.

11. The transistor according to claim 1, characterized in that, The thickness of the first semiconductor layer is h1, where 2 nm ≤ h1 ≤ 10 nm; The grain size m1 of the first semiconductor layer increases with the increase of the thickness h1 of the first semiconductor layer.

12. The transistor according to claim 1, characterized in that, The carrier mobility of the first semiconductor layer is y1, and the carrier mobility of the second semiconductor layer is y2, where 3.5 ≤ y1 / y2 ≤ 10.

13. A display panel, characterized in that, Includes the transistor as described in any one of claims 1-12.

14. A display device, characterized in that, Includes the display panel as described in claim 13.

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