Variable input power control for reducing ac-dc converter input capacitance

Abstract

A variable input power (VIP) control method is presented that is capable of reducing the capacitance value of the input capacitor. By reducing the capacitance value of the input capacitor, both a smaller input capacitor Cin can be used and the system performance can be improved at a given capacitance value, thus increasing the available power density of the system. In essence, the VIP control technique is used to redistribute the output power Pin over the AC half-cycle period. Thus, during the charging phase, the discharge power of Cin is significantly reduced compared to the output power Pin, thus reducing the required Cin.

Description

[0001] Cross-referencing This application is a Chinese translation of international application PCT / CA2024 / 050342, filed on March 21, 2024, during its Chinese phase. This application is a non-provisional patent application and claims the full benefit, including priority, of U.S. Provisional Application No. 63 / 551930, filed on February 9, 2024, entitled "Variable Input Power Control for Reducing Input Capacitance of AC / DC Converter," the entire contents of which are incorporated herein by reference. Technical Field

[0002] The embodiments of this disclosure generally relate to the field of USB power transfer, and more specifically, to apparatus, systems and methods for improving the power density of a conversion system using variable input power (VIP) control technology. Background Technology

[0003] Since 2012, the USB Power Delivery Protocol (USB PD) based on the USB Type-C interface has standardized the charging protocol for most consumer electronic devices. This protocol promotes charger reusability between different devices and effectively reduces electronic waste. USB PD supports negotiation of multiple power delivery levels between the load device and the power supply device. It has proven to be highly advantageous in powering a wide range of devices, including smartphones, tablets, and laptops.

[0004] For USB-PD power adapters that do not include a PFC stage, a single-stage architecture is typically used.

[0005] The size of the input capacitor Cin is a major power density limiting factor for USB-PD power adapters, accounting for approximately one-quarter of the total converter volume. To reduce the required capacitance value of Cin and improve the power density of the entire converter system, this application proposes a variable input power (VIP) control method. Summary of the Invention

[0006] This invention proposes a variable input power (VIP) control method that reduces the capacitance value of the input capacitor. By reducing the input capacitor value, a smaller input capacitor Cin can be used, thereby increasing the available power density of the system.

[0007] In practice, this design allows the system to draw more power from the capacitor when the input voltage is high, and conversely, to draw less power from the capacitor when the input voltage is low, thus effectively reducing ripple. The principle is as follows: In the first period, when the input voltage is high, the power is likely to come from the AC power supply, which, from the device's perspective, can be considered to provide virtually unlimited power. Conversely, in the second period, power is drawn from the input capacitor Cin, but since the available power is finite, less power is drawn.

[0008] Essentially, the VIP control method is used to redistribute power within the AC power frequency half-cycle. The capacitance value. Therefore, with compared to, The discharge power decreases during charging, thereby reducing Required capacitance value.

[0009] One engineering goal of the VIP control method and its corresponding circuit is to reduce the ripple of the maximum and minimum Vbus values ​​using the proposed method while using the same capacitor capacity; or to reduce the required capacitor capacity while maintaining the same ripple level, thereby saving costs and reducing size, since capacitor components increase cost and size.

[0010] In the first embodiment, the proposed VIP control method can be achieved by keeping the input current of the DC-DC converter constant. In this case, the input power of the DC-DC converter will completely follow the bus voltage waveform: the input power increases when the bus voltage increases and decreases accordingly when the bus voltage decreases. Other implementations exist, such as the second embodiment where the input current of the DC-DC converter completely follows the bus voltage waveform; the third embodiment where the input current follows the bus voltage waveform in segments; and the fourth embodiment employing a segmented constant input current scheme. All these implementations are potential variations of the circuit structure and operating principle proposed in this solution.

[0011] Experiments were conducted using a quasi-resonant (QR) flyback converter. This approach enables several technical improvements during testing: for example, it can increase the minimum bus voltage to reduce the high gain requirement of the QR flyback converter under specific capacitance conditions; at the same time, it can reduce the required input capacitance value while keeping the minimum bus voltage specified in the design unchanged.

[0012] This application also describes several solutions related to VIP charging control, including methods for achieving variable input power control by adjusting the operating states of device components. Specifically, these methods offer significant improvements over conventional control schemes (i.e., keeping the input power of the DC-DC converter constant): the required capacitance value for Cin is difficult to reduce in conventional schemes.

[0013] From a practical application perspective, the proposed circuit can be configured for consumer electronics chargers (such as USB CPD chargers) or other types of charging devices, such as chargers for large devices (such as energy storage devices, electric vehicles, etc.).

[0014] One advantage of the method proposed in this application is that by reducing the required capacitance value, or achieving higher performance than other methods at a given capacitance value, the overall cost, size, and weight of these devices can be effectively reduced.

[0015] This circuit can be coupled with a DC-DC converter circuit to form a charging module, which integrates various circuits. One end of the charging module has a plug for inserting into a socket, and the other end has an interface for connecting cables and load devices (such as smartphone chargers).

[0016] It is advisable to integrate the corresponding control software and instruction set into the physical device or computer-readable medium. When these instruction sets are executed by the processor or waveform generator, the proposed VIP control scheme can be implemented. Attached Figure Description

[0017] The figures show exemplary embodiments. It should be clearly understood that the descriptions and illustrations are for illustrative purposes only and to aid understanding.

[0018] The embodiments will now be described by way of example and in conjunction with the accompanying drawings, in which: Figure 1A shows the single-stage architecture circuit diagram of the AC-DC converter.

[0019] Figure 1B This is a schematic diagram of the single-stage architecture control principle of an AC-DC converter.

[0020] Figure 2 is a schematic diagram of key voltage, current, and power waveforms in a full-bridge diode rectifier using a conventional constant input power control method according to some embodiments.

[0021] Figure 3 This is a schematic diagram of key voltage, current, and power waveforms in a full-bridge diode rectifier employing the proposed VIP control scheme according to some embodiments.

[0022] Figure 4 It is a graph showing the change of λ with h when using VIP control in some embodiments.

[0023] Figure 5A This is a control principle diagram for a DC-DC converter with constant input current.

[0024] Figure 5BKey waveforms of voltage, current, and power for a full-bridge diode rectifier with constant input current in a DC-DC converter.

[0025] Figure 6 This is a graph showing the correlation between the capacitance reduction and the bus voltage limit of a DC-DC converter under constant input current conditions.

[0026] Figure 7A This is a block diagram of the full-bridge diode rectifier control when the input current of the DC-DC converter completely follows the bus voltage waveform.

[0027] Figure 7B This is a key waveform diagram of the voltage and current of the full-bridge diode rectifier when the input current of the DC-DC converter completely follows the waveform of the bus voltage.

[0028] Figure 8 This is a graph showing the correlation between the decrease in capacitance and the bus voltage limit when the input current of the DC-DC converter completely follows the bus voltage waveform.

[0029] Figure 9A This is a block diagram of the full-bridge diode rectifier control when the input current of the DC-DC converter follows the bus voltage waveform in segments.

[0030] Figure 9B This is a waveform modulator control block diagram when the input current of the DC-DC converter follows the bus voltage waveform in segments.

[0031] Figure 9C This is a key waveform diagram of the waveform modulator when the input current of the DC-DC converter follows the bus voltage waveform in segments.

[0032] Figure 9D This is a key waveform diagram of the voltage and current of the full-bridge diode rectifier when the input current of the DC-DC converter follows the bus voltage waveform in segments.

[0033] Figure 10 This is a graph showing the correlation between the decrease in capacitance and the bus voltage limit when the input current of the DC-DC converter follows the bus voltage waveform in segments.

[0034] Figure 11A This is a block diagram of a full-bridge diode rectifier control system for a DC-DC converter with segmented constant input current.

[0035] Figure 11B This is a waveform modulator control block diagram of a full-bridge diode rectifier with segmented constant input current in a DC-DC converter.

[0036] Figure 11C This is a key waveform diagram of the waveform modulator of a full-bridge diode rectifier with segmented constant input current in a DC-DC converter.

[0037] Figure 11D This is a key waveform diagram of voltage and current of a full-bridge diode rectifier with segmented constant input current in a DC-DC converter.

[0038] Figure 12 This is a graph showing the correlation between the reduction in capacitance and the bus voltage limit under segmented constant input current conditions in a DC-DC converter.

[0039] Figure 13 These are simulation waveforms of conventional and proposed methods according to some embodiments, both using a 66 μF input capacitor.

[0040] Figure 14 These are simulation waveforms of conventional methods and proposed methods using different input capacitors according to some embodiments. Detailed Implementation

[0041] For USB-PD power adapters that do not include a PFC (Power Factor Correction) stage, a single-stage architecture design is typically used, as shown in Figure 1A. In Figure 1A, the full-bridge diode rectifier 100 converts the AC input voltage Vac to a stable bus voltage Vbus using Cin; the subsequent DC-DC converter is responsible for providing an adjustable output voltage to the load. Figure 1B The control block diagram 100B shown in Figure 1A below is based on the traditional control strategy.

[0042] The output voltage Vo is detected by a voltage sensor, generating a voltage feedback signal Vo_FB. Vo_FB is compared with a preset reference voltage signal Vo_Ref to generate an error signal Verror. The voltage loop compensator processes the Verror signal to generate a gate control signal Uctrl. The gate driver module converts the gate control signal Uctrl into a corresponding gate signal to drive the switching elements in the DC-DC converter. It is important to note that the gate driver generates different gate signals depending on the type of DC-DC converter: for example, if pulse width modulation (PWM) control is used, the gate driver generates a PWM gate drive signal with duty cycle as the control parameter based on the Uctrl signal; as a special case of PWM control, if constant on-time (Ton) control is used, the gate driver generates a constant on-time PWM gate drive signal with Ton time as the control parameter based on the gate control signal Uctrl; if pulse frequency modulation (PFM) control is used, the gate driver generates a PFM gate drive signal with switching frequency as the control parameter based on the Uctrl signal. The gate drive signal (Gate) is used to control the operating state of the DC-DC converter to regulate its output voltage Vo. It should be noted that... Figure 1BThe diagram only shows a single gate signal of a DC-DC converter. When a DC-DC converter includes multiple switches, multiple gate control signals are required; the gate driver module will generate the necessary multiple gate drive signals.

[0043] When using the above-mentioned traditional control method, since the output voltage Vo is controlled to a constant value, the output power also remains constant.

[0044] Therefore, the input power of the DC-DC converter also remains constant. In this application (specification), this conventional control method is referred to as constant input power control.

[0045] As described in this paper, a variable input power (VIP) control method is proposed, which can reduce the capacitance value of the input capacitor.

[0046] In practice, this method designs a system that draws more power from the capacitor when the input voltage is high, and conversely, draws less power from the capacitor when the input voltage is low, thereby helping to reduce ripple.

[0047] The rationale behind this design is that during the first time period, when the input voltage is high, the power is likely to come from the AC power supply, which, from the device's perspective, can be considered to provide virtually unlimited power. Conversely, during the second time period, the power is drawn from the input capacitor Cin, but since the available power is finite, less power is drawn.

[0048] Figure 2 shows the key waveform 200 of the full-bridge diode rectifier shown in Figure 1A under conventional constant input power control. Figure 2 belongs to the prior art.

[0049] It can be observed that the AC input current conducts only during a specific period within the half-cycle of the AC power frequency, denoted by radians θ, where θ represents the AC conduction angle. During [φ1, φ2], the input AC voltage simultaneously provides load power to the DC-DC converter and charges Cin; while during [φ2, φ3], the load power of the DC-DC converter is provided solely by Cin, and its discharge energy can be described by formula (1): in, For AC line frequency, This is the input power of the DC-DC converter, and also the discharge power of Cin. The voltage ratio h is defined as in formula (2): θ can be calculated using formula (3): The energy change of Cin within the half-cycle of the AC power frequency is calculated using formula (4): Combining formulas (1) to (4), the Cin value can be calculated using formula (5): As can be seen from formula (5), under specific voltage ripple conditions, the capacitance value required for Cin is proportional to that for Pin.

[0050] When using traditional control methods, the input power of the DC-DC converter is constant, making it impossible to minimize the required capacitance value of Cin.

[0051] Based on this conclusion, this paper proposes Variable Input Power (VIP) control. Compared with the traditional method of providing constant input power to the DC-DC converter, this VIP control can effectively reduce the Pin value in the [φ2, φ3] time period, thereby reducing the Cin capacitance value and improving the power density of the AC-DC converter.

[0052] Figure 3 Key waveform 300 of a VIP control scheme proposed according to some embodiments is shown. As described herein, there are various feasible methods for VIP control, which will be described in detail in several embodiments in the following examples.

[0053] In terms of waveforms, the Pin waveform in (c) is particularly important because it can be observed that it shifts with the different operating phases used, as described below.

[0054] During the period [φ1, φ2], the average input power of the DC-DC converter is denoted as... During the period [φ2, φ3], this value is denoted as . and Satisfy the relationship in formula (6): Compared with the traditional method of using a constant pin within the AC power frequency half-cycle, the proposed VIP control can redistribute the pin within the AC power frequency half-cycle.

[0055] Therefore, compared to Pin, Cin has lower discharge power in the range [φ2, φ3], thus reducing the required capacitance value of Cin. According to the definition of power ratio k in formula (7), It can be rewritten in the form shown in formula (8): Combining formulas (5) and (8), the required capacitance Cin can be expressed as formula (9): Combining formulas (5), (8), and (9), / The ratio of capacitance can be expressed by formula (10): in This indicates the capacitance value required for Cin when using the traditional method (i.e., the Pin value that remains constant during half a cycle of AC power frequency).

[0056] The capacitance ratio λ and the peak-to-peak ratio of the bus voltage h ( / The relationship is as follows: Figure 4 As shown in Figure 400.

[0057] It can be observed that by reducing the voltage ratio h ( / This can significantly reduce the capacitance value. Furthermore, with a fixed voltage ratio h, the reduction in capacitance value increases with increasing k values ​​of 402, 404, 406, 408, and 410. In other words, smaller... The value means that a smaller capacitance value is required for Cin. and The allocation can be achieved by controlling the operating state of the DC-DC converter.

[0058] Example 1: Constant Input Current of DC-DC Converter The first implementation of VIP control is to maintain a constant input current (iin) for the DC-DC converter.

[0059] Figure 5A A block diagram of a 500A DC-DC converter under constant input current control is shown. Figure 1B The traditional control method shown is different. Figure 5A An additional current loop is introduced to regulate the input current of the DC-DC converter to a constant value.

[0060] exist Figure 1B In this circuit, the output signal of the voltage loop compensator (denoted as Uctrl) is used to generate the gate control signal (Gate) to drive the switches in the DC-DC converter.

[0061] However, in Figure 5A In this circuit, the output signal of the voltage loop compensator (denoted as Iin_Ref) serves as the reference current for the current loop. The input current iin of the DC-DC converter is detected by a current sensor, which generates Iin_sns, which is proportional to iin. Iin_sns reflects the input current state of the DC-DC converter in real time.

[0062] The current error signal Ierror is generated by comparing Iin_sns with Iin_Ref. This error signal is then processed by a current loop compensator to generate the gate control signal Uctrl. The gate driver module converts the gate control signal Uctrl into a gate control signal (Gate) to drive the switching elements of the DC-DC converter. In this dual-loop control architecture, the output voltage can remain stable based on a reference value, and the input current can be adjusted to a constant value.

[0063] The input power of a DC-DC converter is equal to the product of its input current iin and the bus voltage Vbus, i.e., Pin = iin * Vbus. When the input current iin of the DC-DC converter is controlled at a constant value, its input power will automatically adjust with the change of the bus voltage Vbus; in other words, the waveform of the input power and the bus voltage are completely synchronized: the higher the bus voltage Vbus, the greater the input power; and vice versa. Thus, VIP control strategy #1 can be automatically implemented.

[0064] Figure 5B The key waveform 500B of the constant input current full-bridge diode rectifier in the DC-DC converter is shown.

[0065] like Figure 5B As shown, when the bus voltage is high, the input power in (d)Pin is higher when the bus voltage is high and lower when the bus voltage is low.

[0066] During the period [φ1, φ2], the average input power of the DC-DC converter can be expressed by formula (11): During the period [φ2, φ3], the average input power of the DC-DC converter can be expressed by formula (12): Therefore, k can be calculated using formula (13): According to formulas (10) and (13), / The capacitance ratio can be recalculated using formula (14): According to formula (14), the capacitance ratio λ is related to the peak-to-peak ratio h of the bus voltage. / The relationship is as follows: Figure 6 The curve 600 is shown in the figure.

[0067] It can be observed that λ602 decreases monotonically as the value of h decreases. When h = 0.6 (i.e., the minimum voltage is 60% of the maximum voltage), the required capacitance of Cin can be reduced by 2.3%; when h = 0.5, the required capacitance can be reduced by 3.2%.

[0068] Example 2: The input current of the DC-DC converter perfectly follows the bus voltage waveform. The second implementation of VIP control is to adjust (or control) the input current of the DC-DC converter so that it completely follows the bus voltage waveform Vbus. Figure 7A A control block diagram 700A is shown that enables this implementation.

[0069] and Figure 5A Compared to the dual-loop control architecture shown, Figure 7A An additional bus voltage feedforward loop was introduced. Figure 5A In this circuit, the output signal of the voltage loop compensator (denoted as Iin_Ref) serves as the reference current for the current loop.

[0070] However, in Figure 7A In this circuit, the reference current (Iin_Ref1) of the current loop is obtained by adding Iin_Ref to Vbus_flt, i.e., Iin_ref1 = Iin_ref + Vbus_flt. Here, Vbus_flt represents the feedforward signal obtained by bandpass filtering the bus voltage Vbus; this bandpass filter eliminates the DC component of the bus voltage, retaining only the AC component (i.e., the ripple voltage contained in Vbus). It is important to note that Vbus_flt only includes AC voltage; its DC component (or average value) is zero.

[0071] Therefore, in Figure 7A In this process, the real-time value of Iin_Ref1 changes with the bus voltage Vbus, while ensuring that its average value is always equal to Iin_Ref. In other words, the input current of the DC-DC converter is dynamically controlled to follow the changes in the bus voltage in real time, while ensuring the stability of the output voltage.

[0072] The input power of a DC-DC converter is determined by the product of its input current iin and the bus voltage Vbus, i.e., Pin = iin × Vbus. When the input current (iin) of the DC-DC converter is precisely controlled to track the bus voltage waveform, its input power will automatically adjust with changes in the bus voltage Vbus: when the bus voltage Vbus is higher, the input power increases accordingly; conversely, it decreases. Thus, VIP control strategy #2 is automatically implemented.

[0073] Figure 7BThe key waveform 700B of the full-bridge diode rectifier is shown when the input current of the DC-DC converter fully follows the bus voltage waveform.

[0074] It can be observed that the input current of the DC-DC converter completely follows the waveform of the bus voltage: in the interval [φ1, φ2], the input current gradually rises from Iin_min to Iin_max in a sinusoidal waveform; then in the interval [φ2, φ3], the input current linearly decreases from Iin_max to Iin_min.

[0075] Fixed-frequency DCM (Discontinuous Conduction Mode) flyback converters are widely used in AC / DC and DC / DC power conversion. In DCM mode, the energy stored in the transformer is completely transferred to the secondary winding. During the main switch's conduction period, the flyback circuit input current increases linearly from zero; through constant on-time control, the average input current in each switching cycle can be expressed by formula (15): Where Vbus is the instantaneous bus voltage, Ton is the on-time of the main switch, L is the flyback inductance, and Ts is the switching period of the flyback converter. It can be seen that Iin_avg_Ts is proportional to the instantaneous bus voltage.

[0076] In other words, under constant on-time conditions, the input current of a DCM flyback converter changes completely with the bus voltage. The same conclusion applies to a QR (quasi-resonant) flyback converter, as it is essentially a DCM flyback converter using a valley-switching conduction method.

[0077] During the period [φ1, φ2], the average input power of the DC-DC converter is expressed by formula (16): During the period [φ2, φ3], the average input power of the DC-DC converter is expressed by formula (17): Therefore, k can be calculated using formula (18): According to formulas (10) and (18), / The capacitance ratio can be recalculated using formula (19): According to formula (19), the capacitance ratio λ is related to the peak-to-peak ratio h of the bus voltage. / The change curve is as follows: Figure 8 As shown in Figure 800.

[0078] It can be observed that λ802 decreases monotonically as the value of h decreases. When h = 0.6, the required capacitance of Cin can be reduced by 5%; when h = 0.5, the required capacitance can be reduced by about 8%.

[0079] Example 3: Input current of DC-DC converter follows bus voltage waveform in segments It can be observed that the input current of the DC-DC converter follows the bus voltage waveform in segments.

[0080] The third implementation of VIP control aims to regulate the input current of the DC-DC converter so that it follows the bus voltage waveform Vbus in segments.

[0081] Figure 9A A control block diagram 900A implementing this embodiment is shown. Figure 7A The control architectures shown are different. Figure 9A A new waveform modulator #1 has been added. The function of waveform modulator #1 is to convert the detected Vbus waveform into a Vbus_mod waveform. It should be noted that the Vbus_mod waveform will segmentally follow the bus voltage waveform. By inputting Vbus_mod into a bandpass filter, the DC component in Vbus_mod can be eliminated, resulting in Vbus_flt which only includes the AC component of Vbus_mod, and whose DC value (or average value) is zero. Figure 9A As shown, Iin_Ref1 can be obtained by adding Vbus_mod to Iin_Ref (a constant value), i.e., Iin_Ref1 = Vbus_mod + Iin_Ref. Therefore, Iin_Ref1 will segmentally follow the bus voltage waveform Vbus. Under closed-loop control, the input current (Iin) of the DC-DC converter changes accordingly; in other words, the input current of the DC-DC converter will segmentally follow the bus voltage waveform. Thus, VIP control strategy #3 has been successfully implemented.

[0082] Typically, waveform modulator #1 needs to perform two tasks: First, it must distinguish the AC conduction angle θ from the Vbus waveform, such as... Figure 9A As shown; secondly, the Vbus waveform needs to be segmented and multiplied by different scaling factors. For example, when the Vbus waveform is within the AC conduction angle θ, it is multiplied by a scaling factor K1; when the Vbus waveform is not within the AC conduction angle θ, it is multiplied by a scaling factor K2 (where K1 should be greater than K2). If K1 equals K2, then the third implementation of VIP control is completely consistent with the second implementation.

[0083] It should be noted that waveform modulator #1 can be implemented using various analog or digital circuits.

[0084] Figure 9BA block diagram 900B is provided for implementing waveform modulator #1. This block diagram mainly consists of two circuit parts, referred to as circuit A and circuit B, respectively.

[0085] The purpose of circuit A is to accomplish task 1 mentioned above, namely, to distinguish the AC conduction angle from the Vbus waveform. Circuit A includes a voltage sensor for detecting the bus voltage Vbus (denoted as Vbus_sns). The detected Vbus_sns value is compared with two reference values ​​Vref1 and Vref2 by two comparators; Vref1 and Vref2 are both preset constants. The output signals of the comparators are input to a set-reset flip-flop (triggered by a rising edge) to generate a control signal Vsel for use by circuit B.

[0086] The purpose of circuit B is to achieve task 2 mentioned above, that is, to segment the Vbus waveform and multiply it by different scaling factors. Circuit B consists of a multiplexer: its two input signals correspond to two different scaling factors K1 and K2, respectively; the output signal Y of the multiplexer is multiplied by Vbus_sns to obtain the Vbus_mod signal. The truth table of the multiplexer is shown below. Figure 9C Table I shows that when Vsel is 0, Vbus_sns is multiplied by K2; when Vsel is 1, Vbus_sns is multiplied by K1.

[0087] Figure 9C Showing Figure 9B The key waveform 900C in the block diagram is shown. At time t0, when Vbus_sns is just below Vref1, signal V1 goes high, generating a rising edge; this rising edge causes the output signal Vsel of the set-reset flip-flop to switch to a high level (i.e., 1).

[0088] At time t1, when Vbus_sns is just higher than Vref2, signal V2 goes high, generating another rising edge. This rising edge causes the output signal Vsel of the set-reset flip-flop to go low (i.e., 0). Therefore, during the AC conduction angle θ (i.e., within the time interval [t0, t1]), the Vsel signal remains high (i.e., 1); when the Vbus waveform is outside the AC conduction angle θ (i.e., within the time interval [t1, t2]), the Vsel signal remains low (i.e., 0). Thus, Vbus_sns is multiplied by K1 within the time interval [t0, t1], and multiplied by K2 within the time interval [t1, t2].

[0089] Figure 9D The key waveform 900D of the full-bridge diode rectifier is shown when the input current follows the bus voltage waveform in segments.

[0090] Within the interval [φ1, φ2], the input current exhibits a sinusoidal waveform, gradually increasing from Iin_min1 to Iin_max1; within the interval [φ2, φ3], the input current linearly decreases from Iin_max2 to Iin_min2. φ1 and φ2 represent the switching nodes of the DC-DC converter control mode. For a DCM flyback converter, this control can be achieved by using different Ton values ​​corresponding to θ and π-θ duration.

[0091] It should be noted that during the time period from φ1 to φ2, the diode bridge is in the conducting state, and the input AC voltage is used to charge the input capacitor Cin and provide the input power Pin to the DC-DC converter. Therefore, it is necessary to increase the input current iin and input power Pin of the DC-DC converter during this time period.

[0092] like Figure 9D As shown, the total power consumption of the DC-DC converter remains constant during the AC power frequency half-cycle from φ1 to φ3. When the input power of the DC-DC converter is higher during the period from φ1 to φ2, the input power decreases accordingly during the period from φ2 to φ3. It should be noted that during the period from φ2 to φ3, the input capacitor Cin will discharge to power the DC-DC converter; if the required power is lower at this time, the capacitance value of this capacitor can be reduced.

[0093] Assuming that Ton1 and Ton2 are used to control the on-time of the main switch within the intervals [φ1, φ2] and [φ2, φ3], the input current of the DCM flyback converter can be expressed as formula (20): Since Ton1 and Ton2 are constant values, the input current of the DCM flyback converter will follow the bus voltage waveform Vbus(φ) in segments.

[0094] During the period [φ1, φ2], the average input power of the DC-DC converter can be expressed by formula (21): During the period [φ2, φ3], the average input power of the DC-DC converter can be expressed by formula (22): Therefore, k can be calculated using formula (23): According to formulas (10) and (23), / The capacitance ratio can be recalculated using formula (24): According to formula (24), the capacitance ratio λ is related to the peak-to-peak ratio h of the bus voltage. / The change curve is as follows: Figure 10 As shown in Figure 1000.

[0095] It can be observed that λ = 1002, 1004, 1006, 1008, 1010, and 1012 monotonically decreases as the value of h decreases. Furthermore, with a fixed value of h, the decrease in capacitance increases with the increase of the Iin_max1 / Iin_max2 ratio. In other words, the larger the Iin_max1 / Iin_max2 ratio, the lower the capacitance requirement for Cin.

[0096] Example 4: Segmented constant input current of a DC-DC converter The fourth implementation of VIP control aims to regulate the input current of the DC-DC converter to maintain a segmented constant input current.

[0097] Figure 11A A control block diagram 1100A for implementing this embodiment is shown.

[0098] Example #4 (as Figure 11A (as shown) and Example #3 (as shown) Figure 9A The difference (as shown) lies in the waveform change of Vbus_mod.

[0099] When the Vbus waveform is within the AC conduction angle θ range, Vbus_mod is set to a higher level, Vbus_mod_H; when the Vbus waveform exceeds the AC conduction angle θ range, Vbus_mod is set to a lower level, Vbus_mod_L.

[0100] Both of these levels (Vbus_mod_H and Vbus_mod_L) are constant values. Therefore, Iin_Ref1 remains a high constant value during the θ period, resulting in an increase in the input power of the DC-DC converter at this angle, thereby automatically implementing VIP control strategy #4.

[0101] Figure 11B Demonstrates the implementation Figure 11A The diagram shows a block diagram 1100B of waveform modulator #2. This diagram includes two circuits: circuit A and circuit B. Figure 11B Circuit A in Figure 9B Circuit A in the diagram has the same structure and function.

[0102] Figure 11B and Figure 9B The difference lies in circuit B. In Figure 11BIn circuit B, the two input signals of the multiplexer correspond to the high-level signal Vbus_mod_H and the low-level signal Vbus_mod_L of Vbus_mod, respectively. The truth table of this multiplexer is shown below. Figure 11B Table II shows that when the Vsel signal is 0, the multiplexer output is Vbus_mod_L; when the Vsel signal is 1, the output is Vbus_mod_H.

[0103] Figure 11C Showing Figure 11B The key waveform 1100C in the block diagram is shown. It can be seen that during the AC conduction angle θ (i.e., within the time interval [t0, t1]), the Vsel signal is always high (i.e., 1); when the Vbus waveform is outside the AC conduction angle θ (i.e., within the time interval [t1, t2]), the Vsel signal remains low (i.e., 0). Therefore, within the time interval [t0, t1], the output of waveform modulator #2 is Vbus_mod_H; while within the time interval [t1, t2], its output is Vbus_mod_L.

[0104] Figure 11D The key waveform 1100D of a full-bridge diode rectifier with segmented constant input current in a DC-DC converter is shown.

[0105] Within the intervals [φ1, φ2] and [φ2, φ3], the input current of the DC-DC converter is always set to Iin1 and Iin2 (where Iin1 > Iin2). To achieve this piecewise constant input current, different current reference values ​​must be used that match the lengths of θ and the π - θ time interval. For example... Figure 11A As shown, during the period θ (from φ1 to φ2, see...) Figure 11D The current reference value for the DC-DC converter is set to Iin_Ref1_H; while during the π - θ period (from φ2 to φ3, see...) Figure 11D If Iin_Ref1_H is higher than Iin_Ref1_L, then the input current Iin1 of the DC-DC converter will be higher than the input current Iin2 in the π-θ stage under closed-loop control. Note that the ratio of Iin_Ref1_H to Iin_Ref1_L is equal to the ratio of Iin1 to Iin2; the larger the ratio of Iin_Ref1_H to Iin_Ref1_L (i.e., Iin1 to Iin2), the greater the voltage drop across capacitor Cin.

[0106] During the period [φ1, φ2], the average input power of the DC-DC converter can be expressed by formula (25): During the period [φ2, φ3], the average input power of the DC-DC converter can be expressed by formula (26): Therefore, k can be calculated using formula (27): According to formulas (10) and (27), / The capacitance ratio can be recalculated using formula (28): According to formula (28), the capacitance ratio λ and the peak-to-peak ratio h of the bus voltage ( / The relationship is as follows: Figure 12 The curve 1200 is shown in the figure.

[0107] It can be observed that λ1202, 1204, 1206, 1208, 1210, and 1212 monotonically decrease as the value of h decreases. Furthermore, with a fixed value of h, the reduction in capacitance increases with the increase of the Iin1 / Iin2 ratio. In other words, a larger Iin1 / Iin2 ratio corresponds to a reduction in the demand for capacitance Cin.

[0108] This paper takes a QR flyback converter as an example to compare and analyze the performance differences between traditional constant input power control and the proposed VIP control scheme. This converter is widely used in low-power SMPS (Switch-Mode Power Supply) applications, such as chargers, USB-PD adapters, and auxiliary power devices. In the QR flyback circuit, the on-time Ton of the main power switch is used to regulate the output voltage; different Ton values ​​will produce different output voltages. The technical parameters of the QR flyback converter used in the PSIM simulation are summarized as follows: 1.90Vac / 60Hz input, 22Vdc, 2.95A (65W) output.

[0109] 2. The constant forward voltage drop of the diode in the full-bridge rectifier is 0.7Vdc.

[0110] 3. The constant forward voltage drop of the secondary rectifier diode is 0.7Vdc.

[0111] 4. The transformer turns ratio is 26:5. The magnetizing inductance is 140μH. Leakage inductance is negligible.

[0112] 5. The secondary output capacitor is 1700μF.

[0113] The proposed VIP control scheme follows the control strategy shown in Example 2: the input current of the QR flyback converter strictly follows the bus voltage waveform. This implementation can be easily achieved by setting a constant Ton value for the main power switch; in actual circuits, the Ton value of the main power switch can be kept constant by reducing the bandwidth of the voltage feedback loop.

[0114] Using the same input capacitor can increase the minimum bus voltage, thereby reducing the high gain requirement of the QR flyback converter.

[0115] Figure 13 Simulated waveforms 1300 of the traditional method and the proposed method are shown, both using a 66μF input capacitor.

[0116] Table I summarizes the circuit performance. It can be seen that the proposed VIP control scheme exhibits excellent performance in terms of minimum bus voltage, input RMS current, and output RMS current, indicating that this VIP control method can enable the QR flyback converter to achieve higher conversion efficiency.

[0117] However, employing VIP control results in a significant 120 Hz voltage ripple on the output capacitor. This is due to the fundamental characteristic of VIP control—it modulates the power processed by the QR flyback converter at a frequency of 120 Hz.

[0118] Therefore, the charging power of the output capacitor will also change at a frequency of 120 Hz. Since the discharging power of the output capacitor is always equal to the output power, the change in its charging power at 120 Hz will manifest as an amplified 120 Hz voltage ripple on the output voltage.

[0119] Table I: Performance Comparison (Input Capacitor: 66 μF) If the design parameters remain unchanged, the proposed VIP control scheme can be used to reduce the required input capacitance value.

[0120] Figure 14 Simulated waveforms 1400 for the conventional method and the proposed method using different input capacitors are shown.

[0121] Table II presents a summary of circuit performance data. Using the proposed VIP control scheme, the same minimum DC bus voltage of 69V can be achieved while reducing the input capacitor to 61.2μF; the capacitor reduction is approximately (66-61.2) / 66 = 7.3%. The input RMS current can be reduced to 1.06 / 1.09 = 97%, corresponding to a reduction in primary conduction losses of (1-0.972) = 6%.

[0122] However, the increase in secondary output current is (5.21 - 5.15) / 5.15 = 1.2%, resulting in an increase in secondary conduction losses of 1.0122 = 2%. The 120 Hz output voltage ripple increases to 1.75V (peak-to-peak).

[0123] Table II: Performance Comparison (Different Input Capacitors) The proposed VIP control scheme can be used to reduce the capacitance value of the input capacitor, thereby using a smaller input capacitor to improve the system power density.

[0124] It should be noted that with the proposed Variable Input Power (VIP) control scheme, the input power of the DC-DC converter is not constant; however, the power consumed by its load typically remains constant. Therefore, the difference between the input power and the output power will generate a 120Hz ripple at the output of the DC-DC converter. This phenomenon can be observed... Figure 13 and Figure 14 This was observed. Therefore, when using this Variable Input Power (VIP) control scheme, a 120Hz ripple voltage will inevitably be generated at the output of the DC-DC converter. Generally speaking, the smaller the input capacitor value, the larger the amplitude of the 120Hz ripple. However, when designing the output capacitor and the overall system structure, the additional 120Hz current stress caused by the VIP control scheme must be fully considered. For certain applications (such as power adapters), a second-stage buck converter (not shown in this application) can be added to adjust the actual output voltage supplied to devices such as smartphones and laptops—in this case, the 120Hz ripple can be eliminated by the second-stage buck converter without affecting the performance of the power adapter.

[0125] The proposed VIP control scheme is suitable for the operation of QR flyback converters under low input AC voltage (e.g., 90VAC). However, under normal operating conditions of 120VAC, the bus voltage is always higher than the design voltage. Therefore, this control scheme is unnecessary. In other words, the VIP control strategy can be disabled when the input AC voltage exceeds a certain threshold (such as 120V).

[0126] The applicant hereby declares that the embodiments and examples described are illustrative only and not restrictive. Practical applications of these features may combine some or all of them; the features described herein should not be considered as instructions for future or existing product planning. The applicant engages in both basic and applied research, and in some cases, the features were developed based on exploratory research.

[0127] The term “connection” or “coupled to” can include both direct coupling (i.e., two mutually coupled elements in direct contact) and indirect coupling (i.e., at least one additional element is located between the two elements).

[0128] Although the embodiments have been described in detail, it should be understood that various modifications, substitutions, or alterations can be made to these contents without departing from the scope of protection of this patent. Furthermore, the scope of protection of this application is not intended to be limited to the specific implementation methods such as the specific processes, equipment, manufacturing methods, material compositions, means, methods, and steps described in the specification.

[0129] It will be readily understood by those skilled in the art, based on this disclosure, that existing or future-developed processes, equipment, manufacturing methods, material compositions, apparatuses, methods, or steps capable of achieving substantially the same function or effect as the corresponding embodiments described herein can be employed. Therefore, the appended claims are intended to cover the scope of all such processes, equipment, manufacturing methods, material compositions, apparatuses, methods, or steps described above.

[0130] As mentioned above, the examples described and illustrated are for illustrative purposes only.

Claims

1. A variable input power control device for a DC-DC converter, the variable input power control device comprising at least: A full-bridge diode rectifier circuit is connected to an AC voltage source. The rectifier circuit includes a diode bridge and at least one capacitor Cin. The rectifier circuit provides the capacitor Cin and the DC-DC converter with a rectified current irec, a bus voltage Vbus, an input current Iin, and a corresponding output power Pin. The DC-DC converter is used to supply power to the load. The rectifier circuit is configured such that the input power Pin operates within the range corresponding to half a cycle of the AC power frequency; the input power Pin is increased in the first stage when the AC voltage source supplies power to the DC-DC converter via the diode bridge, and the input power Pin is decreased in the second stage when the input capacitor Cin supplies power to the DC-DC converter.

2. The apparatus of claim 1, wherein, By controlling the operating state of the rectifier circuit, variable input power control is achieved while maintaining a constant input current of the DC-DC converter, so that the input power Pin follows the bus voltage waveform.

3. The device as described in claim 2, wherein the phase operating state of the rectifier circuit is adjusted by controlling the value of the AC conduction angle θ.

4. The apparatus of claim 2 further includes an additional current loop configured to regulate the input value of the DC-DC converter to a constant value.

5. The apparatus of claim 1, wherein, It also includes a bus voltage feedforward loop, which controls the operating state of the rectifier circuit to make the input current of the DC-DC converter track the bus voltage waveform, thereby providing variable input power control.

6. The apparatus of claim 5, wherein, The input current of the DC-DC converter that follows the bus voltage waveform is achieved by controlling the flyback converter and the flyback converter input current.

7. The apparatus of claim 1, wherein, Variable input power control is achieved by controlling the operating state of the rectifier circuit to maintain the input current of the DC-DC converter following the bus voltage waveform in segments.

8. The apparatus of claim 7, wherein different T values ​​corresponding to the durations θ and π-θ are employed. on The value controls the flyback converter in discontinuous mode, so that the input current of the DC-DC converter follows the bus voltage waveform in segments.

9. The apparatus of claim 1, wherein, Variable input power control is achieved by controlling the operating state of the rectifier circuit; the control method is to maintain the segmented constant input current of the DC-DC converter by using different Ton values ​​that match the time period of θ and π–θ.

10. The apparatus according to any one of claims 1 to 9, wherein, The device is integrated into a charger for a consumer electronic device, the charger being configured to provide an adjustable output voltage to a load; variable input power control is used to reduce the required capacitance value of capacitor Cin.

11. A method for variable input power control of a DC-DC converter, the method comprising at least: A full-bridge diode rectifier circuit connected to an AC voltage source is driven. The full-bridge diode rectifier circuit includes a diode bridge and at least one capacitor Cin. The rectifier circuit provides the capacitor Cin and the DC-DC converter with the rectified current irec, the bus voltage Vbus, the input current Iin, and the corresponding output power Pin. The DC-DC converter is used to supply power to the load; the input power Pin is controlled to vary within the interval corresponding to the half-cycle of the AC power frequency: in the first stage when the AC voltage source supplies power to the DC-DC converter via the diode bridge, the input power Pin is increased; in the second stage when the capacitor Cin supplies power to the DC-DC converter, the input power Pin is decreased.

12. The method of claim 11, wherein, By controlling the operating state of the rectifier circuit to maintain a constant input current of the DC-DC converter, variable input power control is achieved, so that the input power Pin changes with the waveform of the bus voltage.

13. The method of claim 12, wherein, The phase operation of the rectifier circuit is controlled by adjusting the value of the AC conduction angle θ.

14. The method of claim 12, wherein, It also includes an additional current loop for regulating the input value of the DC-DC converter to a constant value.

15. The method according to claim 11, wherein, It also includes a bus voltage feedforward loop, which controls the operating state of the rectifier circuit to make the input current of the DC-DC converter track the bus voltage waveform, thereby providing variable input power control.

16. The method of claim 15, wherein, The input current of the DC-DC converter that follows the bus voltage waveform is achieved by controlling the flyback converter and the flyback converter input current.

17. The method of claim 11, wherein, Variable input power control is achieved by controlling the operating state of the rectifier circuit to maintain the input current of the DC-DC converter following the bus voltage waveform in segments.

18. The method of claim 17, wherein, Using different T values ​​corresponding to θ and π-θ durations on The value controls the flyback converter in discontinuous mode, so that the input current of the DC-DC converter follows the bus voltage waveform in segments.

19. The method of claim 11, wherein, Variable input power control is achieved by controlling the operating state of the rectifier circuit; the control method is to maintain the segmented constant input current of the DC-DC converter by using different Ton values ​​that match the time period of θ and π–θ.

20. The method according to any one of claims 11 to 19, wherein, The method is operated by a charger for a consumer electronic device, the charger being configured to provide an adjustable output voltage to a load; variable input power control is used to reduce the required capacitance value of capacitor Cin.

21. A non-transient machine-readable medium storing a machine-interpretable instruction set; when the instruction set is executed by a processor, it enables the processor to perform a variable input power control method, said method comprising the method of any one of claims 11 to 20.

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