Circuit board, method of manufacturing the same, and semiconductor package

Abstract

The present application relates to a circuit board and a method of manufacturing the same and a semiconductor package. A circuit board according to one aspect of the present application includes: an insulating layer including a resin and glass fibers provided within the resin; and a circuit portion provided on the insulating layer, wherein the glass fibers include first glass fibers extending in a first horizontal direction and second glass fibers provided on the first glass fibers and extending in a second horizontal direction, wherein a cross section of the first glass fibers and a cross section of the second glass fibers are arranged on a cross section of the circuit portion, wherein the first glass fibers include a plurality of regions provided such that a thickness thereof in a vertical direction varies along a third horizontal direction forming a predetermined angle with the first horizontal direction, and the second glass fibers include a plurality of cross section portions provided spaced apart along the third horizontal direction.

Description

Technical Field

[0001] The teachings of the present invention, through exemplary and non-limiting embodiments, generally relate to circuit boards, methods of manufacturing the same, and semiconductor packaging. Background Technology

[0002] Recent trends in electronics technologies such as AI and servers are moving towards multi-functionality and high-speed operation, and in response to these trends, circuit board technologies for high-layer count and large-area production are also rapidly developing, keeping pace with the rapid development of semiconductor chip manufacturing technologies.

[0003] In particular, as the density of transistors and wiring within semiconductor chips increases, the number of I / O terminals on these chips also rises. To address this trend, circuit boards are not only becoming more refined in terms of wiring density, length, and width, but are also evolving towards higher layer counts and larger area designs.

[0004] Furthermore, from the perspective of miniaturizing finished electronic products, the thickness of the circuit boards used is also decreasing, and research is actively underway on technologies related to multilayer circuit boards, which integrate more circuit layers within a board of the same thickness. Additionally, as semiconductor chip spacing becomes narrower and chip size increases, research is progressing towards chip-on-chip technology, which separates semiconductor chips by function. Furthermore, technologies for connecting these separate chips on circuit boards are being actively researched. Moreover, technologies regarding the interconnection between circuit boards and semiconductor chips, such as circuit boards connecting semiconductor chips together, are being actively researched by connecting semiconductor chips with different functions on the circuit board. This represents a shift from the traditional view of circuit boards being considered solely from the perspective of semiconductor packaging.

[0005] A circuit board is an insulating substrate made of conductive material such as copper, with circuit lines arranged in a pattern. It generally refers to the encapsulation board just before electronic components are mounted. To densely mount many electronic components of various types onto a flat board, the mounting position of each component is determined, and the circuit patterns connecting the components are printed onto the board surface and secured.

[0006] Recently, as the number of signals that semiconductor chips must process increases, there is a trend towards larger chip sizes. Consequently, the size of the circuit boards on which these semiconductor chips are mounted is also increasing.

[0007] With the trend toward higher layers and larger areas on circuit boards, the warpage characteristics of circuit boards have become a key factor in their reliability.

[0008] For example, a circuit board includes a core layer and multiple stacked structures arranged vertically and symmetrically relative to the core layer. Each of the multiple stacked structures includes multiple insulating layers arranged vertically. The multiple stacked structures are electrically interconnected through core via electrodes penetrating the core layer.

[0009] To enhance the durability of a circuit board against bending, the insulating layer constituting the board includes resin and a reinforcing material disposed within the resin. For example, this reinforcing material can be glass fiber. However, when an insulating layer containing glass fiber is deployed, the high dielectric constant of the glass fiber itself leads to a decrease in signal transmission efficiency within the circuitry of the circuit board.

[0010] [Existing technical documents]

[0011] [Patent Literature]

[0012] Korean Patent Publication No. 10-2024-0158112 (Published on November 4, 2024) Summary of the Invention

[0013] [Technical Issues]

[0014] The present invention provides a circuit board and a semiconductor package that minimizes signal loss in the circuit section caused by the glass fibers by adjusting the arrangement structure of the glass fibers forming the insulating layer and the circuit section.

[0015] [Technical Solution]

[0016] The circuit board according to this embodiment may include: an insulating layer comprising resin and glass fibers disposed within the resin; and a circuit portion disposed on the insulating layer, wherein the glass fibers include a first glass fiber extending in a first horizontal direction and a second glass fiber disposed on the first glass fiber and extending in a second horizontal direction, wherein the cross-sections of the first glass fiber and the second glass fiber are arranged on the cross-section of the circuit portion, wherein the first glass fiber includes a plurality of regions, the plurality of regions being configured such that their thickness in the vertical direction varies along a third horizontal direction forming a predetermined angle with the first horizontal direction, and the second glass fiber includes a plurality of cross-sectional portions spaced apart along the third horizontal direction.

[0017] According to another aspect of the present invention, a semiconductor package may include: an insulating layer comprising a resin and glass fibers disposed within the resin; a semiconductor chip disposed on the insulating layer; and a circuit portion disposed on the insulating layer, wherein the glass fibers include a first glass fiber extending in a first horizontal direction and a second glass fiber disposed on the first glass fiber and extending in a second horizontal direction, wherein the cross-sections of the first glass fiber and the second glass fiber are arranged on the cross-section of the circuit portion, wherein the first glass fiber includes a plurality of regions configured such that its thickness in the vertical direction varies along a third horizontal direction forming a predetermined angle with the first horizontal direction, and the second glass fiber includes a plurality of cross-sectional portions spaced apart along the third horizontal direction.

[0018] [Beneficial Effects]

[0019] According to this embodiment, by arranging the circuit section at an angle relative to the glass fiber within the insulating layer, the vertical overlap area between the glass fiber and the circuit section can be minimized.

[0020] Therefore, in signal transmission of multiple circuit sections arranged within a circuit board, there are advantages over conventional methods in reducing signal loss and improving power transmission efficiency. Attached Figure Description

[0021] Figure 1 This is a cross-sectional view of a circuit board according to an embodiment of the present invention.

[0022] Figure 2 This is a diagram illustrating the arrangement of via electrodes within the first core layer, the second core layer, and the upper stacked insulating portion according to an embodiment of the present invention.

[0023] Figure 3 This is a diagram showing a cross-section of the core according to an embodiment of the present invention.

[0024] Figure 4 This is an enlarged photograph of a via according to an embodiment of the present invention, wherein the via is the arrangement area of ​​the second via electrode within the second core layer.

[0025] Figure 5 This is a diagram illustrating the arrangement of glass fibers within an insulating layer according to an embodiment of the present invention.

[0026] Figure 6 and Figure 7 This is a diagram used to illustrate signal loss based on the arrangement of glass fiber and circuit components.

[0027] Figure 8 This is a diagram showing the arrangement of the glass fiber and circuit according to the comparative example.

[0028] Figures 9 to 11 These are various diagrams illustrating the arrangement of glass fibers and circuits according to embodiments of the present invention.

[0029] Figure 12 This is a table comparing the signal loss between the circuit board according to the comparative example and the circuit board according to an embodiment of the present invention.

[0030] Figure 13 This is a diagram illustrating a semiconductor package according to an embodiment of the present invention. Detailed Implementation

[0031] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0032] However, the technical concept of the present invention is not limited to the described embodiments, but can be implemented in various different forms, and one or more components in the embodiments can be selectively combined or replaced within the scope of the technical concept of the present invention.

[0033] Furthermore, the terminology (including technical and scientific terms) used in the embodiments of this invention may be interpreted as meaning what a person skilled in the art would understand, unless explicitly defined and described and generally understood by a person skilled in the art. Commonly used terms, such as those defined in dictionaries, may be interpreted within the context of the relevant art.

[0034] Furthermore, the terminology used in the embodiments of the present invention is intended to describe the embodiments and not to limit the invention. In this specification, the singular form may include the plural form unless otherwise specified herein, and when described as “A and (and / with) B, C, at least one (or more than one) of A, B and C”, it may include one or more of all combinations of A, B and C.

[0035] Furthermore, terms such as 1 and 2, A, B, (a) and (b) may be used to describe components of embodiments of the present invention. Such terms are intended only to distinguish components from other components and are not limited by the nature, order, or sequence of the components.

[0036] Furthermore, if any component is described as “connected,” “joined,” or “attached” to another component, then that component may be directly connected, joined, or attached to that other component, as well as “connected,” “joined,” or “attached” to another component between that component and that other component.

[0037] Furthermore, when stating that each component is formed or arranged "above or below," "above or below" includes not only the case where two components are in direct contact with each other, but also the case where one or more other components are formed or arranged between these two components. Additionally, when expressed as "above" or "below," it can include both the downward and upward directions based on a component.

[0038] In addition, the statement "configuration A is set between configurations B and C" must also include the meaning that configuration A is set such that at least a portion of it overlaps horizontally and / or vertically with configurations B and C.

[0039] Directional expressions include horizontal and vertical directions. Horizontal directions include directions such as a first horizontal direction, a second horizontal direction, and a third horizontal direction. Vertical directions include directions such as a first vertical direction, a second vertical direction, and a third vertical direction. At least one of the first vertical direction, the second vertical direction, and the third vertical direction represents a direction perpendicular to at least one horizontal direction, or a direction perpendicular to all horizontal directions. However, unless otherwise specified, a vertical direction shall be defined as a direction perpendicular to all horizontal directions. Furthermore, some of the aforementioned first horizontal direction, second horizontal direction, and third horizontal direction may be perpendicular to each other; for ease of subsequent description, mutually perpendicular directions shall be defined accordingly.

[0040] Furthermore, the statement "Configuration A is exposed from Configuration B" should be understood as meaning that Configuration A is exposed from Configuration B, not from the entire product. In other words, when stating that Configuration A is exposed from Configuration B, it should be understood that Configuration A is at least partially covered by Configuration C.

[0041] Furthermore, when stating that configuration A “contacts” configuration B, this can include not only cases where components directly “contact” each other, but also cases where “contact” occurs via another configuration located between the two configurations. Therefore, if the intention is for configuration A to only “directly contact” configuration B, it should be stated as “direct contact.”

[0042] Furthermore, when stating that configuration A is "overridden" by configuration B, this should be understood as meaning that configuration A is overridden by configuration B, causing a portion of it to be obscured for the purpose and function it is intended to address. Unless there are exceptional circumstances, it must not be interpreted as meaning that configuration A is completely overridden by configuration B.

[0043] Figure 1 This is a cross-sectional view of a circuit board according to an embodiment of the present invention. Figure 2 This is a diagram illustrating the arrangement of via electrodes within the first core layer, the second core layer, and the upper laminated insulating portion according to an embodiment of the present invention. Figure 3 This is a cross-sectional view showing the core according to an embodiment of the present invention, and Figure 4This is an enlarged photograph of a via according to an embodiment of the present invention, wherein the via is the arrangement area of ​​the second via electrode within the second core layer.

[0044] refer to Figures 1 to 4 According to an embodiment of the present invention, the circuit board (10) may include a core (100), an upper stacked structure (200), a lower stacked structure (300), and a protective layer (410, 420).

[0045] The circuit board (10) may include a core (100). The core 100 may be a component forming the base of the circuit board 10. Based on the vertical direction, the core 100 may be located at the center of the circuit board 10. The material of the core (100) may include at least one selected from the group consisting of glass, resin, plastic and metal. For example, the core (100) may include resin and glass fibers embedded in the resin. As the rigidity of the core (100) is increased by the glass fibers, the bending characteristics of the circuit board (10) may be improved.

[0046] Recently, with the increasing number of signals that semiconductor chips must process, there is a trend towards larger area semiconductor chips. Consequently, the size of the circuit boards on which these semiconductor chips are mounted is also increasing.

[0047] According to this embodiment, in order to improve the bending characteristics of the circuit board (10) in response to the increased number of layers and large area of ​​the circuit board (10), it is preferable to make the core (100) thicker.

[0048] The core assembly (100) may include a first core layer (110) and a second core layer (150) disposed on one surface and the opposite surface of the first core layer (110). The second core layer (150) may be disposed on the upper surface and the lower surface of the first core layer (110), respectively.

[0049] As an example, the second core layer (150) may include multiple insulating layers stacked vertically. Relative to the first core layer (110), the second core layer (150) may include a second-1 core layer (151) disposed on the first core layer (110), a second-2 core layer (152) disposed on the second-1 core layer (151), a second-3 core layer (153) disposed on the bottom surface of the first core layer (110), and a second-4 core layer (154) disposed on the lower surface of the second-3 core layer (153). However, this is not limiting, and the second core layer (150) may also be implemented as a single layer on both the upper and lower surfaces of the first core layer (110). Furthermore, to control the total thickness of the core (100), the second core layer (150) may have a structure in which a greater number of insulating layers are stacked vertically. Furthermore, by arranging multiple stacked second core layers (150) differently on the upper and lower parts of the first core layer (110), warping that occurs during or after the circuit board manufacturing process can be precisely controlled.

[0050] Regarding the vertical direction, the thickness (H1) of the first core layer (110) can be greater than the thickness (H2) of the second core layer (150). Here, the thickness (H2) of the second core layer (150) can represent the vertical thickness of each of the plurality of insulating layers constituting the second core layer (150). According to an exemplary embodiment, the thickness (H1) of the first core layer (110) can be more than 100 μm and less than 300 μm to improve the warpage characteristics of the circuit board (10) and the processability of the first via electrode (130) described later. For example, the first via electrode (130) penetrating the first core layer (110) is advantageously configured such that the entire via penetrating the first core layer (110) is filled with metal. This helps to improve mechanical characteristics (such as heat dissipation) and / or electrical characteristics (such as power and signal transmission).

[0051] However, if the thickness of the first core layer (110) exceeds 300 μm, it becomes difficult to completely fill the vias with metal, and the via processing also becomes difficult. Therefore, it is desirable that the thickness of the first core layer (110) be within the aforementioned range. Furthermore, the thicknesses (H2) of the second-1 core layer (151), the second-2 core layer (152), the second-3 core layer (153), and the second-4 core layer (154) can each have a thickness (H2) of 60 μm or more and 80 μm or less to improve the bending characteristics of the circuit board (10) and advantageously control the total thickness of the core (100). In this case, the ratio of the thicknesses of the first core layer (110) and the second core layer (110) can be from 5:1 to 5:4.

[0052] If the ratio of the thickness of the second core layer (150) to the thickness of the first core layer (110) is less than 5:1, the thickness of the core (100) may not be sufficiently guaranteed. Therefore, warping problems may occur in the circuit board (10) due to reduced durability.

[0053] When the ratio of the thickness of the second core layer (150) to the thickness of the first core layer (110) exceeds 5:4, the manufacturing cost for forming the core (100) increases relatively, or the yield and productivity decrease. Therefore, the practicality of realizing the core (100) through multiple insulating layers is reduced, and the process for forming the second via electrode (170) within the second core layer (150), which will be described later, also becomes problematic.

[0054] The first core layer (110) may include resin and glass fibers (112) disposed within the resin. The first core layer (110) may be a prepreg (PPG). For example, the first core layer (110) may include a plurality of glass fibers (112). Each of the plurality of glass fibers (112) extends in a horizontal direction and may be disposed perpendicular to each other. Figure 3 As shown, the plurality of glass fibers (112) may include a first glass fiber (112a) and a second glass fiber (112b) disposed below the first glass fiber (112a).

[0055] The second core layer (150) may include resin and glass fibers (150a) disposed within the resin. The second core layer (150) may be a prepreg (PPG). Within the resin constituting the second core layer (150), the glass fibers (150a) may be disposed in a horizontal direction. Figure 3 As shown, a single layer of glass fiber (150a) can be disposed within the second core layer (150).

[0056] According to this embodiment, by implementing the glass fiber (112) in the first core layer (110) as multiple layers exceeding the number of glass fiber (150a) in the second core layer (150), the bending characteristics of the circuit board (10) can be improved via the first core layer (110) which is centrally located in the vertical direction.

[0057] Furthermore, by realizing a core (100) with a vertically stacked structure of a second core layer (150) that is thinner than the first core layer (110), the total thickness of the core (100) can be more easily controlled, and the design freedom of the circuit section, such as the wiring within the core (100), can be greatly enhanced.

[0058] Specifically, the core provided by existing technology as a single layer has a relatively thick thickness. Therefore, when machining vias for placing via electrodes, mechanical drilling must be used. When using mechanical drilling, it is difficult to narrow the gap (spacing) between vias, the process time required for mechanical drilling increases, and it leads to expensive process costs. Furthermore, when placing via electrodes in vias with a single-layer core through an electroplating process, it is difficult to fill the entire via. Therefore, a metal layer of predetermined thickness is only deposited horizontally on the inner wall of the via. This limits the improvement of mechanical and / or electrical properties, such as heat dissipation, power transmission, electrical signal transmission, insertion loss, and resistance.

[0059] According to this embodiment, compared to a structure where the core is implemented as a single layer, implementing the core (100) via multiple vertically stacked insulating layers allows for both mechanical drilling and laser processing of vias on the relatively thin individual insulating layers. This reduces manufacturing costs and facilitates complete metal filling of vias. Furthermore, forming a core (100) with a structure of multiple vertically stacked insulating layers increases design freedom regarding the formation of wiring and via electrodes, thus offering the potential advantage of improved production efficiency.

[0060] Meanwhile, in order to prevent the deterioration of the bending characteristics of the circuit board (10) compared with the single-layer core, as described above, each insulating layer constituting the core (100) may include resin and reinforcing material, such as glass fiber disposed within the resin.

[0061] The circuit board (10) may include an upper stacked structure (200) and a lower stacked structure (300). Regarding the core (100), the upper stacked structure (200) may be disposed on the top of the core (100), and the lower stacked structure (300) may be disposed on the lower surface of the core (100).

[0062] The upper layer structure (200) may include an upper layer insulating portion. The upper layer insulating portion may include a plurality of insulating layers (210) stacked in a vertical direction. The plurality of insulating layers (210) of the upper layer insulating portion may be stacked in a vertical direction on top of the core (100). The lowest insulating layer among the plurality of insulating layers (210) constituting the upper layer insulating portion may be disposed on the second core layer (150). The number of the plurality of insulating layers (210) constituting the upper layer insulating portion may be greater than the number of the second core layers (150).

[0063] The lower stacked structure (300) may include a lower stacked insulating portion. The lower stacked insulating portion may include a plurality of insulating layers (310) stacked in a vertical direction. The plurality of insulating layers (310) of the lower stacked insulating portion may be stacked from the lower surface of the core (100) in a vertical direction. The uppermost insulating layer among the plurality of insulating layers (310) constituting the lower stacked insulating portion may be disposed on the lower surface of the second core layer (150).

[0064] Each of the plurality of insulating layers (210) in the upper laminated insulating portion and each of the plurality of insulating layers (310) in the lower laminated insulating portion can be any insulating material, such as photocurable and / or thermosetting materials. Thermosetting insulating materials may include insulating materials having inorganic and / or organic fillers dispersed within a resin, such as ABF (Ajinomoto Build-up Film) (a product released by Ajinomoto Corporation) and glass fiber-containing prepreg (PPG) within the resin. Furthermore, the aforementioned resin may, exemplarily, be epoxy resin, bismaleimide triazine resin (BT resin), phenolic resin, etc., and the inorganic and / or organic fillers may be provided by materials such as silica, plastics, etc. At least one of the plurality of insulating layers (210) in the upper laminated insulating portion or at least one of the plurality of insulating layers (310) in the lower laminated insulating portion may be a photocurable insulator, and if it is a photocurable insulator, it may be a PID (photographic imaging dielectric).

[0065] Specifically, since the core (100) is implemented with multiple insulating layers, the circuit board (10) can be further enhanced in its resistance to bending by using prepreg (PPG) to implement each of the multiple insulating layers (210) of the upper stacked insulating portion and the multiple insulating layers (310) of the lower stacked insulating portion. Therefore, the following description will show by way of example that each of the multiple insulating layers (210) of the upper stacked insulating portion and the multiple insulating layers (310) of the lower stacked insulating portion is a prepreg (PPG).

[0066] When the multiple insulating layers (210) of the upper laminated insulating portion and the multiple insulating layers (310) of the lower laminated insulating portion are prepreg (PPG), glass fibers can be disposed within the resin constituting the multiple insulating layers (210) of the upper laminated insulating portion and the multiple insulating layers (310) of the lower laminated insulating portion.

[0067] The thickness of each of the plurality of insulating layers (210) in the upper stacked insulating portion and the plurality of insulating layers (310) in the lower stacked insulating portion can be less than the thickness of the first core layer (110) and / or the second core layer (150). Therefore, each of the plurality of insulating layers (210) in the upper stacked insulating portion and the plurality of insulating layers (310) in the lower stacked insulating portion can be provided with a via electrode (230) smaller than that provided with the via electrodes (130, 170) in the core (100). Therefore, finer wiring can be provided in the plurality of insulating layers (210) in the upper stacked insulating portion and the plurality of insulating layers (310) in the lower stacked insulating portion than the via electrodes (130, 170) or wiring patterns provided in the core (100).

[0068] Specifically, relative to the vertical direction, the thickness (H7, see below) of each of the plurality of insulating layers (210) in the upper laminated insulating portion and the plurality of insulating layers (310) in the lower laminated insulating portion is... Figure 2 The thickness (H7) of the second core layer (150) can be thinner than that of the second core layer (150). The thickness (H7) of each of the plurality of insulating layers (210) in the upper stacked insulating portion and the plurality of insulating layers (310) in the lower stacked insulating portion can be between 30 μm and 45 μm to ensure vertical insulation and accommodate fine wiring and via electrode placement. Therefore, the ratio of the thickness (H2) of the second core layer (150) to the thickness (H7) of each of the plurality of insulating layers (210) in the upper stacked insulating portion and the plurality of insulating layers (310) in the lower stacked insulating portion can be from 10:3 to 5:4.

[0069] If the ratio of the thickness of each of the plurality of insulating layers (210) of the upper laminated insulating portion and the plurality of insulating layers (310) of the lower laminated insulating portion to the thickness of the second core layer (150) is less than 3:10, delamination may occur due to the stress applied to the insulating layers forming the upper laminated structure (200) and the lower laminated structure (300).

[0070] When the ratio of the thickness of the plurality of insulating layers (210) in the upper stacked insulating portion to the thickness of the plurality of insulating layers (310) in the lower stacked insulating portion relative to the second core layer (150) exceeds 4:5, a pattern with a gap and width similar to that of the via electrodes (130, 170) and / or wiring disposed in the core (100) can be formed. That is, difficulties may arise when placing fine patterns, which not only reduces the design freedom of wiring but also requires a significant increase in the overall size and thickness of the circuit board (10), potentially leading to delamination and / or warping problems. Furthermore, when electrically connected to semiconductor devices, wiring used for impedance matching or for transmitting signals or power may be significantly different from the terminals of the semiconductor devices, potentially making a tight connection between the circuit board (10) and the semiconductor devices difficult.

[0071] The core (100) may house a circuit section for transmitting electrical signals. The circuit section may include multiple wiring sections disposed within the core (100), the upper stacked structure (200), and the lower stacked structure (300), as well as multiple via electrodes.

[0072] Multiple wiring portions may each be disposed on the surfaces of multiple insulating layers. Here, "disposed on the surface" may also mean that at least a portion of the multiple wiring portions is embedded within the multiple insulating layers or protective layers (410, 420) that respectively constitute the core (100), the upper laminated structure (200), and the lower laminated structure (300), and is exposed externally from the surface. The wiring portion may also be referred to as a metal portion. Furthermore, the surfaces of the multiple insulating layers include one surface, another surface, and a side surface located between one surface and another surface. Here, one surface of the insulating layer can be understood as the upper surface, and the other surface can be understood as the lower surface. The meaning of wiring portions being disposed on the surface is that they are disposed on at least one of the one surface, another surface, or a side surface of the multiple insulating layers. The structure may also include wiring portions disposed on one surface and another surface of some of the multiple insulating layers, while in other portions of the multiple insulating layers, wiring portions are disposed on only one surface or another surface.

[0073] The plurality of wiring portions may include a first wiring portion (121) disposed on the upper surface of the first core layer (110), a second wiring portion (123) disposed on the lower surface of the first core layer (110), a third wiring portion (160) disposed on the second core layer (150), a fourth wiring portion (220) disposed on the upper laminated insulating portion, and a fifth wiring portion (320) disposed on the lower laminated insulating portion. The first to fifth wiring portions (121, 122, 160, 220, 320) may be arranged to overlap in mutually perpendicular directions.

[0074] The third wiring portion (160) may be disposed on the surface of each insulating layer constituting the second core layer (150). For example, the third wiring portion (160) may be disposed on the upper surface of the second-1 core layer (151), the upper surface of the second-2 core layer (152), the lower surface of the second-3 core layer (153), and the lower surface of the second-4 core layer (154), respectively.

[0075] The fourth wiring section (220) and the fifth wiring section (320) may each be disposed on the surface of each of the plurality of insulating layers (210) of the upper stacked insulating section and the plurality of insulating layers (310) of the lower stacked insulating section.

[0076] The via electrode can be a metallic material disposed within a via formed in each of a plurality of insulating layers to connect a plurality of wiring portions facing each other in the vertical direction. Here, the via penetrates at least a portion of each of the plurality of insulating layers in the vertical direction, and the via electrode can be disposed within the via.

[0077] The circuit board (10) may include a first via electrode (130). The first via electrode (130) may be configured to penetrate at least a portion of the first core layer (110). The first via electrode (130) may be electrically connected to a first wiring portion (121) and a second wiring portion (123).

[0078] The first electrode (130) may include a first portion (134) and a second portion (132) disposed on the first portion (134), the width of the first portion gradually narrowing as it approaches the upper surface of the first core layer (110) from the lower surface of the first core layer (110), and the width of the second portion gradually narrowing as it approaches the lower surface of the first core layer (110) from the upper surface of the first core layer (110). Figure 2 As shown, relative to the second core layer (150) disposed on the first core layer (110), the first portion (134) may have a shape in which its horizontal width increases from the second core layer (150) toward the first core layer (110), and the second portion (132) may have a shape in which its horizontal width decreases from the second core layer (150) toward the first core layer (110).

[0079] The first part (134) and the second part (132) can be arranged vertically adjacent to each other. The first part (134) and the second part (132) can be integrally formed. The lower end of the first part (134) can be connected to the second wiring portion (123). The upper end of the second part (132) can be connected to the first wiring portion (121). The vertical cross-section of the first via electrode (150) defined by the first part (134) and the second part (132) can have an hourglass shape.

[0080] When a via is formed in the first core layer (110) for placing the first via electrode (150) using a laser, the laser can be irradiated onto both the upper and lower surfaces of the first core layer (110). At this time, depending on conditions such as positioning accuracy and laser intensity, the vertical length (H4) of the first portion (134) and the vertical length (H3) of the second portion (132) of the first via electrode (150) can be the same. The area where the first portion (134) and the second portion (132) meet can be a region that divides the vertical length (H1) of the first via electrode (150) into two equal halves. The ratio of the vertical length (H4) of the first portion (134) to the vertical length (H3) of the second portion (132) can be 1:1. However, this is not necessarily limited to this, and depending on the conditions of the aforementioned process, the vertical length (H4) of the first portion (134) and the vertical length (H3) of the second portion (132) can be different from each other.

[0081] The second via electrode (170) may be configured to penetrate at least a portion of the second core layer (150). The second via electrode (170) may electrically connect the first wiring section (121) and the third wiring section (160), the second wiring section (123) and the third wiring section (160), and a plurality of third wiring sections (160).

[0082] Based on the second core layer (150) disposed on the first core layer (110), the second via electrode (170) may include a fourth portion (172) whose width gradually narrows from the upper surface of the second core layer (150) toward its lower surface, and a third portion (174) disposed below the fourth portion (172), the width of the third portion (174) gradually widening toward the lower surface of the second core layer (150). The third portion (174) may have a shape in which its horizontal width widens from the second core layer (150) toward the first core layer (110). The fourth portion (172) may have a shape in which its horizontal width decreases from the second core layer (150) toward the first core layer (110). The fourth portion (172) may be disposed on the third portion (174). The fourth portion (172) and the third portion (174) may be disposed vertically adjacent to each other. The fourth portion (172) and the third portion (174) may be integrally formed.

[0083] The third part (174) and the fourth part (172) enable the second via electrode (170) to have an hourglass shape, which has an asymmetrical cross-section in the vertical direction. For example... Figure 2 As shown, the vertical length (H5) of the fourth part (172) and the vertical length (H6) of the third part (174) can be different from each other.

[0084] For example, the vertical length (H5) of the fourth part (172) can be longer than the vertical length (H6) of the third part (174). In the second via electrode (170), the ratio of the vertical length (H5) of the fourth part (172) to the vertical length (H6) of the third part (174) can be different from the ratio of the vertical length (H3) of the first region (151) to the vertical length (H4) of the second region (152) in the first via electrode (150). For example, the ratio of the vertical length (H5) of the fourth part (172) to the vertical length (H6) of the third part (174) in the second via electrode (170) can be from 3:2 to 3:1.

[0085] Taking a second core layer (150) disposed above the first core layer (110) as a reference, a via into which a second via electrode (170) is disposed can be formed by irradiating a laser from the upper surface of the second core layer (150) toward the lower surface of the second core layer (150). Specifically, as Figure 4As shown, the via (180) in which the second via electrode (170) is disposed may include a first region (184) having a third portion (174) and a second region (182) having a fourth portion (172) disposed on the first region (184). The first region (184) may have a shape in which the horizontal width widens toward the first core layer (110). The second region (182) may have a shape in which the horizontal width narrows toward the first core layer (110).

[0086] based on Figure 2 Depending on the process conditions, the laser irradiated onto the second core layer (150) can cause scattering on the upper surface of the first wiring portion (121), thereby forming a third portion (174) with a gradually widening width. The third portion (174) increases the bonding area between the second via electrode (170) and the first wiring portion (121), thereby improving the bonding strength of the second via electrode (170).

[0087] Furthermore, when the laser is scattered on the upper surface of the first wiring section (121), it is difficult to uniformly form the shape of the via in the second core layer (150) for placing the second via electrode (170) on the entire circuit board, potentially leading to low yield.

[0088] Therefore, when the second via electrode (170) completely fills the via of the second core layer (150), it is desirable that the ratio of the vertical length (H5) of the fourth portion (172) of the second via electrode (170) to the vertical length (H6) of the third portion (174) be provided as 3:2 to 3:1. Furthermore, refer to... Figure 3 The third part (174) can be disposed below the glass fiber (150a) disposed within the second core layer (150). Therefore, problems such as leakage current or signal loss can be prevented by avoiding excessive exposure of the glass fiber (150a).

[0089] According to this embodiment, the ratio of the vertical lengths of the first portion (134) and the second portion (132) within the first via electrode (130) is different from the ratio of the vertical lengths of the third portion (174) and the fourth portion (172) within the second via electrode (170). Furthermore, the third via electrode (230) of the upper and lower laminated insulating portions described below may include only the region whose width decreases from the upper surface to the lower surface, but is not limited thereto.

[0090] When the third sub-electrode (230) includes a sixth portion having a horizontally narrowing width and a fifth portion disposed below the sixth portion and also having a horizontally narrowing width toward the second core layer (150), the first ratio of the vertical length of the first portion (134) of the first via electrode (150) to the vertical length of the second portion (132), the second ratio of the vertical length of the third portion (174) of the second via electrode (170) to the vertical length of the fourth portion (172), and the third ratio of the vertical length of the fifth portion to the vertical length of the sixth portion of the third via electrode (230) can be different from each other. Here, each ratio is based on the second portion (132), the fourth portion (172), and the sixth portion, whose width gradually narrows from the upper surface toward the lower surface. The first ratio can be greater than the second ratio, and the second ratio can be greater than the third ratio. For example, the aforementioned ratios can vary depending on the different thicknesses of the core (100), the plurality of insulating layers (210) constituting the upper laminated insulating portion, and the plurality of insulating layers (310) constituting the lower laminated insulating portion. Therefore, the difference between the aforementioned first ratio and the third ratio can reduce the stress applied to the upper and / or lower parts of the circuit board (10), can have the effect of suppressing the warping of the circuit board (10), and can have the effect of improving the integration density and design freedom of wiring for connecting electronic components such as semiconductor devices.

[0091] In particular, by making the first ratio and the second ratio different, warping that occurs during the formation process of the core (100) is prevented, and wiring can be arranged on the second core layer (150) to have a wiring density between that of the insulation layers (210, 310) constituting the upper and lower stacked insulation portions and the wiring density of the first core layer (110), thereby helping to control impedance matching, insertion loss, etc.

[0092] Furthermore, it has the effect of reducing the process cost of forming via electrodes disposed on each core (100) and the insulating layers (210, 310) constituting the upper and lower stacked insulating portions, and increasing yield. Here, density or integration density refers to the width and gap of wiring or via electrodes; high density equals high integration density, which should be understood as meaning that the width and / or gap of wiring and / or the width and / or gap of via electrodes are very small.

[0093] Meanwhile, the shape and structure of the aforementioned second via electrode (170) are described using an example of a second via electrode (170) disposed within a second core layer (150) disposed on a first core layer (110). The second via electrode (170) disposed within a second core layer (150) below the first core layer (110) may have a shape in which a third portion (174) and a fourth portion (172) are vertically inverted relative to the aforementioned structure. Therefore, the second via electrode (170) disposed within a second core layer (150) below the first core layer (110) may include a third portion (174) and a fourth portion (172), wherein the third portion (174) has a gradually widening width, and the fourth portion (172) has a gradually shortening vertical length. The vertical length of the fourth portion (172) may be longer than the vertical length of the third portion (174).

[0094] In summary, the second via electrode (170) disposed in a plurality of second core layers (150) arranged symmetrically in the vertical direction relative to the first core layer (110) can be symmetrical in the vertical direction relative to the first core layer (110).

[0095] like Figures 1 to 3 As shown, the second via electrode (170) can be configured to overlap perpendicularly with the first via electrode (130). This minimizes the signal transmission length within the core (100).

[0096] The width of the second via electrode (170) can be smaller than the width of the first via electrode (130). This indicates a relatively larger thickness of the first core layer (110) compared to the second core layer (150). By forming the first via electrode (130) within the relatively thick first core layer (110) with a larger width, the resistance associated with signal transmission can be minimized.

[0097] Meanwhile, at least a portion of the first via electrode (130) may have a smaller width than the second via electrode (170). Specifically, the first via electrode (130) may have a minimum width in the horizontal direction in the area where the first portion (134) and the second portion (132) contact. In this case, the maximum width in the horizontal direction of the area disposed above or below the second via electrode (170) may be greater than the minimum width of the first via electrode (130). Therefore, the amount of electroplating required to form the first via electrode (130) disposed within the first core layer (110) can be reduced.

[0098] However, this is not limiting, and the minimum width in the horizontal direction at the contact area of ​​the first portion (134) and the second portion (132) of the first via electrode (130) may be greater than the maximum width in the horizontal direction of the second via electrode (170).

[0099] The third via electrode (230) may be configured to penetrate each of the plurality of insulating layers (210) of the upper stacked insulating portion. The fourth via electrode (330) may be configured to penetrate each of the plurality of insulating layers (310) of the lower stacked insulating portion. The third via electrode (230) and the fourth via electrode (330) may have a structure that is inverted in the vertical direction relative to the core (100). Therefore, in the following description, the via electrodes provided in the upper stacked structure and the lower stacked structure will be described with reference to the third via electrode (230) provided in each of the plurality of insulating layers (210) constituting the upper stacked insulating portion.

[0100] The third via electrode (230) can electrically connect multiple fourth wiring sections (220) arranged in the vertical direction to the fourth wiring section (220) and the third wiring section (160).

[0101] The third via electrode (230) can be electrically connected to the fourth wiring section (220) and the pad section provided on the upper layer insulation section.

[0102] The third via electrode (230) may have the following shape: its width gradually narrows from the upper surface of the insulating layer (210) constituting the upper stacked insulating portion toward the lower surface of the insulating layer (210). The fourth via electrode (330) may have the following shape: its horizontal width gradually narrows as it moves from the lower surface of the insulating layer (310) constituting the lower stacked insulating portion toward the upper surface of the insulating layer (310).

[0103] The width of the second via electrode (170) can be greater than the width of the third via electrode (230). This explains the fact that the second core layer (150) has a relatively larger thickness than the insulating layer (210) constituting the upper stacked insulating portion. Therefore, the signal transmission resistance in the second via electrode (170) disposed within the core (100) can be minimized.

[0104] Although not explicitly shown, the third via electrode (230) connected to the fourth wiring section (220) may include multiple elements based on a single fourth wiring section (220). This enables improved signal transmission efficiency.

[0105] like Figure 1 As shown, the circuit board (10) according to this embodiment may include a first wiring section (121), a second wiring section (123), a third wiring section (160), a fourth wiring section (220), a fifth wiring section (320), a first via electrode (130), a second via electrode (170), a third via electrode (230), and a fourth via electrode (330) arranged in a vertically stacked configuration. Therefore, the vertical signal path within the circuit board (10) is reduced, thereby improving signal transmission efficiency.

[0106] In semiconductor packaging used in recent AI, cloud, and autonomous driving applications, package sizes are increasing due to the need for high integration to achieve high performance. Therefore, there is a growing demand for stacked vias—structures where via electrodes are vertically stacked and interconnected between as many insulating layers as possible—to reduce the number of insulating layers constituting a circuit board or minimize signal paths.

[0107] However, for circuit boards using conventional technology, as the core thickness increases to suppress board warping, the via processing method is constrained to mechanical drilling, making it difficult to reduce the size of the via electrodes within the core. Furthermore, the increased core thickness and the increased width of the via electrodes also lead to increased stress applied to the via electrodes disposed within the upper and lower stacked structures. Therefore, the problem arises that the number of insulating layers constituting the upper and lower stacked structures must also be increased.

[0108] According to this embodiment, by realizing the core (100) through multiple insulating layers including a first core layer (110) and a second core layer (150), the formation process of via electrodes (130, 170) disposed in each core layer can be more easily realized compared to a conventional single core layer. Furthermore, as the first core layer (110) moves from its vertical center toward the surface of the circuit board (10), the horizontal width of the via electrodes (130, 170, 230, 330) gradually decreases. This allows the stress generated by the vertically overlapping structure of the multiple via electrodes to be evenly distributed. In other words, since the horizontal width of the second via electrode (170) disposed within the second core layer (150) is formed to be smaller than the horizontal width of the first via electrode (130) and larger than the horizontal width of the third via electrode (230), the vertical arrangement of the multiple via electrodes can be more easily realized.

[0109] The circuit board 10 may include protective layers (410, 420). The protective layers (410, 420) may include a first protective layer (410) disposed on the surface of the upper stacked structure (200) and a second protective layer (420) disposed on the surface of the lower stacked structure (300). When semiconductor devices are disposed on the surface of the circuit board (10) using a material such as solder, the first protective layer (410) and the second protective layer (420) can perform the function of preventing short circuits between solders due to their low wettability with the solder. They can also prevent external contaminants from penetrating into the stacked structure and reducing reliability issues. The first protective layer (410) and the second protective layer (420) may each utilize a photocurable insulating material. Therefore, the first protective layer (410) and the second protective layer (420) are provided as solder resists, rather than the aforementioned ABF, PPG, BT resin, or PID. However, this is not a limitation, and as described above, they may be provided with various materials capable of performing the function of preventing short circuits between solders due to the low wettability of the solder.

[0110] The first protective layer (410) may include holes to expose pads disposed on the surface of the upper layer structure (200). Connecting members 415, such as solder balls, may be disposed in the holes. The second protective layer (420) may include holes to expose pads disposed on the surface of the lower layer structure (300) to the underside of the circuit board (10).

[0111] Therefore, the circuit board (10) can be used together with the semiconductor chip connected via the connecting member (415) to achieve semiconductor packaging.

[0112] The arrangement of the circuit section and each insulating layer according to an embodiment of the present invention will be described below.

[0113] The insulating layer described below can be any one of the first core layer (110), the second core layer (150), the multiple insulating layers (210) of the upper stacked insulating portion, or the multiple insulating layers (310) of the lower stacked insulating portion in the aforementioned circuit board (10).

[0114] The circuit section described below can be any one of the multiple wiring sections disposed on the aforementioned circuit board (10), but this does not preclude the possibility that it is any one of the multiple via electrodes.

[0115] Figure 5 This is a diagram illustrating the arrangement of glass fibers within the insulating layer according to an embodiment of the present invention. Figure 6 and Figure 7 This is a diagram used to illustrate signal loss based on the arrangement of glass fiber and circuit components. Figure 8 This is a diagram showing the arrangement of the glass fiber and circuitry according to the comparative example. Figures 9 to 11Various diagrams illustrating the arrangement of glass fibers and circuits according to embodiments of the present invention are provided. Figure 12 This is a table comparing the signal loss between the circuit board according to the comparative example and the circuit board according to an embodiment of the present invention.

[0116] refer to Figures 5 to 12 According to an embodiment of the present invention, the circuit board may include an insulating layer (500) and a circuit section (600).

[0117] The insulating layer (500) may include a resin (510) and glass fibers (520) disposed within the resin (510). The insulating layer (500) may be a prepreg (PPG) in which the resin (510) is impregnated into the glass fibers (520). For example, the resin (510) may include at least one of epoxy resin, polyimide, and bismaleimide. The glass fibers (520) serve as a reinforcing material, enhancing the durability of the insulating layer (500) and thereby improving the bending characteristics of the circuit board (10).

[0118] In addition, although not shown, the insulation layer (500) may include fillers as reinforcing materials in addition to glass fibers (520). The fillers may be composed of organic or inorganic materials.

[0119] The glass fiber (520) may include a first glass fiber (530) extending in a first horizontal direction (X) and a second glass fiber (540) extending in a second horizontal direction (Y) perpendicular to the first horizontal direction (X). The first glass fiber (530) and the second glass fiber (540) may be arranged in a mutually orthogonal configuration.

[0120] like Figures 9 to 11 As shown, the first glass fiber (530) and the second glass fiber (540) can be provided in the form of a warp and weft weave. However, this is not limiting, and the first glass fiber (530) and the second glass fiber (540) can also be arranged in the resin (510) in a vertically spaced manner. In this case, the first glass fiber (530) can be arranged on top of the second glass fiber (540).

[0121] The circuit section (600) can be disposed on the surface of the insulating layer (500). For example, the circuit section (600) can be disposed on the insulating layer (500) and can be electrically connected to a circuit section disposed on another insulating layer. Furthermore, the circuit section (600) can also have an ETS (Embedded Trace Substrate) structure to achieve fine patterning. In this case, the circuit section (600) can be embedded within the insulating layer (500). Here, "embedded" means that at least a portion of the side surface of the circuit section (600) having the ETS structure is covered by the insulating layer (500).

[0122] The insulating layer (500) may include a recess for embedding the circuit portion (600).

[0123] The circuit section (600) can be configured to form lines along the horizontal direction on the surface of the insulating layer (500). Figure 6 This is intended to demonstrate the signal transmission efficiency based on the arrangement of the circuitry and fiberglass. (Reference) Figure 6 When the circuit section (600) includes a first region (602), a second region (604), and a third region (606), the first region (602) has a longitudinal direction along a first horizontal direction (X), which is the extension direction of the first glass fiber (530); the second region (604) has a longitudinal direction along a second horizontal direction (Y), which is the extension direction of the second glass fiber (540); and the third region (606) can be tilted relative to the virtual axis forming the first horizontal direction (X) or the second horizontal direction (Y), such that it forms a predetermined angle with the first region (602) or the second region (604). In this case, the first region (602) can vertically overlap with the first glass fiber (530), and the second glass fiber (604) can vertically overlap with the second glass fiber (540). Furthermore, compared to the first region (602) and the second region (604), the third region (606) may have a relatively small area overlapping the glass fibers (520) in a direction perpendicular to them.

[0124] Here, "small area" can refer to the distribution of the vertical overlap area between each unit area and the glass fiber (520).

[0125] exist Figure 6 In the arrangement of the circuit section (600) shown, for the first region (602) and the second region (604), signal transmission through these regions to other circuit sections suffers loss due to the vertical overlap structure with the glass fiber (520). However, in the case of the third region (606), since at least a portion is misaligned in the direction perpendicular to the glass fiber (520), the signal transmission loss through the third region (606) to other circuit sections is relatively small.

[0126] With this in mind, the circuit board according to the embodiment is characterized in that, as Figure 7 As shown in (b), the arrangement of the circuit section (600) is inclined relative to the extension direction of the glass fiber (520), thereby minimizing the vertical overlap area with the glass fiber (520) and minimizing the signal transmission loss in the circuit section (600).

[0127] refer to Figure 7 (a) and Figure 8According to the comparative example, the circuit board can be configured such that the circuit section (600) overlaps with the first glass fiber (530) or the second glass fiber (540) in the vertical direction (Z). Specifically, the longitudinal direction of the circuit section (600) can be the same as the extension direction of the first glass fiber (530) or the second glass fiber (540). For example, the circuit section (600) can be configured such that its longitudinal direction is aligned with the second horizontal direction (Y), which is the extension direction of the second glass fiber (540). Therefore, the circuit section (600) can be configured such that it overlaps with the second glass fiber (540) in the vertical direction (Z).

[0128] In this case, such as Figure 8 As shown in (b), based on a cross-section perpendicular to the longitudinal direction of the circuit section (600), the first glass fiber (530) can be formed such that its vertical (Z) width remains constant along the horizontal direction. That is, since the circuit section (600) is configured to overlap the first glass fiber (530) extending in the vertical (Z) direction with the first glass fiber (530) extending in the second horizontal (Y) direction, based on a cross-section perpendicular to the longitudinal direction of the circuit section (600), the first glass fiber (530) can be formed such that its vertical (Z) width is uniform along the horizontal direction. Simultaneously, in a cross-section perpendicular to the longitudinal direction of the circuit section (600), each of the plurality of second glass fibers (540) can be horizontally arranged such that a constant gap is formed between it and adjacent second glass fibers (540) along the horizontal direction.

[0129] Figure 9 This shows that the circuit section (600) is inclined on the insulating layer (500) such that the length direction of the circuit section (600) is ( 1) A diagram showing the structure forming a first angle relative to the extension direction (Y) of the second glass fiber (540). The first angle can be 5 degrees.

[0130] refer to Figure 9 The longitudinal direction of the circuit section (600) 1) An angle of 5 degrees can be formed with respect to an imaginary axis parallel to the longitudinal direction (Y) of the second glass fiber (540). Therefore, the circuit section (600) can be configured such that at least a portion of it is not aligned with the second glass fiber (540) in the vertical direction (Z).

[0131] In this case, such as Figure 9 As shown in (b), the cross-section of the circuit section (600) may include the cross-section of the first glass fiber (530) and the cross-section of the second glass fiber (540). Specifically, based on the longitudinal direction perpendicular to the circuit section (600) 1) The cross-section of the first glass fiber (530) may include multiple regions with different widths in the vertical direction (Z).

[0132] Specifically, based on the length direction perpendicular to the circuit section (600) 1) The cross-section of the first glass fiber (530) may include a plurality of regions having varying thickness in the vertical direction, arranged along a third horizontal direction. Here, the third horizontal direction may be about Figure 9 (b) defines the horizontal direction, which is perpendicular to the longitudinal direction of the circuit section (600). 1). Specifically, the first glass fiber (530) may include a first region (532) with a large vertical (Z) width and a second region (534) with a relatively small vertical (Z) width. The vertical (Z) width of the first glass fiber (530) may gradually decrease from the first region (532) toward the second region (534), and may gradually increase from the second region (534) toward the first region (532). The first region (532) and the second region (534) may be alternately arranged along the horizontal direction of the cross-section of the circuit section (600). This is because the circuit section (600) is positioned relative to the glass fiber (520) at a predetermined tilt angle. Figure 8 Compared to the comparative example shown, the longitudinal direction perpendicular to the circuit section (600) is indicated. The cross section of 1) and the cross section along the longitudinal direction of the first glass fiber (530) are different from each other.

[0133] In some cases, based on the length direction perpendicular to the circuit section (600) 1) In the cross-section, the first glass fiber (530) may have horizontally separated regions. These separated regions may be arranged between a plurality of first regions (532).

[0134] Furthermore, in the longitudinal direction perpendicular to the circuit section (600) In the cross-section of 1), the second glass fiber (540) may include multiple regions with varying thickness in the vertical direction (z). The multiple regions of the second glass fiber (540) may be arranged along a third horizontal direction.

[0135] In the longitudinal direction perpendicular to the circuit section (600) In the cross-section of 1), the plurality of second glass fibers (540) can be configured such that each second glass fiber forms a different gap with the adjacent second glass fiber (540) along the horizontal direction. For example, when three (3) second glass fibers (540) arranged sequentially along the horizontal direction are designated as glass fiber 2-1, glass fiber 2-2, and glass fiber 2-3, based on the length direction perpendicular to the circuit section (600) In the cross-section of 1), the 2-1st and 2-2nd glass fibers can be configured to form a first gap (542) in the horizontal direction, and the 2-2nd and 2-3rd glass fibers can be configured to form a second gap (544) in the horizontal direction, different from the first gap (542). This is because the circuit section (600) is arranged at a predetermined tilt angle relative to the glass fiber (520). Figure 8 Compared to the comparative example shown, this means that the length direction perpendicular to the circuit section (600) ( 1) has a cross-section that is different from the cross-section perpendicular to the length direction of the second glass fiber (540).

[0136] From a more diverse perspective, based on the longitudinal direction perpendicular to the circuit section (600) 1) In cross-section, the glass fiber (520) may include a first glass fiber (530) forming a first group (I) and a second glass fiber (540) forming a second group (II). The first group (I) and the second group (II) may be arranged along the vertical direction of the circuit board (10). The first glass fiber (530) constituting the first group (I) may each include a convex portion (535). The convex portions (535) may be provided in multiple ways and in the length direction perpendicular to the circuit portion (600). 1) is horizontally arranged in the cross-section. Between the plurality of convex portions (535), concave portions (536) with relatively small vertical widths can be provided. The plurality of convex portions (535) can be horizontally connected via the concave portions (536). In some cases, based on the longitudinal direction perpendicular to the circuit portion (600) ( 1) The cross-section can be set in a separate area that is horizontally separated between multiple convex parts (535).

[0137] Based on the longitudinal direction perpendicular to the circuit section (600) 1) The cross-section of the second glass fiber (540) constituting the second group (II) can each have a circular or elliptical cross-sectional shape. In this case, relative to the longitudinal direction perpendicular to the circuit section (600) ( 1) The cross-section of the second glass fiber (540) can vary the gap between adjacent second glass fibers (540).

[0138] The above structure is due to the circuit section (600) being arranged at a predetermined tilt angle relative to the glass fiber (520), which means that the length direction perpendicular to the circuit section (600) is... 1) The cross-section is different from the cross-section perpendicular to the length direction of the first glass fiber (530) or the second glass fiber (540).

[0139] Figure 10This shows that the circuit section (600) is inclined on the insulating layer (500), such that the longitudinal direction of the circuit section (600) is ( 2) A diagram showing a structure with a second angle larger than the first angle relative to the extension direction (Y) of the second glass fiber (540). The second angle can be 10 degrees.

[0140] refer to Figure 10 The longitudinal direction of the circuit section (600) 2) An angle of 10 degrees can be formed relative to an imaginary axis parallel to the longitudinal direction (Y) of the second glass fiber (540). Therefore, the circuit section (600) can be configured such that at least a portion of it is misaligned with the second glass fiber (540) in the vertical direction (Z). In this case, the area of ​​the circuit section (600) misaligned with the second glass fiber (540) in the vertical direction (Z) can be larger than the area when the circuit section (600) is tilted at the first angle.

[0141] like Figure 10 As shown in (b), the cross-section of the circuit section (600) may include the cross-section of the first glass fiber (530) and the cross-section of the second glass fiber (540). Specifically, based on the longitudinal direction perpendicular to the circuit section (600) 2) The cross-section of the first glass fiber (530) may include multiple regions with different widths in the vertical direction (Z).

[0142] Specifically, based on the length direction perpendicular to the circuit section (600) 2) The cross-section of the first glass fiber (530) may include multiple regions with different thicknesses in the vertical direction (Z) arranged along the third horizontal direction. That is, based on the longitudinal direction perpendicular to the circuit section (600) 2) In the cross-section, the first glass fiber (530) may include a first region (532) having a large vertical (Z) width and a second region (534) having a relatively small vertical (Z) width. The vertical (Z) width of the first glass fiber (530) may gradually decrease from the first region (532) toward the second region (534), and may gradually increase from the second region (534) toward the first region (532). The first region (532) and the second region (534) may be alternately arranged along the horizontal direction of the cross-section of the circuit section (600). This is because the circuit section (600) is arranged at a predetermined tilt angle relative to the glass fiber (520). Figure 8 Compared to the comparative example shown, this means that in the longitudinal direction perpendicular to the circuit section (600) 2) The cross section is different from the cross section along the longitudinal direction of the first glass fiber (530).

[0143] In some cases, based on the longitudinal direction perpendicular to the circuit section (600) 2) In the cross-section, the first glass fiber (530) may have horizontally separated regions. These separated regions may be arranged between a plurality of first regions (532).

[0144] Meanwhile, compared to a circuit section (600) tilted at a relatively small first angle, the horizontal length between the plurality of first regions (532) in the vertical cross-section of the circuit section (600) tilted at a second angle can be shorter than the horizontal length between the plurality of second regions (534).

[0145] Furthermore, in the length direction perpendicular to the circuit section (600) In the cross-section of 2), the second glass fiber (540) may include multiple regions with varying thickness in the vertical direction (z). The multiple regions of the second glass fiber (540) may be arranged along a third horizontal direction.

[0146] In the longitudinal direction perpendicular to the circuit section (600) In the cross-section of 2), the plurality of second glass fibers (540) can be configured such that each second glass fiber forms a different gap relative to the adjacent second glass fiber (540) along the horizontal direction. For example, when three (3) second glass fibers (540) arranged sequentially along the horizontal direction are designated as glass fiber 2-1, glass fiber 2-2, and glass fiber 2-3, based on the length direction perpendicular to the circuit section (600) 2) In the cross-section, the 2-1 glass fiber and the 2-2 glass fiber can be configured to form a first gap (542) in the horizontal direction, and the 2-2 glass fiber and the 2-3 glass fiber can be configured to form a second gap (544) different from the first gap (542) in the horizontal direction. This is because the circuit section (600) is arranged at a predetermined tilt angle relative to the glass fiber (520). Figure 8 Compared to the comparative example shown, this means that the length direction perpendicular to the circuit section (600) ( 2) has a cross-section that is different from the cross-section perpendicular to the length direction of the second glass fiber (540).

[0147] Meanwhile, compared with the structure of the circuit section (600) which is inclined at a relatively small first angle, the gap between adjacent second glass fibers (540) in the vertical section of the circuit section (600) which is inclined at a second angle can be longer.

[0148] From a broader perspective, based on the longitudinal direction perpendicular to the circuit section (600) ( 1) In cross-section, the glass fiber (520) may include a first glass fiber (530) forming a first group (I) and a second glass fiber (540) forming a second group (II). The first group (I) and the second group (II) may be arranged along the vertical direction of the circuit board (10). The first glass fiber (530) constituting the first group (I) may each include a convex portion (535).

[0149] The convex portion (535) is provided in multiple forms and can be arranged along a longitudinal direction perpendicular to the circuit portion (600). 1) The cross-section is horizontally arranged. Between the plurality of convex portions (535), concave portions (536) with relatively small vertical widths can be provided. The plurality of convex portions (535) can be horizontally connected via the concave portions (536). In some cases, based on the longitudinal direction perpendicular to the circuit portion (600) ( 1) The cross-section, the separated areas can be horizontally arranged between multiple convex parts (535).

[0150] Meanwhile, compared with the structure of the circuit section (600) tilted at a relatively small first angle, in the vertical cross section of the circuit section (600) tilted at a second angle, the horizontal distance between the plurality of convex parts (535) and the horizontal distance between the plurality of concave parts (536) can be shorter.

[0151] Based on the longitudinal direction perpendicular to the circuit section (600) 1) The cross-section of the second glass fiber (540) constituting the second group (II) can each have a circular or elliptical cross-sectional shape. In this case, relative to the longitudinal direction perpendicular to the circuit section (600) ( 1) The cross-section of the second glass fiber (540) can vary the gap between adjacent second glass fibers (540).

[0152] The above structure is due to the circuit section (600) being arranged at a predetermined tilt angle relative to the glass fiber (520), which means that the longitudinal direction perpendicular to the circuit section (600) is... 1) The cross-section is different from the cross-section perpendicular to the longitudinal direction of the first glass fiber (530) or the second glass fiber (540).

[0153] Figure 11 This shows that the circuit section (600) is inclined on the insulating layer (500), such that the longitudinal direction of the circuit section (600) is ( 3) A diagram showing a structure forming a third angle larger than the second angle relative to the extension direction (Y) of the second glass fiber (540). The third angle can be 22.5 degrees.

[0154] refer to Figure 11 The length direction of the circuit section (600) 3) An angle of 22.5 degrees can be formed with respect to an imaginary axis parallel to the length direction (Y) of the second glass fiber (540). Therefore, the circuit section (600) can be configured such that at least a portion is misaligned with the second glass fiber (540) in the vertical direction (Z). In this case, the area of ​​the circuit section (600) misaligned with the second glass fiber (540) in the vertical direction (Z) can be larger than the area when the circuit section (600) is tilted at the first angle.

[0155] like Figure 11 As shown in (b), the cross-section of the circuit section (600) may include the cross-section of the first glass fiber (530) and the cross-section of the second glass fiber (540). Specifically, based on the longitudinal direction perpendicular to the circuit section (600) 3) The cross-section of the first glass fiber (530) may include multiple regions with different widths in the vertical direction (Z).

[0156] Specifically, based on the longitudinal direction perpendicular to the circuit section (600) 3) The cross-section of the first glass fiber (530) may include multiple regions with different thicknesses in the vertical direction (Z). That is, based on the longitudinal direction perpendicular to the circuit section (600) 3) In the cross-section, the first glass fiber (530) may include a first region (532) having a large vertical (Z) width and a second region (534) having a relatively small vertical (Z) width. The vertical (Z) width of the first glass fiber (530) may gradually decrease from the first region (532) toward the second region (534), and may gradually increase from the second region (534) toward the first region (532). The first region (532) and the second region (534) may be alternately arranged along the horizontal direction of the cross-section of the circuit section (600). This is because the circuit section (600) is arranged at a predetermined tilt angle relative to the glass fiber (520). Figure 8 Compared to the comparative example shown, this means that in the longitudinal direction perpendicular to the circuit section (600) 3) The cross section and the cross section along the longitudinal direction of the first glass fiber (530) are different from each other.

[0157] In some cases, based on the longitudinal direction perpendicular to the circuit section (600) 3) The cross-section of the first glass fiber (530) may have horizontally separated regions. These horizontally separated regions may be arranged between a plurality of first regions (532).

[0158] Meanwhile, compared with the structure of the circuit section (600) tilted at a relatively small second angle, the horizontal length between the plurality of first regions (532) and the horizontal length between the plurality of second regions (534) can be shorter in the vertical cross section of the circuit section (600) tilted at a third angle.

[0159] From a more diverse perspective, based on the longitudinal direction perpendicular to the circuit section (600) 1) In cross-section, the glass fiber (520) may include a first glass fiber (530) forming a first group (I) and a second glass fiber (540) forming a second group (II). The first group (I) and the second group (II) may be arranged along the vertical direction of the circuit board (10). The first glass fiber (530) constituting the first group (I) may each include a convex portion (535).

[0160] The convex portion (535) is provided in multiple forms and can be arranged along a longitudinal direction perpendicular to the circuit portion (600). 1) The cross-section is horizontally arranged. Between the plurality of convex portions (535), concave portions (536) with relatively small vertical widths can be provided. The plurality of convex portions (535) can be horizontally connected via the concave portions (536). In some cases, based on the longitudinal direction perpendicular to the circuit portion (600) ( 1) The cross-section, the separated areas can be horizontally arranged between multiple convex parts (535).

[0161] Meanwhile, compared with the structure of the circuit section (600) tilted at a relatively small second angle, the horizontal distance between the multiple convex parts (535) and the horizontal distance between the multiple concave parts (536) in the vertical cross section of the circuit section (600) tilted at a third angle can be shorter.

[0162] Furthermore, in the longitudinal direction perpendicular to the circuit section (600) In the cross-section of 3), the second glass fiber (540) may include multiple regions having varying thicknesses in the vertical direction (z). The multiple regions of the second glass fiber (540) may be arranged along a third horizontal direction.

[0163] Based on the longitudinal direction perpendicular to the circuit section (600) 1) The cross-section of the second glass fiber (540) constituting the second group (II) can each have a circular or elliptical cross-sectional shape. In this case, based on the longitudinal direction perpendicular to the circuit section (600) ( 1) The cross-section of the second glass fiber (540) can vary the gap between adjacent second glass fibers (540).

[0164] The above structure is achieved by arranging the circuit section (600) at a predetermined tilt angle relative to the glass fiber (520), which means that the longitudinal direction perpendicular to the circuit section (600) is... 1) The cross-section is different from the cross-section perpendicular to the longitudinal direction of the first glass fiber (530) or the second glass fiber (540).

[0165] Furthermore, in the length direction perpendicular to the circuit section (600) In the cross-section of 3), a plurality of second glass fibers (540) can be arranged such that each second glass fiber forms a different gap with the adjacent second glass fiber (540) along the horizontal direction. For example, when three (3) second glass fibers (540) arranged sequentially along the horizontal direction are designated as glass fiber 2-1, glass fiber 2-2, and glass fiber 2-3, based on the length direction perpendicular to the circuit section (600) 3) In the cross-section, the 2-1 glass fiber and the 2-2 glass fiber can be configured to form a first gap (542) in the horizontal direction, and the 2-2 glass fiber and the 2-3 glass fiber can be configured to form a second gap (544) different from the first gap (542) in the horizontal direction. This is because the circuit section (600) is arranged at a predetermined tilt angle relative to the glass fiber (520). When with Figure 8 When comparing the examples shown, this means that the length direction perpendicular to the circuit section (600) is ( 3) has a cross-section that is different from the cross-section perpendicular to the length direction of the second glass fiber (540).

[0166] Meanwhile, compared to the circuit section (600) which is inclined at a relatively small second angle, the gap between adjacent second glass fibers (540) in the vertical section of the circuit section (600) which is inclined at a third angle can be longer.

[0167] Figure 12 This is a table comparing the phase difference and power difference between multiple circuit sections (600) according to an exemplary comparative case and an exemplary case. In the exemplary comparative case, the circuit section (600) is arranged to vertically overlap with the glass fiber (520). In the exemplary case, the circuit section (600) is tilted relative to the glass fiber (520) at various angles. Here, multiple circuit sections (600) are arranged in a structure with an insulating layer (500) on which the glass fiber (520) is disposed perpendicularly.

[0168] refer to Figure 12According to the embodiment in which the circuit section (600) is tilted at a predetermined angle relative to the second glass fiber (540), it can be observed that, compared to the comparative example where the circuit section (600) and the second glass fiber (540) are superimposed in the vertical direction (Z), the phase difference and power difference between the plurality of circuit sections (600) are reduced. This indicates that, when the circuit board (10) according to the embodiment is compared with the comparative example, power loss is reduced and electrical signal transmission efficiency is improved in the electrical signal transmission between the plurality of circuit sections (600).

[0169] However, when the longitudinal direction of the circuit section (600) is tilted by 22.5 degrees or more relative to the extending direction of the second glass fiber (540), the phase difference actually increases. Furthermore, as the tilt angle of the circuit section (600) relative to the glass fiber (520) increases, the placement area of ​​the circuit section (600) on the insulating layer (500) becomes too large, making it difficult to achieve fine pitch. Preferably, the longitudinal direction of the circuit section (600) forms an angle of 5 degrees or more but less than 22.5 degrees relative to an imaginary axis parallel to the longitudinal direction of the first glass fiber (530) or the second glass fiber (540). Figure 12 As shown in the table, the specific angle can be 10 degrees.

[0170] According to this embodiment, by arranging the circuit section (600) such that it is tilted relative to the glass fiber (520) in the insulating layer (500), the vertical overlap area between the glass fiber (520) and the circuit section (600) can be minimized.

[0171] Therefore, compared with conventional methods, this provides the advantage of reducing power loss and improving the signal transmission efficiency of multiple circuit sections (600) disposed in the circuit board (10).

[0172] Figure 13 This is a diagram illustrating a semiconductor package according to an embodiment of the present invention.

[0173] refer to Figure 13 According to embodiments of the present invention, a semiconductor package may include a semiconductor chip (1000) disposed on a circuit board (10). Exemplarily, the semiconductor chip (1000) may be disposed on an upper multilayer structure (200). The semiconductor chip (1000) may be electrically and physically connected to pads disposed on the upper multilayer structure (200) via connection members (415).

[0174] The foregoing description of the combination or combined operation of components constituting embodiments of the present invention does not necessarily imply that the invention is limited to these embodiments. That is, within the scope of the invention, all components may also be selectively combined and operated in one or more ways. Furthermore, unless otherwise specifically stated, terms such as “comprising,” “including,” or “having” as described above imply that components may be present. Therefore, they should be interpreted as meaning that a component may include other components, rather than excluding other components. Unless otherwise defined, all terms, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Unless expressly defined herein, commonly used terms (such as those defined in dictionaries) should be interpreted according to their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense.

[0175] The above description is merely illustrative of the technical concept of the present invention. Those skilled in the art will understand that various modifications and variations can be made without departing from the essential characteristics of the invention. Therefore, the embodiments disclosed herein are intended to illustrate the technical concept of the invention, not to limit it, and the scope of the technical concept of the invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the appended claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present invention.

[0176] Furthermore, when a circuit board having the above-described features of this invention is applied to IT devices or home appliances such as smartphones, server computers, or televisions, it can reliably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of this invention performs a semiconductor packaging function, it can safely protect the semiconductor chip from external moisture or contaminants, and can solve problems such as leakage current, electrical short circuits between terminals, or electrical open circuits in the terminals supplying the semiconductor chip. In addition, when responsible for signal transmission functions, it can solve noise problems. Therefore, a circuit board having the above-described features of this invention enables the stable functioning of IT devices or home appliances, thereby achieving functional integrity or technical interconnectivity between the entire product and the circuit board incorporating this invention.

[0177] When a circuit board having the features of the aforementioned invention is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, or safely protect the semiconductor chip controlling the transportation device from external sources. It can also solve problems such as leakage current, electrical short circuits between terminals, or electrical open circuits in the terminals supplying the semiconductor chip, thereby further improving the stability of the transportation device. Therefore, the transportation device and circuit board incorporated into this invention can achieve functional integration or technical interlocking.

Claims

1. A circuit board, comprising: An insulating layer comprising a resin and glass fibers disposed within the resin; as well as The circuit section is disposed on the insulating layer. The glass fiber includes a first glass fiber extending in a first horizontal direction and a second glass fiber disposed on the first glass fiber and extending in a second horizontal direction. The cross-sections of the first glass fiber and the second glass fiber are arranged on the cross-section of the circuit section. The first glass fiber includes multiple regions arranged such that its thickness in the vertical direction varies along a third horizontal direction at a predetermined angle to the first horizontal direction, and the second glass fiber includes multiple cross-sectional portions spaced apart along the third horizontal direction.

2. The circuit board according to claim 1, wherein, The longitudinal direction of the circuit section is inclined at a predetermined angle relative to an imaginary axis parallel to the longitudinal direction of the second glass fiber.

3. The circuit board according to claim 2, wherein, The longitudinal direction of the circuit section has an angle of 5 degrees or more but less than 22.5 degrees relative to an imaginary axis parallel to the longitudinal direction of the second glass fiber.

4. The circuit board according to claim 3, wherein, The longitudinal direction of the circuit section forms a 10-degree angle with respect to an imaginary axis parallel to the longitudinal direction of the second glass fiber.

5. The circuit board according to claim 1, wherein, The plurality of regions of the first glass fiber include a first region and a second region having a smaller vertical width than the first region.

6. The circuit board according to claim 5, wherein, The first region and the second region are arranged alternately along the third horizontal direction.

7. The circuit board according to claim 5, wherein, The vertical width of the first glass fiber gradually increases as it moves from the first region to the second region, and the vertical width of the first glass fiber gradually decreases as it moves from the second region to the first region.

8. The circuit board according to claim 5, wherein, Based on a cross-section perpendicular to the longitudinal direction of the circuit section, the first glass fiber has regions separated in the third horizontal direction.

9. The circuit board according to claim 1, wherein, Based on a cross-section perpendicular to the longitudinal direction of the circuit section, the plurality of cross-sectional portions of the second glass fiber have different gaps with adjacent cross-sectional portions along the third horizontal direction.

10. The circuit board according to claim 9, wherein, The second glass fiber includes a second-1 glass fiber, a second-2 glass fiber, and a second-3 glass fiber arranged sequentially along the third horizontal direction, wherein the first-1 glass fiber and the second-2 glass fiber form a first gap in the third horizontal direction, and the second-2 glass fiber and the second-3 glass fiber form a second gap in the third horizontal direction that is different from the first gap.

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