Voltage stabilizing circuit, memory and electronic device

Abstract

The present disclosure provides a voltage stabilizing circuit, a memory and an electronic device, and relates to the technical field of integrated circuits. The voltage stabilizing circuit comprises a first sub-voltage stabilizing circuit and a second sub-voltage stabilizing circuit. The first sub-voltage stabilizing circuit forms a first control loop by inputting a sampling voltage at a second terminal; the second sub-voltage stabilizing circuit is coupled with the first sub-voltage stabilizing circuit through a fifth terminal and coupled with a first terminal through an eighth terminal to form a second control loop. The first control loop and the second control loop respond to an output voltage greater than a reference voltage to pull down the output voltage to the reference voltage, and respond to the output voltage less than the reference voltage to pull up the output voltage to the reference voltage. The present disclosure adjusts the output voltage through the double control loops formed by the first sub-voltage stabilizing circuit and the second sub-voltage stabilizing circuit, which can further improve the stability and accuracy of the output voltage and achieve a faster transient response.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a voltage regulator circuit, a memory, and an electronic device. Background Technology

[0002] With the continuous development of semiconductor memory technology, the storage density of memory is gradually increasing, and the frequency of read, write, and refresh operations is also continuously accelerating. This technological background places higher demands on the power supply inside the memory. Voltage regulator circuits, especially low dropout regulators (LDOs), are widely used in the power supply modules of memory due to their simple structure and excellent voltage regulation performance. However, existing voltage regulator circuits still have certain shortcomings in terms of output voltage accuracy and voltage regulation capability.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] This disclosure provides a voltage regulator circuit, a memory, and an electronic device that improves the accuracy and regulation capability of the output voltage to at least a certain extent.

[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part by practice of this disclosure.

[0006] According to one aspect of this disclosure, a voltage regulator circuit is provided, comprising: a first sub-voltage regulator circuit including a first terminal, a second terminal, a third terminal, and a fourth terminal; the first terminal serves as an output node, outputting the output voltage of the voltage regulator circuit; the second terminal is used to input a sampled voltage obtained by acquiring the output voltage; the third terminal is used to input a reference voltage; and the fourth terminal is coupled to a first reference potential. The first sub-voltage regulator circuit forms a first control loop by inputting the sampled voltage at the second terminal. The first control loop, in response to the output voltage being greater than the reference voltage, pulls the output voltage down to the reference voltage; and in response to the output voltage being less than the reference voltage, pulls the output voltage down to the reference voltage. The first sub-regulator circuit is pulled up to the reference voltage; the second sub-regulator circuit includes a fifth terminal, a sixth terminal, a seventh terminal, and an eighth terminal. The fifth terminal is coupled to the first sub-regulator circuit. The sixth terminal is used to input the power supply voltage. The seventh terminal is coupled to a second reference potential. The eighth terminal is coupled to the first terminal. The second sub-regulator circuit forms a second control loop through the coupling of the fifth terminal to the first sub-regulator circuit and the coupling of the eighth terminal to the first terminal. The second control loop pulls the output voltage down to the reference voltage in response to the output voltage being greater than the reference voltage, and pulls the output voltage up to the reference voltage in response to the output voltage being less than the reference voltage.

[0007] In one embodiment of this disclosure, the first sub-regulator circuit includes: a first transistor, the source of the first transistor being the first terminal; an error amplifier, the inverting input of the error amplifier being the second terminal, the non-inverting input of the error amplifier being the third terminal, and the output of the error amplifier being coupled to the gate of the first transistor; and a first current source, one end of the first current source being connected to the drain of the first transistor, and the other end being the fourth terminal.

[0008] In one embodiment of this disclosure, the second sub-regulator circuit includes: a second transistor, the drain of which is a seventh terminal, and the gate of which is a fifth terminal, the fifth terminal being coupled to the drain of the first transistor; a second current source, one end of which is coupled to the source of the second transistor, and the other end being a sixth terminal; and N frequency shift units, each of the N frequency shift units including a first connection terminal, a second connection terminal, and a third connection terminal, the first connection terminals of each of the N frequency shift units being coupled together. The first connection terminal is the sixth terminal. The second connection terminals of each of the N frequency shifting units are coupled together. The second connection terminal is the eighth terminal. The third connection terminal of the i-th frequency shifting unit is coupled to the (i-1)-th frequency shifting unit. The third connection terminal of the 1-th frequency shifting unit is coupled to the source of the second transistor. Here, N is an integer greater than or equal to 2, and i is an integer greater than or equal to 2 and less than or equal to N. The N frequency shifting units are used to shift the pole frequency from the first frequency band to the second frequency band, where the second frequency band is higher than the first frequency band.

[0009] In one embodiment of this disclosure, the frequency shifting unit includes: a buffer circuit, the input terminal of which is the third connection terminal; a third transistor, the gate of which is coupled to the output terminal of the buffer circuit, the source of which is the first connection terminal, and the drain of which is the second connection terminal; wherein, the input terminal of the buffer circuit in the i-th frequency shifting unit is coupled to the gate of the third transistor in the (i-1)-th frequency shifting unit, and the buffer circuit is used to reduce the gate impedance of the third transistor.

[0010] In one embodiment of this disclosure, the sum of the powers of the N third transistors in the N frequency shift units is less than or equal to a power threshold.

[0011] In one embodiment of this disclosure, the voltage regulator circuit further includes: a load current mirror unit; the load current mirror unit includes: a fourth transistor, the gate of the fourth transistor being coupled to the source of the second transistor, and the source of the fourth transistor being coupled to the sixth terminal; a fifth transistor, the source of the fifth transistor being coupled to the drain of the fourth transistor, the gate of the fifth transistor being coupled to the output terminal of the error amplifier, and the drain of the fifth transistor being used to output a bias current for controlling the buffer circuit.

[0012] In one embodiment of this disclosure, the current output to each of the buffer circuits is 1 / N of the bias current.

[0013] In one embodiment of this disclosure, the value of N is 2.

[0014] According to another aspect of this disclosure, a memory is provided on which a voltage regulator circuit as described in any of the preceding claims is integrated.

[0015] According to another aspect of this disclosure, an electronic device is provided, the electronic device comprising: a memory as described above.

[0016] In this embodiment, the voltage regulator circuit includes a first sub-voltage regulator circuit and a second sub-voltage regulator circuit. The first terminal of the first sub-voltage regulator circuit serves as an output node, outputting the output voltage of the voltage regulator circuit. The second terminal is used to input a sampled voltage obtained by acquiring the output voltage. The third terminal inputs a reference voltage. The fourth terminal is coupled to a first reference potential. The first sub-voltage regulator circuit forms a first control loop by inputting the sampled voltage at the second terminal. The fifth terminal of the second sub-voltage regulator circuit is coupled to the first sub-voltage regulator circuit. The sixth terminal is used to input a power supply voltage. The seventh terminal is coupled to a second reference potential. The eighth terminal is coupled to the first terminal. The second sub-voltage regulator circuit forms a second control loop by coupling the fifth terminal to the first sub-voltage regulator circuit and the eighth terminal to the first terminal. The first and second control loops respond to the output voltage being greater than the reference voltage by pulling the output voltage down to the reference voltage, and respond to the output voltage being less than the reference voltage by pulling the output voltage up to the reference voltage. The voltage regulator circuit disclosed herein includes a first sub-regulator circuit and a second sub-regulator circuit. The first sub-regulator circuit provides a higher loop gain to improve the accuracy of the output voltage, while the second sub-regulator circuit provides a higher loop bandwidth to achieve a fast transient response. This disclosure regulates the output voltage through a dual control loop formed by the first and second sub-regulator circuits, which can further improve the stability and accuracy of the output voltage and achieve a faster transient response.

[0017] Furthermore, the first sub-regulator circuit provides a loop (first control loop) between the output voltage and the reference voltage, which can ensure that the output voltage can stably follow the reference voltage, so that the output voltage can be stabilized near the reference voltage, thereby further improving the accuracy of the output voltage.

[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0020] Figure 1 A schematic diagram of a voltage regulator circuit is shown.

[0021] Figure 2 A schematic diagram of a voltage regulator circuit based on an FVF structure is shown.

[0022] Figure 3 A schematic diagram of a voltage regulator circuit according to an embodiment of the present disclosure is shown.

[0023] Figure 4 A schematic diagram of the first sub-regulator circuit in one embodiment of this disclosure is shown.

[0024] Figure 5 A schematic diagram of the second sub-regulator circuit is shown in one embodiment of this disclosure.

[0025] Figure 6 A schematic diagram of the connection of the frequency shift unit in one embodiment of the present disclosure is shown.

[0026] Figure 7 A schematic diagram showing the connection of three frequency shifting units in one embodiment of this disclosure is provided.

[0027] Figure 8 A schematic diagram of a voltage regulator circuit according to another embodiment of this disclosure is shown.

[0028] Figure 9 A schematic diagram of a voltage regulator circuit according to another embodiment of the present disclosure is shown.

[0029] Figure 10 A schematic diagram of a voltage regulator circuit according to yet another embodiment of this disclosure is shown.

[0030] Figure 11 A structural block diagram of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0031] Preferred embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0032] The terms "first" and "second" used herein are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0033] In the description of this disclosure, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "coupling" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between the components; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0034] With the continuous advancement of semiconductor memory technology, the storage density of memory has been significantly improved, while the frequency of read, write, and refresh operations has also gradually increased. This trend places more stringent requirements on the power supply system of memory chips. To meet these demands, voltage regulator circuits such as LDOs have been widely used in the power supply modules of memory chips due to their simple structure, stable performance, and ease of integration. However, existing voltage regulator circuits still have certain shortcomings in terms of output voltage accuracy.

[0035] In an exemplary embodiment, such as Figure 1 As shown, the voltage regulator circuit includes an error amplifier EA and a power transistor M. P And a feedback network consisting of resistors R1 / R2. Reference voltage V. REF From the bandgap reference source module, that is, the reference voltage V REF This is the output voltage of the bandgap reference source module. Power transistor M P The drain of the power transistor M is coupled to one end of resistor R1, the other end of resistor R1 is coupled to one end of resistor R2, and the other end of resistor R2 is grounded. P The source and power supply voltage V DD Coupling. The non-inverting input of the error amplifier EA is used to input the feedback signal V. FB Its inverting input terminal is used to input the reference voltage V. REF The output of error amplifier EA is connected to power transistor M. P The gate is coupled, and the power transistor M P The drain and the external large capacitor C L1 One end is coupled to an external large capacitor C. L1 The other end is grounded, power transistor M PDrain and current source I LOAD One end is coupled to the current source I. LOAD The other end is grounded. Power transistor M P The drain of the circuit is used as the output node to output the voltage V of the voltage regulator circuit. OUT .

[0036] Figure 1 The basic voltage regulation principle of the voltage regulator circuit shown is as follows: When external conditions fluctuate, causing the output voltage V to... OUT When it increases, the feedback signal V FB As it increases, the output signal V of the error amplifier EA also increases. EA Increase, power transistor M P The voltage difference between the gate and source decreases, the current flowing through resistor R1 / R2 decreases, thereby reducing the output voltage V. OUT This achieves the effect of voltage stabilization.

[0037] Similarly, when external conditions fluctuate, causing the output voltage V to... OUT When it decreases, the feedback signal V FB As a result, the output signal V of the error amplifier EA decreases. EA Reduce, power transistor M P The increased gate-source voltage difference leads to an increased current flowing through resistors R1 and R2, thereby increasing the output voltage V. OUT This achieves the effect of voltage stabilization.

[0038] It should be noted that this disclosure is for the load that the equivalent voltage regulator circuit needs to drive, at an output voltage V. OUT The node is connected to a current source I. LOAD In the exemplary embodiment described above, the voltage regulator circuit loop contains two high-impedance nodes, namely the output node of the error amplifier EA and the output node of the voltage regulator circuit. In the voltage regulator circuit structure described above, an external large capacitor C is coupled to the output node of the voltage regulator circuit. L1 (For example, capacitors in the hundreds of picofarads to nanofarads range) are used to determine the output node of the voltage regulator circuit as the dominant pole, ensuring loop stability. However, the following shortcomings exist.

[0039] ① The output node impedance of error amplifier EA is relatively high. The output impedance of error amplifier EA and the power transistor M... P The gate-end parasitic capacitance is relatively large, meaning that the non-dominant pole at the output node of the error amplifier EA will be at a relatively low frequency, close to the dominant pole, thus reducing loop stability. To solve this problem, an additional frequency compensation circuit is needed, which increases the circuit complexity.

[0040] ② The two high-impedance nodes place the loop poles at a relatively low frequency, which reduces the overall bandwidth of the voltage regulator circuit and slows down the circuit response. Meanwhile, the operating frequency of chips (such as memory chips) is increasing, and the load current switching of the voltage regulator circuit is becoming more frequent. In this context, if the voltage regulator circuit cannot provide a fast transient response, it will cause large overshoot / undershoot phenomena in the output voltage, making the chip malfunction. It should be noted that the chip has a voltage regulator circuit configured on it.

[0041] ③ When the load current increases, the frequency of the dominant pole will shift to a higher frequency, which will reduce the stability of the loop.

[0042] ④ External capacitor C L1 This does not align with the current trend of miniaturization and increased integration in manufacturing processes.

[0043] To address the problems in the above exemplary embodiments, this disclosure provides the following exemplary embodiments.

[0044] In an exemplary embodiment, such as Figure 2 As shown, in a voltage regulator circuit based on a flipped voltage follower (FVF) structure, the voltage regulator circuit includes an error amplifier EA and a power transistor M. PASS Transistor M C Transistor M B Compensation capacitor C C Current source I B1 and current source I B2 power transistor M PASS The source and power supply voltage V DD Coupled, power transistor M PASS Gate and transistor M C The drain coupling of the power transistor M PASS The drain and transistor M C The source is coupled to the transistor M. C Drain and current source I B2 One end is coupled to the current source I. B2 The other end is grounded, transistor M C The source of the voltage regulator circuit is used as the output node to output the voltage V. OUT transistor M C Gate and transistor M B Gate coupling, transistor M B Gate and transistor M B The drain is coupled to the transistor M. B Drain and current source I B1 One end is coupled to the current source I. B1 The other end is grounded. The non-inverting input of the error amplifier EA is fed with a reference voltage V.REF The inverting input terminal of error amplifier EA is coupled to the output terminal of error amplifier EA, and the output terminal of error amplifier EA is coupled to transistor M. B The source is coupled to the transistor M. C The drain and compensation capacitor C C One end is coupled to the compensation capacitor C. C The other end is grounded.

[0045] To represent the load driven by the voltage regulator circuit, the voltage regulator circuit provided in this disclosure includes a current source I. LOAD and load capacitance C L2 Transistor M C The source and current source I LOAD One end is coupled to the current source I. LOAD The other end is grounded, transistor M C The source and load capacitance C L2 One end is coupled, and the load capacitor C L2 The other end is grounded.

[0046] In the voltage regulator circuit of the exemplary embodiments of this disclosure, the reference voltage V from the bandgap reference source REF The voltage V is generated after passing through an error amplifier EA with a unity-gain negative feedback connection. B Voltage V B Transistor M connected via diode B Generated voltage V CTRL Transistor M B It is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), with a voltage V. CTRL Specific voltage V B The next MOSFET (transistor M) B The gate-source voltage difference V SG_MB And the voltage V CTRL It is also coupled to transistor M C The gate of the transistor M C and power transistor M PASS All are MOSFETs, in transistor M C The source generates an output voltage V. OUT Output voltage V OUT Specific voltage V CTRL One higher MOS transistor (transistor M) C The gate-source voltage difference V SG_MC At the same time, make transistor M B and transistor M C When biased under the same current, i.e., I1 = I2, V can be made SG_MB =VSG_MC Therefore, the output voltage V OUT Voltage V CTRL Voltage V B and reference voltage V REF It can satisfy V OUT =V CTRL +V SG_MC =V CTRL +V SG_MB =V B =V REF .

[0047] The main voltage regulation mechanism of the above voltage regulator circuit consists of transistor M. C and power transistor M PASS This is achieved by forming a feedback loop. In this loop, transistor M... C It can be viewed as a common-gate amplifier, with power transistor M PASS As common-source amplifiers, their combination provides moderate loop gain and brings relative Figure 1 It has a higher bandwidth than the voltage regulator circuit in the exemplary embodiment. Its voltage regulation principle is as follows.

[0048] When the load current suddenly changes from light load to heavy load, the output voltage V OUT It will decrease. This is due to transistor M. C When biased under a constant current I2, under the channel length modulation effect, its source-drain voltage difference V SD_MC It should remain unchanged, therefore its drain voltage V FB Following the source voltage V OUT (i.e., output voltage V) OUT This causes the power transistor M to decrease. PASS Gate-source voltage difference V SG_PASS Increase, thereby increasing the flow through the power transistor M PASS The increased current at node V OUT The voltage is increased to achieve the effect of voltage stabilization and regulation.

[0049] Similarly, when the load current changes abruptly from heavy load to light load, the output voltage V OUT It will rise. Because of transistor M C When biased under a constant current I2, considering the channel length modulation effect, its source-drain voltage difference V SD_MC It should remain unchanged, therefore its drain voltage V FB Following the source voltage V OUT (i.e., output voltage V) OUT This causes the power transistor M to rise. PASS Gate-source voltage difference V SG_PASS Reduce, thereby reducing the flow through the power transistor M PASS The current decreases, causing node V to... OUTThe voltage is reduced, achieving the effect of voltage stabilization and regulation.

[0050] In the above exemplary embodiment, there are two high-impedance nodes in the loop of the voltage regulator circuit. The two high-impedance nodes are voltage V and voltage V. FB The output terminal (abbreviated as V) FB (node) and output voltage V OUT The output terminal (abbreviated as V) OUT (Node). Considering V FB The resistance at the node can be equivalent to that of transistor M. C and power transistor M PASS The output impedance of the common-source cascode device is related to the current source I. B2 The parallel connection of output impedances, while V OUT The equivalent resistance of a node is mainly due to transistor M. C The source impedance can be analyzed to determine V. FB The node impedance is higher than that of node V. OUT The impedance is such that the dominant pole of the loop is set at V. FB At the node, and V OUT The poles corresponding to the nodes are secondary dominant poles. Furthermore, to ensure loop stability, we can... FB Add compensation capacitor C at the location C This is to ensure that the dominant pole is far from the secondary dominant pole. Relative Figure 1 Regarding the voltage regulator circuit in the exemplary embodiment, the FVF-based voltage regulator circuit uses smaller on-chip integrated capacitors, resulting in a higher pole frequency, thereby optimizing bandwidth and improving circuit response speed. However, this voltage regulator circuit still has the following shortcomings.

[0051] ①By transistor M C and power transistor M PASS The loop gain is not high, and the output voltage V OUT With reference voltage V REF The lack of a feedback loop prevents the voltage regulator circuit's output voltage from accurately following the reference voltage V. REF .

[0052] ② To achieve higher bandwidth, the nodes in the voltage regulator circuit need to be generally at relatively high frequencies. However, as mentioned earlier, V FB The node has a large equivalent resistance, and the large-size power transistor M PASS This will introduce a large parasitic capacitance, so the voltage V FB The corresponding poles are located at relatively low frequencies, which limits the increase in bandwidth and thus restricts the response speed of the voltage regulator circuit.

[0053] ③ The memory cell density of the memory chip is relatively large, and the load capacitor C required by the voltage regulator circuit to drive it is large. L2A higher frequency will cause the secondary dominant pole to shift to a lower frequency and move closer to the dominant pole, reducing loop stability and posing a risk of output oscillation.

[0054] To address the problems in the above exemplary embodiments, this disclosure provides the following exemplary embodiments.

[0055] In an exemplary embodiment, such as Figure 3 As shown, this disclosure provides a voltage regulator circuit, which may include a first sub-voltage regulator circuit 31 and a second sub-voltage regulator circuit 32.

[0056] The first sub-regulator circuit 31 includes a first terminal 1, a second terminal 2, a third terminal 3, and a fourth terminal 4. The first terminal 1 serves as the output node, outputting the output voltage V of the regulator circuit. OUT The second terminal 2 is used to input the output voltage V. OUT The sampled voltage is collected, and the third terminal 3 is used to input the reference voltage V. REF The fourth terminal 4 is coupled to the first reference potential V. SS1 The first sub-regulator circuit 31 forms a first control loop by inputting a sampling voltage at the second terminal 2. The first control loop responds to the output voltage V. OUT Greater than the reference voltage V REF The output voltage V OUT Pull down to reference voltage V REF , in response to output voltage V OUT Less than the reference voltage V REF The output voltage V OUT Pull up to reference voltage V REF .

[0057] The second sub-regulator circuit 32 includes a fifth terminal 5, a sixth terminal 6, a seventh terminal 7, and an eighth terminal 8. The fifth terminal 5 is coupled to the first sub-regulator circuit 31, and the sixth terminal 6 is used to input the power supply voltage V. DD The seventh terminal 7 is coupled to the second reference potential V. SS2 The eighth terminal 8 is coupled to the first terminal 1. The second sub-regulator circuit 32 is coupled to the first sub-regulator circuit 31 via the fifth terminal 5 and the eighth terminal 8 is coupled to the first terminal 1, forming a second control loop. The second control loop responds to the output voltage V. OUT Greater than the reference voltage V REF The output voltage V OUT Pull down to reference voltage V REF , in response to output voltage V OUT Less than the reference voltage V REF The output voltage V OUT Pull up to reference voltage V REF .

[0058] In this embodiment, the position of the coupling node between the fifth terminal 5 and the first sub-voltage regulator circuit 31 is not specifically limited, as long as it can follow the output voltage V. OUT A positively changing coupling node is sufficient. For example, when the output voltage V... OUT As the voltage increases, the voltage at the coupling node also increases. When the output voltage V... OUT When the voltage decreases, the voltage at the coupling node also decreases.

[0059] In this embodiment of the disclosure, regarding the first reference potential V SS1 Second reference potential V SS2 The specific potential potential can be set according to the specific application scenario and practical application experience in this embodiment. For example, the first reference potential potential V SS1 Second reference potential V SS2 All are zero potential reference points (i.e., grounded).

[0060] The voltage regulator circuit in this embodiment includes a first sub-regulator circuit and a second sub-regulator circuit. The first sub-regulator circuit provides a higher loop gain for the overall voltage regulation system to improve the accuracy of the output voltage, while the second sub-regulator circuit provides a higher loop bandwidth to achieve a fast transient response. Furthermore, this disclosure regulates the output voltage through a dual control loop formed by the first and second sub-regulator circuits, which can further improve the stability and accuracy of the output voltage and achieve a faster transient response.

[0061] Furthermore, the first sub-regulator circuit provides a first control loop between the output voltage and the reference voltage, ensuring that the output voltage accurately and stably follows the reference voltage, thus stabilizing the output voltage near the reference voltage and further improving the accuracy of the output voltage. The second sub-regulator circuit improves the loop transient response speed by reducing the node impedance to increase the loop bandwidth.

[0062] The first and second sub-regulator circuits are described below.

[0063] In one exemplary embodiment, such as Figure 4 As shown, the first sub-regulator circuit 31 includes: a first transistor M E Error amplifier EA and first current source I h1 Among them, the first transistor M E The source is the first terminal 1, which is used as the output node to output the output voltage V of the voltage regulator circuit. OUT The inverting input of error amplifier EA is terminal 2 (second terminal), and the non-inverting input is terminal 3 (third terminal). Terminal 3 is used to input the reference voltage V. REFThe output of the error amplifier EA is connected to the first transistor M. E The gate is coupled. First current source I h1 One end is connected to the first transistor M E The drain connection, the first current source I h1 The other end is the fourth terminal 4, which is connected to the first reference potential V. SS1 Coupled, first reference potential V SS1 It can serve as a zero-potential reference point.

[0064] In this embodiment of the disclosure, the specific type of transistor used as the first transistor is not limited; any transistor that can meet the functional requirements of this disclosure is acceptable. For example, the first transistor may be a bipolar transistor or a field-effect transistor. Another example is a P-type MOS transistor.

[0065] The first sub-regulator circuit in this embodiment provides a high loop gain, resulting in a higher output voltage V. OUT It can be stabilized at the reference voltage V REF Nearby. When the load current changes, it causes the output voltage V to... OUT When the voltage increases, due to the output voltage V OUT Connecting to the inverting input of error amplifier EA will cause the voltage V at the output of error amplifier EA to... EA Decrease. Because the first transistor M E The drain and the first current source I h1 Coupled, the first transistor M E Biased to a constant current, therefore the first transistor M E Gate-source voltage difference V SG_MP1 The voltage remains unchanged, so its source voltage (i.e., output voltage V) remains constant. OUT Follow voltage V EA Decrease.

[0066] Similarly, when the load current changes, it causes the output voltage V to change. OUT When it decreases, due to the output voltage V OUT Connecting to the inverting input of error amplifier EA will cause the voltage V at the output of error amplifier EA to... EA Increase. Because the first transistor M E The drain and the first current source I h1 Coupled, the first transistor M E Biased to a constant current, therefore the first transistor M E Gate-source voltage difference V SG_MP1 The voltage remains unchanged, so its source voltage (i.e., output voltage V) remains constant. OUT Follow voltage V EA Increase.

[0067] The first sub-regulator circuit in this embodiment provides a high loop gain, and the first control loop formed between the output voltage and the reference voltage can ensure that the output voltage can accurately and stably follow the reference voltage, so that the output voltage can be stabilized near the reference voltage, thereby further improving the accuracy of the output voltage.

[0068] In another exemplary embodiment, such as Figure 5 As shown, the second sub-regulator circuit 32 may include: a second transistor M F Second current source I h2 And N frequency shift units. Among them, the second transistor M... F The drain is at the seventh terminal 7, that is, the second transistor M F The drain is coupled to the second reference potential V SS2 Second reference potential V SS2 The zero potential reference point can be the second transistor M. F The gate is the fifth terminal 5, and the fifth terminal 5 is connected to the first transistor M. E The drain is coupled. Second current source I h2 One end is connected to the second transistor M F The source is coupled, and the second current source I h2 The other end is the sixth terminal 6, which is used to input the power supply voltage V. DD Each of the N frequency shift units includes a first connection terminal L1, a second connection terminal L2, and a third connection terminal L3. The first connection terminals L1 of each of the N frequency shift units are coupled together and are the sixth terminal 6. The second connection terminals L2 of each of the N frequency shift units are coupled together and are the eighth terminal 8. The second connection terminals L2 are coupled to the first terminal 1 of the first sub-regulator circuit 31. The third connection terminal L3 of the i-th frequency shift unit is coupled to the (i-1)-th frequency shift unit. The third connection terminal L3 of the 1-th frequency shift unit is coupled to the second transistor M. F The source is coupled, where N is an integer greater than or equal to 2, i is an integer greater than or equal to 2 and less than or equal to N, and N frequency shift units are used to shift the pole frequency from the first frequency band to the second frequency band, which is higher than the first frequency band.

[0069] In this embodiment of the disclosure, the specific value of N is not limited. For example, the value of N can be in the range of 2-20. As another example, the value of N can be any one of 2, 3, 4, 5, 6, 8, 10, or 20.

[0070] The present disclosure does not specify the type of transistor used for the second transistor, and it can be determined based on the actual application scenario and specific application experience. For example, the second transistor may be a bipolar transistor or a field-effect transistor. Another example is a P-type MOSFET.

[0071] In this embodiment, the fifth terminal 5 is connected to the first transistor M. E The drain of the circuit is coupled, and the second connection terminal L2 is coupled to the first terminal 1 of the first sub-voltage regulator circuit 31 to form a second control loop. The second control loop works in conjunction with the first control loop to realize the regulation of the output voltage by the dual control loop, thereby improving the stability and accuracy of the output voltage.

[0072] Furthermore, the frequency shifting unit can shift the corresponding pole frequency to a higher frequency band, thereby increasing the circuit bandwidth and providing a fast transient response.

[0073] In yet another exemplary embodiment, such as Figure 6 As shown, the frequency shifting unit may include a buffer circuit 61 and a third transistor. The input terminal of the buffer circuit 61 is the third connection terminal L3, the gate of the third transistor is coupled to the output terminal of the buffer circuit 61, the source of the third transistor is the first connection terminal L1, and the drain of the third transistor is the second connection terminal L2. The input terminal of the buffer circuit in the i-th frequency shifting unit is coupled to the gate of the third transistor in the (i-1)-th frequency shifting unit, and the buffer circuit is used to reduce the gate impedance of the third transistor.

[0074] In this embodiment, the buffer circuit is used for signal isolation, transmission, or improving driving capability in electronic circuits. The buffer circuit in this embodiment features low input capacitance and low output impedance. This embodiment does not limit the specific type of buffer circuit; any circuit with the above characteristics is acceptable. For example, the buffer circuit can be a buffer.

[0075] The specific type of transistor used in this disclosure is not limited and can be determined based on actual application scenarios and practical experience. For example, the third transistor may be a bipolar transistor or a field-effect transistor. Another example is a P-type MOS transistor.

[0076] For example, such as Figure 7 As shown, there are 3 frequency shift units. The input terminal of the buffer circuit B3 in the 3rd frequency shift unit is connected to the third transistor M in the 2nd frequency shift unit. P2 The gate is coupled, and the input terminal of the buffer circuit B2 in the second frequency shift unit is connected to the third transistor M in the first frequency shift unit. P1The gate is coupled, and the input of the buffer circuit B3 in the first frequency shift unit is used to connect with the second transistor M. F The source is coupled. That is, from the second transistor M F The signal output from the source is delayed by one time interval before being input to the third transistor M in the first frequency shift unit. P1 The gate of the second transistor M F The signal output from the source is delayed by twice the interval before being input to the third transistor M in the second frequency shift unit. P2 The gate of the second transistor M F The signal output from the source is delayed by three times the interval before being input to the third transistor M in the third frequency shift unit. P3 The gate of the buffer circuit. Delaying the operation of each third transistor alters the current path, thus achieving frequency shifting. It should be noted that the interval duration is the delay time of the buffer circuit, and its length is determined by the specific structure of the buffer circuit.

[0077] The buffer circuit in this embodiment features low input capacitance and low output impedance, which effectively reduces the impedance of the internal nodes of the second control loop, thereby increasing bandwidth. It should be noted that because the buffer circuit has low input capacitance, this disclosure eliminates the need for additional external large coupling capacitors, thus reducing the complexity of layout design.

[0078] In one embodiment, the sum of the powers of the N third transistors in the N frequency shift units is less than or equal to a power threshold. The power threshold is set based on the actual application scenario and specific application experience.

[0079] It should be noted that the third transistor in this embodiment is a power transistor, specifically a small-sized power transistor (its size is smaller than...). Figure 2 Medium power transistor M PASS The size of a power transistor is much smaller than that of a conventional transistor. A larger power transistor can typically handle greater power; in other words, the size of a power transistor is directly proportional to its power output. This disclosed embodiment, compared to… Figure 2 In the corresponding exemplary embodiment, the originally larger power transistor (power transistor M) is replaced with a smaller one. PASS Decomposing the power transistor into multiple smaller power transistors (e.g., multiple small third transistors) can reduce the parasitic capacitance of the corresponding node. This embodiment utilizes the low input capacitance and low output impedance of the buffer circuit to significantly reduce the node impedance within the second control loop. Furthermore, decomposing the originally large power transistor into multiple smaller power transistors can reduce the parasitic capacitance of the corresponding node. In this way, the corresponding pole frequency can be shifted to a higher frequency band, resulting in increased circuit bandwidth and providing a fast transient response.

[0080] The first and second sub-regulator circuits have been described above. The load current mirror unit of the voltage regulator circuit disclosed herein will be described below through exemplary embodiments.

[0081] In an exemplary embodiment, such as Figure 8 As shown, the voltage regulator circuit may further include a load current mirror unit 33. The load current mirror unit 33 may include a fourth transistor M. MIR and the fifth transistor M G The fourth transistor M MIR The gate and the second transistor M F The source is coupled, and the fourth transistor M MIR The source of the fifth transistor is coupled to the sixth terminal 6. G The source and the fourth transistor M MIR The drain is coupled, and the fifth transistor M G The gate of the transistor is coupled to the output of the error amplifier EA, meaning that the voltage at the output of the error amplifier EA is used to control the fifth transistor M. G Working, fifth transistor M G The drain is used to output the bias current I that controls the buffer circuit 61. h .

[0082] In this embodiment of the disclosure, regarding the fourth transistor M MIR and the fifth transistor M G The specific type of transistor used is not limited in this disclosure, and can be determined based on actual application scenarios and specific application experience. For example, the fourth transistor M MIR It is a bipolar transistor or a field-effect transistor, the fifth transistor M G This is a bipolar transistor or a field-effect transistor. For example, the fourth transistor M... MIR and the fifth transistor M G All are P-type MOSFETs.

[0083] This embodiment of the disclosure uses a fourth transistor M. MIR and the fifth transistor M G The load current mirroring unit 33 is a load current adaptive circuit used to mirror the load current, so that the voltage regulator circuit can maintain sufficient loop stability under different load current conditions.

[0084] In one embodiment, the current output to each buffer circuit 61 is 1 / N of the bias current.

[0085] In this embodiment of the disclosure, the load current mirrored by the load current mirroring unit 33 is used to control the operation of each buffer circuit 61, thereby enabling the bias current of the buffer circuit 61 to dynamically track the load current, and further enabling the voltage regulator circuit to maintain sufficient loop stability under different load current conditions.

[0086] To better illustrate the voltage regulator circuit of this disclosure, a specific embodiment will be used to describe this disclosure below.

[0087] For example, such as Figure 9 As shown, the value of N is 2. The voltage regulator circuit of this disclosure includes a first control loop and a second control loop; that is, the voltage regulator circuit of this disclosure includes, as shown... Figure 9 The two feedback loops shown are provided, one of which is controlled by the first transistor M. E Error amplifier EA and first current source I h1 The slow loop (first control loop) is composed of the first transistor M; the other feedback loop is composed of the first transistor M. E Second transistor M F Third transistor M P1 Third transistor M P2 Buffer circuit B1, buffer circuit B2, first current source I h1 Second current source I h2 This forms a fast loop (second control loop). The first transistor M... E Second transistor M F Third transistor M P1 and the third transistor M P2 These are all power transistors, unlike typical structures that use a single large-size power transistor (such as power transistor M). P In this embodiment of the disclosure, Figure 1 The power transistor M in the corresponding embodiment P Break it down into, for example Figure 9 The third transistor M shown P1 and the third transistor M P2 The combination, in which the third transistor M P1 and the third transistor M P2 The dimensions are all smaller than those of the power transistor M. P The third transistor M P1 The gate is coupled to the third transistor M after passing through the buffer circuit 61. P2 The gate is used to reduce gate impedance. Meanwhile, the third transistor M... P1 and the third transistor M P2 The drain outputs are connected in parallel to ensure that there is enough current at the output of the voltage regulator circuit.

[0088] The slow-loop voltage regulation principle: The first sub-regulator circuit provides a high loop gain, making the output voltage V... OUT It can be stabilized at the reference voltage V REF Nearby. When the load current changes, it causes the output voltage V to... OUT When the voltage increases, due to the output voltage V OUT Connecting to the inverting input of error amplifier EA will cause the voltage V at the output of error amplifier EA to... EA Decrease. Because the first transistor M E The drain and the first current source I h1 Coupled, the first transistor M E Biased to a constant current, therefore the first transistor M E Gate-source voltage difference V SG_MP1 It remains unchanged, so its source voltage V OUT (output voltage V) OUT Follow voltage V EA Decrease. Similarly, when the load current changes, it causes the output voltage V to decrease. OUT When it decreases, due to the output voltage V OUT Connecting to the inverting input of error amplifier EA will cause the voltage V at the output of error amplifier EA to... EA Increase. Because the first transistor M E The drain and the first current source I h1 Coupled, the first transistor M E Biased to a constant current, therefore the first transistor M E Gate-source voltage difference V SG_MP1 It remains unchanged, so its source voltage V OUT (output voltage V) OUT Follow voltage V EA Increase.

[0089] The fast response principle of a fast loop: Utilizing the low input capacitance and low output impedance of a buffer circuit, the impedance of the internal nodes of the fast loop can be significantly reduced. Furthermore, the originally larger power transistor is replaced by a relatively smaller third transistor M. P1 and the third transistor M P2 The combination of these elements can reduce the parasitic capacitance of the corresponding node. In this way, the frequency of the corresponding pole can be shifted to a higher frequency band, resulting in increased circuit bandwidth and a faster transient response.

[0090] The voltage regulation principle of a fast loop: When load fluctuations cause the output voltage V to fluctuate... OUT When it increases, due to the first current source I h1 With the first transistor M E The drain is coupled, therefore the first transistor M EWith a constant bias current, and considering the channel length modulation effect, the first transistor M... E The drain-source voltage remains constant, so the first transistor M E Drain voltage V F It will increase with the source voltage. The second transistor M F Biased to a constant current (second current source I) h2 The generated constant current), the second transistor M F The gate-source voltage difference remains constant, so the voltage V AB As a result, it increases. Voltage V AB After transmission through the buffer circuit, the third transistor M will be activated. P1 Gate voltage V GP1 and the third transistor M P2 Gate voltage V GP2 The increase in [value] causes the flow through the third transistor M to [become more efficient]. P1 and the third transistor M P2 The current decreases, ultimately causing the output voltage V to decrease. OUT Decrease.

[0091] Similarly, when load fluctuations cause the output voltage V to... OUT When it decreases, due to the first current source I h1 With the first transistor M E The drain is coupled, therefore the first transistor M E With a constant bias current, and considering the channel length modulation effect, the first transistor M... E The drain-source voltage remains constant, so the first transistor M E Drain voltage V F It will decrease with the source voltage. The second transistor M F Biased to a constant current (second current source I) h2 The generated constant current), the second transistor M F The gate-source voltage difference remains constant, so the voltage V AB Consequently, it decreases. Voltage V AB After transmission through the buffer circuit, the third transistor M will be activated. P1 Gate voltage V GP1 and the third transistor M P2 Gate voltage V GP2 The reduction in [something] causes current to flow through the third transistor M. P1 and the third transistor M P2 The increased current eventually leads to an increase in the output voltage V. OUT Increase.

[0092] In another embodiment, such as Figure 10 As shown, to represent the load driven by the voltage regulator circuit, the voltage regulator circuit provided in this disclosure also includes a load capacitor C.L3 and current source I LOAD Load capacitance C L3 One end is connected to the first transistor M E The source is coupled, and the load capacitance C L3 The other end is grounded, current source I LOAD One end is connected to the first transistor M E The source is coupled, and the current source I LOAD The other end is grounded.

[0093] In this embodiment, the voltage regulator circuit consists of a dual-loop system (a fast loop and a slow loop). The high-bandwidth fast loop provides rapid transient response to handle frequent load current switching. The high-gain slow loop provides the output voltage V. OUT With reference voltage V REF The loop between them ensures that the output voltage V OUT It can stably follow the reference voltage V REF Furthermore, the use of frequency shifting units in the fast loop ensures that the poles within the fast loop are generally at higher frequencies, which not only guarantees loop stability but also increases bandwidth, thus accelerating circuit response. It should be noted that multiple frequency shifting units can ensure that the output signal characteristics of the third transistor's drain meet the required impedance and attenuation. The load current mirroring unit in this embodiment can enable the voltage regulator circuit to maintain sufficient loop stability under different load current conditions.

[0094] In other words, the slow loop of this disclosure provides high loop gain to improve the accuracy of the output voltage and enhance regulation and regulation capabilities; the fast loop provides fast transient response without requiring large capacitors. Furthermore, replacing a single large power transistor with a combination of small-sized power transistors avoids the parasitic large capacitance associated with large transistors, further reduces the node impedance of the fast loop, thereby shifting the corresponding poles to higher frequencies, further increasing bandwidth and response speed. Multiple frequency shift units can be cascaded to achieve buffer impedance attenuation.

[0095] Compared to the embodiments disclosed herein... Figure 1 The corresponding voltage regulator circuit does not require additional large off-chip capacitors, which can reduce the difficulty of layout design; the node impedance of the fast loop in the embodiment of this disclosure is compared to Figure 2 The corresponding voltage regulator circuit has a smaller node impedance, thus improving bandwidth and achieving a faster response speed. Furthermore, the voltage regulator circuit disclosed in this embodiment adds a high-loop-gain feedback loop between the output voltage and the reference voltage, enabling the output voltage to better maintain consistency with the reference voltage. The load current mirror unit allows the bias current of the buffer circuit to dynamically track the load current, thereby ensuring sufficient loop stability under different load current conditions.

[0096] Based on the same inventive concept, this disclosure also provides a memory that integrates the voltage regulator circuit described in any of the above claims.

[0097] The memory can be either non-volatile or volatile. Non-volatile memory includes flash memory such as NOR flash and NAND flash, or read-only memory such as PROM (Programmable Read-Only Memory), EAROM (Electrically Alterable Read-Only Memory), EPROM (Erasable Programmable Read-Only Memory), and EEPROM (Electrically Erasable Programmable Read-Only Memory). For example, NOR flash memory can be a type of non-volatile memory based on the CHE (Channel Hot Electron) effect.

[0098] For example, the memory may include a voltage regulator circuit, wherein the output voltage of the memory is adjusted by the voltage regulator circuit. The voltage regulator circuit can be found in the relevant descriptions in the preceding sections of the embodiments of this disclosure, and will not be repeated here.

[0099] In addition, this disclosure also provides an electronic device.

[0100] Figure 11 A schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure is shown. Figure 11 As shown, the electronic device 1100 includes a memory. The memory includes a voltage regulator circuit, which can be found in the relevant descriptions of the embodiments of this disclosure above, and will not be repeated here.

[0101] Among them, the voltage regulator circuit can be a combination of Figures 1-10 The above embodiments illustrate any of the voltage regulator circuits.

[0102] For example, electronic device 1100 may be a terminal device such as a mobile phone or computer, or a network device such as a server, without specific limitation.

[0103] In another exemplary embodiment, the electronic device 1100 may include a voltage regulator circuit that adjusts the output voltage. The voltage regulator circuit is described in detail in the preceding sections of the embodiments of this disclosure and will not be repeated here.

[0104] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. This disclosure is not limited to the specific steps and structures described above and shown in the figures. Those skilled in the art can make various changes, modifications, and additions after understanding the spirit of this disclosure. Furthermore, for the sake of brevity, detailed descriptions of known technologies are omitted here.

[0105] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0106] In addition, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0107] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A voltage regulator circuit, characterized in that, include: The first sub-regulator circuit includes a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal serves as an output node, outputting the output voltage of the regulator circuit. The second terminal is used to input a sampled voltage obtained by acquiring the output voltage. The third terminal is used to input a reference voltage. The fourth terminal is coupled to a first reference potential. The first sub-regulator circuit forms a first control loop by inputting the sampled voltage at the second terminal. The first control loop pulls the output voltage down to the reference voltage in response to the output voltage being greater than the reference voltage, and pulls the output voltage up to the reference voltage in response to the output voltage being less than the reference voltage. The second sub-regulator circuit includes a fifth terminal, a sixth terminal, a seventh terminal, and an eighth terminal. The fifth terminal is coupled to the first sub-regulator circuit. The sixth terminal is used to input the power supply voltage. The seventh terminal is coupled to a second reference potential. The eighth terminal is coupled to the first terminal. The second sub-regulator circuit forms a second control loop through the coupling of the fifth terminal to the first sub-regulator circuit and the coupling of the eighth terminal to the first terminal. The second control loop responds to the output voltage being greater than the reference voltage by pulling the output voltage down to the reference voltage and responds to the output voltage being less than the reference voltage by pulling the output voltage up to the reference voltage.

2. The voltage regulator circuit according to claim 1, characterized in that, The first sub-regulator circuit includes: The first transistor, wherein the source of the first transistor is the first terminal; An error amplifier, wherein the inverting input terminal of the error amplifier is the second terminal, the non-inverting input terminal of the error amplifier is the third terminal, and the output terminal of the error amplifier is coupled to the gate of the first transistor. A first current source, one end of which is connected to the drain of the first transistor, and the other end of which is the fourth terminal.

3. The voltage regulator circuit according to claim 2, characterized in that, The second sub-regulator circuit includes: The second transistor has its drain as the seventh terminal and its gate as the fifth terminal, which is coupled to the drain of the first transistor. The second current source has one end coupled to the source of the second transistor and the other end connected to the sixth terminal. N frequency shift units, each of the N frequency shift units including a first connection terminal, a second connection terminal and a third connection terminal, the first connection terminals of each of the N frequency shift units being coupled together, the first connection terminal being the sixth terminal, the second connection terminals of each of the N frequency shift units being coupled together, the second connection terminal being the eighth terminal, the third connection terminal of the i-th frequency shift unit being coupled to the (i-1)-th frequency shift unit, and the third connection terminal of the 1-th frequency shift unit being coupled to the source of the second transistor, wherein N is an integer greater than or equal to 2, and i is an integer greater than or equal to 2 and less than or equal to N, the N frequency shift units being used to shift the pole frequency from a first frequency band to a second frequency band, the second frequency band being higher than the first frequency band.

4. The voltage regulator circuit according to claim 3, characterized in that, The frequency shifting unit includes: A buffer circuit, wherein the input terminal of the buffer circuit is the third connection terminal; The third transistor has its gate coupled to the output terminal of the buffer circuit, its source terminal is the first connection terminal, and its drain terminal is the second connection terminal. The input terminal of the buffer circuit in the i-th frequency shift unit is coupled to the gate of the third transistor in the (i-1)-th frequency shift unit, and the buffer circuit is used to reduce the gate impedance of the third transistor.

5. The voltage regulator circuit according to claim 4, characterized in that, The sum of the power of the N third transistors in the N frequency shift units is less than or equal to the power threshold.

6. The voltage regulator circuit according to claim 4, characterized in that, The voltage regulator circuit further includes: a load current mirror unit; The load current mirror unit includes: A fourth transistor, the gate of which is coupled to the source of the second transistor, and the source of which is coupled to the sixth terminal. The fifth transistor has its source coupled to the drain of the fourth transistor, its gate coupled to the output of the error amplifier, and its drain used to output a bias current for controlling the buffer circuit.

7. The voltage regulator circuit according to claim 6, characterized in that, The current output to each of the buffer circuits is 1 / N of the bias current.

8. The voltage regulator circuit according to claim 3, characterized in that, The value of N is 2.

9. A memory, characterized in that, The memory integrates a voltage regulator circuit as described in any one of claims 1 to 8.

10. An electronic device, characterized in that, The electronic device includes: the memory as described in claim 9.

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