Bond wire voltage drop compensation circuit, method, and packaged chip

Abstract

This disclosure provides a bond wire voltage drop compensation circuit, method, and packaged chip. The circuit includes a digital current sampling circuit, a digital trimming code module, and an error amplifier. The digital current sampling circuit samples the load current of the LDO circuit to obtain a load current sampling voltage and converts the load current sampling voltage into a digital compensation code. The digital trimming code module generates a bond wire compensation code based on the digital compensation code and bond wire compensation parameters, and determines a target trimming code based on the bond wire compensation code. The error amplifier trims the offset voltage of the error amplifier based on the target trimming code, and generates an error amplification voltage based on the reference voltage and feedback voltage after trimming. This circuit can cancel the bond wire voltage drop to improve the accuracy of the packaged chip's output voltage. It can also compensate for the bond wire voltage drop in the digital domain outside the LDO feedback loop to maintain the loop transfer function unchanged and not affect the loop stability, thus eliminating the need to redesign the loop stability.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more particularly to bonding wire voltage drop compensation circuits, methods, and packaged chips. Background Technology

[0002] In a packaged chip, internal metal pads (PADs) are connected to package pins (PINs) via bonding wires. These bonding wires have a non-negligible parasitic resistance (typically between 20 milliohms and 100 milliohms). For low dropout regulators (LDOs), the feedback sampling point for the output voltage is typically located on the internal PADs. When load current flows through the bonding wires, a voltage drop occurs, causing the output voltage at the PIN to drop as the load current increases.

[0003] In existing technologies, an analog compensation voltage is superimposed at the input of the error amplifier to offset the bond wire voltage drop. However, the analog compensation voltage superimposed at the input of the error amplifier causes the LDO feedback loop gain to change with the load current, resulting in changes in the loop parameters and requiring a redesign of the loop stability. Summary of the Invention

[0004] This disclosure provides a bonding wire voltage drop compensation circuit, method, and packaged chip, which can offset the bonding wire voltage drop to improve the accuracy of the packaged chip's output voltage and maintain the loop transfer function unchanged, thereby avoiding the impact on loop stability and eliminating the need for redesigning the loop stability.

[0005] In a first aspect, this disclosure provides a bonding wire voltage drop compensation circuit for use in a packaged chip. The packaged chip includes a low dropout linear regulator (LDO) circuit and an output voltage on-chip pad, bonding wire, and output voltage package pin connected in sequence to the output terminal of the LDO circuit. The LDO circuit includes an error amplifier and an output power transistor. The control terminal of the output power transistor is connected to the output terminal of the error amplifier, and the output terminal of the output power transistor is connected to the output voltage on-chip pad.

[0006] The bonding wire voltage drop compensation circuit includes a digital current sampling circuit, a digital trimming code module, and the error amplifier. The digital trimming code module is connected between the output terminal of the digital current sampling circuit and the trimming terminal of the error amplifier.

[0007] The digital current sampling circuit is configured to sample the load current of the LDO circuit to obtain a load current sampling voltage, and convert the load current sampling voltage into a digital compensation code.

[0008] The digital correction code module is configured to generate a bond line compensation code based on the digital compensation code and the bond line compensation parameters, and to determine a target correction code based on the bond line compensation code.

[0009] The error amplifier is configured to adjust the offset voltage of the error amplifier based on the target adjustment code to offset the bond line voltage drop, and to generate an error amplification voltage based on the reference voltage and the feedback voltage after adjustment.

[0010] In some embodiments of this disclosure, the digital adjustment code module includes a fusion unit, a first input terminal of which receives the bond line compensation code, a second input terminal of which receives the initial adjustment code, and an output terminal of which is connected to the adjustment terminal of the error amplifier.

[0011] The fusion unit is configured to fuse the bonding wire compensation code and the initial adjustment code to obtain the target adjustment code, wherein the initial adjustment code is used to adjust at least one of process deviation, temperature coefficient and initial offset voltage.

[0012] In some embodiments of this disclosure, the bonding wire compensation parameters are determined based on preset bonding wire length, bonding wire cross-sectional area, and bonding wire resistivity.

[0013] In some embodiments of this disclosure, the bonding wire compensation parameters are determined by the automated test equipment (ATE) based on different load test currents and the output test voltage at the output voltage package pin under each load test current.

[0014] In some embodiments of this disclosure, the fusion unit includes an adder, a first input of which receives the bond line compensation code, a second input of which receives the initial adjustment code, and an output of which is connected to the adjustment terminal of the error amplifier.

[0015] In some embodiments of this disclosure, the bonding wire compensation code is positively correlated with the bonding wire compensation parameter, the feedback voltage divider ratio of the LDO circuit, and the digital compensation code.

[0016] In some embodiments of this disclosure, the error amplifier includes a digital trimming circuit and a differential amplifier circuit. The non-inverting input of the differential amplifier circuit receives the feedback voltage, and the inverting input of the differential amplifier circuit receives the reference voltage. The control terminal of the digital trimming circuit is connected to the output terminal of the digital trimming code module.

[0017] The digital adjustment circuit is configured to adjust one of the reference voltage, the feedback voltage, and the differential amplified voltage between the reference voltage and the feedback voltage based on the target adjustment code to obtain the error amplified voltage.

[0018] In some embodiments of this disclosure, the digital current sampling circuit includes a first analog-to-digital converter, a first sampling transistor, and a first sampling resistor. The second analog-to-digital converter in the packaged chip is multiplexed as the first analog-to-digital converter, the second sampling transistor in the packaged chip is multiplexed as the first sampling transistor, and the second sampling resistor in the packaged chip is multiplexed as the first sampling resistor.

[0019] The control terminal of the first sampling tube is connected to the output terminal of the error amplifier, the output terminal of the first sampling tube is connected to the first terminal of the first sampling resistor and the input terminal of the first analog-to-digital converter, the second terminal of the first sampling resistor is grounded, and the output terminal of the first analog-to-digital converter is connected to the input terminal of the digital trimming code module.

[0020] Secondly, this disclosure provides a bonding wire voltage drop compensation method, applicable to any bonding wire voltage drop compensation circuit provided in the first aspect. The bonding wire voltage drop compensation method includes: The load current of the LDO circuit is sampled to obtain a load current sampling voltage; the load current sampling voltage is converted into a digital compensation code; a bond wire compensation code is generated based on the digital compensation code and bond wire compensation parameters; a target adjustment code is determined based on the bond wire compensation code; the offset voltage of the error amplifier is adjusted based on the target adjustment code to offset the bond wire voltage drop, and an error amplification voltage is generated based on the reference voltage and the feedback voltage after adjustment.

[0021] Thirdly, this disclosure provides a packaged chip including an LDO circuit, an output voltage in-chip pad, a bonding wire, an output voltage package pin, and any of the bonding wire voltage drop compensation circuits provided in the first aspect, wherein the output terminal of the LDO circuit is sequentially connected to the output voltage in-chip pad, the bonding wire, and the output voltage package pin.

[0022] In the technical solution disclosed herein, the bond wire voltage drop compensation circuit includes a digital current sampling circuit, a digital adjustment code module, and an error amplifier. The digital current sampling circuit samples the load current of the LDO circuit to obtain a load current sampling voltage, and converts the load current sampling voltage into a digital compensation code. The digital adjustment code module generates a bond wire compensation code based on the digital compensation code and bond wire compensation parameters, and determines a target adjustment code based on the bond wire compensation code. The error amplifier adjusts the offset voltage of the error amplifier based on the target adjustment code, and generates an error amplification voltage based on the reference voltage and feedback voltage after adjustment. This can offset the bond wire voltage drop, thereby improving the accuracy of the output voltage of the packaged chip.

[0023] In addition, the bond wire voltage drop compensation circuit compensates for the bond wire voltage drop in the digital domain outside the LDO feedback loop, avoiding the introduction of additional nodes or impedances in the LDO feedback loop. Therefore, it does not change the LDO feedback loop parameters, that is, it keeps the loop transfer function unchanged and does not affect the loop stability. Thus, there is no need to redesign the loop stability. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein: Figure 1 This is a schematic diagram of the structure of a packaged chip provided in an embodiment of this disclosure.

[0025] Figure 2 This is a schematic diagram of the bonding wire voltage drop compensation circuit provided in an embodiment of the present disclosure.

[0026] Figure 3 A circuit diagram of another bonding wire voltage drop compensation circuit provided in an embodiment of this disclosure.

[0027] Figure 4 This is a schematic flowchart of a bonding wire voltage drop compensation method provided in an embodiment of this disclosure. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0029] In this disclosure, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of the phrase "embodiment" in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this disclosure can be combined with other embodiments.

[0030] Furthermore, the terms "first," "second," etc., in the specification, claims, or the accompanying drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0031] In the description of this disclosure, unless otherwise stated, "multiple" and "at least two" mean two or more (including two), and similarly, "multiple groups" and "at least two groups" mean two or more (including two groups).

[0032] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0033] In a packaged chip including an LDO circuit, the output feedback sampling point of the LDO circuit is located on the on-chip pad PAD_Vout of the output voltage. When the load current ILOAD flows through the bonding wire, a voltage drop is generated, causing the output voltage Vout_pin at the output voltage package pin PIN_Vout to drop as the load current ILOAD increases. The output voltage Vout_pin can be expressed as: Vout_pin = Vout_pad - ILOAD × Rbond, where Vout_pad is the voltage at the on-chip pad PAD_Vout of the output voltage, and Rbond is the bonding wire impedance.

[0034] For example, when the load current ILOAD is 1A and the bond wire impedance Rbond is 50mΩ, the bond wire voltage drop can reach 50mV. If the rated output voltage of the LDO circuit is 1.8V and the accuracy requirement is ±1%, the output voltage Vout_pin of the packaged chip will far exceed the accuracy range, and the load regulation will deteriorate significantly.

[0035] To address the aforementioned problems, existing technologies mainly employ the following two types of solutions: One approach is Kelvin remote sampling: an additional bonding wire is added as a remote sampling line, extending the output feedback sampling point to the output voltage package pin PIN_Vout. However, this solution requires adding a dedicated PAD on the chip and an extra wire in the package, significantly increasing the package chip area and cost, which is particularly disadvantageous for automotive-grade high-reliability applications.

[0036] Second, simulated feedforward compensation: By sampling the load current, a simulated compensation voltage is superimposed on the feedback path / input terminal of the error amplifier to offset the bond wire voltage drop. However, this scheme has the following drawbacks: 1. Change the loop parameters: The analog compensation voltage is superimposed on the input of the error amplifier, which effectively changes the feedback voltage division ratio or input impedance of the feedback network, so that the gain of the LDO feedback loop changes with the load current ILOAD.

[0037] 2. Stability redesign: Since the loop transfer function of the LDO feedback loop is changed, the loop stability must be redesigned and the phase margin and gain margin must be verified across the entire load range, which significantly increases the design complexity.

[0038] 3. Additional analog overhead: Additional operational amplifier units or digital-to-analog converters and other analog circuits are required, increasing chip area and cost, and adding noise sources.

[0039] 4. Limited compensation accuracy: The analog compensation coefficient is determined by the on-chip resistor ratio or preset circuit parameters, which cannot accurately adapt to the differences in impedance of different chips and different batches of bonding wires.

[0040] In view of this, this disclosure provides a bonding wire voltage drop compensation circuit, including a digital current sampling circuit, a digital trimming code module, and an error amplifier. The digital current sampling circuit samples the load current of the LDO circuit to obtain a load current sampling voltage, and converts the load current sampling voltage into a digital compensation code. The digital trimming code module generates a bonding wire compensation code based on the digital compensation code and bonding wire compensation parameters, and determines a target trimming code based on the bonding wire compensation code. The error amplifier trims the offset voltage of the error amplifier based on the target trimming code, and generates an error amplification voltage based on the reference voltage and feedback voltage after trimming. This can offset the bonding wire voltage drop, thereby improving the accuracy of the output voltage of the packaged chip.

[0041] In addition, the bond wire voltage drop compensation circuit compensates for the bond wire voltage drop in the digital domain outside the LDO feedback loop, avoiding the introduction of additional nodes or impedances in the LDO feedback loop. Therefore, it does not change the LDO feedback loop parameters, that is, it keeps the loop transfer function unchanged and does not affect the loop stability. Thus, there is no need to redesign the loop stability.

[0042] The technical solutions provided in this disclosure are described in detail below with reference to several specific embodiments.

[0043] Figure 1 This is a schematic diagram of the structure of a packaged chip provided in an embodiment of the present disclosure, such as... Figure 1As shown, the packaged chip includes an LDO circuit, an output voltage on-chip pad PAD_Vout, bonding wires, an output voltage package pin PIN_Vout, and a bonding wire voltage drop compensation circuit 100. The output terminal of the LDO circuit is connected in sequence to the output voltage on-chip pad PAD_Vout, the bonding wires, and the output voltage package pin PIN_Vout.

[0044] The LDO circuit includes an error amplifier EA and an output power transistor M_Power. The non-inverting input of the error amplifier EA receives the feedback voltage Vfb0, and the inverting input of the error amplifier EA receives the reference voltage Vref0. The output of the error amplifier EA is connected to the control terminal of the output power transistor M_Power, and the output of the output power transistor M_Power is connected to the on-chip pad PAD_Vout for the output voltage.

[0045] For example, such as Figure 1 As shown, the output power transistor M_Power is a P-type metal-oxide-semiconductor field-effect transistor (PMOS). The gate of the output power transistor M_Power is connected to the output terminal of the error amplifier EA, the source of the output power transistor M_Power is connected to the input voltage Vin, and the drain of the output power transistor M_Power is connected to the on-chip pad PAD_Vout of the output voltage.

[0046] The LDO circuit also includes a feedback resistor network connected between the output voltage pad PAD_Vout and ground. The common terminal of the feedback network is connected to the non-inverting input of the error amplifier EA to provide the feedback voltage Vfb0. For example, as Figure 1 As shown, the feedback resistor network includes a first feedback resistor Rf1 and a second feedback resistor Rf2. The first feedback resistor Rf1 and the second feedback resistor Rf2 are connected in series between the output voltage chip pad PAD_Vout and ground. The connection point of the first feedback resistor Rf1 and the second feedback resistor Rf2 is connected to the non-inverting input terminal of the error amplifier EA.

[0047] Figure 2 This is a schematic diagram of a bonding wire voltage drop compensation circuit provided in an embodiment of the present disclosure, as shown below. Figure 2 As shown, the bonding wire voltage drop compensation circuit 100 includes a digital current sampling circuit 110, a digital trimming code module 120, and an error amplifier EA. The digital trimming code module 120 is connected between the output terminal of the digital current sampling circuit 110 and the trimming terminal of the error amplifier EA.

[0048] The digital current sampling circuit 110 is configured to sample the load current ILOAD of the LDO circuit to obtain the load current sampling voltage Vsense, and convert the load current sampling voltage Vsense into a digital compensation code D_ILOAD.

[0049] The digital trimming code module 120 is configured to generate a bond line compensation code D_bond based on the digital compensation code D_ILOAD and the bond line compensation parameters, and to determine the target trimming code D_Trim based on the bond line compensation code D_bond.

[0050] Error amplifier EA is configured to adjust the offset voltage offset of error amplifier EA based on the target trimming code D_Trim to offset the bond line voltage drop, and generate error amplification voltage Vea based on the reference voltage Vref0 and the feedback voltage Vfb0 after trimming.

[0051] For example, Figure 3 This is a schematic diagram of another bonding wire voltage drop compensation circuit provided in an embodiment of this disclosure, as shown below. Figure 3 As shown, the digital current sampling circuit 110 includes a first analog-to-digital converter (ADC), a first sampling transistor M_Sense, and a first sampling resistor Rsense. The second ADC in the packaged chip is multiplexed as the first ADC, the second sampling transistor in the packaged chip is multiplexed as the first sampling transistor M_Sense, and the second sampling resistor in the packaged chip is multiplexed as the first sampling resistor Rsense. In other words, the first sampling transistor M_Sense, the first sampling resistor Rsense, and the first ADC are already present in the packaged chip.

[0052] The control terminal of the first sampling transistor M_Sense is connected to the output terminal of the error amplifier EA. The output terminal of the first sampling transistor M_Sense is connected to the first terminal of the first sampling resistor Rsense and the input terminal of the first analog-to-digital converter ADC. The second terminal of the first sampling resistor Rsense is grounded. The output terminal of the first analog-to-digital converter ADC is connected to the input terminal of the digital trimming code module 120.

[0053] In this circuit, the first sampling transistor M_Sense and the output power transistor M_Power form a mirror circuit. For example, combining... Figure 1 and Figure 3 As shown, the output power transistor M_Power and the first sampling transistor M_Sense are PMOS transistors. The source of the output power transistor M_Power and the source of the first sampling transistor M_Sense are connected to the input voltage Vin. The gate of the output power transistor M_Power and the gate of the first sampling transistor M_Sense are connected to the output terminal of the error amplifier EA. That is, the output power transistor M_Power and the first sampling transistor M_Sense are common source and common gate transistors.

[0054] The aspect ratio of the first sampling transistor M_Sense to the output power transistor M_Power is 1:N, where N is an integer greater than 1. Therefore, the drain current of the first sampling transistor M_Sense (load current sampling current ILOAD_sense) = the drain current of the output power transistor M_Power (load current ILOAD) / N. Consequently, the load current sampling voltage Vsense = ILOAD_sense × R_sen = ILOAD × R_sen / N, where R_sen is the resistance value of the first sampling resistor Rsense.

[0055] The first analog-to-digital converter (ADC) quantizes the load current sampling voltage Vsense to obtain the digital compensation code D_ILOAD.

[0056] In this way, by reusing the existing sampling tube, sampling resistor and analog-to-digital converter in the packaged chip to form a digital current sampling circuit 110, no additional analog devices are required, which can reduce the area and cost of the packaged chip.

[0057] See also Figure 3 The digital trimming code module 120 includes a compensation code generation unit 121 and a fusion unit 122. The first input terminal of the compensation code generation unit 121 is connected to the output terminal of the digital current sampling circuit 110 to receive the digital compensation code D_ILOAD. The second input terminal of the compensation code generation unit 121 receives the bonding wire compensation parameters. The first input terminal of the fusion unit 122 is connected to the output terminal of the compensation code generation unit 121 to receive the bonding wire compensation code D_bond. The second input terminal of the fusion unit 122 receives the initial trimming code D_Trim0. The output terminal of the fusion unit 122 is connected to the trimming terminal of the error amplifier EA.

[0058] For example, if the bond wire compensation parameter is the bond wire impedance Rbond, then the bond wire compensation parameter Rbond is determined based on the preset bond wire length, bond wire cross-sectional area, and bond wire resistivity.

[0059] Due to process variations during chip packaging, the bond wire compensation parameter Rbond will differ between different chips within the same batch. After chip packaging, the bond wire length and cross-sectional diameter / radius can be measured. Based on the measured cross-sectional diameter / radius, the bond wire cross-sectional area can be calculated, and the bond wire cross-sectional area, length, and resistivity are preset within the packaged chip. Therefore, the preset bond wire length, cross-sectional area, and resistivity can accurately reflect the bond wire compensation parameter Rbond between different chips within the same batch.

[0060] Furthermore, different batches of chips may have different bond wire lengths, different bond wire cross-sectional diameters / radiuses, or different bond wire materials during the packaging process. Therefore, the preset bond wire length, bond wire cross-sectional area, and bond wire resistivity can accurately reflect the bond wire compensation parameter Rbond of different batches of chips.

[0061] Thus, by using the preset bonding wire cross-sectional area, bonding wire length, and bonding wire resistivity, the bonding wire compensation parameter Rbond can be calculated, which can reduce the bonding wire impedance error of the chip, improve the compensation accuracy of the bonding wire voltage drop, and thus improve the accuracy of the packaged chip output voltage Vout_pin.

[0062] In other embodiments, the bond wire compensation parameter is the equivalent total voltage drop factor Rbond_eff, which is determined by the Automatic Test Equipment (ATE) based on different load test currents ILOAD_test and the output test voltage Vout_pin_test at the output voltage package pin PIN_Vout under each load test current ILOAD_test. The bond wire compensation parameter Rbond_eff comprehensively reflects the bond wire impedance Rbond and the overall gain characteristics of the digital current sampling circuit 110.

[0063] During the testing phase of the packaged chip, the ATE first provides a first load test current ILOAD_test1 to the LDO circuit, for example, ILOAD_test1 = 10mA, and measures the first output test voltage Vout_pin_test1 at the output voltage package pin PIN_Vout. Then, it provides a second load test current ILOAD_test2 to the LDO circuit, for example, ILOAD_test2 = 500mA, and measures the second output test voltage Vout_pin_test2 at the output voltage package pin PIN_Vout.

[0064] Subsequently, the voltage difference ΔV between the first output test voltage Vout_pin_test1 and the second output test voltage Vout_pin_test2 is determined, i.e., ΔV = |Vout_pin_test1 - Vout_pin_test2|. The current difference ΔI between the first load test current ILOAD_test1 and the second load test current ILOAD_test2 is also determined, i.e., ΔI = |ILOAD_test1 - ILOAD_test2|.

[0065] Finally, under the ideal load regulation of the LDO circuit, the ratio of voltage difference ΔV to current difference ΔI is determined as the bond wire compensation parameter Rbond_eff, i.e., Rbond_eff=ΔV / ΔI=|Vout_pin_test1-Vout_pin_test2| / |ILOAD_test1-ILOAD_test2|.

[0066] Thus, by determining the bonding wire compensation parameter Rbond_eff based on different load test currents ILOAD_test and the output test voltage Vout_pin_test at the package pin PIN_Vout under each load test current ILOAD_test, the bonding wire impedance error and current sampling gain error of the chip can be reduced, thereby improving the accuracy of the package chip's output voltage Vout_pin.

[0067] For example, the bond wire compensation code D_bond is positively correlated with the bond wire compensation parameter Rbond, the feedback voltage divider ratio A of the LDO circuit, and the digital compensation code D_ILOAD, i.e., D_bond ∝ ILOAD × Rbond × A = N × D_ILOAD × Rbond × A / R_sen. Where A = R2 / (R1 + R2), R1 is the resistance value of the first feedback resistor Rf1, and R2 is the resistance value of the second feedback resistor Rf2.

[0068] Therefore, the compensation code generation unit 121 can generate the bond wire compensation code D_bond based on the digital compensation code D_ILOAD, the width-to-length ratio N, the resistance value R_sen of the first sampling resistor Rsense, the bond wire compensation parameter Rbond, and the feedback voltage division ratio A.

[0069] The fusion unit 122 can fuse the bond wire compensation code D_bond and the initial trimming code D_Trim0 to obtain the target trimming code D_Trim. The target trimming code D_Trim is used to trim at least one of process deviation, temperature coefficient, and initial offset voltage. For example, the fusion unit 122 includes an adder. The first input of the adder is connected to the output of the compensation code generation unit 121 to receive the bond wire compensation code D_bond. The second input of the adder receives the initial trimming code D_Trim0. The output of the adder is connected to the trimming terminal of the error amplifier EA. Then, D_Trim = D_bond + D_Trim0.

[0070] See also Figure 3The error amplifier EA includes a digital trimming circuit 131 and a differential amplifier circuit 132. The non-inverting input of the differential amplifier circuit 132 receives the feedback voltage Vfb0, and the inverting input of the differential amplifier circuit 132 receives the reference voltage Vref0. The control terminal of the digital trimming circuit 131 is connected to the output terminal of the digital trimming code module 120.

[0071] For example, if the output of the digital trimming circuit 131 is connected to the inverting input of the differential amplifier circuit 132, then the digital trimming circuit 131 will trim the reference voltage Vref0 based on the target trimming code D_Trim to compensate for the offset voltage offset.

[0072] The adjusted reference voltage is denoted as the equivalent reference voltage Vref, then Vref = Vref0 + ΔVref, where ΔVref is the reference voltage adjustment amount, and ΔVref ∝ ILOAD × Rbond × A. The differential amplifier circuit 132 amplifies the differential voltage between the equivalent reference voltage Vref and the feedback voltage Vfb0 to obtain the error amplification voltage Vea.

[0073] When the differential amplifier circuit 132 is in steady state, the differential amplifier circuit 132 forces Vref=Vfb0, then Vout_pad=Vref / A=Vref0 / A+ILOAD×Rbond, Vout_pin= Vout_pad-ILOAD×Rbond =Vref0 / A.

[0074] Therefore, the output voltage Vout_pin of the packaged chip is independent of the load current ILOAD, thus offsetting the bond line voltage drop and improving the accuracy of the packaged chip's output voltage Vout_pin. Furthermore, the aforementioned bond line voltage drop compensation circuit 100 does not introduce any additional nodes or impedances into the LDO feedback loop. Therefore, it does not change parameters such as the LDO feedback loop's gain, pole distribution, phase margin, and gain margin. Consequently, the loop transfer function remains unchanged, and loop stability is not affected, eliminating the need for redesigning the loop stability.

[0075] In some other implementations, the output of the digital trimming circuit 131 is connected to the non-inverting input of the differential amplifier circuit 132. The digital trimming circuit 131 then trims the feedback voltage Vfb0 based on the target trimming code D_Trim to compensate for the offset voltage.

[0076] The adjusted feedback voltage is denoted as the equivalent feedback voltage Vfb, then Vfb = Vfb0 + ΔVfb, where ΔVfb is the feedback voltage adjustment amount, and ΔVfb ∝ ILOAD × Rbond × A. The differential amplifier circuit 132 amplifies the difference between the reference voltage Vref0 and the equivalent feedback voltage Vfb to obtain the error amplification voltage Vea, Vout_pad = Vfb / A = Vfb0 / A + ILOAD × Rbond, Vout_pin = Vout_pad - ILOAD × Rbond = Vfb0 / A.

[0077] The output voltage Vout_pin of the packaged chip is also independent of the load current ILOAD, and has the same beneficial effect as the above embodiments, which will not be repeated here.

[0078] In some other embodiments, the output of the digital trimming circuit 131 is connected to the output of the differential amplifier circuit 132. The differential amplifier circuit 132 determines and outputs the differential amplified voltage Vea0 of the feedback voltage Vfb0 and the reference voltage Vref0. Then, the digital trimming circuit 131 trims the differential amplified voltage Vea0 based on the target trimming code D_Trim to compensate for the offset voltage.

[0079] The adjusted differential amplification voltage is denoted as the error amplification voltage Vea, then Vea = Vea0 + ΔVea, where ΔVea is the differential amplification voltage adjustment amount, and ΔVea ∝ ILOAD × Rbond × A. The packaged chip output voltage Vout_pin is also independent of the load current ILOAD, and has the same beneficial effects as in the above embodiment, which will not be elaborated further here.

[0080] Thus, the digital trimming circuit 131 can trim the reference voltage Vref0 / feedback voltage Vfb0, or the differential amplified voltage Vea0 of the reference voltage Vref0 and the feedback voltage Vfb0, based on the target trimming code D_Trim, to obtain the error amplified voltage Vea.

[0081] In this embodiment, the bond wire voltage drop compensation circuit includes a digital current sampling circuit, a digital adjustment code module, and an error amplifier. The digital current sampling circuit samples the load current of the LDO circuit to obtain a load current sampling voltage, and converts the load current sampling voltage into a digital compensation code. The digital adjustment code module generates a bond wire compensation code based on the digital compensation code and bond wire compensation parameters, and determines a target adjustment code based on the bond wire compensation code. The error amplifier adjusts the offset voltage of the error amplifier based on the target adjustment code, and generates an error amplification voltage based on the reference voltage and feedback voltage after adjustment. This can offset the bond wire voltage drop and improve the accuracy of the packaged chip's output voltage.

[0082] In addition, the bond wire voltage drop compensation circuit 100 compensates for the bond wire voltage drop in the digital domain outside the LDO feedback loop, avoiding the introduction of additional nodes or impedances in the LDO feedback loop. Therefore, it does not change the LDO feedback loop parameters, that is, it keeps the loop transfer function unchanged and does not affect the loop stability. Thus, there is no need to redesign the loop stability.

[0083] This disclosure also provides a bonding wire voltage drop compensation method, which is applied to the bonding wire voltage drop compensation circuit 100 provided in any of the above embodiments.

[0084] Figure 4 This is a flowchart illustrating a bonding wire voltage drop compensation method provided in an embodiment of this disclosure, as shown below. Figure 4 As shown, the specific steps of the bond wire voltage drop compensation method include: S101 samples the load current of the LDO circuit to obtain the load current sampling voltage.

[0085] S102 converts the load current sampling voltage into a digital compensation code.

[0086] S103, Generates bond line compensation code based on digital compensation code and bond line compensation parameters.

[0087] S104, determine the target tuning code based on the bond line compensation code.

[0088] S105 adjusts the offset voltage of the error amplifier based on the target adjustment code to compensate for the bond line voltage drop, and generates the error amplification voltage based on the reference voltage and the feedback voltage after adjustment.

[0089] In this embodiment, the load current of the LDO circuit is sampled to obtain a load current sampling voltage, which is then converted into a digital compensation code. A bond wire compensation code is generated based on the digital compensation code and bond wire compensation parameters. A target adjustment code is determined based on the bond wire compensation code, and the offset voltage of the error amplifier is adjusted based on the target adjustment code. After adjustment, an error amplification voltage is generated based on the reference voltage and the feedback voltage, which can offset the bond wire voltage drop and improve the accuracy of the packaged chip's output voltage. Furthermore, the bond wire voltage drop can be compensated in the digital domain outside the LDO feedback loop, avoiding the introduction of additional nodes or impedances in the LDO feedback loop. Therefore, the LDO feedback loop parameters are not changed, i.e., the loop transfer function remains unchanged, and the loop stability is not affected, thus eliminating the need for redesigning the loop stability.

[0090] In some embodiments, a specific description of a possible implementation of S104 is as follows: The target adjustment code is obtained by fusing the bond wire compensation code and the initial adjustment code, wherein the initial adjustment code is used to adjust at least one of process deviation, temperature coefficient, and initial offset voltage. For example, the target adjustment code is the sum of the bond wire compensation code and the initial adjustment code.

[0091] In some embodiments, the bonding wire compensation parameters are determined based on preset bonding wire length, bonding wire cross-sectional area, and bonding wire resistivity.

[0092] In some embodiments, the bonding wire compensation parameters are determined by the ATE based on different load test currents and the output test voltage at the output voltage package pin under each load test current.

[0093] In some embodiments, the bond wire compensation code is positively correlated with the bond wire compensation parameters, the feedback voltage divider ratio of the LDO circuit, and the digital compensation code.

[0094] In some embodiments, a specific description of a possible implementation of S105 is as follows: The reference voltage is adjusted based on the target adjustment code to obtain the error amplification voltage.

[0095] In some embodiments, another possible implementation of S105 is described as follows: Based on the target adjustment code, the feedback voltage is adjusted to obtain the error amplification voltage.

[0096] In some embodiments, a specific description of another possible implementation of S105 is as follows: Based on the target adjustment code, the differential amplified voltage between the reference voltage and the feedback voltage is adjusted to obtain the error amplified voltage.

[0097] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” are to be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” should be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, the “example” is merely exemplary and illustrative, and should not be considered exclusive or extensive.

[0098] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A bonding wire voltage drop compensation circuit, characterized in that, The chip is used in a packaged chip, which includes a low dropout linear regulator (LDO) circuit and an output voltage on-chip pad, a bonding wire, and an output voltage package pin connected in sequence to the output terminal of the LDO circuit. The LDO circuit includes an error amplifier and an output power transistor. The control terminal of the output power transistor is connected to the output terminal of the error amplifier, and the output terminal of the output power transistor is connected to the output voltage on-chip pad. The bonding wire voltage drop compensation circuit includes a digital current sampling circuit, a digital trimming code module, and the error amplifier. The digital trimming code module is connected between the output terminal of the digital current sampling circuit and the trimming terminal of the error amplifier. The digital current sampling circuit is configured to sample the load current of the LDO circuit, obtain a load current sampling voltage, and convert the load current sampling voltage into a digital compensation code. The digital correction code module is configured to generate a bond line compensation code based on the digital compensation code and the bond line compensation parameters, and to determine a target correction code based on the bond line compensation code. The error amplifier is configured to adjust the offset voltage of the error amplifier based on the target adjustment code to offset the bond line voltage drop, and to generate an error amplification voltage based on the reference voltage and the feedback voltage after adjustment.

2. The bonding wire voltage drop compensation circuit according to claim 1, characterized in that, The digital modification code module includes a fusion unit; The first input terminal of the fusion unit receives the bonding wire compensation code, the second input terminal of the fusion unit receives the initial adjustment code, and the output terminal of the fusion unit is connected to the adjustment terminal of the error amplifier. The fusion unit is configured to fuse the bonding wire compensation code and the initial adjustment code to obtain the target adjustment code, wherein the initial adjustment code is used to adjust at least one of process deviation, temperature coefficient and initial offset voltage.

3. The bonding wire voltage drop compensation circuit according to claim 1, characterized in that, The bonding wire compensation parameters are determined based on preset bonding wire length, bonding wire cross-sectional area, and bonding wire resistivity.

4. The bonding wire voltage drop compensation circuit according to claim 1, characterized in that, The bonding wire compensation parameters are determined by the automated test equipment (ATE) based on different load test currents and the output test voltage at the output voltage package pin under each load test current.

5. The bonding wire voltage drop compensation circuit according to claim 2, characterized in that, The fusion unit includes an adder; The first input terminal of the adder receives the bond line compensation code, the second input terminal of the adder receives the initial adjustment code, and the output terminal of the adder is connected to the adjustment terminal of the error amplifier.

6. The bonding wire voltage drop compensation circuit according to claim 1, characterized in that, The bonding wire compensation code is positively correlated with the bonding wire compensation parameters, the feedback voltage division ratio of the LDO circuit, and the digital compensation code.

7. The bonding wire voltage drop compensation circuit according to claim 1, characterized in that, The error amplifier includes a digital trimming circuit and a differential amplifier circuit; The non-inverting input terminal of the differential amplifier circuit receives the feedback voltage, the inverting input terminal of the differential amplifier circuit receives the reference voltage, and the control terminal of the digital trimming circuit is connected to the output terminal of the digital trimming code module. The digital adjustment circuit is configured to adjust one of the reference voltage, the feedback voltage, and the differential amplified voltage between the reference voltage and the feedback voltage based on the target adjustment code to obtain the error amplified voltage.

8. The bonding wire voltage drop compensation circuit according to any one of claims 1-7, characterized in that, The digital current sampling circuit includes a first analog-to-digital converter, a first sampling transistor, and a first sampling resistor. The second analog-to-digital converter in the packaged chip is multiplexed as the first analog-to-digital converter, the second sampling transistor in the packaged chip is multiplexed as the first sampling transistor, and the second sampling resistor in the packaged chip is multiplexed as the first sampling resistor. The control terminal of the first sampling tube is connected to the output terminal of the error amplifier, the output terminal of the first sampling tube is connected to the first terminal of the first sampling resistor and the input terminal of the first analog-to-digital converter, the second terminal of the first sampling resistor is grounded, and the output terminal of the first analog-to-digital converter is connected to the input terminal of the digital trimming code module.

9. A method for compensating for bond wire voltage drop, characterized in that, Applied to the bonding wire voltage drop compensation circuit according to any one of claims 1-8, the method includes: The load current of the LDO circuit is sampled to obtain the load current sampling voltage; Convert the load current sampling voltage into a digital compensation code; Based on the digital compensation code and the bond line compensation parameters, a bond line compensation code is generated. The target adjustment code is determined based on the bond line compensation code; Based on the target tuning code, the offset voltage of the error amplifier is tuned to compensate for the bond line voltage drop, and an error amplification voltage is generated based on the reference voltage and the feedback voltage after tuning.

10. A packaged chip, characterized in that, The device includes an LDO circuit, an output voltage on-chip pad, a bonding wire, an output voltage package pin, and a bonding wire voltage drop compensation circuit as described in any one of claims 1-8, wherein the output terminal of the LDO circuit is sequentially connected to the output voltage on-chip pad, the bonding wire, and the output voltage package pin.

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