Semiconductor structure and method of manufacturing the same, memory system

Abstract

The present disclosure provides a semiconductor structure, a manufacturing method thereof and a memory system, the semiconductor structure comprising: a stack structure comprising gate structures and first dielectric layers alternately and stacked; a channel structure penetrating through the stack structure along a first direction; the channel structure comprising a channel layer, a tunneling layer, a storage layer, a functional layer and a barrier layer arranged in sequence along a second direction; wherein the second direction intersects the first direction.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor structure and its manufacturing method, and a memory system. Background Technology

[0002] In recent years, the semiconductor integrated circuit industry has experienced rapid development. The feature size of semiconductor devices has continued to shrink, and the integration density of memory has become increasingly higher, resulting in more and more powerful performance. Currently, memory manufacturing technology has gradually transitioned from simple planar structures to more complex three-dimensional structures. The number of stacked layers in memory structures is increasing, and the manufacturing process is becoming more and more complex. Therefore, how to balance the size and performance of memory has become an urgent problem to be solved in the industry. Summary of the Invention

[0003] This disclosure provides semiconductor structures and their manufacturing methods, as well as memory systems.

[0004] In a first aspect, embodiments of this disclosure provide a semiconductor structure, including:

[0005] A stacked structure, comprising alternating stacked gate structures and a first dielectric layer;

[0006] A trench structure extends through the stacked structure along a first direction; the trench structure includes a trench layer, a tunneling layer, a storage layer, a functional layer, and a barrier layer arranged sequentially along a second direction; wherein the second direction intersects with the first direction.

[0007] In some embodiments, the polarization direction of the material in the functional layer is not perpendicular to the second direction.

[0008] In some embodiments, the material of the functional layer includes a dipole material.

[0009] In some embodiments, the material of the functional layer includes ferroelectric materials and / or antiferroelectric materials.

[0010] In some embodiments, the material of the functional layer includes at least one of hafnium oxide, zirconium oxide, and aluminum oxide.

[0011] In some embodiments, the thickness of the functional layer is less than the thickness of the storage layer.

[0012] In some embodiments, the thickness of the functional layer is less than the thickness of the barrier layer.

[0013] In some embodiments, the gate structure includes:

[0014] A first conductive layer extends along the second direction;

[0015] The second conductive layer is located between the first conductive layer and the first dielectric layer, and between the first conductive layer and the barrier layer.

[0016] The second dielectric layer is located between the second conductive layer and the first dielectric layer, and between the second conductive layer and the barrier layer.

[0017] In some embodiments, the semiconductor structure further includes:

[0018] A contact structure that connects the channel structure in the first direction;

[0019] An isolation structure extends through the stacked structure along the first direction.

[0020] In a second aspect, embodiments of this disclosure provide a method for manufacturing a semiconductor structure, the method comprising:

[0021] A stacked structure is formed; the stacked structure includes alternately stacked gate structures and a first dielectric layer;

[0022] A channel structure is formed that runs through the stacked structure along a first direction; the channel structure includes a channel layer, a tunneling layer, a storage layer, a functional layer and a barrier layer stacked sequentially along a second direction; wherein the second direction intersects with the first direction.

[0023] In some embodiments, the polarization direction of the material in the functional layer is not perpendicular to the second direction.

[0024] In some embodiments, the material of the functional layer includes a dipole material.

[0025] In some embodiments, the material of the functional layer includes ferroelectric materials and / or antiferroelectric materials.

[0026] In some embodiments, the material of the functional layer includes at least one of hafnium oxide, zirconium oxide, and aluminum oxide.

[0027] In some embodiments, the thickness of the functional layer is less than the thickness of the storage layer.

[0028] In some embodiments, the thickness of the functional layer is less than the thickness of the barrier layer.

[0029] In some embodiments, forming the stacked structure includes:

[0030] An alternately stacked sacrificial layer and the first dielectric layer are formed;

[0031] Remove the sacrificial layer to create voids;

[0032] The gate structure is formed in the gap;

[0033] The process of forming the gate structure in the gap includes:

[0034] A second dielectric layer is formed covering the inner wall of the void;

[0035] A second conductive layer is formed covering the second dielectric layer;

[0036] A first conductive layer is formed covering the second conductive layer.

[0037] In some embodiments, the manufacturing method further includes:

[0038] A contact structure is formed connecting the channel structure in the first direction;

[0039] An isolation structure is formed that extends through the stacked structure along the first direction.

[0040] Thirdly, embodiments of this disclosure provide a memory system, including: a memory device comprising the semiconductor structure described in any of the above embodiments; and a memory controller coupled to the memory device and configured to control the memory device.

[0041] In this embodiment of the disclosure, the semiconductor structure includes a stacked structure and a channel structure that penetrates the stacked structure. The channel structure includes a functional layer located between a storage layer and a barrier layer. The functional layer can attract the charge trapped in the storage layer to improve the problem of charge leakage in the storage layer, thereby improving the data retention capability of the memory. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure. Figure 1 .

[0043] Figure 2 This is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure.

[0044] Figure 3 This is a schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of the present disclosure.

[0045] Figure 4 This is a schematic diagram of an exemplary memory device including peripheral circuitry according to an embodiment of the present disclosure.

[0046] Figure 5 This is a cross-sectional schematic diagram of a storage array including a string of storage cells, provided for an embodiment of the present disclosure.

[0047] Figure 6 This is a schematic diagram of an exemplary memory device including a memory array and peripheral circuitry according to an embodiment of the present disclosure.

[0048] Figure 7a and Figure 7b This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure.

[0049] Figure 8a and Figure 8b This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure.

[0050] Figure 9 This is a schematic diagram of a functional layer in another semiconductor structure provided in an embodiment of the present disclosure.

[0051] Figure 10 This is a schematic diagram of yet another semiconductor structure provided in an embodiment of the present disclosure.

[0052] Figure 11 This is a flowchart illustrating the steps of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure.

[0053] Figures 12a to 12h This is a schematic diagram of the manufacturing process of a semiconductor structure according to an embodiment of the present disclosure.

[0054] Figure 13 This is a schematic diagram of the structure of a memory device provided in an embodiment of the present disclosure. Detailed Implementation

[0055] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0056] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0057] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0058] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0059] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0060] Figure 1 This is a schematic diagram of an exemplary system with a memory system provided for embodiments of this disclosure. In embodiments of this disclosure, system 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein. Figure 1 As shown, system 100 may include a host system 101 and a memory system 102. The memory system 102 may include one or more memory devices 103 and a memory controller 104. The host system 101 may include a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). The host system 101 may be configured to send data to or receive data from the memory system 102.

[0061] In some embodiments, memory controller 104 is coupled to memory device 103 and host 101 and is configured to control memory device 103. Memory controller 104 can manage data stored in memory device 103 and communicate with host 101. In some embodiments, memory controller 104 is designed to operate in low duty cycle environments, such as in secure digital cards, compact flash cards (CFC), universal serial bus (USB) flash drives, or in other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. In other embodiments, memory controller 104 is designed to operate in high duty cycle environments, such as in solid-state drives or embedded multi-media cards (eMMC).

[0062] In some embodiments, the memory controller 104 and one or more memory devices 103 can be integrated into various types of storage devices, that is, the memory system 102 can be implemented and packaged into different types of terminal electronic products.

[0063] In such Figure 2 In one example shown, the memory controller 104 and a single memory device 103 can be integrated into the memory card 201. The memory card 201 can be a compact flash memory card, a smart media card (SMC), a memory stick (MS), a multi-media card (MMC) such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card such as a Mini SD card, Micro SD card, SDHC card, etc., or a general-purpose flash memory card. The memory card 201 may also include a connection between the memory card 201 and a host device (e.g., Figure 1 The memory card connector 202 is coupled to the host 101. Figure 3 In another example shown, the memory controller 104 and multiple memory devices 103 may be integrated into the SSD 203. The SSD 203 may also include components for connecting the SSD 203 to host devices (e.g., Figure 1 The SSD connector 204 is coupled to the host 101. In some embodiments, the storage capacity and / or operating speed of the SSD 203 is greater than the storage capacity and / or operating speed of the memory card 201.

[0064] Figure 4A circuit diagram of an exemplary memory device 300 including peripheral circuitry, provided for embodiments of this disclosure. The memory device 300 may be... Figure 1 An example of memory device 103 is provided. Memory device 300 may include memory array 301 and peripheral circuitry 302 coupled to memory array 301. Taking memory array 301 as an example of a three-dimensional NAND type memory array, where memory cells 305 are NAND memory cells, provided in the form of an array of memory cell strings 304, each memory cell string 304 extending vertically above a substrate (not shown). In some embodiments, each memory cell string 304 includes a plurality of memory cells 305 coupled in series and stacked vertically. Each memory cell 305 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of memory cell 305. Each memory cell 305 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0065] In some implementations, each memory cell 305 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 305 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, such as a multi-level cell (MLC) storing two bits per cell, a triple-level cell (TLC) storing three bits per cell, or a quad-level cell (QLC) storing four bits per cell.

[0066] like Figure 4As shown, each memory cell string 304 may include a bottom select transistor (BST) 307 at its source end and a top select transistor (TST) 306 at its drain end. The bottom select transistor 307 and the top select transistor 306 may be configured to activate the selected memory cell string 304 during read and program operations. In some embodiments, the sources of memory cell strings 304 within the same memory block 303 may be coupled via a common source line (CSL) 310. In other words, all memory cell strings 304 within the same memory block 303 share a common source (ACS). According to some embodiments, the top select transistor 306 of each memory cell string 304 is coupled to a corresponding bit line (BL) 311, from which data can be read or written via an output bus (not shown). In some implementations, each memory cell string 304 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the top select transistor 306) or a deselect voltage (e.g., 0V) to the top select gate (TSG) of the corresponding top select transistor 306 via one or more top select lines (TSL) 308 and / or by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the bottom select transistor 307) or a deselect voltage (e.g., 0V) to the bottom select gate (BSG) of the corresponding bottom select transistor 307 via one or more bottom select lines (BSL) 309.

[0067] like Figure 4 As shown, the memory cell string 304 can be organized into multiple memory blocks 303, each of which may have a common source line 310. In some embodiments, each memory block 303 is the basic data unit for an erase operation, i.e., all memory cells 305 on the same memory block 303 are erased simultaneously. To erase memory cells 305 in a selected memory block, an erase voltage bias can be used to couple the common source line 310 to the selected memory block and the unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 305 of adjacent memory cell strings 304 can be coupled via word lines 312, which select which row of memory cells 305 is affected by a read or program operation.

[0068] In some embodiments, peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry for applying voltage and / or current signals to each target memory cell 305 via bit line 311, word line 312, common-source line 310, bottom select line 309, and top select line 308, and for sensing voltage and / or current signals from each target memory cell 305 to operate the memory array 301. Peripheral circuitry 302 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MODS) technology.

[0069] Figure 5 A schematic cross-sectional view of an exemplary memory array including a string of memory cells 304, according to some aspects of this disclosure, is shown. Figure 5 As shown, the stacked structure 320 includes a plurality of gate layers 321 and a plurality of insulating layers 322 alternately stacked in sequence, and a string of memory cells 304 perpendicularly penetrating the gate layers 321 and the insulating layers 322. The gate layers 321 and the insulating layers 322 can be stacked alternately, and two adjacent gate layers 321 are separated by an insulating layer 322. The number of memory cells included in the memory array is mainly related to the number of pairs of gate layers 321 and insulating layers 322 in the stacked structure 320.

[0070] The constituent materials of the gate layer 321 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 321 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 321 includes a doped polysilicon layer. Each gate layer 321 may include a control gate surrounding a memory cell. The gate layer 321 at the top of the stack 320 may extend laterally as a top select line, the gate layer 321 at the bottom of the stack 320 may extend laterally as a bottom select line, and the gate layer 321 extending laterally between the top select line and the bottom select line may serve as a word line layer.

[0071] In some embodiments, the stacked structure 320 may be disposed on the semiconductor layer 330. The semiconductor layer 330 may include silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. In other embodiments, the semiconductor device may not include the semiconductor layer.

[0072] In some embodiments, the memory cell string 304 includes a channel structure extending vertically through the stacked structure 320. In some embodiments, the channel structure includes channel vias filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0073] Figure 6 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 401, a column decoder / bit line driver 402, a row decoder / word line driver 403, a voltage generator 404, control logic 405, a register set 406, a flash memory interface 407, and a data bus 408. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 6 Additional peripheral circuitry not shown.

[0074] Page buffer / sensor amplifier 401 can be configured to read data from and program (write) data to memory array 301 according to control signals from control logic 405. In one example, page buffer / sensor amplifier 401 can store a page of programming data (write data) to be programmed into memory array 301. In another example, page buffer / sensor amplifier 401 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, page buffer / sensor amplifier 401 can also sense a low-power signal from the bit line representing the data bits stored in the memory cell and amplify a small voltage swing to a recognizable logic level during a read operation. Column decoder / bit line driver 402 can be configured to be controlled by control logic 405 and select one or more memory cell strings by applying a bit line voltage generated from voltage generator 404.

[0075] The row decoder / word line driver 403 can be configured to be controlled by control logic 405 and to select / deselect memory blocks of memory array 301 and select / deselect word lines of memory blocks. The row decoder / word line driver 403 can also be configured to drive word lines using word line voltages generated from voltage generator 404. In some embodiments, the row decoder / word line driver 403 can also select / deselect and drive bottom select lines and top select lines. As described in detail below, the row decoder / word line driver 403 is configured to perform programming operations on memory cells coupled to one or more selected word lines. The voltage generator 404 can be configured to be controlled by control logic 405 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 301.

[0076] Control logic 405 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register set 406 can be coupled to control logic 405 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Flash interface 407 can be coupled to control logic 405 and acts as a control buffer to buffer control commands received from host devices (not shown) and relay them to control logic 405, as well as to buffer status information received from control logic 405 and relay it to the memory controller. Flash interface 407 can also be coupled to column decoder / bitline driver 402 via data bus 408 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 301.

[0077] In some embodiments, such as Figure 7a and Figure 7b As shown, the semiconductor structure 500 can be located in the memory array of a Charge Trap Flash (CTF) NAND memory. The semiconductor structure 500 includes a stacked structure 510 and a channel structure 520 penetrating the stacked structure 510; the stacked structure 510 includes alternately stacked gate structures 511 and a first dielectric layer 512; the channel structure 520 can be columnar, and a filling layer 526, a channel layer 521, a tunneling layer 522, a storage layer 523, and a barrier layer 524 are sequentially arranged radially from the center of the column towards its outer surface. Because the thermal excitation of charge carriers trapped in the storage layer 523 and the direct tunneling through the tunneling layer 522 both cause charge loss in the memory cells, the CTF NAND memory suffers from poor data retention performance.

[0078] To clearly describe this disclosure, the first direction is the Z direction in the accompanying drawings, and the second direction is the X direction in the accompanying drawings, as an example. The first direction and the second direction can be perpendicular to each other, or the first direction and the second direction can have an angle greater than 0 degrees and less than 180 degrees. However, it should be noted that the description of directions in the following embodiments is only for illustrating this disclosure and is not intended to limit the scope of this disclosure.

[0079] like Figure 8a and Figure 8b As shown, this embodiment of the present disclosure provides a semiconductor structure 600, including: a stacked structure 610, including a gate structure 611 and a first dielectric layer 612 alternately stacked; a channel structure 620 penetrating the stacked structure 610 along a first direction; the channel structure 620 includes a channel layer 621, a tunneling layer 622, a storage layer 623, a functional layer 625 and a barrier layer 624 sequentially disposed along a second direction; wherein the second direction intersects the first direction.

[0080] In this embodiment of the disclosure, the semiconductor structure 600 may be located in the memory array of a CTF NAND memory. The semiconductor structure 600 includes a stacked structure 610 and a channel structure 620 extending through the stacked structure 610. The stacked structure 610 includes gate structures 611 and a first dielectric layer 612 alternately stacked along the Z-direction, with adjacent gate structures 611 separated by the first dielectric layer 612. The gate structure 611 may include one or more conductive layers, and one or more gate dielectric layers covering the conductive layers. Specifically, the conductive layer can be a metallic or alloy material, such as a material containing metals like tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can also be a metal oxide, metal nitride, metal silicide, or metal carbide, such as tin-doped indium oxide (ITO), indium-doped zinc oxide (IZO), indium oxide (InO), aluminum-doped zinc oxide (Al-doped ZnO, AZO), iridium oxide (IrOx), and ruthenium oxide (RuOx); or metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN); or it can be a doped silicon, polycrystalline silicon, or silicide. The constituent materials of the gate dielectric layer include, but are not limited to, silicon oxide (such as silicon dioxide), silicon nitride (such as silicon oxynitride), nitride (such as silicon nitride), high-K dielectric materials (dielectric constant greater than 3.9), low-K dielectric materials (dielectric constant greater than or equal to 2.5 and less than 3.9), and ultra-low-K dielectric materials (dielectric constant less than 2.5).

[0081] The channel structure 620 can be columnar, and from the center of the column towards its outer surface, a filling layer 626, a channel layer 621, a tunneling layer 622, a storage layer 623, a functional layer 625, and a barrier layer 624 are sequentially arranged radially. The filling layer 626 comprises a dielectric material, such as an oxide material; the channel layer 621 comprises a semiconductor material, such as polysilicon. The tunneling layer 622 may comprise silicon oxide, silicon oxynitride, or any combination thereof; the storage layer 623 may comprise silicon nitride, silicon oxynitride, or any combination thereof; and the barrier layer 624 may comprise silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. During programming, a programming voltage is applied to the gate structure 611. Charge from the channel layer 621 passes through the tunneling layer 622 and is trapped in the storage layer 623, which increases the threshold voltage of the storage cell, thereby causing the storage cell to transition from a non-programmed state to a programmed state. The functional layer 625 can attract the trapped charge in the storage layer 623 to improve the charge leakage problem of the storage layer 623, thereby improving the data retention capability of the memory. Exemplarily, the tunneling layer 622, the storage layer 623 and the barrier layer 624 can be a silicon oxide layer, a silicon nitride layer and a silicon oxide layer, respectively, i.e., an ONO (Oxide-Nitride-Oxide) stacked structure.

[0082] In some embodiments, the polarization direction of the material in the functional layer 625 is not perpendicular to the second direction.

[0083] like Figure 9 As shown, the polarization direction of the material in the functional layer 625, disposed between the storage layer 623 and the barrier layer 624, is not perpendicular to the X-direction. That is, the polarization direction of the material in the functional layer 625 is parallel to the X-direction, or the polarization direction of the material in the functional layer 625 forms an angle with the X-direction other than 90 degrees. Thus, the polarization effect of the functional layer 625 can attract the charge stored in the storage layer 623, thereby reducing charge leakage in the storage layer 623 and improving the data retention capability of the memory. Exemplarily, the functional layer 625 may include a material with spontaneous polarization characteristics, or a material with polarization characteristics due to external factors (such as electric fields, stress, etc.).

[0084] In some embodiments, the material of the functional layer 625 includes a dipole material.

[0085] like Figure 9As shown, the functional layer 625 disposed between the storage layer 623 and the barrier layer 624 may include a dipole material, that is, there are electric dipoles in the functional layer 625. The polarization characteristics of these dipoles can attract the charge stored in the storage layer 623, thereby reducing charge leakage in the storage layer 623 and improving the data retention capability of the memory. Exemplarily, the material of the functional layer 625 includes, but is not limited to, ferroelectric materials, antiferroelectric materials, fluorinated polymers, carbonyl polymers, and perovskite materials.

[0086] In some embodiments, the above-described functional layer can also be applied to 2D NAND memory. It is understood that 2D NAND memory refers to NAND memory that does not contain the above-described stacked structure, and whose channel structure extends in the horizontal direction.

[0087] In some embodiments, the material of the functional layer 625 includes ferroelectric materials and / or antiferroelectric materials.

[0088] In this embodiment of the disclosure, the functional layer 625 may include ferroelectric materials and / or antiferroelectric materials. Ferroelectric materials and antiferroelectric materials have good polarization characteristics and are compatible with various semiconductor manufacturing processes.

[0089] In some embodiments, the material of the functional layer 625 includes transition metal oxides such as hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), titanium oxide (TiO2), niobium oxide (Nb2O5), tantalum oxide (Ta2O5), tungsten oxide (WO3), molybdenum oxide (Mo3), vanadium oxide (V2O3), lanthanum oxide (La2O3), and / or any combination thereof. Furthermore, ferroelectric materials can be doped. For example, the functional layer 625 can be HfO2 doped with silicon (Si), yttrium (Y), gadolinium (Gd), lanthanum (La), zirconium (Zr), or aluminum (Al), or any combination thereof.

[0090] In some embodiments, the thickness of the functional layer 625 is less than the thickness of the storage layer 623; and / or, the thickness of the functional layer 625 is less than the thickness of the barrier layer 624.

[0091] In this embodiment of the disclosure, the thickness of the functional layer 625 may be less than the thickness of the storage layer 623 and / or the barrier layer 624. Thus, a thinner functional layer 625 is beneficial to reducing the volume of the semiconductor structure 600, thereby improving the integration density of the semiconductor structure 600.

[0092] In some embodiments, such as Figure 8a and Figure 8bAs shown, the gate structure 611 includes: a first conductive layer 613 extending along the second direction; a second conductive layer 614 located between the first conductive layer 613 and the first dielectric layer 612 and between the first conductive layer 613 and the barrier layer 624; and a second dielectric layer 615 located between the second conductive layer 614 and the first dielectric layer 612 and between the second conductive layer 614 and the barrier layer 624.

[0093] In this embodiment, the gate structure 611 includes a first conductive layer 613, a second conductive layer 614, and a second dielectric layer 615. Exemplarily, the second conductive layer 614 may cover the first conductive layer 613, and the second dielectric layer 615 may cover the second conductive layer 614. The first conductive layer 613 extends along the X-direction, and its material includes, but is not limited to, conductive metals such as tungsten, cobalt, copper, aluminum, titanium, tantalum, or nickel. The second conductive layer 614 is made of, but is not limited to, conductive materials such as titanium, titanium nitride, tantalum, and tantalum nitride, and can serve as an adhesion layer. The second dielectric layer 615 is made of, but is not limited to, a high dielectric constant dielectric material.

[0094] In some embodiments, such as Figure 10 As shown, the semiconductor structure 600 further includes: a contact structure 630 connecting the channel structure 620 in the first direction; and an isolation structure 640 penetrating the stacked structure 610 along the first direction.

[0095] In this embodiment, the semiconductor structure 600 includes a contact structure 630 and an isolation structure 640. In the Z direction, the contact structure 630 may be located on top of the channel structure 620, serving as a channel plug for the channel structure 620. The material of the contact structure 630 includes, but is not limited to, semiconductor materials, such as polysilicon. In some embodiments, the contact structure 630 may also serve as the drain of a NAND flash memory cell string.

[0096] The isolation structure 640 can be a gate line slot filled with dielectric material, which is used to form the gate structure 611. Exemplarily, during the formation of the stacked structure 610, multiple sacrificial layers and multiple first dielectric layers 612 can be formed alternately; then, a gate line slot is formed penetrating the multiple sacrificial layers and multiple first dielectric layers 612 along the Z direction; next, the sacrificial layer can be removed through the gate line slot to form a void; then, conductive material is filled into the void to form the gate structure 611; after forming the gate structure 611, dielectric material can be filled into the gate line slot to finally form the isolation structure 640. In some embodiments, the isolation structure 640 can have an air gap.

[0097] Based on the above-described semiconductor structure, embodiments of this disclosure provide a method for manufacturing a semiconductor structure, such as... Figure 11 As shown, the manufacturing method includes the following steps:

[0098] Step S10: Form a stacked structure; the stacked structure includes alternating stacked gate structures and a first dielectric layer;

[0099] Step S20: Form a channel structure that runs through the stacked structure along a first direction; the channel structure includes a channel layer, a tunneling layer, a storage layer, a functional layer and a barrier layer stacked sequentially along a second direction; wherein the second direction intersects with the first direction.

[0100] It should be understood that Figure 11 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 11 The steps shown can be adjusted in order according to actual needs. See below for reference. Figures 12a to 12h The manufacturing process of the semiconductor structure shown in the figure is described in detail.

[0101] In some embodiments, forming the stacked structure includes: forming a sacrificial layer and a first dielectric layer that are alternately stacked; removing the sacrificial layer to form a gap; forming the gate structure in the gap; the forming of the gate structure in the gap includes: forming a second dielectric layer covering the inner wall of the gap; forming a second conductive layer covering the second dielectric layer; and forming a first conductive layer covering the second conductive layer.

[0102] like Figure 12aAs shown, multiple sacrificial layers 601 and multiple first dielectric layers 612 alternately stacked in the Z direction can be formed using processes such as deposition and epitaxial growth. Exemplarily, the materials of the sacrificial layers 601 include, but are not limited to, polycrystalline silicon and silicon nitride. The deposition processes in this disclosure include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), and combinations thereof. The epitaxial growth processes in this disclosure include, but are not limited to, vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MBE), ion beam epitaxy, solid phase epitaxy, and combinations thereof.

[0103] like Figure 12b As shown, channel holes 602 penetrating multiple sacrificial layers 601 and multiple first dielectric layers 612 along the Z direction can be formed using photolithography, etching, and other processes. The channel holes 602 are used to form a channel structure. The etching processes in this disclosure can be divided into dry etching and wet etching. Dry etching can include ion milling etching, plasma etching, reactive ion etching, or laser ablation; wet etching uses solvents or solutions, such as acid or alkaline solutions, for etching.

[0104] like Figure 12c As shown, a barrier layer 624, a functional layer 625, a storage layer 623, a tunneling layer 622, a channel layer 621, and a filling layer 626 can be sequentially formed in the channel hole 602 using processes such as deposition and epitaxial growth, thereby forming a channel structure 620.

[0105] In some embodiments, the polarization direction of the material in the functional layer 625 is not perpendicular to the second direction.

[0106] In some embodiments, the material of the functional layer 625 includes a dipole material.

[0107] In some embodiments, the material of the functional layer 625 includes ferroelectric materials and / or antiferroelectric materials.

[0108] In some embodiments, the material of the functional layer 625 includes transition metal oxides such as hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), titanium oxide (TiO2), niobium oxide (Nb2O5), tantalum oxide (Ta2O5), tungsten oxide (WO3), molybdenum oxide (Mo3), vanadium oxide (V2O3), lanthanum oxide (La2O3), and / or any combination thereof. Furthermore, ferroelectric materials can be doped. For example, the functional layer 625 can be HfO2 doped with silicon (Si), yttrium (Y), gadolinium (Gd), lanthanum (La), zirconium (Zr), or aluminum (Al), or any combination thereof.

[0109] In some embodiments, the thickness of the functional layer 625 is less than the thickness of the storage layer 623; and / or, the thickness of the functional layer 625 is less than the thickness of the barrier layer 624.

[0110] In some embodiments, the manufacturing method further includes: forming a contact structure that connects the channel structure in the first direction; and forming an isolation structure that extends through the stacked structure along the first direction.

[0111] like Figure 12d As shown, a third dielectric layer 616 can be formed above multiple stacked sacrificial layers 601, multiple first dielectric layers 612, and the channel structure 620 using processes such as deposition and epitaxial growth; then, contact holes exposing the top of the channel structure 620 can be formed in the third dielectric layer 616 using processes such as photolithography and etching; then, conductive material can be filled into the contact holes using processes such as deposition to form a contact structure 630 connecting the channel structure 620 above the channel structure 620.

[0112] like Figure 12e As shown, photolithography, etching and other processes can be used to form gate line gaps 603 that extend along the Z direction and expose each sacrificial layer 601, and the sacrificial layer can be removed through the gate line gaps 603 to form gaps 604.

[0113] like Figure 12f As shown, a second dielectric layer 615, a second conductive layer 614, and a first conductive layer 613 can be sequentially formed in the void 604 using processes such as deposition and epitaxial growth, thereby completing the replacement of the sacrificial layer by the gate structure 611.

[0114] like Figure 12g As shown, dielectric material can be filled into the gaps in the gate lines using processes such as deposition and epitaxial growth to form an isolation structure 640.

[0115] like Figure 12h As shown, the original substrate located below the stacked structure 610 can be removed first by etching, chemical mechanical polishing and other processes; then the barrier layer 624, functional layer 625, storage layer 623 and tunneling layer 622 located below the stacked structure 610 can be removed to expose the channel layer 621 located below the stacked structure 610; finally, a semiconductor layer 617 covering the channel layer 621 can be formed under the stacked structure 610 by deposition, epitaxial growth and other processes. Here, the semiconductor layer 617 can serve as a common source layer.

[0116] It should be noted that, Figures 12a to 12h The present invention provides only an exemplary process for manufacturing a semiconductor structure 600, wherein the order of the steps may be adjusted as needed, and other steps may be performed before, after, or between any step. This disclosure does not impose any limitations.

[0117] like Figure 13 The diagram shows a schematic representation of a memory device 103 including a memory array 301 and peripheral circuitry 302, provided in an embodiment of this disclosure. The memory array 301 and peripheral circuitry 302 can be formed on different substrates and connected vertically via bonding technology, thereby saving area and improving integration density. It should be noted that the memory array 301 may include the semiconductor structure 600 in any of the above embodiments, the specific structure of which has been described in detail above and will not be repeated here. The peripheral circuitry 302 can be referred to... Figure 6 To understand.

[0118] Based on the above-described semiconductor structure, this disclosure provides a memory system, including: a memory device comprising the semiconductor structure described in any one of the above embodiments; and a memory controller coupled to the memory device and configured to control the memory device.

[0119] The structure and composition of the memory system here can be referenced from the... Figure 1 For the sake of brevity, a detailed description of the memory system 102 will not be repeated.

[0120] In the semiconductor structure and manufacturing method thereof and memory system provided in this disclosure, on the one hand, the dipole material of the functional layer can attract the charge trapped in the storage layer to improve the problem of charge leakage in the storage layer, thereby improving the data retention capability of the memory; on the other hand, the thickness of the functional layer is relatively thin, which makes it easier to meet the requirements of 3D gate stacking technology for size miniaturization; and on the other hand, the process of forming the functional layer is relatively simple, which is conducive to saving costs.

[0121] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0122] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0123] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure includes: A stacked structure, comprising alternating stacked gate structures and a first dielectric layer; A trench structure extends through the stacked structure along a first direction; the trench structure includes a trench layer, a tunneling layer, a storage layer, a functional layer, and a barrier layer arranged sequentially along a second direction; wherein the second direction intersects with the first direction.

2. The semiconductor structure according to claim 1, characterized in that, The polarization direction of the material in the functional layer is not perpendicular to the second direction.

3. The semiconductor structure according to claim 2, characterized in that, The material of the functional layer includes dipole materials.

4. The semiconductor structure according to claim 3, characterized in that, The materials of the functional layer include ferroelectric materials and / or antiferroelectric materials.

5. The semiconductor structure according to claim 4, characterized in that, The material of the functional layer includes at least one of hafnium oxide, zirconium oxide, and aluminum oxide.

6. The semiconductor structure according to claim 1, characterized in that, The thickness of the functional layer is less than the thickness of the storage layer.

7. The semiconductor structure according to claim 1, characterized in that, The thickness of the functional layer is less than the thickness of the barrier layer.

8. The semiconductor structure according to claim 1, characterized in that, The gate structure includes: A first conductive layer extends along the second direction; The second conductive layer is located between the first conductive layer and the first dielectric layer, and between the first conductive layer and the barrier layer. The second dielectric layer is located between the second conductive layer and the first dielectric layer, and between the second conductive layer and the barrier layer.

9. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: A contact structure that connects the channel structure in the first direction; An isolation structure extends through the stacked structure along the first direction.

10. A method for manufacturing a semiconductor structure, characterized in that, The manufacturing method includes: A stacked structure is formed; the stacked structure includes alternately stacked gate structures and a first dielectric layer; A channel structure is formed that runs through the stacked structure along a first direction; the channel structure includes a channel layer, a tunneling layer, a storage layer, a functional layer and a barrier layer stacked sequentially along a second direction; wherein the second direction intersects with the first direction.

11. The manufacturing method according to claim 10, characterized in that, The polarization direction of the material in the functional layer is not perpendicular to the second direction.

12. The manufacturing method according to claim 11, characterized in that, The material of the functional layer includes dipole materials.

13. The manufacturing method according to claim 12, characterized in that, Its features are, The materials of the functional layer include ferroelectric materials and / or antiferroelectric materials.

14. The manufacturing method according to claim 13, characterized in that, The material of the functional layer includes at least one of hafnium oxide, zirconium oxide, and aluminum oxide.

15. The manufacturing method according to claim 10, characterized in that, The thickness of the functional layer is less than the thickness of the storage layer.

16. The manufacturing method according to claim 10, characterized in that, The thickness of the functional layer is less than the thickness of the barrier layer.

17. The manufacturing method according to claim 10, characterized in that, The formation of the stacked structure includes: An alternately stacked sacrificial layer and the first dielectric layer are formed; Remove the sacrificial layer to create voids; The gate structure is formed in the gap; The process of forming the gate structure in the gap includes: A second dielectric layer is formed covering the inner wall of the void; A second conductive layer is formed covering the second dielectric layer; A first conductive layer is formed covering the second conductive layer.

18. The manufacturing method according to claim 10, characterized in that, The manufacturing method further includes: A contact structure is formed connecting the channel structure in the first direction; An isolation structure is formed that extends through the stacked structure along the first direction.

19. A memory system, characterized in that, include: A memory device comprising the semiconductor structure as described in any one of claims 1 to 9; A memory controller is coupled to the memory device and configured to control the memory device.

Images