Multi-channel semiconductor refrigeration plate control method and temperature regulation system

Abstract

The application discloses a kind of multi-path semiconductor refrigeration piece control method and temperature regulating system, applied to semiconductor temperature control technical field, to solve the problem of existing in prior art that multiple semiconductor refrigeration pieces are simultaneously turned on, leading to the instantaneous peak power of power supply is too high.Specifically: obtain the opening time length and current opening sequence of each semiconductor refrigeration piece in current scheduling period;According to each opening time length, determine the current control mode;Current control mode includes single-path opening mode and multi-path overlapping mode;Based on current control mode and current opening sequence, the opening time length of each semiconductor refrigeration piece in current scheduling period is time-sequenced distribution, to obtain the driving time sequence of each semiconductor refrigeration piece and drive each semiconductor refrigeration piece to work;By corresponding time-sequenced distribution to the opening time length of each semiconductor refrigeration piece, reduce the current superposition degree of power supply bus, reduce the instantaneous peak power that power supply bears.

Description

Technical Field

[0001] This application relates to the field of semiconductor temperature control technology, and in particular to a multi-channel semiconductor cooling chip control method and temperature regulation system. Background Technology

[0002] A thermoelectric cooler is a thermoelectric device based on the Peltier effect. It can achieve cooling or heating by changing the direction of the driving current and is widely used in multi-temperature control scenarios such as laser temperature control, medical equipment, and precision instruments.

[0003] Currently, multiple thermoelectric coolers are typically used to independently regulate the temperature of multiple target areas. Each thermoelectric cooler is driven by a corresponding drive circuit, and all drive circuits are powered by a unified power supply via a bus. The drive current of each thermoelectric cooler when it is turned on is taken from the power supply bus. The drive of each thermoelectric cooler is independent, and each circuit is controlled independently by its corresponding temperature control loop according to its own temperature requirements. When multiple thermoelectric coolers are running simultaneously, they commonly turn on and off at the same time. During certain periods of the switching cycle, multiple drive currents flow through the power supply bus simultaneously. The bus currents are superimposed during this period, and the instantaneous current of the bus is the sum of the drive currents of all the simultaneously conducting circuits. This significantly increases the instantaneous peak power load on the power supply, increasing its peak power burden. Furthermore, this current superposition occurs repeatedly in each switching cycle, subjecting the power supply to periodic peak current surges over a long period, accelerating the aging of the power supply and shortening its lifespan.

[0004] Therefore, existing technologies suffer from the problem of excessively high instantaneous peak power of the power supply due to the simultaneous conduction of multiple semiconductor cooling chips. Summary of the Invention

[0005] This application provides a multi-channel thermoelectric cooler control method and temperature regulation system to solve the problem of excessively high instantaneous peak power of the power supply caused by the simultaneous conduction of multiple thermoelectric coolers in the prior art.

[0006] The technical solutions provided in this application are as follows: On one hand, embodiments of this application provide a method for controlling a multi-channel semiconductor cooling chip, including: Obtain the activation duration and current activation order of each semiconductor cooling chip within the current scheduling cycle; The current control mode is determined based on the activation duration of each semiconductor cooling chip within the current scheduling cycle; the current control mode includes single-channel activation mode and multi-channel overlapping mode. Based on the current control mode and the current activation sequence, the activation duration of each thermoelectric cooler is allocated in the current scheduling cycle to obtain the driving timing of each thermoelectric cooler. Drive each thermoelectric cooler to work according to its driving timing sequence.

[0007] Optionally, the current control mode is determined based on the on-time duration of each thermoelectric cooler during the current scheduling cycle, including: When the total on-time of each semiconductor cooling chip in the current scheduling cycle is not greater than the current scheduling cycle, the current control mode is determined to be the single-channel on-time mode. When the total on-time of all semiconductor cooling chips in the current scheduling cycle is greater than the current scheduling cycle, the current control mode is determined to be multi-channel overlapping mode.

[0008] Optionally, when the current control mode is single-channel activation mode, based on the current control mode and current activation sequence, the activation duration of each thermoelectric cooler in the current scheduling cycle is allocated to obtain the drive timing of each thermoelectric cooler, including: According to the current activation order, the activation durations of each semiconductor cooling chip are arranged sequentially from beginning to end within the current scheduling cycle to obtain the first arrangement result; Based on the activation duration of each thermoelectric cooler in the current scheduling cycle and the first arrangement result, the driving timing of each thermoelectric cooler is determined.

[0009] Optionally, when the current control mode is multi-channel overlapping mode, based on the current control mode and the current activation sequence, the activation duration of each thermoelectric cooler in the current scheduling cycle is allocated to obtain the drive timing of each thermoelectric cooler, including: According to the current activation order, the activation duration of each semiconductor cooling chip is arranged sequentially along the time axis, and the second arrangement result is obtained. Map the second permutation result to the current scheduling period to obtain the third permutation result; Based on the turn-on duration of each thermoelectric cooler in the current scheduling cycle and the third arrangement result, the driving timing of each thermoelectric cooler is determined.

[0010] Optionally, the second permutation result is mapped to the current scheduling period to obtain the third permutation result, including: The second arrangement result is divided into units based on the current scheduling cycle. The segments obtained from the division are then overlapped and arranged within the current scheduling cycle to obtain the third arrangement result.

[0011] Optionally, obtain the activation duration of each semiconductor cooling chip within the current scheduling cycle, including: Obtain the target temperature, current temperature, and current scheduling cycle of each semiconductor cooling chip; Based on the target temperature and current temperature of each thermoelectric cooler, determine the target duty cycle of each thermoelectric cooler; Based on the target duty cycle and the current scheduling cycle, determine the activation duration of the corresponding circuit's thermoelectric cooler within the current scheduling cycle.

[0012] Optionally, retrieve the current activation order, including: Obtain the setting position and priority setting value of each semiconductor cooling chip; The adjustment priority of each thermoelectric cooler is determined based on its setting position and priority setting value. The current activation sequence of each semiconductor cooling chip is determined according to the order of adjustment priority from high to low.

[0013] Optionally, the multi-channel thermoelectric cooler control method also includes: During the current scheduling cycle, when the turn-on duration of at least one thermoelectric cooler changes, the current turn-on order is updated so that the thermoelectric cooler whose turn-on duration has changed is placed before the thermoelectric coolers whose turn-on duration has not changed.

[0014] On the other hand, embodiments of this application provide a temperature regulation system, including: a controller, multiple semiconductor coolers, and multiple drive circuits; the semiconductor coolers and drive circuits are correspondingly arranged. The control terminal of each drive circuit is connected to the controller, the input terminal of each drive circuit is connected to the power supply via the power supply bus, and the output terminal of each drive circuit is connected to the corresponding thermoelectric cooler; the thermoelectric cooler is located in the corresponding target area. The controller is used to execute the above-mentioned multi-channel thermoelectric cooler control method and output corresponding control signals to each drive circuit. The driving circuit is used to drive the corresponding semiconductor cooler to work according to the control signal; Semiconductor coolers are used to regulate the temperature of a target area under the drive of a driving circuit.

[0015] Optionally, the driving circuit includes: a first switching transistor, a second switching transistor, a third switching transistor, and a fourth switching transistor; The first terminal of the first switch is connected to the high-potential terminal of the power supply bus, the second terminal of the first switch is connected to the first terminal of the second switch, and the second terminal of the second switch is connected to the low-potential terminal of the power supply bus; the control terminals of the first and second switches are respectively connected to the corresponding output terminals of the controller. The first terminal of the third switch is connected to the high-potential terminal of the power supply bus, the second terminal of the third switch is connected to the first terminal of the fourth switch, and the second terminal of the fourth switch is connected to the low-potential terminal of the power supply bus; the control terminals of the third and fourth switches are respectively connected to the corresponding output terminals of the controller. The second terminals of the first and third switching transistors are connected to the corresponding thermoelectric coolers.

[0016] The beneficial effects of the embodiments of this application are as follows: This application determines the current control mode based on the turn-on duration of each thermoelectric cooler, and allocates the turn-on duration of each circuit according to the current control mode and the current turn-on sequence. This ensures that the turn-on periods of each circuit are uniformly included in the controlled arrangement within the current scheduling cycle. In single-circuit turn-on mode, the superposition of bus currents can be avoided after the turn-on periods of each circuit are allocated according to the time sequence. In multi-circuit overlapping mode, the overlap of the turn-on periods of each circuit is uniformly determined by the time sequence allocation, rather than random superposition under independent control of each circuit, thus reducing the degree of superposition of bus currents. Therefore, without changing the turn-on duration of each circuit or affecting the temperature control effect, by allocating the turn-on duration of each thermoelectric cooler according to the time sequence corresponding to the current control mode within the current scheduling cycle, the degree of current superposition of the power supply bus is reduced, the instantaneous peak power borne by the power supply is reduced, the peak load of the power supply is alleviated, and the service life of the power supply is extended.

[0017] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a schematic flowchart illustrating the multi-channel semiconductor cooling chip control method in the embodiments of this application; Figure 2 This is a schematic diagram illustrating the specific process of determining the driving timing in the single-path activation mode in the embodiments of this application; Figure 3 This is a schematic diagram of the single-channel activation mode driving timing in the embodiments of this application; Figure 4 This is a schematic diagram illustrating the specific process of determining the driving timing under multi-path overlap mode in the embodiments of this application; Figure 5This is a schematic diagram of the driving timing in the multi-path overlapping mode in the embodiments of this application; Figure 6 This is a schematic diagram illustrating the specific process of obtaining the activation duration of each semiconductor cooling chip in the current scheduling cycle in the embodiments of this application; Figure 7 This is a schematic diagram illustrating the specific process of obtaining the current activation order in this application embodiment; Figure 8 This is a schematic diagram of the first system framework of the temperature control system in the embodiments of this application; Figure 9 This is a schematic diagram of the circuit structure of the drive circuit in the temperature regulation system of this application embodiment. Detailed Implementation

[0019] To make the objectives, technical solutions, and beneficial effects of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] This application provides a method for controlling a multi-channel semiconductor cooling chip, see below. Figure 1 As shown, the general flow of the multi-channel semiconductor cooling chip control method provided in this application embodiment is as follows: Step 101: Obtain the activation duration and current activation order of each semiconductor cooling chip in the current scheduling cycle.

[0021] In practical applications, the current scheduling cycle is the time base for unified timing scheduling of each semiconductor cooling chip. Each chip shares a scheduling cycle, and its actual value corresponds to the switching cycle of the drive signal.

[0022] The activation duration refers to the absolute length of time that a thermoelectric cooler needs to remain in the conductive state within a complete current scheduling cycle. The activation duration is determined by the temperature control requirements of that circuit; the higher the temperature requirement, the longer the activation duration. When demand is met, the activation duration equals a complete scheduling cycle. The current activation sequence defines the logical order in which each thermoelectric cooler is arranged on the timeline. It can be dynamically generated based on physical channel numbers, preset priorities, or real-time operating conditions. The initial value of the current activation sequence can be determined according to the channel numbers of each circuit and dynamically updated during operation. The controller can trigger this acquisition operation at the beginning or end of each current scheduling cycle to ensure the real-time nature of control commands.

[0023] Step 102: Determine the current control mode based on the activation duration of each semiconductor cooling chip in the current scheduling cycle; wherein, the current control mode includes single-channel activation mode and multi-channel overlapping mode.

[0024] In practical applications, the current control mode is not a fixed configuration parameter after the system is powered on, but rather a dynamically determined operating state based on the actual heat load changes of each thermoelectric cooler. When the system is under low load, it may enter a single-channel on-state mode to achieve complete current peak shifting; while when the system is under high load, it automatically switches to a multi-channel overlapping mode to accommodate greater power demand. This mode determination logic based on real-time data allows the control system to operate with a timing strategy that minimizes power supply impact while ensuring cooling performance. The mode determination is based on the overall statistical characteristics of the on-time of each channel, which ensures global power balance and avoids the limitation of focusing only on single-channel control while ignoring bus pressure.

[0025] Step 103: Based on the current control mode and the current activation sequence, allocate the activation duration of each thermoelectric cooler in the current scheduling cycle to obtain the driving timing of each thermoelectric cooler.

[0026] In practical applications, timing allocation is a crucial step in transforming abstract time requirements into concrete waveform signals, mapping discrete activation durations onto a continuous time axis. The algorithmic logic of timing allocation differs fundamentally under different current control modes. In single-path activation mode, the activation periods of each path are arranged sequentially and do not overlap; in multi-path overlapping mode, the activation periods of each path are arranged sequentially, with some overlapping periods. In both modes, the activation duration of each path remains unchanged; that is, the actual conduction time of each path within the current scheduling cycle is equal to the acquired activation duration.

[0027] Step 104: Drive each semiconductor cooler to work according to its driving timing sequence.

[0028] In practical applications, the controller generates corresponding PWM signals for each channel according to the driving timing sequence and outputs the PWM signals to the corresponding channel's drive circuit to control the on and off of the corresponding thermoelectric cooler. The period of the PWM signal is equal to the current scheduling cycle, and the pulse width is equal to the on duration of the corresponding channel. The position of the pulse within the current scheduling cycle is determined by the on and off times obtained from the timing sequence allocation: when the corresponding channel is turned on, the controller sets the PWM signal of that channel to the on level, the drive circuit is turned on, and the power supply bus outputs drive current to the corresponding thermoelectric cooler through the drive circuit of that channel; when the corresponding channel is turned off, the controller sets the PWM signal of that channel to the off level, the drive circuit is turned off, and the corresponding thermoelectric cooler stops drawing power. For a path whose activation period crosses the boundary of the current scheduling cycle, the controller sets the PWM signal to the activation level at the activation time of the path. The activation level continues from the activation time to the end of the current scheduling cycle, and continues to be maintained from the start time of the next scheduling cycle until the deactivation time of the path is reached and set to the deactivation level. The conduction of the path is not interrupted at the cycle boundary, and its actual conduction time is equal to its activation duration.

[0029] Furthermore, the driving process is executed periodically. Each new current scheduling cycle will repeat the complete process of steps 101 to 104 above based on the latest operating conditions, thereby achieving continuous adaptive adjustment to variable heat loads.

[0030] In this way, this application determines the current control mode based on the turn-on duration of each semiconductor cooling chip, and allocates the turn-on duration of each chip according to the current control mode and the current turn-on sequence. This ensures that the turn-on periods of each chip are uniformly included in the controlled arrangement within the current scheduling cycle. In the single-chip turn-on mode, the superposition of bus currents can be avoided after the turn-on periods of each chip are allocated according to the time sequence. In the multi-chip overlapping mode, the overlap of the turn-on periods of each chip is uniformly determined by the time sequence allocation, rather than being a random superposition under independent control of each chip. The degree of superposition of bus currents can be reduced. Thus, without changing the turn-on duration of each chip or affecting the temperature control effect, the degree of current superposition of the power supply bus is reduced, the instantaneous peak power borne by the power supply is reduced, the peak load of the power supply is alleviated, and the service life of the power supply is extended.

[0031] In one possible implementation, the current control mode is determined based on the on-time of each thermoelectric cooler during the current scheduling cycle, including: When the total on-time of each semiconductor cooling chip in the current scheduling cycle is not greater than the current scheduling cycle, the current control mode is determined to be the single-channel on-time mode. When the total on-time of all semiconductor cooling chips in the current scheduling cycle is greater than the current scheduling cycle, the current control mode is determined to be multi-channel overlapping mode.

[0032] In practical applications, the sum of the on-time of each circuit represents the cumulative absolute on-time required for all thermoelectric coolers to maintain the target temperature within one cycle. When the sum of the on-time of each circuit is no greater than the current scheduling cycle, it means that the system has sufficient redundancy in the time dimension. Physically, it is entirely possible to serially arrange the on-time periods of all loads end-to-end, so that at most one load is in the working state at any given time in the entire cycle. In this case, determining it as a single-circuit on-time mode can fundamentally eliminate the possibility of multiple current superposition, making the instantaneous power demand of the external power supply bus constant at the power level of a single load, thus minimizing the peak power requirements of the upstream power supply.

[0033] When the total activation duration of all channels exceeds the current scheduling cycle, it indicates that the total conduction demand of multiple loads has exceeded the linear time capacity of a single cycle. In this situation, regardless of the sorting method used, there will inevitably be an overlapping interval where at least two loads are simultaneously activated within the same time period. If a sequential arrangement is forcibly maintained at this point, the activation duration of some loads will be truncated or overflow into the next cycle, thus affecting the temperature control accuracy. Therefore, the system automatically switches to a multi-channel overlapping mode, compressing the width and amplitude of the overlapping area as much as possible while ensuring that each load receives its full activation duration.

[0034] In this way, by comparing the total duration of operation with the current scheduling cycle, the appropriate control mode can be automatically selected according to the relative size of the total conduction demand and time resources. Under light load, a single-path operation mode is used to avoid any current superposition; under heavy load, a multi-path overlapping mode is used to limit the superposition to a local range while meeting the conduction demand of each path. The control mode automatically adapts to the load conditions without manual intervention.

[0035] In one possible implementation, see [reference] Figure 2 As shown, when the current control mode is single-channel activation mode, based on the current control mode and the current activation sequence, the activation duration of each thermoelectric cooler in the current scheduling cycle is allocated in a timing sequence to obtain the drive timing of each thermoelectric cooler, including: Step 201: According to the current activation order, arrange the activation durations of each semiconductor cooling chip in the current scheduling cycle, one end to the other, to obtain the first arrangement result.

[0036] In practical applications, the sequential arrangement refers to arranging the conduction time windows of each thermoelectric cooler adjacent to each other on the time axis. This ensures that the turn-off time of one thermoelectric cooler is continuous with the turn-on time of the next on the time axis. The conduction requirements of multiple loads are thus allocated to different time periods for sequential execution, with no time gaps or overlaps between adjacent circuits. The first arrangement result is the time sequence distribution formed after the above arrangement, used to characterize the position and order of each thermoelectric cooler within the current scheduling cycle. It should be understood that since entering single-circuit on-state mode requires the total on-state duration of all circuits to be no greater than the current scheduling cycle, the first arrangement result will not exceed the current scheduling cycle, and a period of idle time where all circuits are off is usually reserved at the end of the cycle. Under this arrangement, at any given time, at most one thermoelectric cooler is on, and the current on the power supply bus is only the drive current of that circuit.

[0037] Step 202: Based on the turn-on duration of each thermoelectric cooler in the current scheduling cycle and the first arrangement result, determine the driving timing of each thermoelectric cooler.

[0038] In practical applications, the controller determines the turn-on and turn-off times of each path based on the arrangement position of each path in the first arrangement result and the turn-on duration of each path, thus obtaining the drive timing sequence. In engineering implementation, the controller can convert the turn-on and turn-off times of each path into timing comparison values ​​and configure a timer. When the timing reference reaches the turn-on time of a certain path, it outputs an turn-on control signal, and when it reaches the turn-off time, it outputs a turn-off control signal, thereby controlling the operation of the drive circuit of the corresponding path.

[0039] To more intuitively illustrate the technical solution of this embodiment, a specific four-channel semiconductor cooling chip control scenario will be used as an example for explanation. (See attached document.) Figure 3 As shown, the current scheduling cycle is set to T. The target duty cycles of the four semiconductor cooling chips, calculated based on temperature control requirements, are 30%, 15%, 25%, and 20%, respectively, with corresponding on-time durations of 0.3T, 0.15T, 0.25T, and 0.2T. At this point, the total on-time duration of each chip is 0.9T, which is less than the current scheduling cycle T, so it enters single-chip on-time mode. According to the preset on-time sequence, for example, ordered by channel numbers 1 to 4, the first chip (CH1) is on during the period from 0 to 0.3T, the second chip (CH2) is on during the period from 0.3T to 0.45T, the third chip (CH3) is on during the period from 0.45T to 0.7T, and the fourth chip (CH4) is on during the period from 0.7T to 0.9T. The period from 0.9T to T is the idle period. Under this driving sequence, the instantaneous power of the power supply bus throughout the entire cycle is equal to the power of a single chip, and there will be no peak current superimposed from multiple chips.

[0040] In one possible implementation, see [reference] Figure 4As shown, when the current control mode is multi-channel overlapping mode, based on the current control mode and the current activation sequence, the activation duration of each thermoelectric cooler in the current scheduling cycle is allocated to obtain the drive timing of each thermoelectric cooler, including: Step 401: According to the current activation order, arrange the activation duration of each semiconductor cooling chip sequentially along the time axis to obtain the second arrangement result.

[0041] In practical applications, the turn-on durations of each semiconductor cooler are arranged sequentially along the time axis according to the current turn-on order, meaning the turn-off time of one cooler is continuous with the turn-on time of the next. This arrangement is not limited by the current scheduling cycle boundary and continues continuously along the time axis until all turn-on durations are arranged, resulting in a second arrangement. The total length of the second arrangement on the time axis is equal to the sum of the turn-on durations of all coolers. Since the sum of the turn-on durations in the multi-channel overlapping mode is greater than the current scheduling cycle, the second arrangement will inevitably exceed the current scheduling cycle; that is, at least one cooler in the second arrangement will have a turn-on period that crosses the boundary of the current scheduling cycle. Each cooler's turn-on period in the second arrangement is a continuous segment, not divided by crossing cycle boundaries, nor increased or decreased by changes in arrangement position; the turn-on duration of each cooler remains unchanged before and after the arrangement.

[0042] Step 402: Map the second permutation result to the current scheduling period to obtain the third permutation result.

[0043] In practical applications, since the driving timing needs to be executed with the current scheduling cycle as the driving cycle, the controller cannot directly output control signals according to the second permutation result that exceeds the current scheduling cycle. Therefore, it is necessary to map the second permutation result to the current scheduling cycle. The mapping is done by folding back the portion of the second permutation result that exceeds the current scheduling cycle while keeping the on-time of each path unchanged, so that the conduction requirements of each path are all constrained within one scheduling cycle, thus obtaining the third permutation result. After mapping, there are at least two paths whose on-time periods overlap within the current scheduling cycle, and the overlapping periods are concentrated at the beginning of the current scheduling cycle. The on-time period of each path remains continuous after mapping. For paths that cross the boundary of the current scheduling cycle, their on-time period consists of the part at the end of the current scheduling cycle and the part at the beginning of the current scheduling cycle. This path is continuously on at the cycle boundary without interruption, and its actual conduction time is equal to its on-time.

[0044] Step 403: Based on the turn-on duration of each thermoelectric cooler in the current scheduling cycle and the third arrangement result, determine the driving timing of each thermoelectric cooler.

[0045] In practical applications, the controller determines the activation and deactivation times of each path based on its position in the third permutation result and its activation duration within the current scheduling cycle, thus obtaining the driving timing sequence for each path. For paths that cross the boundary of the current scheduling cycle, their deactivation time is determined by the sum of their activation time and activation duration. If this sum is greater than the current scheduling cycle, the deactivation time is the sum minus the current scheduling cycle. In other words, the path's activation period extends from its activation time to the end of the cycle, and from the beginning of the cycle to its deactivation time. The controller converts the activation and deactivation times of each path into timing comparison values ​​and controls the activation and deactivation of each path according to the driving timing sequence during subsequent driving processes.

[0046] Specifically, see Figure 5As shown, taking a four-channel thermoelectric cooler as an example, with the current scheduling period set to T, the target duty cycles of the first channel CH1 to the fourth channel CH4 are 40%, 50%, 80%, and 60%, respectively, with corresponding on-time durations of 0.4T, 0.5T, 0.8T, and 0.6T, respectively, totaling 2.3T, which is greater than the current scheduling period T, thus entering a multi-channel overlap mode. The second arrangement result shows that the on-time period of the first channel CH1 is 0 to 0.4T, the on-time period of the second channel CH2 is 0.4T to 0.9T, the on-time period of the third channel CH3 is 0.9T to 1.7T, and the on-time period of the fourth channel CH4 is 1.7T to 2.3T. Among them, the on-time periods of the third channel CH3 and the fourth channel CH4 both cross the boundary of the scheduling period. The portion between T and 2T, namely 0.7T of the third CH3 and 0.3T of the fourth CH4, needs to be returned to the current scheduling cycle and arranged sequentially within 0 to T. That is, the returned portion of the third CH3 occupies 0 to 0.7T, and the returned portion of the fourth CH4 occupies 0.7T to T. The portion between 2T and 2.3T, namely the remaining 0.3T of the fourth CH4, needs to be returned again and arranged within 0 to 0.3T. The third permutation result after mapping is as follows: During the period from 0 to 0.3T, the return portions of the first path CH1 and the third path CH3, and the secondary return portion of the fourth path CH4 are simultaneously activated; During the period from 0.3T to 0.4T, the return portions of the first path CH1 and the third path CH3 are simultaneously activated; During the period from 0.4T to 0.7T, the return portions of the second path CH2 and the third path CH3 are simultaneously activated; During the period from 0.7T to 0.9T, the return portions of the second path CH2 and the fourth path CH4 are simultaneously activated; During the period from 0.9T to T, the portion of the third path CH3 within the current scheduling period and the return portion of the fourth path CH4 are simultaneously activated. Thus, under the condition that the total activation time is 2.3T, the number of paths that can be activated simultaneously is at most three, and the simultaneous activation of the three paths only exists in the 0 to 0.3T period at the beginning of the cycle. During other periods, the number of paths that can be activated simultaneously does not exceed two. Compared with the existing technology that activates four paths simultaneously throughout the entire scheduling cycle, the instantaneous peak current of the power supply bus is significantly reduced, the current superposition is limited to a local period of the current scheduling cycle, and the activation time of each path does not change before and after the timing allocation, so the temperature control effect of each path is not affected.

[0047] In practice, the second permutation result is mapped to the current scheduling period to obtain the third permutation result, including: The second arrangement result is divided into units based on the current scheduling cycle. The segments obtained from the division are then overlapped and arranged within the current scheduling cycle to obtain the third arrangement result.

[0048] In practical applications, the controller segments the second arrangement result sequentially along the time axis according to the duration of the current scheduling period: Let the total length of the second arrangement result be L, and the current scheduling period be T. Then, the second arrangement result is divided into N segments of length T and one segment of length less than T, where N is the integer quotient of L divided by T. The division only changes the period position of each segment; the activation time and duration of each path within each segment remain unchanged. After the division, the controller aligns each segment within the current scheduling period: the second segment moves T towards the beginning of the current scheduling period, the third segment moves 2T, and so on, until all segments are within the current scheduling period and overlap, resulting in the third arrangement result. Since the length of each segment is no greater than the current scheduling period, each segment can fall completely within the current scheduling period; after the segments overlap, multiple paths may be simultaneously active during certain time periods within the current scheduling period, and the number of simultaneously active paths equals the number of overlapping segments within that time period.

[0049] Taking a four-channel thermoelectric cooler as an example, the current scheduling cycle is set to T. The target duty cycles of the first channel CH1 to the fourth channel CH4 are 40%, 50%, 80%, and 60%, respectively, with corresponding on-time durations of 0.4T, 0.5T, 0.8T, and 0.6T, totaling 2.3T. The second arrangement result is divided into three segments: the first segment is from 0 to T, including the entire first channel, the entire second channel, and 0.1T of the third channel; the second segment is from T to 2T, including 0.7T of the third channel and 0.3T of the fourth channel; the third segment is from 2T to 2.3T, including the remaining 0.3T of the fourth channel. After the second segment is moved by T and the third segment is moved by 2T, the three segments overlap within the range of 0 to T: in the period from 0 to 0.3T, there are on-time periods in all three segments, and all three channels are simultaneously activated; in the period from 0.3T to T, there are on-time periods in two segments, and both channels are simultaneously activated. The degree of overlap decreases from the beginning of the cycle. If the total duration of each channel is slightly greater than T, for example, 1.1T, then the second arrangement result is divided into two segments. After overlapping arrangement, there are only two channels conducting simultaneously in the period from 0 to 0.1T at the beginning of the cycle, while the remaining periods are still single-channel conducting.

[0050] Furthermore, this embodiment uses the arrangement of the foldback portion starting from the beginning of the current scheduling cycle as an example. Arranging the segments overlapping at the beginning of the current scheduling cycle is preferred. The position of the overlapping time period within the cycle is fixed, and the timing of the peak current occurrence is predictable, facilitating power supply design and power bus current detection. In other embodiments, the divided segments can also be overlapped in the middle or end of the current scheduling cycle. For example, when the controller performs electromagnetically sensitive actions such as temperature sampling within the current scheduling cycle, the segments are overlapped at positions far from the execution time of that action to reduce interference from switching actions within the overlapping time period. Regardless of their position within the current scheduling cycle, the on-time of each path must remain unchanged before and after mapping; that is, mapping only changes the position of each on-time period within the cycle, not its length. Furthermore, the on-time periods of the same path must not overlap within the current scheduling cycle; that is, the drive signal of the same path can only execute one on-time command at any given moment. If the foldback portion of the same path overlaps with the original on-time period of that path within the current scheduling cycle, the drive timing of that path will not be executed. Since the activation duration of any path is no longer than the current scheduling cycle, the activation periods of the same path, after being rounded back, can be arranged non-overlappingly within the current scheduling cycle. The above constraints can be satisfied under all load conditions. Under the premise of satisfying the above two conditions, various arrangement positions can achieve the technical effects of this embodiment.

[0051] In one possible implementation, see [reference] Figure 6 As shown, the activation duration of each semiconductor cooling chip within the current scheduling cycle is obtained, including: Step 601: Obtain the target temperature, current temperature, and current scheduling cycle of each semiconductor cooling chip.

[0052] In practical applications, the target temperature refers to the desired temperature of the target area corresponding to the thermoelectric cooler, i.e., the set value for temperature control. Each thermoelectric cooler corresponds to a target area, and the target temperatures of each target area can be the same or different. The target temperature is issued by the host computer or set by the user through a local human-machine interface. The controller reads the target temperature of each channel from the communication interface or storage unit. The current scheduling cycle is the scheduling parameter set by the controller itself, read from the controller's configuration register. The above acquisition is performed once at the beginning of each scheduling cycle, so that the activation duration of the current cycle is calculated based on the latest target temperature.

[0053] Step 602: Determine the target duty cycle of each thermoelectric cooler based on the target temperature and current temperature of each thermoelectric cooler.

[0054] In practical applications, the target duty cycle refers to the duty cycle corresponding to the temperature regulation requirements of the corresponding path. It represents the degree of conduction required to adjust the current temperature to the target temperature, and its value ranges from 0 to 100%. When the target duty cycle is 0, the corresponding path is not conducting during the current scheduling cycle; when the target duty cycle is 100%, the corresponding path is continuously conducting during the current scheduling cycle. The controller calculates the temperature deviation between the target temperature and the current temperature for each path, performs PID control calculations on the temperature deviation, and obtains the target duty cycle for the corresponding path. The larger the absolute value of the temperature deviation, the larger the target duty cycle output by the PID control calculation, and the longer the required on-time of the corresponding path. When the temperature deviation is zero, the target duty cycle maintains a value adapted to the current thermal balance. When the output of the PID control calculation exceeds the value range of the duty cycle, the target duty cycle is limited to the range of 0 to 100%. The direction of cooling or heating is determined by the sign of the temperature deviation: when the target temperature is lower than the current temperature, the corresponding path is in cooling mode; when the target temperature is higher than the current temperature, the corresponding path is in heating mode. The target duty cycle only represents the degree of conduction and does not include directional information. The duty cycle of each target path is calculated independently based on its respective temperature deviation, without affecting each other.

[0055] Step 603: Based on the target duty cycle and the current scheduling cycle, determine the activation duration of the corresponding circuit's thermoelectric cooler within the current scheduling cycle.

[0056] In practical applications, the on-time of a thermoelectric cooler within the current scheduling cycle is equal to the target duty cycle multiplied by the current scheduling cycle. For example, if the target duty cycle of a certain path is 40% and the current scheduling cycle is 10 milliseconds, the on-time of that path within the current scheduling cycle is 4 milliseconds; if the target duty cycle is 100%, the on-time is equal to 10 milliseconds, meaning that the path is continuously conducting throughout the entire current scheduling cycle.

[0057] In one possible implementation, see [reference] Figure 7 As shown, the current activation order is retrieved, including: Step 701: Obtain the setting position and priority setting value of each semiconductor cooling chip.

[0058] In practical applications, the setting position refers to the installation location of each thermoelectric cooler chip in the application device. It characterizes the location and function of the target area corresponding to each chip within the device, such as the main heat dissipation area and auxiliary heat dissipation area. Different setting positions correspond to different levels of importance for the target areas; thermoelectric coolers installed in the main heat dissipation area have a higher initial priority than those installed in the auxiliary heat dissipation area. The priority setting value is a configuration parameter characterizing the relative importance of each chip. It is set by the user through a human-machine interface or issued by a host computer and is used to adjust the priority of each chip according to actual application requirements. The controller reads the setting position of each chip from its configuration register and the priority setting value of each chip from the communication interface or storage unit.

[0059] Step 702: Determine the adjustment priority of each thermoelectric cooler based on its setting position and priority setting value.

[0060] In practical applications, the controller pre-stores the correspondence between setting positions and initial priorities. Each setting position corresponds to a specific initial priority, with the initial priority of the setting position corresponding to a target area of ​​higher importance being higher than that of a target area of ​​lower importance. The controller queries the above correspondence based on the setting position of each channel to obtain the initial priority of each channel. Subsequently, the controller sums the initial priority of each channel with the corresponding priority setting value to obtain the adjustment priority of each channel. The priority setting value can be positive, negative, or zero, representing increasing, decreasing, or maintaining the priority of the corresponding channel, respectively. The importance of each target area may vary in different application scenarios for the same device. The adjustment priority of each channel can be adjusted by modifying the priority setting value without changing the hardware structure. Both the initial priority and the priority setting value are configuration variables. Once determined, the adjustment priority remains stable and is only updated when the configuration changes, avoiding frequent changes in the current activation order caused by sorting based on runtime changes.

[0061] Step 703: Determine the current turn-on sequence of each semiconductor cooling chip according to the order of adjustment priority from high to low.

[0062] In practical applications, the controller arranges the various thermoelectric coolers in descending order of adjustment priority to obtain the current activation sequence. When at least two channels have the same adjustment priority, these two channels are arranged according to the inherent order of their set locations, i.e., the channel with higher importance corresponding to the target area is placed first, to avoid the order of channels with the same adjustment priority changing in different scheduling cycles. The determined current activation sequence serves as the input for timing allocation, and the controller arranges the activation periods of each channel sequentially according to the current activation sequence within the current scheduling cycle.

[0063] In one possible implementation, the multi-channel semiconductor cooling chip control method further includes: During the current scheduling cycle, when the turn-on duration of at least one thermoelectric cooler changes, the current turn-on order is updated so that the thermoelectric cooler whose turn-on duration has changed is placed before the thermoelectric coolers whose turn-on duration has not changed.

[0064] In practical applications, after acquiring the activation duration of each channel in each scheduling cycle, the controller compares the activation duration acquired in the current cycle with that of the previous scheduling cycle. If the activation duration of a channel in the current cycle differs from that of the previous cycle, it is determined that the activation duration of that channel has changed. The controller can also set a preset change threshold. For each semiconductor cooling chip, the change in activation duration is calculated based on the difference between the activation duration acquired in the current cycle and that of the previous scheduling cycle. A change is only determined when the change in activation duration of a channel exceeds the preset change threshold, thus avoiding frequent updates to the current activation order caused by minor fluctuations in activation duration. Since the temperature control algorithms for each channel operate independently, one channel may change within the same scheduling cycle, or multiple channels may change simultaneously. The controller extracts the channels with changed activation durations and arranges them at the beginning of the current activation order, while the channels with unchanged activation durations maintain their original relative order and are arranged at the end. When at least two channels have changed activation durations, these two channels are arranged sequentially at the front according to their relative order in the current activation sequence before the update. The update takes effect from the next scheduling cycle, and the drive timing of the current scheduling cycle remains unchanged. Modifying the output control signal during the execution of the drive timing may cause abnormal pulse truncation or mis-enabling of the switching transistor. Delaying the update to the boundary of the scheduling cycle can avoid these problems. Due to the large thermal inertia of the thermoelectric cooler, a delay of one scheduling cycle has no substantial impact on the temperature control accuracy.

[0065] In this way, routes with changing temperature requirements are prioritized for opening in the next scheduling cycle, and the changed opening duration is prioritized for the beginning of the current scheduling cycle. Meanwhile, the relative order of routes that have not changed remains unchanged, and the scheduling maintains the stability of the timing while responding to changes in demand.

[0066] Based on the above embodiments, this application provides a temperature control system, see below. Figure 8 As shown, the temperature regulation system 100 provided in this application embodiment includes at least: a controller 110, a plurality of semiconductor coolers 120 and a plurality of drive circuits 130; the semiconductor coolers 120 and the drive circuits 130 are respectively arranged; The control terminal of each drive circuit 130 is connected to the controller 110, the input terminal of each drive circuit 130 is connected to the power supply via the power supply bus, and the output terminal of each drive circuit 130 is connected to the corresponding thermoelectric cooler 120; the thermoelectric cooler 120 is disposed in the corresponding target area. The controller 110 is used to execute the above-mentioned multi-channel thermoelectric cooler control method and output corresponding control signals to each drive circuit 130; The drive circuit 130 is used to drive the corresponding semiconductor cooler 120 to work according to the control signal; The semiconductor cooler 120 is used to adjust the temperature of the corresponding target area under the drive of the drive circuit 130.

[0067] exist Figure 8 In the temperature control system 100 shown, multiple drive circuits 130 are configured one-to-one with multiple thermoelectric coolers 120. Each thermoelectric cooler 120 is mounted on its corresponding target component. The power supply provides input to each drive circuit 130 via a power supply bus. When any drive circuit 130 is turned on, it transmits the input provided by the power supply bus to the corresponding thermoelectric cooler 120; that is, the drive current of each thermoelectric cooler 120 comes from the power supply bus. Therefore, when multiple drive circuits 130 are turned on simultaneously, the drive currents of each circuit are superimposed on the power supply bus, and the instantaneous current of the power supply bus is equal to the sum of the drive currents of all circuits that are turned on simultaneously. The controller 110 is connected to each drive circuit 130 and outputs independent control signals to each drive circuit 130.

[0068] The controller 110 is the core of the system's computation and scheduling. It can be implemented using a microcontroller, digital signal processor, field-programmable gate array, or application-specific integrated circuit (ASIC). Internally, it integrates a timer and multiple PWM output channels. Within each scheduling cycle, the controller 110 sequentially completes temperature acquisition, on-time calculation, timing allocation, and PWM output. Temperature acquisition is performed through a temperature acquisition circuit, which includes temperature sensors mounted on each target component and corresponding sampling circuits. The controller 110 reads the sampled values ​​from each temperature sensor to obtain the current temperature of each target component. On-time calculation is performed independently for each channel. The controller 110 calculates the temperature deviation between the target temperature and the current temperature for that channel, obtains the target duty cycle for that channel through proportional-integral-derivative (PID) control, and then multiplies the target duty cycle by the current scheduling cycle to obtain the on-time of that channel. Timing allocation is performed according to the rules of the aforementioned embodiments. The controller 110 determines the current control mode based on the sum of the on-times of all channels, and then arranges the on-times of each channel according to the current control mode and the current on-time sequence to obtain the on-time and off-time of each channel. The PWM output is implemented by a timer. The controller 110 writes the turn-on and turn-off times of each channel into the comparison register of the corresponding PWM channel. When the timer count reaches the comparison value corresponding to the turn-on time, the channel outputs a high level, and when it reaches the comparison value corresponding to the turn-off time, it outputs a low level. Thus, each PWM channel outputs PWM signals with staggered pulse positions.

[0069] The drive circuit 130 is the power execution unit of the system and can be implemented using a full-bridge circuit or other controllable power circuits. The drive circuit 130 is turned on and off under the control of a PWM signal. When on, it transmits the input of the power supply bus to the corresponding thermoelectric cooler 120; when off, the corresponding thermoelectric cooler 120 stops drawing power. The drive circuit 130 can also change the direction of the output current. When the output current is in a first direction, the corresponding thermoelectric cooler 120 cools; when it is in a second direction, the corresponding thermoelectric cooler 120 heats. The switching between cooling and heating is completed during the period when the thermoelectric cooler 120 stops drawing power, avoiding current surges to the power supply bus during the commutation process. The specific structure of the drive circuit 130 will be described in subsequent embodiments.

[0070] A thermoelectric cooler 120 is attached to the surface of a target component at a target location. When a drive current flows through the thermoelectric cooler 120 in a first direction, the thermoelectric cooler 120 absorbs heat on the side facing the target component, cooling the target component. When a drive current flows through the thermoelectric cooler 120 in a second direction, the thermoelectric cooler 120 releases heat on the side facing the target component, heating the target component. The temperature change of the target component is fed back to the controller 110 via a temperature sensor. The controller 110 recalculates the on-time based on the new current temperature in the next scheduling cycle, forming a closed-loop regulation until the temperature of the target component stabilizes at the target temperature.

[0071] In one possible implementation, see [reference] Figure 9 As shown, the drive circuit 130 includes: a first switch Q1, a second switch Q2, a third switch Q3, and a fourth switch Q4; The first terminal of the first switch Q1 is connected to the high potential terminal of the power supply bus, the second terminal of the first switch Q1 is connected to the first terminal of the second switch Q2, and the second terminal of the second switch Q2 is connected to the low potential terminal of the power supply bus; the control terminal of the first switch Q1 and the control terminal of the second switch Q2 are respectively connected to the corresponding output terminals of the controller 110. The first terminal of the third switch Q3 is connected to the high potential terminal of the power supply bus, the second terminal of the third switch Q3 is connected to the first terminal of the fourth switch Q4, and the second terminal of the fourth switch Q4 is connected to the low potential terminal of the power supply bus; the control terminals of the third switch Q3 and the fourth switch Q4 are respectively connected to the corresponding output terminals of the controller 110. The second terminal of the first switching transistor Q1 and the second terminal of the third switching transistor Q3 are connected to the corresponding semiconductor cooler 120.

[0072] exist Figure 9In the circuit shown, when the controller 110 controls the first switch Q1 and the fourth switch Q4 to be turned on, and the second switch Q2 and the third switch Q3 to be turned off, current flows through the first switch Q1, the thermoelectric cooler 120, and the fourth switch Q4, and the thermoelectric cooler 120 is in a cooling state. When the controller 110 controls the third switch Q3 and the second switch Q2 to be turned on, and the first switch Q1 and the fourth switch Q4 to be turned off, current flows through the thermoelectric cooler 120 in the opposite direction, and the thermoelectric cooler 120 is in a heating state. The switching between the cooling state and the heating state is completed during the period when the thermoelectric cooler 120 stops drawing power, that is, the controller 110 first turns off all four switches, and then turns on another set of diagonal switches to avoid short circuits in the power supply bus caused by two switches on the same bridge arm being turned on at the same time.

[0073] Specifically, the switching transistor can be a metal-oxide-semiconductor field-effect transistor, in which case the control terminal is the gate, the first terminal is the drain, and the second terminal is the source; it can also be an insulated-gate bipolar transistor, a bipolar junction transistor, or a gallium nitride or silicon carbide power device. This embodiment does not limit the type of switching transistor. The driving circuit 130 can also include auxiliary components such as a freewheeling diode, a buffer capacitor, and a current sampling resistor to improve the reliability of the circuit. These auxiliary components do not affect the establishment of the above-mentioned connection relationship.

[0074] In this way, the drive circuit 130 can achieve bidirectional driving of cooling and heating while adapting to the timing of peak-shaving scheduling. In single-path activation mode, only one drive circuit 130 outputs current to the corresponding semiconductor cooler 120 at any given time, and the current of the power supply bus is limited to the single-path level; in multi-path overlapping mode, multiple drive circuits 130 output current simultaneously only in local time periods, and the superposition range is determined by the timing allocation, so there will be no disorderly superposition throughout the entire cycle.

[0075] It should be noted that although several units or sub-units of the device have been mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of this application, the features and functions of two or more units described above can be embodied in one unit. Conversely, the features and functions of one unit described above can be further divided and embodied by multiple units.

[0076] Furthermore, although the operations of the method of this application are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0077] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0078] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. A method for controlling a multi-channel semiconductor cooling chip, characterized in that, include: Obtain the activation duration and current activation order of each semiconductor cooling chip within the current scheduling cycle; The current control mode is determined based on the activation duration of each semiconductor cooling chip in the current scheduling cycle; wherein, the current control mode includes single-channel activation mode and multi-channel overlapping mode; Based on the current control mode and the current activation sequence, the activation duration of each of the semiconductor cooling chips in the current scheduling cycle is allocated in a timing sequence to obtain the driving timing sequence of each of the semiconductor cooling chips. Drive each of the aforementioned semiconductor cooling chips to operate according to the driving timing sequence of each chip.

2. The multi-channel semiconductor cooling chip control method as described in claim 1, characterized in that, The step of determining the current control mode based on the on-time duration of each of the semiconductor cooling chips within the current scheduling cycle includes: When the sum of the on-time of each of the semiconductor cooling chips in the current scheduling period is not greater than the current scheduling period, the current control mode is determined to be a single-channel on-time mode. When the sum of the on-time of each of the semiconductor cooling chips in the current scheduling period is greater than the current scheduling period, the current control mode is determined to be a multi-channel overlapping mode.

3. The multi-channel semiconductor cooling chip control method as described in claim 1, characterized in that, When the current control mode is a single-channel activation mode, the activation duration of each of the semiconductor cooling chips is allocated in the current scheduling cycle based on the current control mode and the current activation sequence to obtain the drive timing of each of the semiconductor cooling chips, including: According to the current activation order, the activation durations of each of the semiconductor cooling chips are arranged sequentially from beginning to end within the current scheduling cycle to obtain the first arrangement result; Based on the on-time of each of the semiconductor cooling chips in the current scheduling cycle and the first arrangement result, the driving timing of each of the semiconductor cooling chips is determined.

4. The multi-channel semiconductor cooling chip control method as described in claim 1, characterized in that, When the current control mode is a multi-channel overlapping mode, the timing allocation of the activation duration of each of the thermoelectric coolers within the current scheduling cycle is performed based on the current control mode and the current activation sequence to obtain the driving timing of each of the thermoelectric coolers, including: According to the current activation sequence, the activation durations of each of the semiconductor cooling chips are arranged sequentially along the time axis to obtain the second arrangement result; The second arrangement result is mapped to the current scheduling period to obtain the third arrangement result; Based on the on-time of each of the semiconductor cooling chips in the current scheduling cycle and the third arrangement result, the driving timing of each of the semiconductor cooling chips is determined.

5. The multi-channel semiconductor cooling chip control method as described in claim 4, characterized in that, The step of mapping the second arrangement result to the current scheduling period to obtain the third arrangement result includes: The second arrangement result is divided into units based on the current scheduling period, and the resulting segments are overlapped and arranged within the current scheduling period to obtain the third arrangement result.

6. The multi-channel semiconductor cooling chip control method as described in claim 1, characterized in that, Obtain the activation duration of each semiconductor cooling chip within the current scheduling cycle, including: Obtain the target temperature, current temperature, and current scheduling cycle of each of the semiconductor cooling chips; Based on the target temperature and current temperature of each of the aforementioned semiconductor cooling chips, the target duty cycle of each of the aforementioned semiconductor cooling chips is determined; Based on the target duty cycle and the current scheduling period, the on-time of the corresponding semiconductor cooling chip within the current scheduling period is determined.

7. The multi-channel semiconductor cooling chip control method as described in claim 1, characterized in that, Get the current activation order, including: Obtain the setting position and priority setting value of each of the semiconductor cooling chips; The adjustment priority of each semiconductor cooling chip is determined based on the setting position of each chip and the priority setting value. The current activation sequence of each semiconductor cooling chip is determined according to the order of adjustment priority from high to low.

8. The multi-channel semiconductor cooling chip control method according to any one of claims 1-7, characterized in that, Also includes: During the current scheduling cycle, when the turn-on duration of at least one of the thermoelectric coolers changes, the current turn-on order is updated so that the thermoelectric cooler whose turn-on duration has changed is placed before the thermoelectric coolers whose turn-on duration has not changed.

9. A temperature control system, characterized in that, include: Controller, multiple semiconductor coolers, and multiple drive circuits; The semiconductor cooler is configured in correspondence with the driving circuit; The control terminal of each drive circuit is connected to the controller, the input terminal of each drive circuit is connected to the power supply via the power supply bus, and the output terminal of each drive circuit is connected to the corresponding semiconductor cooler; the semiconductor cooler is disposed in the corresponding target area. The controller is configured to execute the multi-channel semiconductor cooling chip control method as described in any one of claims 1-8, and output corresponding control signals to each of the driving circuits. The driving circuit is used to drive the corresponding semiconductor cooler to work according to the control signal; The semiconductor cooler is used to adjust the temperature of the corresponding target area under the drive of the driving circuit.

10. The temperature control system as described in claim 9, characterized in that, The driving circuit includes: a first switching transistor, a second switching transistor, a third switching transistor, and a fourth switching transistor; The first terminal of the first switch is connected to the high-potential terminal of the power supply bus, the second terminal of the first switch is connected to the first terminal of the second switch, and the second terminal of the second switch is connected to the low-potential terminal of the power supply bus; the control terminals of the first switch and the second switch are respectively connected to the corresponding output terminals of the controller. The first terminal of the third switch is connected to the high-potential terminal of the power supply bus, the second terminal of the third switch is connected to the first terminal of the fourth switch, and the second terminal of the fourth switch is connected to the low-potential terminal of the power supply bus; the control terminals of the third switch and the fourth switch are respectively connected to the corresponding output terminals of the controller. The second end of the first switching transistor and the second end of the third switching transistor are connected to the corresponding semiconductor cooler.

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