Method for failure diagnosis of semiconductor devices

Abstract

The application discloses a failure diagnosis method of a semiconductor device, comprising the following steps: obtaining an electrical parameter of a to-be-tested semiconductor device under a first electrical performance test condition; obtaining a first thermal performance function curve of the to-be-tested semiconductor device under a first temperature condition and a second thermal performance function curve of a standard semiconductor device under the first temperature condition; obtaining a thermal resistance parameter of the to-be-tested semiconductor device under the first temperature condition according to the first thermal performance function curve and the second thermal performance function curve; and diagnosing failure information of the to-be-tested semiconductor device according to the electrical parameter and the thermal resistance parameter. According to the embodiment of the application, lossless failure analysis of the semiconductor device can be realized without the aid of visual analysis technology.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a method for diagnosing the failure of semiconductor devices. Background Technology

[0002] In semiconductor device packaging, ceramic sheets are typically used as the insulating and thermally conductive medium inside the package. The mechanical properties of the ceramic sheet are crucial to the insulation and heat dissipation reliability of the package. However, brittle ceramic sheets are prone to microcracks during processing, soldering, or temperature cycling tests, which can further lead to premature failure of the package.

[0003] In some packaged products, the cause of failure cannot be determined through conventional visual analysis due to limitations in the material and structure of the casing. Summary of the Invention

[0004] This application provides a method for diagnosing failures in semiconductor devices, which can achieve lossless failure location of semiconductor devices and further clarify the failure type without relying on visual analysis technology.

[0005] This application provides a method for diagnosing failures in semiconductor devices. The failure diagnosis method includes: Electrical parameter acquisition: Acquire the electrical parameters of the semiconductor device under test under the first electrical performance test conditions; Thermal resistance parameter acquisition: Obtain the first thermal performance function curve of the semiconductor device under test under the first temperature condition and the second thermal performance function curve of the standard semiconductor device under the first temperature condition. Based on the first thermal performance function curve and the second thermal performance function curve, obtain the thermal resistance parameter of the semiconductor device under test under the first temperature condition. Failure Information Diagnosis: Based on either the electrical parameters or the thermal resistance parameters, the primary failure information of the semiconductor device under test is obtained. Based on the primary failure information and the other of the electrical parameters and thermal resistance parameters, the failure information of the semiconductor device under test is diagnosed.

[0006] In some embodiments, failure information diagnosis includes: Based on whether the thermal resistance parameter of the semiconductor device under test meets the first preset condition, the primary failure information of the semiconductor device under test is obtained. Based on the primary failure information and whether the electrical parameters of the semiconductor device under test meet the second preset condition, the failure type information of the semiconductor device under test is determined.

[0007] In some embodiments, the semiconductor device under test includes an insulating and thermally conductive layer. Obtaining primary failure information of the semiconductor device under test based on whether its thermal resistance parameter meets a first preset condition includes: If the thermal resistance parameter of the semiconductor device under test meets the first preset condition, then the failure location of the semiconductor device under test is determined to be the insulating thermally conductive layer. The first preset condition includes a first A preset condition, which includes that the steady-state thermal resistance of the semiconductor device under test is greater than that of the standard semiconductor device.

[0008] In some of these embodiments, the steady-state thermal resistance is calculated using the following formula:

[0009] In the formula, Junction temperature of semiconductor devices This refers to the case temperature of a semiconductor device. This is the drain voltage of the semiconductor device under the first temperature condition. This refers to the drain current of the semiconductor device under the first temperature condition. This refers to the temperature-sensitive parameter coefficient of a semiconductor device. This refers to the source-drain voltage of a semiconductor device. This is the offset for thermal testing calibration.

[0010] In some embodiments, the failure diagnosis method further includes: In a no-power state, the semiconductor device under test is placed under different temperature conditions and the source-drain forward voltage drop is measured respectively. The temperature sensitivity parameter coefficient of the semiconductor device under test is obtained by fitting the curve of the source-drain forward voltage drop of the semiconductor device under different temperature conditions.

[0011] In some embodiments, both the first thermal performance function curve and the second thermal performance function curve are integral structure function curves. The first preset condition also includes a first second preset condition, which includes that the length of the flat segment of the first thermal performance function curve is greater than the length of the flat segment of the second thermal performance function curve.

[0012] In some embodiments, determining the failure type information of the semiconductor device under test based on whether the primary failure information and the electrical parameters of the device under test meet a second preset condition includes: When the failure location of the semiconductor device under test is the insulating and thermally conductive layer, if the electrical parameters meet the second preset condition, the semiconductor device under test is determined to be of the first defect type; if the electrical parameters do not meet the second preset condition, the semiconductor device under test is determined to be of the second defect type. The electrical parameters include resistance value, the second preset condition includes resistance value less than or equal to second verification value, and / or, the electrical parameters include at least one of current value and conductance value, and the second preset condition includes electrical parameters greater than or equal to third verification value.

[0013] In some embodiments, the failure diagnosis method further includes: The second verification value is determined based on the electrical parameters of the standard semiconductor device under the first electrical performance test conditions.

[0014] In some of these embodiments, obtaining the electrical parameters includes: A test voltage of not less than 500V is provided between the drain of the semiconductor device under test and the package. After a first time interval, the first electrical parameters of the semiconductor device under test are obtained.

[0015] In some embodiments, the failure diagnosis method further includes: Perform static testing on the target semiconductor device to obtain its static parameters; When the static parameters of the target semiconductor device meet the third preset condition, the target semiconductor device is determined to be the semiconductor device under test.

[0016] According to the semiconductor device failure diagnosis method of this application, electrical parameters and thermal resistance parameters of the semiconductor device under test are obtained by performing electrical performance tests and thermal performance tests on the semiconductor device under test, respectively. Failure information diagnosis of the semiconductor device under test is then achieved based on these electrical and thermal resistance parameters. In this way, failure causes can be diagnosed using only electrical and thermal performance parameters without damaging the semiconductor device under test, improving the effectiveness of semiconductor device failure analysis. Specifically, one of the electrical parameters and the thermal resistance parameter is used to determine the primary failure information of the semiconductor device under test to narrow down the possible failure causes, while the other of the electrical parameters and the thermal resistance parameter is used to further clarify the failure cause of the semiconductor device under test within the aforementioned failure cause range. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating a failure diagnosis method for a semiconductor device according to some embodiments of this application; Figure 2 This is a schematic diagram of a sub-process of a failure diagnosis method for semiconductor devices according to some embodiments of this application; Figure 3 This is a schematic diagram of a sub-process of a failure diagnosis method for semiconductor devices according to some embodiments of this application; Figure 4 This is a schematic diagram of a sub-process of a failure diagnosis method for semiconductor devices according to some embodiments of this application; Figure 5 This is a schematic diagram of a sub-process of a failure diagnosis method for semiconductor devices according to some embodiments of this application; Figure 6 This is a schematic diagram comparing the curves of a first thermal performance function and a second thermal performance function in a failure diagnosis method for a semiconductor device according to some embodiments of this application. Detailed Implementation

[0019] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0021] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0022] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0023] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0024] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0025] In the description of the embodiments of this application, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0026] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0027] In semiconductor device packaging, ceramic sheets are typically used as the insulating and thermally conductive medium inside the package. The mechanical properties of the ceramic sheet are crucial to the insulation and heat dissipation reliability of the package. However, brittle ceramic sheets are prone to microcracks during processing, soldering, or temperature cycling tests, which can further lead to premature failure of the package.

[0028] Taking the TO-254 metal packaged vertical double diffused metal oxide semiconductor field-effect transistor as an example, this product is widely used in high-reliability fields such as aviation, aerospace, radar and power supply. When packaging, beryllium oxide (BeO) ceramic sheet is used as the insulating and thermally conductive medium between the drain and the metal shell. The brittle beryllium oxide ceramic sheet is prone to cracking defects during processing, welding and extreme mechanical testing, which can further lead to high voltage leakage, increased thermal resistance and even early failure of the device.

[0029] However, the TO-254 package uses a hermetically sealed metal casing. Due to the material properties of the outer metal shell, visible light or X-rays cannot penetrate the shell to enter the product for visual analysis of the chip or ceramic substrate using image inspection or other methods. Furthermore, beryllium oxide is a highly toxic compound, posing extremely high safety risks when performing destructive failure analysis.

[0030] Therefore, it is necessary to provide a diagnostic method that can pinpoint the cause of failure in TO-254 or similar packaged products without relying on visual analysis techniques or destructive analysis methods.

[0031] To address the problems of existing technologies, embodiments of this application provide a method for diagnosing failures in semiconductor devices, which can achieve lossless failure location of semiconductor devices and further clarify the failure type without relying on visual analysis technology.

[0032] The failure diagnosis method for semiconductor devices provided in the embodiments of this application will be described below.

[0033] Please see Figures 1 to 5 This application provides a method for diagnosing failures in semiconductor devices, the method comprising: S100, Electrical Parameter Acquisition: Acquire the electrical parameters of the semiconductor device under test under the first electrical performance test conditions.

[0034] For example, the electrical performance of the semiconductor device under test is determined to be up to standard by judging whether the electrical parameters of the semiconductor device under test under the first electrical performance test condition meet the second preset condition.

[0035] S200. Acquisition of thermal resistance parameters: Obtain the first thermal performance function curve of the semiconductor device under test under the first temperature condition and the second thermal performance function curve of the standard semiconductor device under the first temperature condition. Based on the first thermal performance function curve and the second thermal performance function curve, obtain the thermal resistance parameters of the semiconductor device under test under the first temperature condition.

[0036] Among them, standard semiconductor devices refer to semiconductor devices with the same specifications as the semiconductor device under test and known to be defect-free.

[0037] For example, the thermal resistance parameter of the semiconductor device under test under the first temperature condition is determined by comparing the fitting of the first thermal performance function curve of the semiconductor device under test under the first temperature condition with the second thermal performance function curve of the standard semiconductor device under the first temperature condition.

[0038] S300 Failure Information Diagnosis: Based on electrical and thermal resistance parameters, diagnose the failure information of the semiconductor device under test.

[0039] For example, when the thermal resistance parameter and the electrical parameter respectively meet the first preset condition and the second preset condition, the failure type of the semiconductor device under test is determined. The first preset condition and the second preset condition can be relatively independent, or they can be mutually referenced.

[0040] Specifically, the S300 includes: S310. Obtain primary failure information of the semiconductor device under test based on either the electrical parameters or the thermal resistance parameters. S320. Based on the primary failure information and either the electrical parameter or the thermal resistance parameter, diagnose the failure information of the semiconductor device under test.

[0041] The failure diagnosis method of this application uses either electrical parameters or thermal resistance parameters to determine the primary failure information of the semiconductor device under test (DUT). This primary failure information can narrow down the possible causes of failure in the DUT. The other parameter, either electrical or thermal resistance, is then used to further clarify the cause of failure within that range. Step S300 provides a two-level failure information diagnosis method for the DUT, which helps to improve the accuracy and efficiency of the failure diagnosis operation.

[0042] Optionally, step S100 is executed before step S200, or step S200 is executed before step S100. This application embodiment uses non-destructive testing to obtain the electrical and thermal resistance parameters of the semiconductor device under test, where the completion of one test does not affect the performance of the other test. Therefore, this application embodiment does not specifically limit the execution order between steps S100 and S200.

[0043] According to the failure diagnosis method for semiconductor devices provided in this application, the electrical parameters and thermal resistance parameters of the semiconductor device under test are obtained through non-destructive experimental means. The electrical parameters and thermal resistance parameters are then combined to determine whether the semiconductor device under test has failed and further determine the cause of failure. This enables failure analysis of the semiconductor device under test without relying on visual analysis technology. It is particularly helpful for failure diagnosis of TO-254 or similar packaged products that are not suitable for destructive methods and cannot achieve accurate failure analysis through visual analysis technology.

[0044] According to some embodiments of the first aspect of this application, the failure diagnosis method further includes: S010. Perform static testing on the target semiconductor device to obtain its static parameters.

[0045] Optionally, in step S010, the target semiconductor device is subjected to static testing under DC steady-state conditions to obtain the static parameters of the target semiconductor device.

[0046] For example, static parameters include at least one of drain-source leakage current, gate-source leakage current, threshold voltage, on-resistance, source-drain diode forward voltage drop, breakdown voltage, and transconductance.

[0047] S020. When the static parameters of the target semiconductor device meet the third preset condition, the target semiconductor device is determined to be the semiconductor device under test.

[0048] Optionally, in step S020, the static parameters of the target semiconductor device satisfying the third preset condition means that the static parameters of the target semiconductor device are normal.

[0049] For example, the third preset condition is that the static parameter is less than a preset threshold.

[0050] When the static parameters of the target semiconductor device meet the third preset condition, the target semiconductor device is determined to be the semiconductor device under test, and step S100 or S200 is further executed to obtain electrical parameters or thermal resistance parameters; when the static parameters of the target semiconductor device do not meet the third preset condition, the defect type is determined according to the static parameters of the target semiconductor device.

[0051] Optionally, determining the defect type based on the static parameters of the target semiconductor device includes determining at least one of the defect location and the defect cause based on the static parameters of the target semiconductor device.

[0052] For example, the static parameters include at least one of gate-source leakage current and drain-source leakage current. When the gate-source leakage current or drain-source leakage current is greater than a preset threshold, it is determined that the gate oxide layer of the target semiconductor device is damaged.

[0053] For example, the static parameters include at least one of the on-resistance and the forward voltage drop of the source-drain diode. When the on-resistance or the forward voltage drop of the source-drain diode is greater than a preset threshold, the failure location of the target semiconductor device is determined to be the bonding process structure.

[0054] For example, static parameters include breakdown voltage. When the breakdown voltage is greater than a preset threshold, the failure location of the target semiconductor device is determined to be the bonding process structure, the chip termination region, or an assembly error of the target semiconductor device.

[0055] Therefore, by performing static testing before obtaining electrical and thermal resistance parameters, some causes of failure can be eliminated, the number of semiconductor devices tested in a batch can be reduced, and the possibility of failure causes can be further reduced.

[0056] According to some embodiments of the first aspect of this application, step S100 includes: S110. Provide a test voltage of not less than 500V between the drain of the semiconductor device under test and the package. S120. After a first time interval, acquire the first electrical parameters of the semiconductor device under test.

[0057] Optionally, in step S110, the test voltage is 500V, and the allowable error is ±5%.

[0058] Optionally, in step S100, the first electrical performance test conditions include an ambient temperature of 25℃±5℃ and a relative humidity of 40%~60%.

[0059] Optionally, before performing step S110, the drain and case of the semiconductor device under test should be cleaned to reduce contact resistance.

[0060] Optionally, step S110 includes: S111. Connect the positive terminal of the high voltage tester to the drain of the semiconductor device under test and the negative terminal to the metal casing of the semiconductor device under test, wherein the metal casing and the negative terminal of the high voltage tester are kept in good contact through a special clamp. S112. After shorting the gate and source of the semiconductor device under test, turn on the high voltage tester.

[0061] Optionally, in step S120, the first duration is 5 seconds, and after turning on the high voltage tester, the first electrical parameters of the semiconductor under test are obtained after waiting for at least 5 seconds.

[0062] Optionally, in step S120, the first electrical parameter of the semiconductor device under test is read at each first time interval. If the first electrical parameter in the preceding sequence is the same as the first electrical parameter in the following sequence or the difference is less than a preset threshold, the first electrical parameter of the semiconductor device under test is determined.

[0063] Optionally, in step S120, the first electrical parameter includes at least one of the current value and the resistance value.

[0064] Optionally, in step S120, the first electrical parameter includes the conductivity value.

[0065] Therefore, a high-voltage environment is provided between the drain and the package of the semiconductor device under test, and the insulation performance of the semiconductor device under test under the high-voltage environment is used to determine whether there is a leakage defect.

[0066] It is understandable that the first thermal performance function curve and the second thermal performance function curve are of the same type, that is, the scale and units of their horizontal and vertical axes are exactly the same, so that the first thermal performance function curve and the second thermal performance function curve can intuitively reflect the difference between the thermal performance of the semiconductor device under test and the thermal performance of the standard semiconductor device through curve comparison.

[0067] According to some embodiments of the first aspect of this application, in step S200, both the first thermal performance function curve and the second thermal performance function curve are integral structure function curves.

[0068] Specifically, the horizontal axis of the integral structure function curve represents the cumulative thermal resistance inside the semiconductor device under test (SDD) from the chip junction to the current location, while the vertical axis represents the cumulative heat capacity inside the SDD from the chip junction to the current location. Each inflection or plateau of the integral structure function curve can be considered as a layer of physical structure along the heat flow path inside the SDD. Based on this, by comparing the first thermal performance function curve and the second thermal performance function curve, the presence of layered structures with defects such as cracks or voids in the SDD can be visually observed, thus enabling the determination of the failure location of the SDD.

[0069] According to some other embodiments of the first aspect of this application, in step S200, both the first thermal performance function curve and the second thermal performance function curve are differential structure function curves.

[0070] Specifically, the differential structure function curve has thermal resistance on the horizontal axis and the derivative of thermal capacity with respect to thermal resistance on the vertical axis. Each peak on the differential structure function curve corresponds to an interlayer interface encountered by heat propagation along its path. Based on this, by identifying the position and width of each peak on the horizontal axis, the ability of the corresponding layer structure to impede heat flow can be roughly determined. By comparing the peak patterns of the first and second thermal performance function curves, the failure location of the semiconductor device under test can be determined.

[0071] According to some other embodiments of the first aspect of this application, in step S200, both the first thermal performance function curve and the second thermal performance function curve are transient thermal impedance curves.

[0072] Specifically, for semiconductor devices under test with layered packaged structures, the transient thermal impedance curve can be transformed into a differential structure function curve or an integral structure function curve after deconvolution and other calculations. The differential structure function curve or integral structure function curve can intuitively show the thermal resistance difference between the semiconductor device under test and the standard semiconductor device at different layer structures based on the graphical differences, thereby obtaining the thermal resistance parameters of the semiconductor device under test and determining the failure location of the semiconductor device under test.

[0073] According to some embodiments of the first aspect of this application, step S300 includes: S310A: Obtain primary failure information of the semiconductor device under test based on whether the thermal resistance parameter of the semiconductor device under test meets the first preset condition.

[0074] Optionally, in step S310A, the primary failure information includes the failure location.

[0075] Optionally, in step S310A, the primary failure information includes whether there is a defect in the semiconductor device under test at a specified location.

[0076] For example, the thermal resistance parameter is the thermal resistance value of the semiconductor device under test at a specified location, determined based on the thermal performance function curve.

[0077] For example, when the thermal resistance parameter of the semiconductor device under test meets the first preset condition, it is determined that the semiconductor device under test is damaged at a specified location; when the thermal resistance parameter of the semiconductor device under test does not meet the first preset condition, it is determined that the semiconductor device under test is defect-free at a specified location.

[0078] According to some embodiments of the first aspect of this application, the semiconductor device under test includes an insulating and thermally conductive layer, and step S310A includes: S311A If the thermal resistance parameter of the semiconductor device under test meets the first preset condition, then the failure location of the semiconductor device under test is determined to be the insulating thermally conductive layer.

[0079] For example, the first preset condition includes a first preset condition A and a first preset condition B. When the thermal resistance parameter of the semiconductor device under test simultaneously meets both the first preset condition A and the first preset condition B, the failure location of the semiconductor device under test is determined to be the insulating thermally conductive layer. The first preset condition A includes that the steady-state thermal resistance value of the semiconductor device under test is greater than that of the standard semiconductor device.

[0080] In one example, the first preset condition also includes that the difference between the steady-state thermal resistance of the semiconductor device under test and the steady-state thermal resistance of the standard semiconductor device is greater than a preset value, so as to exclude device error or calculation error.

[0081] According to some embodiments of the first aspect of this application, the steady-state thermal resistance value is calculated by the following formula:

[0082] In the formula, Junction temperature of semiconductor devices This refers to the case temperature of a semiconductor device. This is the drain voltage of the semiconductor device under the first temperature condition. This refers to the drain current of the semiconductor device under the first temperature condition. This refers to the temperature-sensitive parameter coefficient of a semiconductor device. This refers to the source-drain voltage of a semiconductor device. This is the offset for thermal testing calibration.

[0083] For example, the first preset condition includes that the length of the flat segment in the integral structure function curve of the semiconductor device under test is greater than the length of the flat segment in the integral structure function curve of the standard semiconductor device.

[0084] Specifically, taking a VDMOS device in a TO-254 package as an example, the insulating thermal conductive layer has a transition plate and an alloy frame on both sides. The thermal conductivity of the insulating thermal conductive layer is significantly better than that of the transition plate and the alloy frame. Therefore, in the integral structure function, it is represented by a flat segment in the middle of two curves with large slopes. The length of this flat segment can be used to characterize the equivalent thermal resistance of the insulating thermal conductive layer in the VDMOS device.

[0085] For example, please refer to Figure 6For ease of observation, arrows indicate the flat sections corresponding to the insulating and thermally conductive layers. The curve on the right is the integral structure function curve of the semiconductor device under test, and the curve on the left is the integral structure function curve of the standard semiconductor device. Observing the lengths of the two arrows, it is easy to see that the equivalent thermal resistance of the semiconductor device under test in the insulating and thermally conductive layer is greater than that of the standard semiconductor device in the insulating and thermally conductive layer, that is, the semiconductor device under test meets the first preset condition.

[0086] When the thermal resistance parameters of the semiconductor device under test simultaneously meet both the first preset condition A and the first preset condition B, that is, the steady-state thermal resistance of the semiconductor device under test and the thermal resistance of the internal insulating thermal conductive layer are both greater than those of the standard semiconductor device, the failure location of the semiconductor device under test is determined to be the insulating thermal conductive layer.

[0087] According to some embodiments of the first aspect of this application, the failure diagnosis method further includes: S301. In a no-power-out state, the semiconductor device under test is placed under different temperature conditions and the source-drain forward voltage drop is measured respectively. The temperature sensitivity parameter coefficient of the semiconductor device under test is obtained based on the slope of the curve formed by fitting the source-drain forward voltage drop of the semiconductor device under test under different temperature conditions.

[0088] Optionally, step S301 further includes: The thermal test calibration offset is obtained by fitting the curves formed by the source and drain forward voltage drops of the semiconductor device under test under different temperature conditions.

[0089] According to some embodiments of the first aspect of this application, step S300 further includes: S320A. Determine the failure type information of the semiconductor device under test based on whether the primary failure information and the electrical parameters of the semiconductor device under test meet the second preset conditions.

[0090] Optionally, step S320A includes: S321A. When the failure location of the semiconductor device under test is the insulating and thermally conductive layer, if the electrical parameters meet the second preset condition, the semiconductor device under test is determined to be of the first defect type; if the electrical parameters do not meet the second preset condition, the semiconductor device under test is determined to be of the second defect type.

[0091] Optionally, the first defect type is a through defect, and the second defect type is a non-through defect.

[0092] Optionally, in step S321A, the second preset condition is that the electrical parameter is less than or equal to the second verification value, and the electrical parameter includes the resistance value.

[0093] Alternatively, the second verification value is 100 MΩ.

[0094] For example, when the failure location of the semiconductor device under test is the insulating and thermally conductive layer, if the resistance value of the semiconductor device under test is greater than the second verification value, it is determined that the semiconductor device under test has a non-through defect in the insulating and thermally conductive layer; if the resistance value of the semiconductor device under test is less than or equal to the second verification value, it is determined that the semiconductor device under test has a through defect in the insulating and thermally conductive layer.

[0095] Non-penetrating defects include microcracks.

[0096] Optionally, in step S321A, the second preset condition is that the electrical parameter is greater than or equal to the third verification value, and the electrical parameter includes at least one of the current value and the conductance value.

[0097] By determining whether the defects inside the semiconductor device under test are through defects, it is possible to classify the defects of the semiconductor device under test, which helps in the subsequent classification of the product or the adjustment and improvement of process parameters.

[0098] Optionally, step S320A further includes: S322A: If the insulating and thermally conductive layer of the semiconductor device under test is not in failure, and the electrical parameters of the semiconductor device under test meet the fourth preset condition, the semiconductor device under test is determined to be qualified; if the electrical parameters of the semiconductor device under test do not meet the fourth preset condition, the semiconductor device under test is determined to have a packaging failure.

[0099] Optionally, in step S322A, the fourth preset condition is that the electrical parameter is greater than the third verification value, and the electrical parameter includes the resistance value.

[0100] Alternatively, the third verification value is 100 MΩ.

[0101] Optionally, in step S322A, the fourth preset condition is that the electrical parameter is less than the third verification value, and the electrical parameter includes at least one of the current value and the conductance value.

[0102] For example, encapsulation failure includes at least one of surface contamination and abnormality of the insulator between the electrode leads and the housing.

[0103] According to some embodiments of the first aspect of this application, step S300 includes: S310B: Based on whether the electrical parameters of the semiconductor device under test meet the fifth preset condition, obtain the primary failure information of the semiconductor device under test. S320B: Based on the primary failure information and whether the thermal resistance parameters of the semiconductor device under test meet the first preset condition, determine the failure type information of the semiconductor device under test.

[0104] Specifically, the fifth preset condition is that the impedance between the drain and the package of the semiconductor device under test is less than the impedance between the drain and the package of the standard semiconductor device.

[0105] For example, when the impedance between the drain and the package of the semiconductor device under test is less than that between the drain and the package of a standard semiconductor device, the insulation performance of the semiconductor device under test is determined to be abnormal; when the impedance between the drain and the package of the semiconductor device under test is greater than or equal to that between the drain and the package of a standard semiconductor device, the insulation performance of the semiconductor device under test is determined to be normal.

[0106] Further optionally, step S320B includes: S321B. When the insulation performance of the semiconductor device under test is abnormal, if the thermal resistance parameter of the semiconductor device under test meets the first preset condition, it is determined that there is a through-hole defect in the insulating thermal conductive layer of the semiconductor device under test; if the thermal resistance parameter of the semiconductor device under test does not meet the first preset condition, it is determined that there is a packaging failure in other locations of the semiconductor device under test besides the insulating thermal conductive layer.

[0107] For example, in step S321B, the encapsulation failure includes at least one of surface contamination and abnormality of the insulator between the electrode lead and the housing.

[0108] Further optionally, step S320B includes: S322B: When the insulation performance of the semiconductor device under test is normal, if the thermal resistance parameter of the semiconductor device under test meets the first preset condition, it is determined that there is a non-penetrating defect in the insulating thermal conductive layer of the semiconductor device under test; if the thermal resistance parameter of the semiconductor device under test does not meet the first preset condition, it is determined that the semiconductor device under test is qualified.

[0109] Optionally, in step S322B, non-penetrating defects include microcracks or other early mechanical damage.

[0110] According to some embodiments of the first aspect of this application, the failure diagnosis method further includes: S101. Determine the second verification value based on the electrical parameters of the standard semiconductor device under the first electrical performance test conditions.

[0111] Understandably, the second verification value has the same unit as the first electrical parameter so that the defect level of the semiconductor device under test can be intuitively understood compared to a standard semiconductor device by comparing the first electrical parameter with the second verification value. Optionally, the second verification value includes at least one of resistance, conductance, and current values.

[0112] For example, the second verification value is determined based on the measurement value of a standard semiconductor device after it has been stabilized under a 500V DC high voltage environment.

[0113] According to some embodiments of the first aspect of this application, the failure diagnosis method further includes: S102. Calculate and determine the second verification value based on the structure and material parameters of the semiconductor device under test.

[0114] Furthermore, in conjunction with the semiconductor device failure diagnosis methods in the above embodiments, this application embodiment can provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when these computer program instructions are executed by a processor, they implement any of the semiconductor device failure diagnosis methods in the above embodiments.

[0115] This application also provides a computer program product, including a computer program, which, when executed, implements any of the semiconductor device failure diagnosis methods described in the above embodiments.

[0116] The above are merely specific embodiments of this disclosure, enabling those skilled in the art to understand or implement this disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to these embodiments, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for diagnosing failures in a semiconductor device, characterized in that, include: Electrical parameter acquisition: Acquire the electrical parameters of the semiconductor device under test under the first electrical performance test conditions; Thermal resistance parameter acquisition: Obtain the first thermal performance function curve of the semiconductor device under test under the first temperature condition and the second thermal performance function curve of the standard semiconductor device under the first temperature condition. Based on the first thermal performance function curve and the second thermal performance function curve, obtain the thermal resistance parameter of the semiconductor device under test under the first temperature condition. Failure Information Diagnosis: Based on one of the electrical parameters and the thermal resistance parameters, the primary failure information of the semiconductor device under test is obtained; based on the primary failure information and the other of the electrical parameters and the thermal resistance parameters, the failure information of the semiconductor device under test is diagnosed.

2. The failure diagnosis method for semiconductor devices according to claim 1, characterized in that, The failure information diagnosis includes: Based on whether the thermal resistance parameter of the semiconductor device under test meets the first preset condition, the primary failure information of the semiconductor device under test is obtained. The failure type information of the semiconductor device under test is determined based on whether the primary failure information and the electrical parameters of the semiconductor device under test meet the second preset condition.

3. The failure diagnosis method for semiconductor devices according to claim 2, characterized in that, The semiconductor device under test includes an insulating and thermally conductive layer. The step of obtaining primary failure information of the semiconductor device under test based on whether its thermal resistance parameter meets a first preset condition includes: If the thermal resistance parameter of the semiconductor device under test meets the first preset condition, then the failure location of the semiconductor device under test is determined to be the insulating thermally conductive layer. The first preset condition includes a first A preset condition, which includes that the steady-state thermal resistance of the semiconductor device under test is greater than the steady-state thermal resistance of the standard semiconductor device.

4. The failure diagnosis method for semiconductor devices according to claim 3, characterized in that, The steady-state thermal resistance value is calculated by the following formula: ， In the formula, Junction temperature of semiconductor devices This refers to the case temperature of a semiconductor device. This is the drain voltage of the semiconductor device under the first temperature condition. This refers to the drain current of the semiconductor device under the first temperature condition. This refers to the temperature-sensitive parameter coefficient of a semiconductor device. This refers to the source-drain voltage of a semiconductor device. This is the offset for thermal testing calibration.

5. The failure diagnosis method for semiconductor devices according to claim 4, characterized in that, The failure diagnosis method further includes: In a no-power state, the semiconductor device under test is placed under different temperature conditions and the source-drain forward voltage drop is measured respectively. The temperature sensitivity parameter coefficient of the semiconductor device under test is obtained based on the slope of the curve formed by fitting the source-drain forward voltage drop of the semiconductor device under different temperature conditions.

6. The failure diagnosis method for semiconductor devices according to claim 3, characterized in that, Both the first thermal performance function curve and the second thermal performance function curve are integral structure function curves. The first preset condition also includes a first preset condition B, which includes that the length of the flat segment of the first thermal performance function curve is greater than the length of the flat segment of the second thermal performance function curve.

7. The failure diagnosis method for semiconductor devices according to claim 3, characterized in that, The step of determining the failure type information of the semiconductor device under test based on whether the primary failure information and the electrical parameters of the semiconductor device under test meet the second preset condition includes: When the failure location of the semiconductor device under test is the insulating and thermally conductive layer, if the electrical parameters meet the second preset condition, the semiconductor device under test is determined to be of the first defect type; if the electrical parameters do not meet the second preset condition, the semiconductor device under test is determined to be of the second defect type. Wherein, the electrical parameter includes a resistance value, the second preset condition includes a resistance value less than or equal to a second verification value, and / or, the electrical parameter includes at least one of a current value and a conductance value, and the second preset condition includes an electrical parameter greater than or equal to a third verification value.

8. The failure diagnosis method for semiconductor devices according to claim 7, characterized in that, The failure diagnosis method further includes: The second verification value is determined based on the electrical parameters of the standard semiconductor device under the first electrical performance test conditions.

9. The failure diagnosis method for semiconductor devices according to claim 1, characterized in that, The acquisition of the electrical parameters includes: A test voltage of not less than 500V is provided between the drain of the semiconductor device under test and the package. After a first time interval, the first electrical parameters of the semiconductor device under test are obtained.

10. The failure diagnosis method for semiconductor devices according to claim 1, characterized in that, The failure diagnosis method further includes: Perform static testing on the target semiconductor device to obtain its static parameters; When the static parameters of the target semiconductor device meet the third preset condition, the target semiconductor device is determined to be the semiconductor device under test.

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