A MEMS micromirror chip structure and a preparation method thereof

Abstract

The application discloses a MEMS micromirror chip structure and a preparation method thereof, and belongs to the technical field of micro-mechanical electronics. The chip is bonded and integrated by a device mirror surface, an upper comb layer, a substrate lower comb and a TSV layer two-layer structure wafer. The upper and lower silicon surfaces are vertically connected by locally etching an SOI wafer buried oxygen layer and in-situ epitaxial doping polysilicon, so that the bonding surface flatness out-of-tolerance problem caused by the traditional TSV filling process is avoided. Meanwhile, a gradient thickness silicon oxide dielectric layer is prepared in the annular deep hole, the weak area of the deep groove bottom is reinforced, and the isolation structure is formed by cooperating with the multi-layer LPCVD polysilicon filling, so that the TSV structure and the lower comb structure are integrated. The application solves the technical defects of low bonding reliability, poor voltage resistance and small driving rotation angle of the traditional TSV type micromirror chip, can effectively improve the device driving voltage by more than 30% and the rotation angle by more than 50%, has the advantages of low structural stress, high stability, strong process compatibility, low mass production cost, is suitable for high-end optical MEMS application scenes such as laser radar, optical communication and projection display, and has a wide industrialization prospect.

Description

Technical Field

[0001] This invention belongs to the field of microelectromechanical technology, specifically relating to a MEMS micromirror chip structure and its fabrication method. Background Technology

[0002] Optical MEMS devices are micro-nano integrated devices that integrate miniature optical elements and MEMS actuators. They mainly include MEMS micro mirrors, optical switches, micromirror arrays, etc. With the advantages of miniaturization, low power consumption and high integration, they have broad market application prospects in fields such as lidar, optical communication, projection display, and medical imaging.

[0003] Existing MEMS micromirror chips mostly employ traditional TSV (Through Silicon Via) structures. Their fabrication process relies on an SOI wafer substrate, achieving vertical connectivity through deep silicon etching followed by filling with polysilicon or metal materials. Furthermore, the top silicon layer of the SOI wafer must be removed, and integration is achieved through silicon-silicon bonding between the TSV layer and the structural layer. However, this structure has significant technical drawbacks: silicon-silicon bonding demands stringent flatness requirements on the bonding surface, needing to be less than 1 nm. Traditional TSV structures, due to polysilicon or metal filling processes, result in TSV layer interface flatness exceeding 5 nm, failing to meet high-precision bonding requirements. This directly degrades the bonding quality between the TSV layer and the structural layer, significantly reducing device reliability.

[0004] Meanwhile, the dielectric layer thickness of traditional TSV isolation trenches is uniform. Due to the undercut effect of deep silicon etching process, the bottom of the deep trench becomes a weak area in the device's voltage resistance, which greatly limits the driving voltage and rotation angle of the micromirror chip, resulting in poor device driving performance and insufficient operating stability, making it difficult to meet the needs of high-end precision optical equipment.

[0005] Based on this, this invention relies on mature MEMS micro-nano fabrication technology to design a novel MEMS micromirror chip structure and its fabrication method. It uses only two SOI wafers to complete the fabrication. Through structural and process optimization, it solves the problems of low bonding reliability, poor voltage resistance and insufficient driving performance of traditional TSV structures, and has the technical advantages of low cost, high reliability and high performance. Summary of the Invention

[0006] The purpose of this invention is to address the shortcomings of existing technologies by providing a MEMS micromirror chip structure and its fabrication method. Based on achieving vertical conduction between the upper and lower electrodes of the chip substrate, this invention constructs an integrated micromirror architecture with low stress, high voltage resistance, low cost, and high reliability, effectively improving device driving performance and structural stability.

[0007] To achieve the above technical objectives, the present invention adopts the following technical solution: I. This invention provides a MEMS micromirror chip structure, comprising a comb layer on the mirror surface and a comb layer under the substrate: A cavity is provided at the center of the top silicon layer of the substrate comb layer, and lower comb structures are provided on both sides of the cavity. An epitaxial polycrystalline silicon TSV structure is formed on the outer side of the top silicon layer of the substrate comb layer. The substrate silicon of the substrate comb layer has a TSV isolation ring that penetrates the substrate silicon. The TSV isolation ring is composed of two annular deep holes that penetrate the substrate silicon. Each annular deep hole is filled with an insulating dielectric layer. The space between the two annular deep holes is first etched and then filled with polycrystalline silicon. The substrate silicon inside the TSV isolation ring forms a silicon conductive pillar. The epitaxial polycrystalline silicon TSV structure is connected to the silicon conductive pillar. A metal electrode connected to the silicon conductive pillar is provided on the bottom surface of the substrate silicon of the substrate comb layer. The device has an optical metal mirror and an upper comb structure on the top silicon layer of the comb tooth layer, which are corresponding to the cavity. The upper comb tooth structure and the lower comb tooth structure are arranged alternately. The comb layer on the mirror surface and the comb layer under the substrate are bonded together by a wafer bonding process to achieve vertical conduction and electrostatic drive functions of the device.

[0008] Based on the above technical solutions, the following further technical solutions are proposed: The insulating dielectric layer filled with the annular deep hole is a gradient thickness silicon oxide dielectric layer, which adopts a gradient structure that is thicker at the top and thinner at the bottom, to reinforce the weak area at the bottom of the trench formed by the deep silicon etching undercut effect.

[0009] The annular deep holes are formed by LPCVD polycrystalline silicon layer filling, with the polycrystalline silicon interface height being lower than the oxide layer interface, thus forming an insulating and isolation structure.

[0010] The lower comb tooth structure is a stepped comb tooth structure, with a gap between the stepped comb tooth structure and the top silicon layer, so that the outer upper comb tooth fits into the gap.

[0011] The core innovative principle of this invention for a MEMS micromirror chip structure is as follows: This invention abandons the processing logic of traditional TSV structures. It removes the buried oxide layer on the SOI wafer through local etching and directly connects the upper and lower silicon surfaces using in-situ epitaxial growth of doped polysilicon. This completely avoids the bonding surface flatness deviation problem caused by traditional TSV filling processes, significantly improving wafer bonding accuracy and reliability. Simultaneously, a gradient-thickness silicon oxide dielectric layer is prepared inside the annular deep hole, specifically reinforcing the weak voltage withstand area at the bottom of the deep hole, solving the problem of insufficient voltage withstand caused by undercut defects in deep silicon etching. Compared to traditional uniform thickness dielectric layer structures, this invention can increase the micromirror chip driving voltage by 30% and the device rotation angle by more than 50%, significantly optimizing device driving performance. Furthermore, this invention achieves an isolation structure by filling polysilicon with a multi-layer LPCVD process, integrating the traditionally independent TSV layer with the lower comb tooth structure into an integrated architecture of stepped gradient insulating TSV and comb tooth stress coupling, effectively reducing internal device stress and improving overall structural stability.

[0012] II. This invention also provides a method for fabricating a MEMS micromirror chip, comprising the following steps: S1. Fabrication of the under-substrate comb layer (1) Select <100> The first SOI wafer with crystal orientation determines the top silicon thickness based on the device cavity depth and comb structure depth. Blind via patterns are fabricated through photolithography and etching processes. The blind vias are then etched to form the top silicon and buried oxide layer. (2) Using thermal oxidation and in-situ epitaxial growth process, doped polysilicon is filled in the blind hole to form an epitaxial polysilicon TSV structure 1. Then, the excess polysilicon and oxide layer on the surface are removed by CMP chemical mechanical polishing combined with wet etching process to obtain an ultra-flat bonding interface. (3) A stepped lower comb structure 4 is fabricated on the top silicon layer by photolithography and deep silicon etching process, and the cavity 5 of the device is formed simultaneously; (4) Another option <100> The second SOI wafer with crystal orientation is bonded with the prepared under-substrate comb and epitaxial polycrystalline structure with high precision. (5) Two annular deep holes 8a are prepared on the substrate silicon of the lower comb layer by photolithography and etching process. A dielectric layer of gradient thickness is formed on the inner wall of the annular deep holes by oxidation and etching process. A TSV isolation ring 8 is formed by depositing and filling polycrystalline silicon 8b between the two annular deep holes 8a by LPCVD process. A conductive silicon pillar 6 is formed on the substrate silicon between the TSV isolation rings. The epitaxial polycrystalline TSV structure 1 of the upper layer is connected to the conductive silicon pillar. (6) Use CMP polishing and wet etching processes to remove excess polysilicon from the surface, ensuring that the polysilicon interface height is lower than the oxide layer interface; (7) Electrode contact holes are prepared on the bottom surface of the substrate silicon by photolithography and etching processes, and metal thin film is deposited by metal sputtering process to pattern metal electrode 7 connected to conductive silicon pillar 6.

[0013] S2, Fabrication of the device mirror surface and upper comb layer (1) The second wafer structure after bonding is subjected to back-side thinning to remove the substrate silicon and buried oxide layer on the non-structured surface, and fully expose the top silicon of the device layer. (2) A high-reflectivity metal thin film is deposited on the top silicon surface using a metal sputtering process, and patterned by photolithography and wet etching processes, and an optical metal mirror 3 is prepared at the center of the top silicon surface; (3) The comb structure 2 is prepared on the top silicon layer by photolithography and deep reactive ion etching process to form a movable micromirror driving structure and complete the overall chip fabrication.

[0014] Furthermore, the gradient thickness dielectric layer inside the annular deep hole 8a is prepared using a partitioned oxidation and selective gradient etching process to achieve a gradual change in the thickness of the oxide layer on the inner wall of the deep hole, thereby enhancing the pressure resistance of the bottom of the trench. Beneficial effects of the present invention Compared with the prior art, the present invention has the following significant technical advantages: 1. High bonding reliability: The process of local etching of buried oxide layer and in-situ epitaxial doping of polysilicon to connect the upper and lower silicon surfaces replaces the traditional TSV filling structure, completely solving the problem of excessive flatness of bonding surface caused by TSV filling, and greatly improving silicon-silicon bonding accuracy and overall structural reliability.

[0015] 2. Excellent driving performance: The innovative gradient thickness silicon oxide dielectric layer structure is used to specifically reinforce the weak voltage-resistant area at the bottom of the deep trench, effectively improving the device's voltage resistance, increasing the driving voltage by 30%, and increasing the micromirror rotation angle by more than 50%, thus significantly optimizing the device's optical driving performance.

[0016] 3. Low structural stress and good stability: The TSV structure and the lower comb tooth structure are integrated into one, and a low-stress architecture with stepped gradient insulating TSV and comb tooth stress coupling is constructed, which effectively alleviates the stress concentration problem during device processing and operation and improves the long-term working stability of the device.

[0017] 4. Strong process adaptability and low cost: It only uses two SOI wafers to complete the fabrication, and relies entirely on existing mainstream MEMS micro-nano processing technology. No special equipment or process steps are required. It is compatible with conventional electrostatic comb micromirror mass production system, with low mass production cost and strong industrialization feasibility.

[0018] This invention achieves an integrated design of MEMS micromirror chip with vertical conduction, high voltage resistance, large rotation angle, and high reliability, solving the core pain points of traditional TSV structure micromirror chips, greatly improving the overall performance and application scenario adaptability of micromirror chips, and providing a brand-new technical solution for the industrialization of high-end optical MEMS devices. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a MEMS micromirror chip structure according to the present invention; Figure 2 This is a schematic diagram of the first SOI wafer and the epitaxially grown polyjunction TSV structure used in the chip fabrication process of the present invention. Figure 3 This is a schematic diagram of the stepped lower comb structure fabricated on the top silicon layer of the first SOI wafer in the chip fabrication process of the present invention. Figure 4 This is a schematic diagram of the high-precision wafer bonding between the second SOI wafer and the top silicon layer of the first SOI wafer, as well as the fabrication of the TSV isolation ring, in the chip fabrication process of the present invention. Figure 5 This is a schematic diagram of the structure of the metal electrode fabricated on the first SOI wafer substrate silicon in the chip fabrication process of the present invention. Figure 6 This is a schematic diagram of the structure for fabricating a metal mirror on the top silicon layer of the second SOI wafer in the chip fabrication process of the present invention. Figure 7 This is a schematic diagram of the upper comb teeth fabricated on the top silicon layer of the second SOI wafer in the chip fabrication process of the present invention. Figure 8 This is a schematic diagram of the TSV isolation ring fabricated in the chip fabrication process of the present invention. Detailed Implementation

[0020] The preferred embodiments of the present invention will now be described in detail and in complete form with reference to the accompanying drawings, so that the technical solutions and beneficial effects of the present invention will be clearer and more explicit.

[0021] Example 1, as Figure 1 As shown, the present invention provides a MEMS micromirror chip structure, including a comb layer on the mirror surface and a comb layer under the substrate: The under-substrate comb layer is fabricated from a first SOI wafer, such as Figure 3 As shown, the top silicon layer of the first SOI wafer has a stepped lower comb structure 4 in the middle position. There are gaps X between the top silicon layer and the steps on both sides. A cavity 5 is provided in the middle of the steps. The lower comb structure 4 is provided on both sides of the cavity. An epitaxial polycrystalline silicon TSV structure 1 is formed on the outer side of the top silicon layer of the substrate lower comb layer. The epitaxial polycrystalline silicon TSV structure penetrates the top silicon layer and the buried oxide layer and is connected to the substrate silicon. According to the specific design requirements, the epitaxial polycrystalline silicon TSV structure 1 is symmetrically distributed with respect to the center of the cavity.

[0022] like Figure 1 , Figure 7 and Figure 8As shown, a TSV isolation ring 8 penetrating the substrate silicon is provided on the substrate silicon of the comb layer under the substrate. According to specific design requirements, the isolation rings 8 are symmetrically distributed around the cavity center. Each TSV isolation ring consists of two annular deep holes 8a penetrating the substrate silicon and filled with an insulating dielectric layer. The space between the two annular deep holes 8a is first etched and then filled with polysilicon 8b. The insulating dielectric layer filled by the annular deep holes 8a is a gradient thickness silicon oxide dielectric layer with a gradient structure that is thicker at the top and thinner at the bottom, which is used to reinforce the weak area at the bottom of the trench formed by the deep silicon etching undercut effect. The polysilicon 8b filled between the two annular deep holes is formed by multiple LPCVD polysilicon layer fillings. The height of the polysilicon interface is lower than that of the oxide layer interface, forming an insulating isolation structure. The substrate silicon in the TSV isolation ring 8 forms silicon conductive pillars 6. The epitaxial polysilicon TSV structure 1 is connected to the silicon conductive pillars 6. The bottom surface of the substrate silicon of the comb layer under the substrate is provided with a metal electrode 7 connected to the silicon conductive pillars. The device has an optical metal mirror 3 corresponding to the cavity 5 and an upper comb structure 2 on the top silicon layer of the comb tooth layer. A portion of the upper comb structure 2 and the lower comb structure 4 are staggered, and the outermost upper comb tooth 2 is suspended in the gap below.

[0023] The comb layer on the mirror surface and the comb layer under the substrate are bonded together by a wafer bonding process to achieve vertical conduction and electrostatic drive functions of the device.

[0024] Example 2: This invention provides a method for fabricating a MEMS micromirror chip structure, the specific process flow of which is shown in the figure below: Step 1: Fabrication of the under-substrate comb teeth and TSV layer 1. For example Figure 2 As shown, select <100> The first SOI wafer with crystal orientation is matched with the top silicon thickness according to the cavity depth and comb structure height of the device design to ensure structural dimensional accuracy. 2. For example Figure 3 As shown, the blind hole pattern is defined by photolithography, and the top silicon and buried oxide layer are locally etched by deep silicon etching to expose the blind hole that connects the top silicon and the substrate silicon. High-energy ion implantation is performed on the blind hole to reduce the contact resistance of the subsequent polysilicon and improve the conductivity. 3. After thermal oxidation treatment of the blind via region, doped polysilicon is grown in situ to completely fill the blind via; then CMP polishing process is used to flatten the surface, and wet etching is used to remove the residual polysilicon and oxide layer on the surface to form a high-flatness polysilicon interconnect structure 1. 4. For example Figure 3 As shown, a stepped lower comb structure 4 is formed by photolithography and selective etching processes. Simultaneously, a device cavity 5 is etched in the middle of the step to reserve movement space for the movable structure of the micromirror. 5. For example Figure 4Take another standard one <100> The second SOI wafer with the crystal orientation is precisely aligned and bonded to the first SOI wafer with the prepared underlying structure. 6. For example Figure 4 , Figure 8 As shown, two annular deep holes 8a are fabricated on the substrate silicon of the first SOI wafer by photolithography and deep silicon etching processes. A gradient silicon oxide dielectric layer with a thicker upper layer and a thinner lower layer is formed on the inner wall of the annular deep holes by using partitioned oxidation and gradient etching processes to enhance the withstand voltage performance of the bottom of the hole. Polycrystalline silicon 8b is deposited layer by layer between the two annular deep holes 8a by multiple LPCVD processes to finally form a TSV isolation ring 8. 7. For example Figure 5 As shown, CMP polishing and wet etching processes are used again to repair the surface to ensure that the polysilicon interface is lower than the oxide layer interface, so that the substrate silicon in the TSV isolation ring 8 forms a conductive silicon pillar 6 with excellent insulation and isolation performance. 8. For example Figure 5 As shown, electrode contact holes are prepared by photolithography etching, metal materials are deposited by magnetron sputtering, and metal electrodes 7 are patterned to complete the preparation of the underlying structure.

[0025] Step 2: Fabrication of the device mirror surface and upper comb layer 1. For example Figure 6 As shown, the back side of the bonded second SOI wafer is ground and etched to completely remove the substrate silicon and buried oxide layer on the unstructured surface, exposing the complete top silicon structure of the device layer. 2. A high-reflectivity metal thin film is sputtered in the middle of the top silicon surface, and patterned by photolithography and wet etching processes to prepare a mirror metal with high flatness and excellent reflectivity. 3. For example Figure 7 As shown, the upper comb structure 2 is fabricated using photolithography and deep reactive ion etching processes. Part of the upper comb structure is arranged alternately with the lower comb teeth, and the outer upper comb teeth correspond to and fit with the gap X below. Finally, structure release etching is performed to remove excess sacrificial layer structure, forming a movable micromirror structure, thus completing the overall chip fabrication.

[0026] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made by those skilled in the art to the technical solutions of the present invention within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A MEMS micromirror chip structure, comprising a comb layer on a mirror surface and a comb layer under a substrate, characterized in that: A cavity (5) is provided at the center of the top silicon layer of the substrate comb layer, and a lower comb structure (4) is provided on both sides of the cavity. An epitaxial polycrystalline silicon TSV structure (1) is formed on the outer side of the top silicon layer of the substrate comb layer. The substrate silicon of the substrate comb layer is provided with a TSV isolation ring (8) that penetrates the substrate silicon. The TSV isolation ring is composed of two annular deep holes (8a) that penetrate the substrate silicon. Each annular deep hole is filled with an insulating dielectric layer. Polycrystalline silicon (8b) is filled between the two annular deep holes (8a). The substrate silicon in the TSV isolation ring (8) forms a silicon conductive pillar (6). The epitaxial polycrystalline silicon TSV structure (1) is connected to the silicon conductive pillar. A metal electrode (7) connected to the silicon conductive pillar is provided on the bottom surface of the substrate silicon of the substrate comb layer. The top silicon layer of the comb tooth layer on the mirror surface of the device is provided with a metal mirror (3) corresponding to the cavity (5) and an upper comb tooth structure (2), and the upper comb tooth structure (2) and the lower comb tooth structure (4) are arranged alternately. The comb layer on the mirror surface and the comb layer under the substrate are bonded together by a wafer bonding process to achieve vertical conduction and electrostatic drive functions of the device.

2. The MEMS micromirror chip structure according to claim 1, characterized in that, The insulating dielectric layer filling the annular deep hole (8a) is a gradient thickness silicon oxide dielectric layer with a thicker upper layer and a thinner lower layer, which is used to reinforce the weak area at the bottom of the trench formed by the deep silicon etching undercut effect.

3. The MEMS micromirror chip structure according to claim 1, characterized in that, The annular deep holes (8a) are formed by LPCVD polycrystalline silicon layer filling, and the polycrystalline silicon interface height is lower than the oxide layer interface to form an insulating isolation structure.

4. The MEMS micromirror chip structure according to claim 1, characterized in that, The lower comb tooth structure is a stepped comb tooth structure, and there is a gap between the stepped comb tooth structure and the top silicon layer, so that the outer upper comb tooth (2) fits into the gap.

5. A method for fabricating a MEMS micromirror chip, used to fabricate the MEMS micromirror chip structure according to any one of claims 1-4, characterized in that, Includes the following steps: S1. Fabrication of the under-substrate comb layer (1) Select <100> The first SOI wafer with crystal orientation determines the top silicon thickness based on the device cavity depth and comb structure depth. Blind via patterns are fabricated through photolithography and etching processes. The blind vias are then etched to form the top silicon and buried oxide layer. (2) Using thermal oxidation and in-situ epitaxial growth process, doped polysilicon is filled in the blind hole to form an epitaxial polysilicon TSV structure (1). Then, the excess polysilicon and oxide layer on the surface are removed by CMP chemical mechanical polishing combined with wet etching process to obtain an ultra-flat bonding interface. (3) A stepped lower comb structure is fabricated on the top silicon layer by photolithography and deep silicon etching process (4) and the cavity of the device is formed simultaneously (5). (4) Another option <100> The second SOI wafer with the crystal orientation is bonded to the prepared under-substrate comb layer with high precision. (5) Two annular deep holes (8a) are prepared on the substrate silicon of the lower comb layer by photolithography and etching process. A dielectric layer of gradient thickness is formed on the inner wall of the annular deep holes by oxidation and etching process. A TSV isolation ring (8) is formed by depositing and filling polycrystalline silicon (8b) between the two annular deep holes (8a) by LPCVD process. A conductive silicon pillar (6) is formed on the substrate silicon between the TSV isolation rings. The epitaxial polycrystalline TSV structure (1) of the upper layer is connected to the conductive silicon pillar. (6) Use CMP polishing and wet etching processes to remove excess polysilicon from the surface, ensuring that the polysilicon interface height is lower than the oxide layer interface; (7) Electrode contact holes are prepared on the bottom surface of the substrate silicon by photolithography and etching processes, and metal thin film is deposited by metal sputtering process to pattern the metal electrode (7) connected to the conductive silicon pillar (6). S2, Fabrication of the comb layer on the mirror surface of the device (1) The second wafer structure after bonding is subjected to back-side thinning to remove the non-structured substrate silicon and buried oxide layer, and fully expose the top silicon of the device layer. (2) A high-reflectivity metal thin film is deposited on the top silicon surface using metal sputtering process, and patterned by photolithography and wet etching process. A metal mirror corresponding to the cavity is prepared at the center of the top silicon surface (3). (3) An upper comb structure (2) intersects with the lower comb structure on the top silicon layer by photolithography and deep reactive ion etching process, forming a movable micromirror driving structure and completing the overall chip fabrication.

6. The method for fabricating a MEMS micromirror chip according to claim 5, characterized in that, In step S1, the gradient thickness dielectric layer inside the annular deep hole (8a) is prepared by partitioned oxidation and selective gradient etching processes to achieve a gradual change in the thickness of the oxide layer on the inner wall of the deep hole and enhance the pressure resistance of the bottom of the trench.

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