A digitally controllable eye-crossing adjustment circuit

Abstract

The application relates to a digital-controllable eye-crossing point adjusting circuit, belonging to the field of integrated circuits and optical communication technologies. The circuit comprises a bias voltage generating circuit, a switch selecting circuit and an edge rate adjusting circuit. The bias voltage generating circuit generates a pair of complementary variable bias voltages V REF and V P and V N through a digital-to-analog converter (DAC) to control a reference voltage V P ; the switch selecting circuit converts V N and V P0 into two groups of controlled voltage signals V N0 and V P1 and V N1 and selects one to output; and the edge rate adjusting circuit adopts a differential structure and adjusts the resistance value of an internal voltage-controlled resistor by using the controlled voltage, so that the ratio of the rising time and the falling time of a signal is changed, and the digital adjustment of the eye-crossing point position is realized. The application solves the problem that the traditional common-mode feedback adjustment cannot be digitally controlled and influences the output swing, and has the advantages of high adjustment precision, no influence on the signal amplitude and easy automatic correction.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit and optical communication technology, and specifically relates to a digitally controllable eye diagram crossover adjustment circuit. Background Technology

[0002] Optical fiber communication boasts advantages such as high bandwidth, low loss, and strong anti-interference capabilities, making it a mainstream communication transmission method. In optical communication systems, the eye diagram is a key indicator for observing the integrity of high-speed signal transmission. The eye diagram crossover points reflect the signal's duty cycle and symmetry. Figure 1 The ideal eye diagram for transmitted signals is given. Except for special designs, the crossover point should be located at 50% of the vertical amplitude of the eye diagram. However, in actual design and manufacturing, due to DC offset, impedance mismatch, duty cycle distortion, etc., the eye diagram crossover point may shift upward or downward, resulting in increased eye diagram closure and jitter, ultimately leading to an increase in the system bit error rate.

[0003] To address crossover point offset issues, many designers incorporate crossover point adjustment circuits into optical communication chip designs. A common approach involves using a common-mode feedback loop (CMLU). This method detects the common-mode voltage at the output, compares it to a reference voltage, amplifies the difference using an error amplifier, and then controls the load current of the current-mode logic (CML) circuit to stabilize the crossover point. While this method reduces crossover point offset by stabilizing the common-mode voltage, it lacks the capability for digital automatic adjustment, limiting its application. Furthermore, altering the CML's load current can also affect the system output swing. Summary of the Invention

[0004] The purpose of this invention is to solve the problems existing in the prior art and provide a digitally controllable eye diagram crossover point adjustment circuit to solve the eye diagram crossover point offset caused by output signal duty cycle distortion and other reasons, without affecting the output swing.

[0005] To achieve the above objectives, the technical solution of the present invention is: a digitally controllable eye diagram crossover adjustment circuit, mainly used in the transmit / receive main path of an optical communication chip, comprising a bias voltage generation circuit, a switch selection circuit, and an edge rate adjustment circuit connected in sequence.

[0006] The bias voltage generation circuit is used to receive digital control signals and output a pair of complementary variable bias voltages V. P and V N ;

[0007] The switch selection circuit is used to select the V P and V N Converted into two sets of controlled voltage signals V P0 V N0 and VP1 V N1 And selectively output one set of voltages to the edge rate regulation circuit;

[0008] The edge rate adjustment circuit is used to adjust the rise time and fall time of the input signal according to the received controlled voltage signal, so as to adjust the position of the eye diagram crossover point.

[0009] Furthermore, the bias voltage generating circuit includes V N Bias voltage generation circuit and V P Bias voltage generation circuit;

[0010] The V N The bias voltage generation circuit includes a first current mirror, a first voltage-controlled resistor group, and a first driving transistor. The digital-to-analog converter (DAC) outputs a reference voltage V. REF The current coefficient k flowing through the first current mirror is controlled, thereby adjusting the output bias voltage V. N The size of V, and V N It is positively correlated with k;

[0011] The V P The bias voltage generation circuit includes a second current mirror, a second voltage-controlled resistor group, and a second driver transistor. The V output of the digital-to-analog converter (DAC) is... REF By controlling the current coefficient k flowing through the second current mirror, the output bias voltage V is adjusted. P The size of V, and V P It is negatively correlated with k.

[0012] Furthermore, the V N In the bias voltage generation circuit, MOSFETs M21 and M22, M23 and M24 form a 1:1 common source common gate current mirror; MOSFETs M25, M26, M27 and M28 operate in the deep transistor region as voltage-controlled resistors; MOSFET M29 is the output driver transistor.

[0013] Furthermore, the V P In the bias voltage generation circuit, MOSFETs M34, M35, M36, and M37 and resistor Rb form a low-voltage common-source common-gate current mirror; MOSFETs M30, M31, M32, and M33 operate in the deep linear region and are used as voltage-controlled resistors; MOSFET M38 is the output driver transistor.

[0014] Furthermore, the switch selection circuit is configured as follows:

[0015] When the first set of voltages is output, V P0 = V P V N0 = V N And V P1 VN1 At the default level;

[0016] When the second set of voltages is output, V P1 = V P V N1 = V N And V P0 V N0 At the default level.

[0017] Furthermore, the edge rate adjustment circuit adopts a differential structure, including a P-terminal circuit and an N-terminal circuit;

[0018] Both the P-terminal circuit and the N-terminal circuit include multiple controlled resistors. The resistance value of the controlled resistor changes with the received controlled voltage signal, thereby changing the RC time constant on the signal path.

[0019] Furthermore, the P-terminal circuit includes resistors R1 and R2, the resistance values ​​of which are positively correlated with the controlled voltage; the P-terminal circuit also includes resistors R5 and R6, the resistance values ​​of which are negatively correlated with the controlled voltage.

[0020] The N-terminal circuit includes resistors R3 and R4, whose resistance values ​​are positively correlated with the controlled voltage; the N-terminal circuit also includes resistors R7 and R8, whose resistance values ​​are negatively correlated with the controlled voltage.

[0021] Furthermore, the controlled resistor is implemented by a MOS transistor, wherein the resistor positively correlated with voltage is implemented by a PMOS transistor, and the resistor negatively correlated with voltage is implemented by an NMOS transistor.

[0022] Furthermore, when it is necessary to move the eye diagram intersection point upward, control V P0 and V N0 V remains unchanged N1 Voltage drop, V P1 The voltage is increased to increase the rise time of the P-terminal circuit and the fall time of the N-terminal circuit.

[0023] When the eye diagram crossover point needs to be shifted downwards, control V P1 and V N1 V remains unchanged N0 Voltage drop, V P0 The voltage is increased to increase the fall time of the P-terminal circuit and the rise time of the N-terminal circuit.

[0024] Furthermore, the input and output terminals of the edge rate adjustment circuit are connected to buffers for signal shaping to achieve rail-to-rail output.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] This invention proposes a digitally controllable eye diagram crossover adjustment circuit to solve the problem of eye diagram crossover distortion in optical communication. The core idea is to control the signal rise and fall speed by adjusting the driving capability of the driving transistor, thereby affecting the crossover position. Compared to traditional solutions, this invention does not affect the output swing and achieves multi-level crossover control through a DAC-adjustable bias voltage control circuit. It can be integrated with digital software to achieve automated eye diagram crossover correction. Attached Figure Description

[0027] Figure 1 This is the ideal lower signal eye diagram.

[0028] Figure 2 This is a system structure diagram.

[0029] Figure 3 This is a circuit block diagram of the present invention.

[0030] Figure 4 For V N Bias voltage generation circuit.

[0031] Figure 5 For V P Bias voltage generation circuit.

[0032] Figure 6 This is a circuit for adjusting the edge rate at the P terminal.

[0033] Figure 7 This is an N-terminal edge rate adjustment circuit.

[0034] Figure 8 This is for adjusting the cross-point effect.

[0035] Figure 9 This is a specific example of a P-terminal edge rate adjustment circuit.

[0036] Figure 10 This is a specific example of an N-terminal edge rate adjustment circuit.

[0037] Figure 11 Adjusting the lower eyelid for different settings. Detailed Implementation

[0038] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings.

[0039] This invention provides a digitally controllable eye diagram crossover adjustment circuit, mainly used in the transmit / receive main path of optical communication chips, and its position in the system is as follows: Figure 2 As shown, the circuit's block diagram is as follows: Figure 3 As shown. Different reference voltages V can be achieved by configuring the DAC. REF The setting of this setting affects the V output of the bias voltage generation circuit.P and V N The value of V. P and V N It is a pair of complementary voltage signals, when V P When the value increases, V N The value decreases accordingly; when V N When the value increases, V P The value then decreases. V P and V N Two sets of voltage signals are generated by a switch, where V N0 =V N1 = V N V P0 =V P1 = V P V P0 and V N0 When in effect, V P1 and V N1 At default level; V P1 and V N1 When in effect, V P0 and V N0 At the default level. The edge rate adjustment circuit is used to change the rise and fall rates of the signal, thereby adjusting the position of the eye diagram crossover point. Its edge rate adjustment level is affected by V. P0 V N0 and V P1 V N1 control.

[0040] V N Bias voltage generation circuit such as Figure 4 As shown, the control voltage V used in the output edge rate regulation circuit N The DAC controls the reference voltage V by controlling the proportional current kI. REF This enables digital adjustment; MOSFETs M21~M22 and M23~M24 form a 1:1 common-source cascode current mirror, ensuring that the current flowing through M19~M20, I1=I2=V. X / R=V REF / R=kI; MOSFETs M25~M28 operate in the deep transistor region and are used as voltage-controlled resistors; MOSFETs M21~M22 and M23~M24 form a current mirror with source negative feedback; the width-to-length ratio of M18 and M20 is 1:a; MOSFET M29 is the output driver. According to Figure 4 The bias voltage V can be obtained. N The expression is:

[0041]

[0042] Among them, V N For V NThe output value of the bias voltage generation circuit, where k is a constant variable, V G,N for Figure 4 Up G N The voltage at the node, V GS18 VC is the gate-source voltage of transistor M18, VCC is the power supply voltage, and VS is the gate-source voltage of transistor M18. TH Let be the threshold voltage of the MOSFET, and 'a' be the width-to-length ratio of M20 and M18. Since M18 is an N-type transistor operating in the linear region, (V GS18 -V TH The value is greater than 0, therefore the bias voltage V N The bias voltage V is positively correlated with k. The current coefficient k can be adjusted by digitally adjusting the DAC, thereby achieving the desired bias voltage V. N Control.

[0043] V P Bias voltage generation circuit such as Figure 5 As shown, the core idea is the same as V. N The bias voltage generation circuit is the same, I4=V Y / R=V REF / R=kI; MOSFETs M34~M37 and resistor R b This forms a low-voltage common-source cascode current mirror; MOSFETs M30~M33 operate in the deep linear region and are used as voltage-controlled resistors; MOSFET M38 is the output driver. According to... Figure 5 The bias voltage V can be obtained. P The expression is:

[0044]

[0045] Among them, V P For V P The output value of the bias voltage generation circuit, where k is a constant, V G,P for Figure 5 Up G P The voltage at the node, V GS34 VC is the gate-source voltage of transistor M34, VS is the power supply voltage, and VS is the gate-source voltage of transistor M34. TH Let be the threshold voltage of the MOSFET, and 'a' be the width-to-length ratio of M35 and M34. Since M34 is a P-type transistor operating in the linear region, (V...) GS34 -V TH The value is less than 0, therefore the bias voltage V P It is negatively correlated with k. The current coefficient k can be adjusted by digitally adjusting the DAC, thereby achieving the bias voltage V. P Control.

[0046] The edge rate adjustment circuit adopts a differential structure, and the P-terminal circuit is as follows: Figure 6 As shown, the N-terminal circuit is as follows Figure 7As shown, the input / output terminals are buffers used for signal shaping, enabling rail-to-rail output. Resistors R1~R8 are voltage-controlled resistors, where the resistance values ​​of R1~R4 are positively correlated with the voltage, and the resistance values ​​of R5~R8 are negatively correlated with the voltage. The main difference between the P-terminal and N-terminal circuits lies in the control voltage of R1~R8, where V P0 and V N0 A set of complementary voltage signals, V P1 and V N1 This is another set of complementary voltage signals. Let the swing on the eye diagram be V. top The hem is V-shaped. bottom The signal rise time is t r The descent time is t f The eye diagram crossover point level V is obtained. c Calculation formula:

[0047]

[0048] From the formula, it can be seen that the position of the eye diagram crossover point can be adjusted by controlling the edge rate. The rise and fall times of the signal are related to the load resistances R1~R8 and the parasitic capacitance C. C The product of the two is positively correlated. When the crossover point needs to be moved upward, V is controlled by a switch. P0 and V N0 The voltage remains constant, V N1 As the voltage decreases, the resistance of R5 increases, and V... P1 As the voltage increases, the resistance of R2 increases, causing the rise time of channel P to increase while the fall time remains unchanged, thus shifting the crossover point upwards. Simultaneously, the resistances of R3 and R8 in channel N increase, increasing the fall time while the rise time remains unchanged, also shifting the crossover point upwards. When it is necessary to shift the crossover point downwards, V is controlled by a switch. P1 and V N1 The voltage remains constant, V N0 As the voltage decreases, the resistance of R6 increases, and V P0 As the voltage increases, the resistance of R1 increases, causing the fall time of channel P to increase while the rise time remains unchanged, thus shifting the crossover point downwards. Simultaneously, the resistances of R4 and R7 in channel N increase, increasing the rise time while the fall time remains unchanged, also shifting the crossover point downwards. Therefore, by adjusting the voltage V... P0 V N0 and V P1 V N1 The value of V can affect the rise and fall times, and thus the position of the eye diagram crossover point. Based on the above, (V) is obtained. out,P - V out,N The output of the differential eye diagram is as follows: Figure 8 As shown, V out,P V is the non-inverting output port of the edge rate regulation circuit. out,P This is the inverting output port of the edge rate regulation circuit.

[0049] Implementation examples.

[0050] A digitally controllable eye diagram crossover adjustment circuit, via V N and V P The bias voltage control circuit outputs a pair of digitally adjustable complementary voltages. By controlling the rise and fall times of the edge rate adjustment circuit through the conduction of these complementary voltages at different stages, the crossover point is shifted upwards or downwards. Specifically, a concrete implementation scheme is proposed in the edge rate adjustment circuit section, with the P-channel circuit as follows: Figure 9 As shown, the N-channel circuit is as follows: Figure 10 As shown, PMOS transistors are used to implement voltage-dependent controlled resistors R1~R4, and NMOS transistors are used to implement voltage-dependent controlled resistors R5~R8. In the default state, V... P0 =V P1 =GND,V N1 =V N0 =VCC. When it is necessary to move the crossover point upward, the bias voltage control circuit can be used to make V... P0 and V N0 The voltage remains constant, V N1 Voltage drop, V P1 As voltage increases, the crossover point moves upward; when it's necessary to move the crossover point downward, let V... P1 and V N1 The voltage remains constant, V N0 Voltage drop, V P0 As voltage increases, the crossover point shifts downward.

[0051] This invention is applied to a 10Gbps NRZ optical line terminal (OLT) chip, and uses a 5-bit DAC to achieve the adjustment of the eye diagram crossover point from 0% to 100%. Figure 11 The output signal eye diagrams after adjustment by the present invention are provided at different levels. It can be seen that the crosspoint adjustment function is consistent with the expectation, and the signal amplitude has not changed.

[0052] The above are preferred embodiments of the present invention. Any changes made to the technical solution of the present invention that do not exceed the scope of the technical solution of the present invention shall fall within the protection scope of the present invention.

Claims

1. A digitally controllable eye diagram crossover point adjustment circuit, characterized in that, It includes a bias voltage generation circuit, a switch selection circuit, and an edge rate adjustment circuit connected in sequence. The bias voltage generation circuit is used to receive digital control signals and output a pair of complementary variable bias voltages V. P and V N ; The switch selection circuit is used to select the V P and V N Converted into two sets of controlled voltage signals V P0 V N0 and V P1 V N1 And selectively output one set of voltages to the edge rate regulation circuit; The edge rate adjustment circuit is used to adjust the rise time and fall time of the input signal according to the received controlled voltage signal, so as to adjust the position of the eye diagram crossover point.

2. The digitally controllable eye diagram crossover adjustment circuit according to claim 1, characterized in that, The bias voltage generating circuit includes V N Bias voltage generation circuit and V P Bias voltage generation circuit; The V N The bias voltage generation circuit includes a first current mirror, a first voltage-controlled resistor group, and a first driving transistor. The digital-to-analog converter (DAC) outputs a reference voltage V. REF The current coefficient k flowing through the first current mirror is controlled, thereby adjusting the output bias voltage V. N The size of V, and V N It is positively correlated with k; The V P The bias voltage generation circuit includes a second current mirror, a second voltage-controlled resistor group, and a second driver transistor. The V output of the digital-to-analog converter (DAC) is... REF By controlling the current coefficient k flowing through the second current mirror, the output bias voltage V is adjusted. P The size of V, and V P It is negatively correlated with k.

3. The digitally controllable eye diagram crossover adjustment circuit according to claim 2, characterized in that, The V N In the bias voltage generation circuit, MOSFETs M21 and M22, M23 and M24 form a 1:1 common source common gate current mirror; MOSFETs M25, M26, M27 and M28 operate in the deep transistor region as voltage-controlled resistors; MOSFET M29 is the output driver transistor.

4. The digitally controllable eye diagram crossover adjustment circuit according to claim 2, characterized in that, The V P In the bias voltage generation circuit, MOSFETs M34, M35, M36, and M37 and resistor Rb constitute a low-voltage common-source cascode current mirror. MOSFETs M30, M31, M32, and M33 operate in the deep linear region and are used as voltage-controlled resistors; MOSFET M38 is the output driver transistor.

5. The digitally controllable eye diagram crossover adjustment circuit according to claim 1, characterized in that, The switch selection circuit is configured as follows: When the first set of voltages is output, V P0 = V P V N0 = V N And V P1 V N1 At the default level; When the second set of voltages is output, V P1 = V P V N1 = V N And V P0 V N0 At the default level.

6. The digitally controllable eye diagram crossover adjustment circuit according to claim 1, characterized in that, The edge rate adjustment circuit adopts a differential structure, including a P-terminal circuit and an N-terminal circuit; Both the P-terminal circuit and the N-terminal circuit include multiple controlled resistors. The resistance value of the controlled resistors changes with the received controlled voltage signal, thereby changing the RC time constant on the signal path.

7. The digitally controllable eye diagram crossover adjustment circuit according to claim 6, characterized in that, The P-terminal circuit includes resistors R1 and R2, whose resistance values ​​are positively correlated with the controlled voltage; the P-terminal circuit also includes resistors R5 and R6, whose resistance values ​​are negatively correlated with the controlled voltage. The N-terminal circuit includes resistors R3 and R4, whose resistance values ​​are positively correlated with the controlled voltage; the N-terminal circuit also includes resistors R7 and R8, whose resistance values ​​are negatively correlated with the controlled voltage.

8. The digitally controllable eye diagram crossover adjustment circuit according to claim 7, characterized in that, The controlled resistors are implemented by MOS transistors, wherein the resistors positively correlated with voltage are implemented by PMOS transistors, and the resistors negatively correlated with voltage are implemented by NMOS transistors.

9. A digitally controllable eye diagram crossover adjustment circuit according to claim 6, characterized in that, When the eye diagram intersection point needs to be moved upwards, control V P0 and V N0 V remains unchanged N1 Voltage drop, V P1 The voltage is increased to increase the rise time of the P-terminal circuit and the fall time of the N-terminal circuit. When the eye diagram crossover point needs to be shifted downwards, control V P1 and V N1 V remains unchanged N0 Voltage drop, V P0 The voltage is increased to increase the fall time of the P-terminal circuit and the rise time of the N-terminal circuit.

10. The digitally controllable eye diagram crossover adjustment circuit according to claim 1, characterized in that, The input and output terminals of the edge rate adjustment circuit are connected to buffers for signal shaping to achieve rail-to-rail output.

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