A bus clock dynamic frequency modulation method, device, and SoC chip

Abstract

The present disclosure provides a bus clock dynamic frequency modulation method and device, and a SoC chip. The method is applied to a bus module in a system on chip (SoC), and comprises: monitoring an idle state of the bus; when the bus is in the idle state, incrementing a count value of a counter; generating a signal for adjusting a clock frequency of the bus according to the count value, wherein the clock frequency decreases with the increment of the count value; and when a transmission request is detected, clearing the count value to restore the clock frequency of the bus. The present disclosure can automatically reduce dynamic power consumption when the bus is idle by monitoring the idle state of the bus and gradually reducing the clock frequency by using the counter. Meanwhile, the frequency is restored by clearing the counter immediately when a transmission request is detected, thereby shortening the wake-up delay and ensuring the quick response capability of the bus to the transmission request.

Description

Technical Field

[0001] This disclosure relates to the field of chip design technology, and more specifically, to a method, apparatus, and SoC chip for dynamic frequency modulation of a bus clock. Background Technology

[0002] In a System-on-Chip (SoC) bus subsystem, the bus clock frequency is typically output by a Clock and Reset Generator (CRG) module with a fixed division factor, which remains essentially constant during system operation. Even when the bus is idle, the clock continues to run at full speed, generating dynamic power consumption.

[0003] To reduce power consumption when the bus is idle, some solutions directly turn off the bus clock after detecting that the bus is idle. However, when a new transmission request arrives, it is necessary to wait for the clock to be relocked, resulting in a wake-up delay of tens to hundreds of cycles, which seriously affects the system response performance.

[0004] In summary, existing solutions cannot reduce power consumption during idle periods when the bus clock frequency is fixed; while directly shutting down the clock can reduce power consumption, it results in excessive wake-up latency. Neither approach achieves a balance between reducing idle power consumption and ensuring fast response. Summary of the Invention

[0005] This disclosure provides at least one method, apparatus, and SoC chip for dynamic frequency modulation of bus clock to solve the above-mentioned technical problems.

[0006] In a first aspect, embodiments of this disclosure provide a method for dynamic frequency modulation of a bus clock, applied to a bus module in a System-on-a-Chip (SoC), comprising:

[0007] Monitor the idle status of the bus; When the bus is idle, increment the counter value; Based on the count value, a signal is generated for adjusting the clock frequency of the bus, wherein the clock frequency decreases as the count value increases; When a transmission request is detected on the bus, the counter value is cleared to restore the clock frequency of the bus.

[0008] In one possible implementation, generating the signal for adjusting the clock frequency of the bus includes: The signal carrying the count value is output to the clock reset generator, so that the clock reset generator determines the actual frequency division value based on the count value and outputs the bus clock according to the actual frequency division value.

[0009] In one possible implementation, the method further includes: The increment step size and / or increment rate of the count value are configured via registers.

[0010] In one possible implementation, the count value of the incrementing counter includes: When the bus is idle, the count value is incremented by the incrementing step size and / or the incrementing rate.

[0011] In one possible implementation, the bus is determined to be in an idle state by the following steps: Monitor various status signals of the bus; When all the status signals indicate no transmission activity, the bus is determined to be in an idle state.

[0012] Secondly, this disclosure also provides a method for dynamic frequency modulation of a bus clock, applied to a clock reset generator in a System-on-a-Chip (SoC), wherein the clock reset generator is connected to a bus module, and includes: Receive the signal output by the bus module, the signal carrying a count value for indicating the duration of bus idle time; Determine the actual frequency division value based on the signal; Output the bus clock according to the actual frequency division value.

[0013] In one possible implementation, the count value is obtained by the bus module incrementing it when the bus is in an idle state.

[0014] In one possible implementation, determining the actual frequency division value based on the signal includes: The sum of the base division value and the count value is taken as the actual division value, wherein the base division value is the division coefficient corresponding to the bus under normal operating conditions.

[0015] In one possible implementation, the actual frequency division value has an upper limit value, which does not exceed the sum of the upper limit value and the basic frequency division value.

[0016] In one possible implementation, the method further includes: When the actual frequency division value changes, a Gray code transition method is used or the current frequency division period ends before switching to the changed actual frequency division value.

[0017] Thirdly, this disclosure also provides a bus clock dynamic frequency modulation device, applied to a bus module in a system-on-a-chip (SoC), comprising: A monitoring module is used to monitor the idle status of the bus; A counting module is used to increment the counter value when the bus is idle. A generation module is configured to generate a signal for adjusting the clock frequency of the bus based on the count value, wherein the clock frequency decreases as the count value increases; The reset module is used to reset the count value when a transmission request is detected on the bus, so as to restore the clock frequency of the bus.

[0018] Fourthly, this disclosure also provides a bus clock dynamic frequency modulation device, applied to a clock reset generator in a system-on-a-chip (SoC), wherein the clock reset generator is connected to a bus module and includes: A receiving module is used to receive a signal output by the bus module, the signal carrying a count value for indicating the idle time of the bus; The determining module is used to determine the actual frequency division value based on the signal; The output module is used to output the bus clock according to the actual frequency division value.

[0019] Fifthly, this disclosure also provides a system-on-a-chip (SoC) chip, including: a bus module and a clock reset generator, wherein the bus module includes a bus clock dynamic frequency modulation device as described in the third aspect, and the clock reset generator includes a bus clock dynamic frequency modulation device as described in the fourth aspect.

[0020] In a sixth aspect, this disclosure also provides an electronic device, including: a processor, a memory, and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the memory via the bus, and when the machine-readable instructions are executed by the processor, a bus clock dynamic frequency adjustment method as described in any one of the first aspect and its various embodiments, the second aspect and its various embodiments is performed.

[0021] The aforementioned bus clock dynamic frequency adjustment method, device, and SoC chip, when monitoring that the bus is in an idle state, increment a counter value and dynamically generate a signal to adjust the bus clock frequency based on the count value, wherein the clock frequency decreases as the count value increases. When a transmission request is detected on the bus, the counter value is reset to zero to restore the bus clock frequency. This disclosure, by monitoring the bus idle state and using a counter to gradually reduce the clock frequency, can automatically reduce dynamic power consumption when the bus is idle; simultaneously, by immediately resetting the counter to zero upon detecting a transmission request to restore the frequency, it shortens the wake-up delay and ensures the bus's rapid response capability to transmission requests.

[0022] Other advantages of this disclosure will be explained in more detail in conjunction with the following description and accompanying drawings.

[0023] It should be understood that the above description is merely an overview of the technical solution of this disclosure, so as to provide a general understanding of the technical means of this disclosure and to implement it in accordance with the contents of the specification. In order to make the above and other objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure are illustrated below. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly described below. The accompanying drawings are incorporated in and constitute a part of this specification. These drawings illustrate embodiments conforming to this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure. It should be understood that the drawings only illustrate certain embodiments of this disclosure and should not be considered as a limitation on the scope of protection. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. Furthermore, the same reference numerals denote the same components throughout the drawings. In the drawings: Figure 1 A block diagram of the overall architecture of dynamic frequency modulation of the bus clock provided in an embodiment of this disclosure is shown; Figure 2 A flowchart of a bus clock dynamic frequency modulation method provided in an embodiment of this disclosure is shown; Figure 3 A flowchart of another bus clock dynamic frequency modulation method provided by an embodiment of this disclosure is shown; Figure 4 A schematic diagram of a bus clock dynamic frequency modulation device provided in an embodiment of this disclosure is shown; Figure 5 A schematic diagram of another bus clock dynamic frequency modulation device provided in an embodiment of this disclosure is shown; Figure 6 A schematic diagram of an electronic device provided in an embodiment of the present disclosure is shown. Detailed Implementation

[0025] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0026] In the description of embodiments disclosed herein, it should be understood that terms such as “comprising” or “having” are intended to indicate the presence of the disclosed features, figures, steps, behaviors, components, portions or combinations thereof in this specification, and do not exclude the possibility of the presence of one or more other features, figures, steps, behaviors, components, portions or combinations thereof.

[0027] Unless otherwise stated, " / " means "or". For example, A / B can mean A or B. In this article, "and / or" is merely a way of describing the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A alone, A and B at the same time, and B alone.

[0028] The terms "first," "second," etc., are used only for ease of description to distinguish identical or similar technical features and should not be construed as indicating or implying the relative importance or number of these technical features. Therefore, a feature defined by "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, the term "multiple" means two or more.

[0029] Research has revealed that in traditional SoC clock management, the bus clock is uniformly managed by the CRG module, with a fixed division ratio (DIV) preset during design. The bus clock frequency = source clock frequency / division ratio. This division ratio remains basically unchanged during system operation, or is only subject to limited static adjustments through software register writing.

[0030] However, since the bus frequency is fixed, it cannot be dynamically adjusted according to the actual load, and it still consumes dynamic power consumption at full speed even when idle, so the power optimization effect is limited.

[0031] To alleviate the aforementioned technical issues, some low-power solutions, upon detecting that the bus is idle, directly request the CRG to disable the bus clock to achieve zero dynamic power consumption. After disabling the clock, if a new transmission request arrives, the clock must be woken up first, and the clock must be waited for to stabilize (usually tens to hundreds of cycles) before responding to the request, resulting in a significant wake-up delay.

[0032] To at least partially address one or more of the aforementioned problems and other potential issues, this disclosure provides a bus clock dynamic frequency adjustment method, apparatus, and SoC chip that can reduce the clock frequency during bus idle periods to reduce dynamic power consumption while ensuring a fast response to new transmission requests.

[0033] To clearly illustrate the embodiments of this disclosure, some concepts that may appear in subsequent embodiments will be introduced first.

[0034] Idle state: This refers to the state when there is no transmission activity on the bus. It is determined by monitoring the bus status signals, which include, but are not limited to, the data valid signal and receive ready signal for AXI / Advanced High-performance Bus (AHB) / Advanced Peripheral Bus (APB), etc. When all monitoring signals indicate no transmission activity and no pending commands for a period of time, the bus can be determined to be in an idle state.

[0035] Base division value (div_default): The software-preconfigured division factor, which is the division value used by the bus in normal operating mode (non-idle state). This base division value can be pre-written into the configuration register by the software according to system requirements, serving as the reference for the actual division value.

[0036] Actual frequency division (div_actual): The actual frequency division factor used by the bus, determined by the base frequency division and the counter's count value. The relationship between the frequency division and the operating frequency is: fact = fmax / div_actual, where fmax is the theoretical maximum frequency (i.e., the source clock frequency), and fact is the actual output bus clock frequency. From this relationship, it can be seen that the larger the frequency division, the lower the bus clock frequency; the smaller the frequency division, the higher the bus clock frequency.

[0037] Idle Counter (cnt): This embodiment of the present disclosure adds a counter inside the bus, which is used to increment from 0 when the bus is idle. Its count value serves as the basis for dynamic frequency division. The larger the count value, the longer the bus idle time.

[0038] To facilitate understanding of the bus clock dynamic frequency adjustment method disclosed in this disclosure, the following detailed description of the embodiments is provided in conjunction with the accompanying drawings.

[0039] The bus clock dynamic frequency adjustment method provided in this disclosure can be applied to various electronic devices that include a bus subsystem, such as user equipment (UE), mobile devices, user terminals, personal digital assistants (PDAs), handheld devices, and in-vehicle devices. These electronic devices typically incorporate a System-on-a-Chip (SoC) chip, and the method is applied to the bus module and clock reset generator within the SoC chip. The bus module can be a bus controller or bus interface unit within the SoC chip, and the clock reset generator is a clock management module within the SoC chip. In some possible implementations, this bus clock dynamic frequency adjustment method can be implemented using hardware logic circuits (such as state machines or combinational logic circuits), by the processor calling computer-readable instructions stored in memory, or by a combination of hardware and software.

[0040] The bus clock dynamic frequency adjustment method provided in this disclosure can be applied to SoC bus subsystems. For example... Figure 1 As shown, the system includes a bus module and a CRG module.

[0041] The CRG module provides the bus clock (bus_clk) for the bus module's normal operation. Internally, the bus module contains a monitoring unit and a counter. The monitoring unit monitors the bus for idle time in real time. The counter increments automatically when the monitoring unit detects an idle state; its count value, denoted as cnt, serves as the basis for dynamic frequency division. A larger cnt indicates a longer idle time.

[0042] The bus module transmits the real-time counter value cnt as a dynamic frequency division input signal to the CRG module. The frequency divider inside the CRG module receives the cnt signal and performs real-time frequency division on the bus clock using a frequency division formula, with the frequency gradually decreasing as the idle time increases.

[0043] When the monitoring unit detects that the bus is not idle (i.e., there is service transmission), the counter is reset to zero. Since cnt is reset to zero, the frequency division value is restored to the basic frequency division value, and the bus clock is restored to the normal frequency.

[0044] The following provides a detailed description of the bus clock dynamic frequency adjustment method provided in the embodiments of this disclosure.

[0045] See Figure 2 In the bus clock dynamic frequency adjustment method provided in this embodiment, the execution flow on the bus module side includes the following steps: S101: Monitors the idle status of the bus; S102: Increment the counter value when the bus is idle; S103: Based on the count value, generate a signal for adjusting the clock frequency of the bus, wherein the clock frequency decreases as the count value increases; S104: When a transmission request is detected on the bus, the counter value is cleared to restore the bus clock frequency.

[0046] Here, the bus status signals are monitored in real time to determine whether the bus is currently idle. Specifically, the bus module monitors various bus status signals, including but not limited to the valid / ready handshake signal of the AXI / AHB / APB bus and the outstanding transaction count signal. When all monitoring signals indicate no transmission activity, the bus is determined to be idle; when any monitoring signal indicates transmission activity, the bus is determined to be non-idle.

[0047] When the bus is idle, the bus module controls a counter to start incrementing from 0, and the count value is recorded as cnt. As the bus idle time increases, the count value continues to increase; the longer the idle time, the larger the count value.

[0048] In practical applications, the increment step size and / or increment rate of the count value can be configured via registers. The increment step size determines the amount the count value increases with each increment, while the increment rate determines how many clock cycles it increments (e.g., every N clock cycles). By configuring the increment step size and / or increment rate, a flexible trade-off between power consumption optimization and response speed can be achieved in different application scenarios.

[0049] Here, a signal for adjusting the bus clock frequency is generated based on the count value. In one implementation, the bus module transmits the count value as a dynamic frequency division input signal to the CRG module. After receiving the signal, the CRG module determines the actual frequency division value based on the count value and divides the source clock according to the actual frequency division value to obtain the bus clock frequency.

[0050] In practical applications, the CRG module determines the actual frequency division value based on the count value as follows: div_actual = div_default + cnt, where div_default is the base frequency division value (i.e., the frequency division coefficient corresponding to the bus under normal operating conditions), and cnt is the current count value of the counter. From the relationship between frequency and frequency division value, fact = fmax / div_actual, it can be seen that as cnt increases, div_actual increases, and the bus clock frequency fact gradually decreases.

[0051] This embodiment of the disclosure can also set a preset upper limit value cnt_max for the count value, so that the actual frequency division value does not exceed the sum of the preset upper limit value and the basic frequency division value, i.e., div_actual ≤ cnt_max + div_default. Setting an upper limit value for the count value can avoid excessively large frequency division values ​​and excessively low bus clock frequencies due to excessively long idle time, thereby preventing the bus response delay from exceeding the acceptable range of the system.

[0052] Furthermore, embodiments of this disclosure continuously monitor for transmission requests on the bus. When a transmission request is detected, the bus module immediately clears the counter value cnt to zero. After the counter value is cleared, the actual frequency division value div_actual is restored to the basic frequency division value div_default, and the bus clock frequency is restored to the normal operating frequency.

[0053] Since the embodiments of this disclosure retain the bus clock without shutting it off, the clearing and recovery operations can be completed within the current clock cycle, and the wake-up delay is only 4 to 5 clock switching cycles (nanosecond level), which is far better than the relocking delay of tens to hundreds of cycles in the direct clock shutdown scheme.

[0054] In step S103, the bus module generates the signal for adjusting the bus clock frequency in the following specific way: The bus module uses the count value as the signal content, generates a signal carrying that count value, and outputs this signal to the CRG. Upon receiving this signal, the CRG module determines the actual frequency division value based on the count value carried in the signal, divides the source clock according to the actual frequency division value, and outputs the bus clock at the corresponding frequency. The specific calculation method for the frequency division value will be explained in detail below in conjunction with the CRG-side process.

[0055] In step S102, the count value is incremented as follows: The increment step size and / or increment rate of the count value can be configured via registers. The increment step size determines the amount the count value increases with each increment, and the increment rate determines how many clock cycles it increments (e.g., every N clock cycles).

[0056] The significance of the increment step size lies in determining the rate at which the bus clock frequency decreases. When using large increments (i.e., each increment is large), the count value increases rapidly, the actual prescaler value increases rapidly, and the bus clock frequency decreases rapidly, resulting in significant power optimization. However, because the frequency decreases quickly, the bus's response speed to transmission requests also slows down accordingly. When using small increments (i.e., each increment is small), the count value increases slowly, the actual prescaler value increases slowly, and the bus clock frequency decreases slowly, resulting in gradual power optimization, but the bus's response speed to transmission requests remains relatively fast.

[0057] The significance of configuring the increment rate is that it determines the time interval for the count value to increment. When the increment rate is fast (i.e., increments once every few clock cycles), the count value accumulates rapidly, and the frequency decreases rapidly; when the increment rate is slow (i.e., increments once every many clock cycles), the count value accumulates slowly, and the frequency decreases slowly.

[0058] By configuring the increment step size and / or increment rate through registers, designers can flexibly configure and balance power consumption optimization and response speed according to the actual needs of different SoC application scenarios.

[0059] When the bus is idle, the counter increments the count value by the configured increment step and / or increment rate.

[0060] In step S101, the bus module monitors the idle state of the bus in the following specific way: The bus module monitors various status signals of the bus in real time, including but not limited to the valid / ready handshake signal and outstanding transaction count signal of the AXI / AHB / APB bus.

[0061] Specifically, the valid / ready handshake signal is used to indicate whether there is ongoing data transmission on the bus. When both the valid and ready signals are valid, it indicates that data transmission is in progress on the bus; when both valid and ready signals are invalid or not valid at the same time, it indicates that there is no ongoing data transmission on the bus. The outstanding transaction count signal is used to indicate the number of incomplete transmission transactions on the bus. When the outstanding transaction count is zero, it indicates that there are no incomplete transmission transactions on the bus.

[0062] When all monitoring signals indicate no transmission activity, such as all valid / ready handshake signals indicating no ongoing data transmission and an outstanding transaction count of zero, the bus module can determine that the bus has entered an idle state.

[0063] When any monitoring signal indicates that there is transmission activity (such as a valid / ready handshake signal or an outstanding transaction count that is not zero), the bus module determines that the bus is in a non-idle state.

[0064] This disclosure also provides a method for dynamic frequency adjustment of the bus clock from the perspective of CRG. For example... Figure 3 As shown, the execution process on the CRG side includes the following steps: S201: Receives a signal output from the bus module, which carries a count value indicating the duration of bus idle time; S202: Determine the actual frequency division value based on the signal; S203: Outputs the bus clock according to the actual frequency division value.

[0065] The CRG module receives signals output by the bus module. These signals carry a counter value indicating the duration of bus idle time. This counter value is incremented by the bus module while the bus is idle, reflecting the length of the bus idle period.

[0066] Then, the actual frequency division value is determined based on the count value carried in the received signal.

[0067] In practical applications, the CRG module uses the sum of the base divider value div_default and the count value cnt as the actual divider value div_actual, i.e., div_actual = div_default + cnt. The base divider value div_default is the divider coefficient corresponding to the bus under normal operating conditions and is pre-configured by software.

[0068] The physical meaning of this formula is as follows: When the bus is in normal operating condition (non-idle), cnt = 0, div_actual = div_default, and the bus clock runs at the normal operating frequency. When the bus enters an idle state, cnt starts to increase from 0, div_actual gradually increases, and the bus clock frequency gradually decreases. The longer the idle time, the larger cnt and div_actual become, and the lower the frequency. From the relationship between frequency and the division value, fact = fmax / div_actual, it can be seen that the increase in the actual division value corresponds to the decrease in the bus clock frequency, achieving a gradual frequency reduction effect of "the longer the idle time, the lower the frequency".

[0069] The count value has a preset upper limit of cnt_max, and the actual frequency division value also has an upper limit, i.e., div_actual ≤ cnt_max + div_default. This upper limit can be determined based on the system's requirement for the minimum operating frequency of the bus. The higher the system's requirement for the minimum operating frequency of the bus, the smaller the value of cnt_max; conversely, the value of cnt_max can be appropriately increased. By setting an upper limit for the count value, it can be ensured that the bus clock frequency is not lower than the minimum operating frequency required by the system, avoiding response delays for transmission requests that exceed the system's acceptable range due to excessively low frequencies.

[0070] After determining the actual frequency division value, the source clock can be divided to output the bus clock of the corresponding frequency.

[0071] When the actual division value changes (e.g., the division value increases due to an increment in the count value, or the division value recovers after the count value is reset to zero), it is necessary to switch from the current division value to the new division value. To ensure that no clock glitches or metastability issues occur during the division value switching process, the CRG module uses one of the following methods for division switching: Method 1: Gray code transition. Gray code encoding is used during frequency division value switching. Since only one bit changes between two adjacent Gray code values, it effectively avoids race conditions and hazards caused by multiple bit flips simultaneously, thus eliminating glitch clocks.

[0072] Method 2: Wait for the current division cycle to finish before switching (stabilize first, then switch). When switching the division value, wait for the current division cycle to finish before switching, i.e., the "stabilize first, then switch" mechanism. Specifically, switch to the new division value only after the current division cycle has finished running and the clock signal is in a stable state, ensuring that the clock signal is continuous and stable during the switching process and does not produce glitches.

[0073] By using the above method, the switching of the frequency division value will not produce clock glitches or metastability problems, thus ensuring the quality of the bus clock signal and the stability of the system.

[0074] To facilitate a further understanding of the embodiments of this disclosure, two specific examples are provided for illustration.

[0075] Example 1: Typical Application Scenarios In this embodiment, it is assumed that the SoC bus subsystem adopts the AXI bus protocol, the source clock frequency of the bus clock is 100MHz, and the base divider value div_default is set to 2 (i.e., the bus clock frequency during normal operation is 50MHz). The initial value of the counter cnt is 0.

[0076] When the bus enters an idle state, the counter starts incrementing from 0, with an increment step size of 1 and an increment rate of once every 2 clock cycles. The actual frequency division value is div_actual = div_default + cnt.

[0077] First idle cycle: cnt = 1, div_actual = 3, bus frequency = 100MHz / 3 ≈ 33.3MHz; Second idle cycle: cnt = 2, div_actual = 4, bus frequency = 100MHz / 4 = 25MHz; The third idle cycle: cnt = 3, div_actual = 5, bus frequency = 100MHz / 5 = 20MHz; Similarly, the bus frequency gradually decreases as the idle time increases, and the dynamic power consumption gradually decreases.

[0078] When a new transmission request arrives, cnt is immediately cleared to zero, div_actual is restored to 2, the bus frequency is immediately restored to 50MHz, and the wake-up delay is only 4~5 clock cycles (about 20~40ns).

[0079] Example 2: Configuration of Incremental Step Size In this disclosed embodiment, two application scenarios are assumed to exist: Scenario 1 is for power-sensitive applications (such as battery-powered IoT devices), which have high power consumption requirements. Designers can configure the increment step size to a larger value (e.g., a step size of 2) through registers, allowing the bus to quickly reduce its frequency when idle and quickly enter a low-power state. With a large step size configuration, the increment speed of cnt doubles, and the frequency reduction speed doubles, but the response speed decreases accordingly.

[0080] Scenario 2 is for performance-sensitive applications (such as real-time systems requiring rapid response to bus requests), which have high demands for response speed. Designers can configure the increment step size to a small value (e.g., a step size of 1) through registers, allowing the bus frequency to decrease slowly when idle, maintaining a relatively fast response capability. With a small step size configuration, the frequency decreases more slowly, but the bus response speed to transmission requests remains faster.

[0081] By flexibly configuring the increment step size through registers, different application scenarios can make flexible trade-offs between power consumption optimization and response speed.

[0082] The above-disclosed technical solution has the following beneficial effects: First, by monitoring the bus idle state and using a counter to gradually reduce the clock frequency, dynamic power consumption can be automatically reduced when the bus is idle. The longer the idle time, the lower the frequency, and the more significant the power consumption optimization effect.

[0083] Secondly, by immediately resetting the counter to restore the frequency when a transmission request is detected, the wake-up latency is shortened to 4-5 clock cycles (nanosecond level). Compared with the wake-up latency of tens to hundreds of cycles of the direct clock shutdown scheme, this ensures the bus's rapid response capability to transmission requests.

[0084] Third, by setting the actual division value to the sum of the base division value and the count value, an adaptive and gradual frequency reduction effect is achieved where the longer the idle time, the larger the division value and the lower the frequency.

[0085] Fourth, by setting an upper limit for the count value, the upper limit of the actual frequency division value is indirectly limited, thus preventing the system response delay from failing to meet requirements due to an excessively low bus clock frequency.

[0086] Fifth, by configuring the increment step size and / or rate through registers, the frequency reduction speed can be flexibly adjusted, achieving a flexible trade-off between power consumption optimization and response speed in different application scenarios.

[0087] Sixth, by using Gray code transition or waiting for the frequency division cycle to end before switching, we can ensure that no clock glitches or metastability issues are generated during the frequency division value switching process, thus ensuring the quality of the clock signal.

[0088] In the description of this specification, references to terms such as "some possible implementations," "some implementations," "example," "specific example," or "some examples" indicate that a specific feature, structure, material, or characteristic described in connection with that implementation or example is included in at least one implementation or example of this disclosure, and the aforementioned terms do not necessarily refer to the same implementation or example. Furthermore, the described specific features, structures, materials, or characteristics can be combined in a suitable manner in any one or more implementations or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different implementations or examples described in this specification, as well as the features of different implementations or examples.

[0089] Regarding the method flowcharts of embodiments of this disclosure, certain operations are described as different steps performed in a certain order. Such flowcharts are illustrative and not restrictive. Some steps described herein may be grouped together and performed in a single operation, or some steps may be divided into multiple sub-steps, and some steps may be performed in an order different from that shown herein. The various steps shown in the flowcharts may be implemented in any way by any circuit structure and / or tangible mechanism (e.g., software running on a computer device, hardware (e.g., logic functions implemented by a processor or chip), and / or any combination thereof).

[0090] Those skilled in the art will understand that in the methods described in the above specific embodiments, the order in which the steps are written does not imply a strict execution order, and the specific execution order of each step should be determined by its function and possible internal logic.

[0091] Based on the same inventive concept, this disclosure also provides a bus clock dynamic frequency modulation device corresponding to the bus clock dynamic frequency modulation method. Since the principle of the device in this disclosure for solving the problem is similar to the bus clock dynamic frequency modulation method described above in this disclosure, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be described again.

[0092] Reference Figure 4The diagram shown is a schematic of a bus clock dynamic frequency adjustment device provided in an embodiment of this disclosure. This device is applied to a bus module in a System-on-a-Chip (SoC) and specifically includes: a monitoring module 301, a counting module 302, a generation module 303, and a clearing module 304; wherein, Monitoring module 301 is used to monitor the idle status of the bus; The counting module 302 is used to increment the counter value when the bus is idle. The generation module 303 is used to generate a signal for adjusting the clock frequency of the bus based on the count value, wherein the clock frequency decreases as the count value increases; The reset module 304 is used to reset the counter value when a transmission request is detected on the bus, so as to restore the clock frequency of the bus.

[0093] This embodiment of the disclosure monitors the bus idle state and uses a counter to gradually reduce the clock frequency, which can automatically reduce dynamic power consumption when the bus is idle; at the same time, by detecting transmission requests and immediately clearing the counter to restore the frequency, the wake-up delay is shortened, ensuring the bus's rapid response capability to transmission requests.

[0094] In one possible implementation, generation module 303 is specifically configured to generate a signal for adjusting the clock frequency of the bus according to the following steps: The signal carrying the count value is output to the clock reset generator, so that the clock reset generator determines the actual frequency division value based on the count value and outputs the bus clock according to the actual frequency division value.

[0095] In one possible implementation, the counting module 302 is further configured to: Configure the increment step size and / or increment rate of the count value through registers.

[0096] In one possible implementation, the counting module 302 is specifically configured to increment the counter value according to the following steps: When the bus is idle, increment the count value by incrementing the step size and / or incrementing the growth rate.

[0097] In one possible implementation, the monitoring module 301 is specifically configured to determine that the bus is in an idle state by the following steps: Monitor various status signals of the monitoring bus; When all status signals indicate no transmission activity, the bus is considered to be in an idle state.

[0098] Reference Figure 5The diagram shows another bus clock dynamic frequency modulation device provided in this embodiment of the present disclosure. This device is applied to a clock reset generator in a System-on-a-Chip (SoC). The clock reset generator is connected to a bus module and specifically includes: a receiving module 401, a determining module 402, and an output module 403; wherein, The receiving module 401 is used to receive signals output by the bus module, the signals carrying a count value for indicating the idle time of the bus; The determining module 402 is used to determine the actual frequency division value based on the signal; Output module 403 is used to output the bus clock according to the actual frequency division value.

[0099] In one possible implementation, the count value is obtained by the bus module incrementing it when the bus is idle.

[0100] In one possible implementation, the determining module 402 is specifically configured to determine the actual frequency division value based on the signal according to the following steps: The sum of the base division value and the count value is used as the actual division value, where the base division value is the division coefficient corresponding to the bus under normal operating conditions.

[0101] In one possible implementation, the actual frequency division value has an upper limit, which does not exceed the sum of the upper limit and the basic frequency division value.

[0102] In one possible implementation, it also includes: The switching module 404 is used to switch to the changed actual frequency division value when the actual frequency division value changes, either by using Gray code transition or by waiting for the current frequency division period to end.

[0103] It should be noted that the apparatus in this embodiment can implement the various processes of the aforementioned method and achieve the same effects and functions, which will not be elaborated here.

[0104] This disclosure also provides a SoC chip, including a bus module and a clock reset generator. The bus module includes the bus-side bus clock dynamic frequency modulation device as described above, and the clock reset generator includes the CRG-side bus clock dynamic frequency modulation device as described above.

[0105] Specifically, the bus module transmits the idle counter's count value cnt as a dynamic frequency division input signal to the CRG module in real time. The frequency divider inside the CRG module receives the cnt signal, determines the actual frequency division value according to the frequency division formula div_actual = div_default + cnt, and divides the source clock according to the actual frequency division value to output the bus clock of the corresponding frequency.

[0106] Corresponding to Figure 2 or Figure 3In addition to the bus clock dynamic frequency modulation method, this disclosure also provides an electronic device, such as... Figure 6 The diagram shown is a schematic representation of the structure of an electronic device provided in an embodiment of this disclosure, including: The system includes a processor 501, a memory 502, and a bus 503. The memory 502 stores execution instructions and includes main memory 5021 and external memory 5022. Main memory 5021, also called internal memory, temporarily stores the processing data in the processor 501, as well as data exchanged with external memory such as a hard disk 5022. The processor 501 exchanges data with external memory 5022 through main memory 5021. When the electronic device is running, the processor 501 communicates with the memory 502 through the bus 503, causing the processor 501 to execute the following instructions: Monitor the idle status of the bus; When the bus is idle, increment the counter value; Based on the count value, a signal is generated to adjust the clock frequency of the bus, wherein the clock frequency decreases as the count value increases; When a transmission request is detected on the bus, the counter value is cleared to restore the bus clock frequency; Alternatively, execute the following command: The signal is received from the bus module and carries a count value indicating the duration of bus idle time. Determine the actual frequency division value based on the signal; Output the bus clock according to the actual frequency division value.

[0107] This disclosure also provides a computer program product carrying program code. The program code includes instructions that can be used to execute the steps of the bus clock dynamic frequency modulation method described in the above method embodiments. For details, please refer to the above method embodiments, which will not be repeated here.

[0108] The aforementioned computer program product can be implemented through hardware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied in a computer storage medium; in another optional embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0109] The various embodiments in this disclosure are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments. In particular, the description of the apparatus, device, and computer-readable storage medium embodiments is simplified because they are basically similar to the method embodiments, and the relevant parts can be referred to the description of the method embodiments.

[0110] The apparatus, device, and computer-readable storage medium provided in this disclosure correspond one-to-one with the method. Therefore, the apparatus, device, and computer-readable storage medium also have similar beneficial technical effects as their corresponding methods. Since the beneficial technical effects of the method have been described in detail above, the beneficial technical effects of the apparatus, device, and computer-readable storage medium will not be repeated here.

[0111] Those skilled in the art will understand that embodiments of this disclosure can be implemented as methods and apparatus (devices or systems), or as computer-readable storage media. Therefore, this disclosure can be implemented entirely in hardware, entirely in software, or in a combination of software and hardware. Furthermore, this disclosure can be implemented as a computer-readable storage medium on one or more computer-readable storage media containing computer-usable program code (including, but not limited to, disk storage, read-only optical disc storage (CD-ROM), optical storage, etc.).

[0112] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (devices or systems), and computer-readable storage media according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to create a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or block diagrams.

[0113] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article including instruction means, wherein the instruction means implement the functions specified in one or more flowcharts and / or one or more blocks in a block diagram.

[0114] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more blocks in the block diagram.

[0115] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0116] Memory can include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0117] Computer-readable media include permanent and non-permanent, removable and non-removable media, which can store information by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer-readable storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory, read-only memory, electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device. Furthermore, although the operations of the methods of this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all of the operations shown must be performed to achieve the desired result. Additionally, certain steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple sub-steps.

[0118] While the spirit and principles of this disclosure have been described above with reference to several specific embodiments, it should be understood that this disclosure is not limited to the disclosed specific embodiments, and the division of aspects does not imply that features in these aspects cannot be combined. This disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A method for dynamic frequency adjustment of a bus clock, applied to a bus module in a System-on-a-Chip (SoC), characterized in that, include: Monitor the idle status of the bus; When the bus is idle, increment the counter value; Based on the count value, a signal is generated for adjusting the clock frequency of the bus, wherein the clock frequency decreases as the count value increases; When a transmission request is detected on the bus, the counter value is cleared to restore the clock frequency of the bus.

2. The method according to claim 1, characterized in that, The generation of the signal for adjusting the clock frequency of the bus includes: The signal carrying the count value is output to the clock reset generator, so that the clock reset generator determines the actual frequency division value based on the count value and outputs the bus clock according to the actual frequency division value.

3. The method according to claim 1, characterized in that, The method further includes: Configure the increment step size and / or increment rate of the count value through a register.

4. The method according to claim 3, characterized in that, The count value of the incrementing counter includes: When the bus is idle, the count value is incremented by the incrementing step size and / or the incrementing rate.

5. The method according to any one of claims 1 to 4, characterized in that, Determine that the bus is in an idle state by following these steps: Monitor various status signals of the bus; When all the status signals indicate no transmission activity, the bus is determined to be in an idle state.

6. A method for dynamic frequency adjustment of a bus clock, applied to a clock reset generator in a System-on-a-Chip (SoC), wherein the clock reset generator is connected to a bus module, characterized in that... include: Receive the signal output by the bus module, the signal carrying a count value for indicating the duration of bus idle time; Determine the actual frequency division value based on the signal; Output the bus clock according to the actual frequency division value.

7. The method according to claim 6, characterized in that, The count value is obtained by the bus module incrementing the count value when the bus is in an idle state.

8. The method according to claim 6, characterized in that, Determining the actual frequency division value based on the signal includes: The sum of the base division value and the count value is taken as the actual division value, wherein the base division value is the division coefficient corresponding to the bus under normal operating conditions.

9. The method according to claim 6, characterized in that, The actual frequency division value has an upper limit, and the actual frequency division value does not exceed the sum of the upper limit value and the basic frequency division value.

10. The method according to claim 6, characterized in that, The method further includes: When the actual frequency division value changes, a Gray code transition method is used or the current frequency division period ends before switching to the changed actual frequency division value.

11. A bus clock dynamic frequency modulation device, applied to a bus module in a System-on-a-Chip (SoC), characterized in that, include: A monitoring module is used to monitor the idle status of the bus; A counting module is used to increment the counter value when the bus is idle. A generation module is configured to generate a signal for adjusting the clock frequency of the bus based on the count value, wherein the clock frequency decreases as the count value increases; The reset module is used to reset the count value when a transmission request is detected on the bus, so as to restore the clock frequency of the bus.

12. A bus clock dynamic frequency adjustment device, applied to a clock reset generator in a System-on-a-Chip (SoC), wherein the clock reset generator is connected to a bus module, characterized in that... include: A receiving module is used to receive a signal output by the bus module, the signal carrying a count value for indicating the idle time of the bus; The determining module is used to determine the actual frequency division value based on the signal; The output module is used to output the bus clock according to the actual frequency division value.

13. A system-on-a-chip (SoC) chip, characterized in that, include: A bus module and a clock reset generator, wherein the bus module includes the bus clock dynamic frequency modulation device as described in claim 11, and the clock reset generator includes the bus clock dynamic frequency modulation device as described in claim 12.

14. An electronic device, characterized in that, include: The device includes a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, the bus clock dynamic frequency adjustment method as described in any one of claims 1 to 10 is performed.

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