Time service module and electronic equipment

Abstract

The invention discloses a time service module and electronic equipment. The time service module comprises a programmable logic module, a main control module and a crystal oscillator module; the programmable logic module is connected with the crystal oscillator module, the crystal oscillator module outputs a clock frequency signal, and the programmable logic module outputs a first pulse signal according to the clock frequency signal; the programmable logic module comprises a source end logic gate unit, an output end logic gate unit and a counting unit, the source end logic gate unit is connected with a source pulse signal, the output end logic gate unit is connected with a first pulse signal, and the counting unit is connected with the source end logic gate unit and the output end logic gate unit; the counting unit outputs a first data signal according to the number of the switched-on logic gates in the source end logic gate unit and the number of the switched-on logic gates in the output end logic gate unit; the master control module calculates the phase difference between the first pulse signal and the source pulse signal according to the first data signal. The time service module provided by the invention has relatively high locking precision.

Description

Technical Field

[0001] The invention relates to the technical field of circuit design, and in particular to a timing module and electronic equipment. Background Art

[0002] The timing module is a module that provides time information and provides accurate time information for the device. The locking accuracy of the timing module is the key to ensuring that the displayed time is consistent with the actual time.

[0003] The locking accuracy of traditional timing modules is affected by two aspects: the stability of the crystal oscillator itself and the phase detection accuracy of the module. For the latter, traditional modules usually use the timer capture method inside the CPLD (Complex Programmable Logic Device) to measure the phase difference between its own output and the source. Therefore, the locking accuracy of the timing module is limited by the clock frequency of the CPLD. The clock frequency must reach more than 1000MHz to achieve a locking accuracy within 1ns, which is unrealistic for module production. Summary of the invention

[0004] The invention provides a timing module and an electronic device to solve the problem in the prior art that the locking accuracy of the timing module is limited by the clock frequency.

[0005] According to one aspect of the present invention, there is provided a timing module, comprising a programmable logic module, a main control module and a crystal oscillator module;

[0006] The editable logic module is connected to the crystal oscillator module, the crystal oscillator module outputs a clock frequency signal, and the programmable logic module is used to output a first pulse signal according to the clock frequency signal;

[0007] The programmable logic module includes a source end logic gate unit, an output end logic gate unit and a counting unit, the source end logic gate unit is connected to the source pulse signal, the output end logic gate unit is connected to the first pulse signal, the counting unit is connected to the source end logic gate unit and the output end logic gate unit, and the counting unit is used to output a first data signal according to the number of logic gates turned on in the source end logic gate unit and the number of logic gates turned on in the output end logic gate unit;

[0008] The main control module is connected to the counting unit and the crystal oscillator module. The main control module is used to calculate the phase difference between the first pulse signal and the source pulse signal according to the first data signal, and adjust the clock frequency signal output by the crystal oscillator module to meet a first preset value according to the phase difference.

[0009] Optionally, the source-end logic gate unit includes multiple first AND gate circuits, the number of the multiple first AND gate circuits satisfies a second preset value, the first ends of the multiple first AND gate circuits are connected to a first power supply, the second end of the first of the first AND gate circuits is connected to the source pulse signal, the multiple first AND gate circuits are connected in series, and the multiple first AND gate circuits are turned on in sequence according to the source pulse signal.

[0010] Optionally, the output end logic gate unit includes multiple second AND gate circuits, the number of the multiple second AND gate circuits satisfies a third preset value, the first ends of the multiple second AND gate circuits are connected to the first power supply, the second end of the first second AND gate circuit is connected to the first pulse signal, the multiple second AND gate circuits are connected in series, and the multiple second AND gate circuits are turned on in sequence according to the first pulse signal.

[0011] Optionally, the counting unit includes a coding subunit and a data storage subunit, the coding subunit is connected to the source end logic gate unit and the output end logic gate unit, the coding subunit is used to output the first data signal according to the number of logic gates turned on in the source end logic gate unit and the number of logic gates turned on in the output end logic gate unit, the data storage subunit is connected to the source end logic gate unit, the output end logic gate unit and the coding subunit, the data storage subunit is used to latch the first data signal when all the logic gates in the source end logic gate unit are turned on, or when all the logic gates in the output end logic gate unit are turned on.

[0012] Optionally, the encoding subunit includes a third AND gate circuit and an encoder, the first end of the third AND gate circuit is connected to the source end logic gate unit, the second end of the third AND gate circuit is connected to the output end logic gate unit, the output end of the third AND gate circuit is connected to the input end of the encoder, and the output end of the encoder is connected to the data storage subunit.

[0013] Optionally, the encoder is an 8-3 encoder, and one 8-3 encoder is connected to eight of the third AND gate circuits.

[0014] Optionally, the data storage subunit includes an XOR gate circuit and a latch, the first end of the XOR gate circuit is connected to the output end of the source end logic gate unit, the second end of the XOR gate circuit is connected to the output end of the output end logic gate unit, and the latch is connected to the output end of the XOR gate circuit and the main control module.

[0015] Optionally, the source-end logic gate unit is connected to the main control module, the source-end logic gate unit outputs a sign bit signal, and the main control module determines whether the phase difference is positive or negative according to the sign bit signal.

[0016] Optionally, the crystal oscillator module includes a constant temperature crystal oscillator.

[0017] According to another aspect of the present invention, an electronic device is provided, comprising the timing module.

[0018] The technical solution of the embodiment of the present invention provides a timing module, including a programmable logic module, a main control module and a crystal oscillator module; the editable logic module is connected to the crystal oscillator module, the crystal oscillator module outputs a clock frequency signal, and the programmable logic module outputs a first pulse signal according to the clock frequency signal; the programmable logic module includes a source end logic gate unit, an output end logic gate unit and a counting unit, the source end logic gate unit is connected to the source pulse signal, the output end logic gate unit is connected to the first pulse signal, the counting unit is connected to the source end logic gate unit and the output end logic gate unit, and the counting unit outputs a first data signal according to the number of logic gates turned on in the source end logic gate unit and the number of logic gates turned on in the output end logic gate unit; the main control module calculates the phase difference between the first pulse signal and the source pulse signal according to the first data signal. Since the opening time end and opening time of the logic gate are stable inside the programmable logic module, and the opening and closing of the logic gate are independent of the clock frequency, the timing module has a higher locking accuracy, and the locking accuracy is independent of the clock frequency, which solves the problem that the locking accuracy of the timing module in the prior art is limited by the clock frequency.

[0019] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 It is a structural schematic diagram of a timing module provided by an embodiment of the present invention;

[0022] Figure 2 is a circuit diagram of a timing module provided by an embodiment of the present invention;

[0023] Figure 3 It is a structural schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0025] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0026] An embodiment of the present invention provides a timing module. Figure 1 is a schematic diagram of the structure of a timing module provided by an embodiment of the present invention, such as Figure 1 As shown, the timing module 100 includes a programmable logic module 110, a main control module 120 and a crystal oscillator module 130; the editable logic module 110 is connected to the crystal oscillator module 130, the crystal oscillator module 130 outputs a clock frequency signal, and the programmable logic module 110 is used to output a first pulse signal according to the clock frequency signal; the programmable logic module 110 includes a source end logic gate unit 111, an output end logic gate unit 112 and a counting unit 113, the source end logic gate unit 111 is connected to the source pulse signal, and the output end logic gate unit 112 is connected to the first pulse signal, The counting unit 113 is connected to the source end logic gate unit 111 and the output end logic gate unit 112, and the counting unit 113 outputs a first data signal according to the number of logic gates turned on in the source end logic gate unit 111 and the number of logic gates turned on in the output end logic gate unit 112; the main control module 120 is connected to the counting unit 113 and the crystal oscillator module 130, and the main control module 120 is used to calculate the phase difference between the first pulse signal and the source pulse signal according to the first data signal, and adjust the clock frequency signal output by the crystal oscillator module 130 according to the phase difference to meet the first preset value.

[0027] In this embodiment, the timing module 100 is a module that provides time information, providing accurate time information for the device. The locking accuracy of the timing module 100 is the key to ensure that the displayed time is consistent with the actual time. The programmable logic module 110 is a module that can design and implement complex logic functions for internal digital integrated circuits as needed. In the timing module, the programmable logic module 110 can control the timing and output a synchronous pulse signal (i.e., a first pulse signal). For example, the programmable logic module 110 uses a complex programmable logic device CPLD. The main control module 120 communicates with other modules through the input and output interface, processes various data instructions and system instructions, and the crystal oscillator module 130 is a module that provides a clock frequency. The system operation requires the drive of the clock frequency.

[0028] In this embodiment, the programmable logic module 110 outputs a first pulse signal according to the clock frequency, the source end logic gate unit 111 is connected to the source pulse signal, and the output end logic gate unit 112 is connected to the first pulse signal. When one of the source end logic gate unit 111 and the output end logic gate unit 112 is turned on first, the counting unit 113 outputs a first data signal according to the number of logic gates turned on in the source end logic gate unit 111 and the number of logic gates turned on in the output end logic gate unit 112, wherein the first data signal is the number of logic gates turned on simultaneously in the source end logic gate unit 111 and the output end logic gate unit 112. The main control module 120 calculates the phase difference between the first pulse signal and the source pulse signal according to the first data signal, and adjusts the clock frequency signal output by the crystal oscillator module 130 according to the phase difference to meet the first preset value.

[0029] The technical solution of this embodiment provides a timing module, including a programmable logic module, a main control module and a crystal oscillator module; the editable logic module is connected to the crystal oscillator module, the crystal oscillator module outputs a clock frequency signal, and the programmable logic module outputs a first pulse signal according to the clock frequency signal; the programmable logic module includes a source end logic gate unit, an output end logic gate unit and a counting unit, the source end logic gate unit is connected to the source pulse signal, the output end logic gate unit is connected to the first pulse signal, the counting unit is connected to the source end logic gate unit and the output end logic gate unit, and the counting unit outputs a first data signal according to the number of logic gates turned on in the source end logic gate unit and the number of logic gates turned on in the output end logic gate unit; the main control module calculates the phase difference between the first pulse signal and the source pulse signal according to the first data signal. Since the opening time end and opening time of the logic gate are stable inside the programmable logic module, and the opening and closing of the logic gate are independent of the clock frequency, the timing module has a higher locking accuracy, and the locking accuracy is independent of the clock frequency, which solves the problem that the locking accuracy of the timing module in the prior art is limited by the clock frequency.

[0030] Figure 2 is a circuit diagram of a timing module provided by an embodiment of the present invention, such as Figure 2 As shown, the source-end logic gate unit 111 includes a plurality of first AND gate circuits Y1, the number of the plurality of first AND gate circuits Y1 satisfies a second preset value n1, the first ends of the plurality of first AND gate circuits Y1 are connected to a first power supply V1, the second end of the first first AND gate circuit Y1 is connected to a source pulse signal, the plurality of first AND gate circuits Y1 are connected in series, and the plurality of first AND gate circuits Y1 are turned on in sequence according to the source pulse signal.

[0031] In this embodiment, the first ends of n1 first AND gate circuits Y1 are connected to the first power supply V1, the second end of the first first AND gate circuit Y1 is connected to the source pulse signal, the second end of the second first AND gate circuit Y1 is connected to the output end of the first first AND gate circuit Y1, the second end of the third first AND gate circuit Y1 is connected to the output end of the second first AND gate circuit Y1... The second end of the n1th first AND gate circuit Y1 is connected to the output end of the n1-1th first AND gate circuit Y1. The source pulse signal is a second pulse signal 1PPS. When the pulse width of the source pulse signal is greater than the opening time of all the first AND gate circuits Y1, the n1 first AND gate circuits Y1 are turned on in sequence.

[0032] Continue to refer Figure 2 The output end logic gate unit 112 includes multiple second AND gate circuits Y2, the number of the multiple second AND gate circuits Y2 meets the third preset value n2, the first ends of the multiple second AND gate circuits Y2 are connected to the first power supply V1, the second end of the first second AND gate circuit Y2 is connected to the first pulse signal, the multiple second AND gate circuits Y2 are connected in series, and the multiple second AND gate circuits Y2 are turned on in sequence according to the first pulse signal.

[0033] In this embodiment, the first ends of the n2 second AND gate circuits Y2 are connected to the first power supply V1, the second end of the first second AND gate circuit Y2 is connected to the first pulse signal, the second end of the second second AND gate circuit Y2 is connected to the output end of the first second AND gate circuit Y2, the second end of the third second AND gate circuit Y2 is connected to the output end of the second second AND gate circuit Y2... The second end of the n2th second AND gate circuit Y2 is connected to the output end of the n2-1th second AND gate circuit Y2. The first pulse signal is a second pulse signal 1PPS. When the pulse width of the first pulse signal is greater than the opening time of all the second AND gate circuits Y2, the n2 second AND gate circuits Y2 are turned on in sequence.

[0034] Continue to refer Figure 2The counting unit 113 includes a coding subunit and a data storage subunit. The coding subunit is connected to the source end logic gate unit and the output end logic gate unit. The coding subunit is used to output the first data signal according to the number of logic gates turned on in the source end logic gate unit and the number of logic gates turned on in the output end logic gate unit. The data storage subunit is connected to the source end logic gate unit, the output end logic gate unit and the coding subunit. The data storage subunit is used to latch the first data signal when all the logic gates in the source end logic gate unit are turned on or when all the logic gates in the output end logic gate unit are turned on.

[0035] In this embodiment, the encoding subunit is a unit that compiles and converts signals or data into a signal form that can be communicated, transmitted and stored. The data storage subunit is a unit that stores the data signal output by the encoding group unit. On the basis of the above embodiment, the encoding subunit outputs the first data signal after encoding according to the number of logic gates turned on in the source end logic gate unit and the number of logic gates turned on in the output end logic gate unit, and the data storage subunit latches the first data signal when all the logic gates in the source end logic gate unit are turned on, or when all the logic gates in the output end logic gate unit are turned on, and the main control module 120 calculates the phase difference between the first pulse signal and the source pulse signal according to the first data signal.

[0036] Specifically, the encoding subunit includes a third AND gate circuit Y3 and an encoder B1, the first end of the third AND gate circuit Y3 is connected to the source end logic gate unit 111, the second end of the third AND gate circuit Y3 is connected to the output end logic gate unit 112, the output end of the third AND gate circuit Y3 is connected to the input end of the encoder B1, and the output end of the encoder B1 is connected to the latch subunit.

[0037] Exemplarily, the encoder B1 is an 8-3 encoder, one 8-3 encoder is connected to eight third AND gate circuits Y3, and the 8-3 encoder is an 8-3 priority encoder. Referring to the above embodiment, when the first AND gate circuit Y1 in the source end logic gate unit 111 and the second AND gate circuit Y2 in the output end logic gate unit 112 at the corresponding position are both turned on, correspondingly, the third AND gate circuit Y3 connected to the first AND gate circuit Y1 and the second AND gate circuit Y2 is turned on, and the corresponding port of the 8-3 priority encoder inputs a high level. For example, 5 first AND gate circuits Y1 in the source end logic gate unit 111 are turned on, and 3 second AND gate circuits Y2 in the output end logic gate unit 112 are turned on. The first three ports of the priority encoder will receive a high level, and the remaining ports are low levels. According to the properties of the 8-3 priority encoder, the 8-3 priority encoder outputs a binary code 011 (i.e., 3 in decimal). That is, the 8-3 priority encoder can output the number of the first AND gate circuit Y1 in the source-end logic gate unit 111 and the second AND gate circuit Y2 in the output-end logic gate unit 112 that are simultaneously turned on.

[0038] Specifically, the latch subunit includes an XOR gate circuit XOR and a latch S1, the first end of the XOR gate circuit XOR is connected to the output end of the source end logic gate unit 111, the second end of the XOR gate circuit XOR is connected to the output end of the output end logic gate unit 112, and the latch S1 is connected to the output end of the XOR gate circuit XOR and the main control module 120.

[0039] In this embodiment, the XOR gate circuit XOR is a logic gate circuit that implements logical XOR operation in digital logic. The XOR gate circuit XOR outputs a high-level signal when the levels of the two inputs are different, and outputs a low-level signal when the levels of the two inputs are the same. Latch S1 is a storage element that is sensitive to pulse levels and can change state under the action of a specific input pulse level. Exemplarily, when all logic gates in the source-end logic gate unit are turned on first, the source-end logic gate unit outputs a high-level signal, the output-end logic gate unit outputs a low-level signal, and the XOR gate circuit XOR outputs a high-level signal, triggering latch S1 to read the sum of all 8-3 priority encoder outputs (that is, the number of the first AND gate circuit Y1 and the second AND gate circuit Y2 that are turned on at the same time).

[0040] On the basis of the above embodiment, the source end logic gate unit 111 is connected to the main control module 120, and the source end logic gate unit 111 outputs a sign bit signal, and the main control module 120 determines the positive or negative of the phase difference according to the sign bit signal. For example, the sign bit signal refers to the signal output by the last first AND gate circuit Y1 in the source end logic gate unit 111 after the XOR gate circuit XOR is triggered. When all the first AND gate circuits Y1 in the source end logic gate unit 111 are first turned on, the first pulse signal lags behind the source pulse signal, and the sign bit signal is 1. When all the second AND gate circuits Y2 in the output end logic gate unit 112 are first turned on, the source pulse signal lags behind the first pulse signal, and the sign bit signal is 0.

[0041] On the basis of the above embodiment, the main control module 120 calculates the phase difference between the first pulse signal and the source pulse signal according to the first data signal, the total number of preset logic gate circuits and the conduction time. For example, the time for each AND gate circuit to be turned on is t1, the time for the XOR gate circuit to be turned on is t2, the time for the latch to receive the rising edge to latch the output of all 8-3 priority encoders is t3, the sum of all encoder outputs is x1 (i.e., the first data signal), the number of the first AND gate circuit or the second AND gate circuit is x2, and the phase difference between the first pulse signal and the source pulse signal is (x2-x1)*t1+t2+t3. Due to the short opening time of the logic gate, the time accuracy of the detection is relatively high. The main control module 120 adjusts the clock frequency signal output by the crystal oscillator module 130 according to the phase difference to meet the first preset value, ensuring the accuracy and stability of the timing module during the taming process.

[0042] On the basis of the above embodiment, the crystal oscillator module 130 includes a constant temperature crystal oscillator, which reduces the impact of ambient temperature changes on the oscillator output frequency and achieves high stability and high precision frequency output.

[0043] An embodiment of the present invention further provides an electronic device, Figure 3 is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention, such as Figure 3 As shown, the electronic device 10 provided in this embodiment includes the timing module 100 provided in any of the above embodiments, and has the beneficial effects of the timing module 100 in any of the above embodiments, which will not be described in detail here.

[0044] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0045] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A timing module, characterized in that: Including programmable logic module, main control module and crystal oscillator module; The editable logic module is connected to the crystal oscillator module, the crystal oscillator module outputs a clock frequency signal, and the programmable logic module is used to output a first pulse signal according to the clock frequency signal; The programmable logic module includes a source end logic gate unit, an output end logic gate unit and a counting unit, the source end logic gate unit is connected to the source pulse signal, the output end logic gate unit is connected to the first pulse signal, the counting unit is connected to the source end logic gate unit and the output end logic gate unit, and the counting unit is used to output a first data signal according to the number of logic gates turned on in the source end logic gate unit and the number of logic gates turned on in the output end logic gate unit; The main control module is connected to the counting unit and the crystal oscillator module. The main control module is used to calculate the phase difference between the first pulse signal and the source pulse signal according to the first data signal, and adjust the clock frequency signal output by the crystal oscillator module to meet a first preset value according to the phase difference.

2. The timing module according to claim 1, characterized in that: The source-end logic gate unit includes a plurality of first AND gate circuits, the number of the plurality of first AND gate circuits meets a second preset value, the first ends of the plurality of first AND gate circuits are connected to a first power supply, the second end of the first of the first AND gate circuits is connected to the source pulse signal, the plurality of first AND gate circuits are connected in series, and the plurality of first AND gate circuits are turned on in sequence according to the source pulse signal.

3. The timing module according to claim 2, characterized in that: The output end logic gate unit includes multiple second AND gate circuits, the number of the multiple second AND gate circuits meets a third preset value, the first ends of the multiple second AND gate circuits are connected to the first power supply, the second end of the first second AND gate circuit is connected to the first pulse signal, the multiple second AND gate circuits are connected in series, and the multiple second AND gate circuits are turned on in sequence according to the first pulse signal.

4. The timing module according to claim 3, characterized in that: The counting unit includes a coding subunit and a data storage subunit, the coding subunit is connected to the source end logic gate unit and the output end logic gate unit, the coding subunit is used to output the first data signal according to the number of logic gates turned on in the source end logic gate unit and the number of logic gates turned on in the output end logic gate unit, the data storage subunit is connected to the source end logic gate unit, the output end logic gate unit and the coding subunit, the data storage subunit is used to latch the first data signal when all the logic gates in the source end logic gate unit are turned on or when all the logic gates in the output end logic gate unit are turned on.

5. The timing module according to claim 4, characterized in that: The encoding subunit includes a third AND gate circuit and an encoder, the first end of the third AND gate circuit is connected to the source end logic gate unit, the second end of the third AND gate circuit is connected to the output end logic gate unit, the output end of the third AND gate circuit is connected to the input end of the encoder, and the output end of the encoder is connected to the data storage subunit.

6. The timing module according to claim 5, characterized in that: The encoder is an 8-3 encoder, and one of the 8-3 encoders is connected to eight of the third AND gate circuits.

7. The timing module according to claim 4, characterized in that: The data storage subunit includes an XOR gate circuit and a latch, wherein a first end of the XOR gate circuit is connected to an output end of the source end logic gate unit, a second end of the XOR gate circuit is connected to an output end of the output end logic gate unit, and the latch is connected to the output end of the XOR gate circuit and the main control module.

8. The timing module according to claim 1, characterized in that: The source-end logic gate unit is connected to the main control module, the source-end logic gate unit outputs a sign bit signal, and the main control module determines whether the phase difference is positive or negative according to the sign bit signal.

9. The timing module according to claim 1, characterized in that: The crystal oscillator module includes a constant temperature crystal oscillator.

10. An electronic device, characterized in that: The invention comprises the timing module described in any one of claims 1 to 9.

Images