A delay-locked loop circuit, chip and electronic device

Abstract

The application discloses a delay-locked loop circuit, a chip and electronic equipment, the delay-locked loop circuit comprises a first delay chain, a second delay chain, an SR latch and a digital control unit, the digital control unit is in a coarse adjustment stage, when a compensation signal is a non-target value, the current first delay offset code is increased, in a fine adjustment stage, when the compensation signal is the non-target value, the current second delay offset code is increased, until the received compensation signal is the target value, entering a locked state, the SR latch inputs a first delay signal and a second delay signal, and outputs a compensation signal.Because the delay-locked loop circuit is based on the mixed mode of digital design and analog design, the circuit structure is simple, the adjustment is carried out in stages through the digital control unit, high-precision clock phase adjustment can be realized, the control is simple, the locking time is short, the calibration process is simple, in addition, the SR latch is used in the delay-locked loop circuit, compared with using a phase detector, the locking precision can be improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a delay phase-locked loop circuit, chip, and electronic device. Background Technology

[0002] A delay-locked loop (DLL) is a synchronous circuit widely used in integrated circuits. In double data rate (DDR) memory chips, the DLL is a crucial circuit module. It is mainly responsible for synchronizing internal and external clocks and compensating for signal delays to ensure that data is sampled and transmitted at the correct time, thereby improving the accuracy and reliability of data transmission.

[0003] During the power-on initialization phase, the DLL is typically enabled by configuring a mode register (e.g., setting a specific bit in the MR1 register) and requires a lockout period (tDLLK, e.g., at least 512 clock cycles). When entering a low-power mode (e.g., self-refresh mode) or performing frequency adjustments, the DLL can be disabled to save power. Disabling the DLL can also be achieved by configuring the mode register (e.g., disabling a specific bit in the MR1 register). After the DLL is disabled, to restore normal operation, it must be re-enabled and the user must wait for the DLL to lock again. This process involves a long lockout period and a cumbersome calibration process.

[0004] The DLL provided by related technologies typically includes a Variable Delay Line (VDL), a Phase Detector (PD), a Charge Pump (CP), and a Low Pass Filter (LPF). The DLL circuit structure is complex and the control is cumbersome. The "dead zone" of the Phase Detector reduces the locking accuracy. Summary of the Invention

[0005] This invention provides a delay phase-locked loop circuit, chip, and electronic device to solve the problems of complex structure, cumbersome control, low locking accuracy, long locking period, and cumbersome calibration process in existing delay phase-locked loop circuits.

[0006] In a first aspect, this application provides a delay phase-locked loop circuit, including: a first delay link, a second delay link, an SR latch, and a digital control unit, wherein the second delay link includes a first delay unit and a second delay unit;

[0007] The digital control unit is configured to, during the coarse adjustment phase, increase the current first delay offset code when the received compensation signal is not the target value, until the received compensation signal is the target value, wherein the first delay offset code is used to adjust the delay amount of the first delay unit; and during the fine adjustment phase following the coarse adjustment phase, when the received compensation signal is not the target value, increase the current second delay offset code until the received compensation signal is the target value, and then enter a locked state, wherein the second delay offset code is used to adjust the delay amount of the second delay unit, and the step time of the first delay unit is greater than the step time of the second delay unit.

[0008] The first delay link is used to delay the input reference clock signal to obtain a first delayed signal;

[0009] The second delay link is used to delay the input reference clock signal under the control of the first delay offset code and the second delay offset code to obtain a second delay signal;

[0010] The SR latch is used to input the first delay signal and the second delay signal, and output the compensation signal.

[0011] In one possible implementation, the delay-locked loop circuit further includes a first inverter;

[0012] The input terminal of the first inverter is electrically connected to the second output terminal of the SR latch;

[0013] The SR latch is specifically used to input the first delay signal and the second delay signal, and output a compensation inverse signal;

[0014] The first inverter is used to input the compensation inverse signal and output the compensation signal.

[0015] In one possible implementation, the delay phase-locked loop circuit also includes a control unit;

[0016] The control unit is configured to process the input reference clock signal based on the received calibration enable signal and phase detection signal, and output a first clock signal to the first delay link and the second delay link.

[0017] The first delay link is specifically used to delay the input first clock signal to obtain the first delayed signal;

[0018] The second delay link is specifically used to delay the input first clock signal under the control of the first delay offset code and the second delay offset code to obtain the second delay signal.

[0019] In one possible implementation, the control unit includes a second inverter, an OR gate, and at least one first D flip-flop;

[0020] In the case of including a first D flip-flop, the D terminal of the first D flip-flop is used to input the calibration enable signal, the Q terminal of the first D flip-flop is electrically connected to the input terminal of the second inverter, the CLK terminal of the first D flip-flop is used to input the reference clock signal, and the RSTB terminal of the first D flip-flop is used to input the phase detection signal.

[0021] In the case of at least two first D flip-flops, the D terminal of the first first D flip-flop is used to input the calibration enable signal, the Q terminal of the previous first D flip-flop is electrically connected to the D terminal of the next first D flip-flop, the Q terminal of the last first D flip-flop is electrically connected to the input terminal of the second inverter, the CLK terminal of each first D flip-flop is used to input the reference clock signal, and the RSTB terminal of each first D flip-flop is used to input the phase detection signal.

[0022] The output of the second inverter is electrically connected to the first input of the OR gate;

[0023] The second input terminal of the OR gate is used to input the reference clock signal, and the output terminal of the OR gate is used to output the first clock signal.

[0024] In one possible implementation, a logic processing unit and a mode selection unit are also included;

[0025] The logic processing unit is configured to perform a first logic processing on the first delayed signal to characterize a first mode based on the calibration enable signal and the phase detection signal, to obtain a first mode delayed signal; perform a second logic processing on the first delayed signal to characterize a second mode based on the calibration enable signal and the phase detection signal, to obtain a second mode delayed signal; and perform a third logic processing on the second delayed signal based on the calibration enable signal and the phase detection signal, to obtain a logic delayed signal.

[0026] The mode selection unit is used to select the output first mode delay signal or the second mode delay signal as the first target delay signal based on the mode selection signal, and to select the output calibration enable signal or logic delay signal as the second target delay signal based on the calibration enable signal.

[0027] The SR latch is specifically used to input the first target delay signal and the second target delay signal, and output the compensation inverse signal.

[0028] In one possible implementation, the logic processing unit includes a fourth D flip-flop, a fifth D flip-flop, a sixth D flip-flop, a seventh D flip-flop, and a third inverter;

[0029] The D terminal of the fourth D flip-flop is used to input the calibration enable signal. The Q terminal of the fourth D flip-flop is electrically connected to the D terminal of the fifth D flip-flop. The CLK terminals of the fourth and fifth D flip-flops are both used to input the first delay signal. The RSTB terminals of the fourth, fifth, sixth, and seventh D flip-flops are all used to input the phase detection signal.

[0030] The Q terminal of the fifth D flip-flop is used to output the first mode delay signal;

[0031] The input terminal of the third inverter is used to input the first delayed signal, and the output terminal of the third inverter is electrically connected to the CLK terminal of the sixth D flip-flop;

[0032] The D terminal of the sixth D flip-flop is used to input the calibration enable signal, and the Q terminal of the sixth D flip-flop is used to output the second mode delay signal.

[0033] The D terminal of the seventh D flip-flop is used to input the calibration enable signal, the CLK terminal of the seventh D flip-flop is used to input the second delay signal, and the Q terminal of the seventh D flip-flop is used to output the logic delay signal.

[0034] In one possible implementation, the mode selection unit includes a first selector and a second selector;

[0035] The first input terminal of the first selector is used to input the first mode delay signal, the second input terminal of the first selector is used to input the second mode delay signal, the control terminal of the first selector is used to input the mode selection signal, and the output terminal of the first selector is used to output the first target delay signal.

[0036] The first input terminal of the second selector is used to input the calibration enable signal, the second input terminal of the second selector is used to input the logic delay signal, the control terminal of the second selector is used to input the calibration enable signal, and the output terminal of the second selector is used to output the second target delay signal.

[0037] In one possible implementation, the digital control unit is specifically used for:

[0038] The current first delay offset code is increased based on the first compensation value;

[0039] The current second delay offset code is increased based on the second compensation value;

[0040] In the coarse adjustment stage, after the received compensation signal is the target value, the current first delay offset code is reduced based on the first compensation value, and then the fine adjustment stage begins.

[0041] In one possible implementation, the digital control unit is specifically used for:

[0042] After controlling the phase detection signal to a first level signal, the calibration enable signal is controlled to be the first level signal, and the coarse adjustment stage is entered.

[0043] In the coarse adjustment stage, it is determined whether the received compensation signal is the target value. If so, the phase detection signal is controlled to be a second level signal, the current first delay offset code is reduced based on the first compensation value, and the phase detection signal is controlled to be a first level signal to enter the fine adjustment stage. Otherwise, the phase detection signal is controlled to be a second level signal, the current first delay offset code is increased based on the first compensation value, and the process returns to the step of determining whether the received compensation signal is the target value.

[0044] During the fine-tuning stage, it is determined whether the received compensation signal is the target value. If so, the current first delay offset code and the current second delay offset code are used as the locked delay offset code, the phase detection signal is controlled to be the second level signal, the calibration enable signal is controlled to be the second level signal, and the locked state is entered. Otherwise, after controlling the phase detection signal to be the second level signal, the current second delay offset code is increased based on the second compensation value, and the process returns to the step of determining whether the received compensation signal is the target value.

[0045] Secondly, this application also provides a chip including a delay phase-locked loop circuit as described in any of the first aspects.

[0046] Thirdly, this application also provides an electronic device including the chip described in the second aspect.

[0047] The beneficial effects of this invention are as follows:

[0048] This application provides a delay phase-locked loop (PLL) circuit, chip, and electronic device. The PLL circuit includes a first delay link, a second delay link, an SR latch, and a digital control unit. In a coarse adjustment phase, if the received compensation signal is not the target value, the digital control unit increases the current first delay offset code until the received compensation signal is the target value. The first delay offset code is used to adjust the number of first delay units. In a fine adjustment phase following the coarse adjustment phase, if the received compensation signal is not the target value, the digital control unit increases the current second delay offset code until the received compensation signal is the target value, after which it enters a locked state. The second delay offset code is used to adjust the number of second delay units, and the step size of the first delay unit is greater than the step size of the second delay unit. The first delay link is used to delay the input reference clock signal to obtain a first delayed signal. The second delay link, under the control of the first and second delay offset codes, delays the input reference clock signal to obtain a second delayed signal. The SR latch is used to input the first and second delayed signals and output a compensation signal. Since the delay phase-locked loop circuit is based on a hybrid digital and analog design, the circuit structure is simple. It can achieve high-precision clock phase adjustment through staged adjustment by digital control unit. It also makes the control simple, the locking time short, and the calibration process simple. In addition, the delay phase-locked loop circuit in this application uses an SR latch, which can improve the locking accuracy compared to using a phase detector. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 A circuit diagram of a delay phase-locked loop circuit provided for related technologies;

[0051] Figure 2 A circuit diagram of a delay phase-locked loop circuit provided in an embodiment of this application;

[0052] Figure 3 A circuit diagram of another delay phase-locked loop circuit provided in an embodiment of this application;

[0053] Figure 4 A circuit diagram of another delay phase-locked loop circuit provided in an embodiment of this application;

[0054] Figure 5 A circuit diagram of a control unit provided in an embodiment of this application;

[0055] Figure 6 A circuit diagram of a frequency division unit and a mode selection unit provided for embodiments of this application;

[0056] Figure 7 A circuit diagram of another frequency division unit and mode selection unit provided in an embodiment of this application;

[0057] Figure 8 A flowchart illustrating a control method provided in an embodiment of this application;

[0058] Figure 9 This is a signal timing diagram provided for an embodiment of this application. Detailed Implementation

[0059] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0060] The DLL circuit dynamically adjusts the delay line through a closed-loop feedback system to ensure that the output clock signal and the input reference clock signal are strictly aligned.

[0061] Typically, the external clock signal input to the DDR memory chip is used as the reference clock signal for the DLL circuit. The DLL circuit has a variable delay line (VDL) consisting of a series of adjustable delay units, such as a voltage-controlled delay line (VCDL). The initial delay is usually set to an estimated value.

[0062] The DLL circuit also includes a phase detector, which compares the phase difference between the reference clock signal input to the delay line and the output clock signal output from the output terminal of the delay line, and outputs a phase difference signal.

[0063] The DLL circuit also includes a charge pump and a low-pass filter. The phase difference signal output by the phase detector passes through the charge pump and the low-pass filter to generate a control voltage Vctrl. The control voltage Vctrl is used to control the delay time of each delay unit in the delay line.

[0064] The DLL circuit continuously adjusts the delay of the delay line to align the edge of the output clock signal with the edge of the reference clock signal. When the edge of the output clock signal aligns with the edge of the reference clock signal, the system enters a "locked" state.

[0065] The DLL circuit actively measures and compensates for fixed delays on the clock path. After the DDR memory chip powers on, the DLL circuit begins operation, calibrating the delay through a training process (usually initiated by the memory controller). It continuously adjusts the delay amount of the delay line until the rising edge of the output clock signal aligns with the rising edge of the reference clock signal. Once locked, the delay amount of the delay line precisely compensates for the fixed delay of the internal path.

[0066] like Figure 1 The diagram shown is a circuit schematic of a delay phase-locked loop circuit provided by related technologies. Figure 1 The delay phase-locked loop circuit shown includes VDL 11, PD, CP, and LPF, wherein VDL 11 includes n-stage delay units ( Figure 1 (The middle triangle is the identifier), where n is a positive integer; n-level delay units are connected in series on the clock signal path. The reference clock signal CKin enters the first-level delay unit, generating the first-level delay signal CK1. The first-level delay signal CK1 enters the second-level delay unit, generating the second-level delay signal CK2. The second-level delay signal CK2 enters the third-level delay unit, generating the third-level delay signal CK3, and so on, until the nth-level delay signal CKn is generated.

[0067] The nth-stage delay signal CKn and the reference clock signal CKin pass through PD, CP and LPF to generate the control voltage Vctrl of the nth-stage delay unit, thereby achieving phase locking of the reference clock signal CKin and the nth-stage delay signal CKn.

[0068] Figure 1 The DLL circuit shown is an analog loop that outputs a control voltage Vctrl through a phase detector, a charge pump, and a low-pass filter to control the delay of a delay line composed of n-stage delay units. This DLL circuit has a complex structure and is cumbersome to control. The "dead zone" (accuracy) of the phase detector will reduce the locking accuracy.

[0069] In addition, the DLL circuits provided by the relevant technologies have long locking cycles and cumbersome calibration processes.

[0070] Based on the above-mentioned technical problems, this application provides a delay phase-locked loop circuit, chip, and electronic device. The delay phase-locked loop circuit is based on a hybrid digital and analog design, with a simple circuit structure. It can achieve high-precision clock phase adjustment through staged adjustment by a digital control unit, and also makes control simple, lock time short, and calibration process simple. In addition, the delay phase-locked loop circuit in this application embodiment also includes an SR latch, which can improve the locking accuracy compared to using a phase detector.

[0071] The delay phase-locked loop circuit, chip, and electronic device provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0072] like Figure 2 The diagram shown is a circuit schematic of a delay phase-locked loop circuit provided in an embodiment of this application. (Refer to...) Figure 2 The delay phase-locked loop circuit includes: a first delay link 11, a second delay link 12, an SR latch 13, and a digital control unit 14, wherein the second delay link 12 includes a first delay unit and a second delay unit;

[0073] The digital control unit 14 is configured to, during the coarse adjustment phase, increase the current first delay offset code I_DLL_CODE<8:3> when the received compensation signal O_DLL-COMP is not the target value, until the received compensation signal O_DLL-COMP reaches the target value, wherein the first delay offset code I_DLL_CODE<8:3> is used to adjust the delay amount of the first delay unit; during the fine adjustment phase following the coarse adjustment phase, when the received compensation signal O_DLL-COMP is not the target value, increase the current second delay offset code I_DLL_CODE<2:0> until the received compensation signal O_DLL-COMP reaches the target value, and then enter a locked state, wherein the second delay offset code I_DLL_CODE<2:0> is used to adjust the delay amount of the second delay unit, and the step size of the first delay unit is greater than the step size of the second delay unit;

[0074] The first delay link 11 is used to delay the input reference clock signal CKin to obtain the first delayed signal CLK_INT;

[0075] The second delay link 12 is used to delay the input reference clock signal CKin under the control of the first delay offset code I_DLL_CODE<8:3> and the second delay offset code I_DLL_CODE<2:0> to obtain the second delay signal CLK_LCLD.

[0076] SR latch 13 is used to input the first delay signal CLK_INT and the second delay signal CLK_LCLD, and output the compensation signal O_DLL-COMP.

[0077] In this embodiment, the first delay link 11 and the second delay link 12 have the same structure. Specifically, both the first delay link 11 and the second delay link 12 can be LCDL (Linear Control Delay Line) circuits. Before locking, an initial delay offset code can be preset. For example, a binary string can be set as the initial delay offset code I_DLL_CODE<8:0>=9b'0000000000, the high 6 bits of the string can be used as the first delay offset code I_DLL_CODE<8:3>, and the low 3 bits can be used as the second delay offset code I_DLL_CODE<2:0>.

[0078] It should be noted that setting the delay offset code to 9 bits is to ensure resolution and depth; setting it to 9 bits here is just an example. The above-mentioned use of the high 6 bits of the string as the first delay offset code I_DLL_CODE<8:3> and the low 3 bits of the string as the second delay offset code I_DLL_CODE<2:0> is just an example, and this application does not impose any limitations on this.

[0079] In this embodiment, the input reference clock signal Ckin can be a phase-locked loop clock (PCLK).

[0080] In this embodiment, the first delay link 11 is a replica circuit of the intrinsic delay of the second delay link 12. The second delay link 12 includes a first delay unit and a second delay unit. The step size of the first delay unit is larger than that of the second delay unit. In other words, the delay accuracy of the first delay unit is greater than that of the second delay unit.

[0081] The first delay offset code I_DLL_CODE<8:0> is used to adjust the delay amount of the first delay unit. In other words, the first delay offset code I_DLL_CODE<8:0> is used to adjust the number of the first delay units. The second delay offset code I_DLL_CODE<2:0> is used to adjust the delay amount of the second delay unit. In other words, the second delay offset code I_DLL_CODE<2:0> is used to adjust the number of the second delay units.

[0082] In one embodiment, such as Figure 3 The diagram shown is a circuit schematic of another delay phase-locked loop circuit provided in an embodiment of this application. (Refer to...) Figure 3 The delay phase-locked loop circuit also includes a first inverter N1;

[0083] The input terminal of the first inverter N1 is electrically connected to the second output terminal of the SR latch 13;

[0084] SR latch 13 is specifically used to input the first delay signal CLK_INT and the second delay signal CLK_LCDL, and output the compensation inverse signal;

[0085] The first inverter N1 is used to input the compensation inverted signal and output the compensation signal O_DLL-COMP.

[0086] In practical implementation, if the delay phase-locked loop circuit is Figure 2 The structure shown indicates that the target value is 1. If the delay-locked loop circuit is... Figure 3 The target value is 0 for the structure shown.

[0087] Reference Figure 3 After the reference clock signal CKin passes through the first delay link 11, it outputs the first delay signal CLK_INT. After the reference clock signal CKin passes through the second delay link 12, under the control of the initial delay offset code, the second delay link 12 outputs the second delay signal CLK_LCDL. After the first delay signal CLK_INT and the second delay signal CLK_LCDL are input to the SR latch 13, the compensation inverse signal output by the SR latch 13 is a low level signal (0). After the low level signal passes through the first inverter N1, the output compensation signal O_DLL-COMP is a high level signal (1). Among them, the high level signal (1) is the non-target value and the low level signal (0) is the target value.

[0088] After the digital control unit 14 determines that the received compensation signal O_DLL-COMP is a high-level signal (1), it enters the coarse adjustment stage. Based on the first compensation value, it increases the current first delay offset code I_DLL_CODE<8:3>. Specifically, the first compensation value can be 1b'1, that is, the increased first delay offset code I_DLL_CODE<8:3>=6b'xxxxxx+1b'1, where I_DLL_CODE<8:3>=6b'xxxxxx is the current first delay offset code. After increasing the first delay offset code I_DLL_CODE<8:3>, the increased first delay offset code is applied to the second delay link 12. The first inverter N1 outputs the compensation signal O_DLL-COMP again. The digital control unit 14 then determines whether the received compensation signal O_DLL-COMP is a low-level signal (0). If not, it continues to increase the current first delay offset code I_DLL_CODE<8:3> until it is determined that the received compensation signal O_DLL-COMP is a low-level signal (0), and the coarse adjustment ends.

[0089] After the digital control unit 14 determines that the received compensation signal O_DLL-COMP is a low-level signal (0), it reduces the current first delay offset code I_DLL_CODE<8:3> based on the first compensation value and enters the fine-tuning stage. Specifically, when the first compensation value is 1b'1, the reduced first delay offset code I_DLL_CODE<8:3> = 6b'xxxxxx-1b'1, where the first delay offset code I_DLL_CODE<8:3> = 6b'xxxxxx is the current first delay offset code.

[0090] After reducing the first delay offset code I_DLL_CODE<8:3>, the current second delay offset code I_DLL_CODE<2:0> is increased based on the second compensation value. Specifically, the second compensation value can also be 1b'1, that is, the increased second delay offset code I_DLL_CODE<2:0>=3b'xxxxxx+1b'1, where I_DLL_CODE<2:0>=3b'xxxxxx is the current second delay offset code. Then it is determined whether the received compensation signal O_DLL-COMP is a low-level signal (0). If not, the current second delay offset code I_DLL_CODE<2:0> is increased until it is determined that the received compensation signal O_DLL-COMP is a low-level signal (0).

[0091] After confirming that the received compensation signal O_DLL-COMP is a low-level signal (0), the fine-tuning ends, the current first delay offset code <8:3> and the current second delay offset code <2:0> are locked, and the second delay link 12 is controlled by the locked first delay offset code <8:3> and the second delay offset code <2:0>, and the locked state is entered.

[0092] In one embodiment, such as Figure 4 The diagram shown is a circuit diagram of another delay phase-locked loop circuit provided in an embodiment of this application. The delay phase-locked loop circuit may further include a fourth inverter N4. The input terminal of the fourth inverter N4 is electrically connected to the first output terminal of the SR latch 13, and the output terminal of the fourth inverter N4 is left floating.

[0093] To facilitate circuit matching and matching loading, a fourth inverter N4 is added in this embodiment.

[0094] like Figure 5 The diagram shown is a circuit diagram of a control unit provided in an embodiment of this application. Figure 5 As shown, the delay phase-locked loop circuit also includes a control unit 15;

[0095] The control unit 15 is used to process the input reference clock signal CKin based on the received calibration enable signal CAL_EN and phase detection signal PHASEDET_EN, and output the first clock signal CLK to the first delay link 11 and the second delay link.

[0096] The first delay link 11 is specifically used to delay the input first clock signal CLK to obtain the first delayed signal;

[0097] The second delay link 12 is specifically used to delay the input first clock signal CLK under the control of the first delay offset code and the second delay offset code to obtain the second delay signal.

[0098] In a specific implementation, the control unit 15 includes a second inverter, an OR gate, and at least one first D flip-flop;

[0099] In the case of including a first D flip-flop, the D terminal of the first D flip-flop is used to input the calibration enable signal CAL_EN, the Q terminal of the first D flip-flop is electrically connected to the input terminal of the second inverter, the CLK terminal of the first D flip-flop is used to input the reference clock signal CKin, and the RSTB terminal of the first D flip-flop is used to input the phase detection signal PHASEDET_EN.

[0100] In the case of at least two first D flip-flops, the D terminal of the first first D flip-flop is used to input the calibration enable signal CAL_EN, the Q terminal of the previous first D flip-flop is electrically connected to the D terminal of the next first D flip-flop, the Q terminal of the last first D flip-flop is electrically connected to the input terminal of the second inverter, the CLK terminal of each first D flip-flop is used to input the reference clock signal CKin, and the RSTB terminal of each first D flip-flop is used to input the phase detection signal PHASEDET_EN.

[0101] The output of the second inverter is electrically connected to the first input of the OR gate;

[0102] The second input of the OR gate is used to input the reference clock signal CKin, and the output of the OR gate is used to output the first clock signal CLK.

[0103] In this embodiment, the first clock signal CLK output by using a D flip-flop, an inverter, and an OR gate has a longer duration and is synchronized with the reference clock signal CKin, which can improve the reliability and anti-interference capability of the signal.

[0104] In practical implementation, the first D flip-flop can include three, such as Figure 5 As shown, the control unit 15 includes a first D flip-flop DFF11, a first D flip-flop DFF12, a first D flip-flop DFF13, a second inverter N2, and an OR gate.

[0105] The D terminal of the first D flip-flop DFF11 is used to input the calibration enable signal CAL_EN. The CLK terminals of the first D flip-flop DFF11, DFF12, and DFF13, as well as the second input terminal of the OR gate, are all used to input the reference clock signal CKin. The RSTB terminals of the first D flip-flop DFF11, DFF12, and DFF13 are all used to input the phase detection signal PHASEDET_EN. The Q terminal of the first D flip-flop DFF11 is electrically connected to the D terminal of the first D flip-flop DFF12.

[0106] The Q terminal of the first D flip-flop DFF12 is electrically connected to the D terminal of the first D flip-flop DFF13;

[0107] The Q terminal of the first D flip-flop DFF13 is electrically connected to the output terminal of the second inverter N2;

[0108] The output of the second inverter N2 is electrically connected to the first input of the OR gate;

[0109] The output of the OR gate is used to output the first clock signal CLK.

[0110] like Figure 6 The diagram shown is a circuit diagram of a frequency division unit and a mode selection unit provided in an embodiment of this application. (Refer to...) Figure 6 The delay phase-locked loop circuit also includes a logic processing unit 16 and a mode selection unit 17;

[0111] The logic processing unit 16 is configured to perform a first logic processing on the first delayed signal CLK_INT to characterize a first mode based on the calibration enable signal CAL_EN and the phase detection signal PHASEDET_EN, to obtain a first mode delayed signal I1R; perform a second logic processing on the first delayed signal CLK_INT to characterize a second mode based on the calibration enable signal CAL_EN and the phase detection signal PHASEDET_EN, to obtain a second mode delayed signal I1F; and perform a third logic processing on the second delayed signal CLK_LCDL based on the calibration enable signal CAL_EN and the phase detection signal PHASEDET_EN, to obtain a logic delayed signal I2R.

[0112] The mode selection unit 17 is used to use the output first mode delay signal I1R or the second mode delay signal I1F as the first target delay signal INT based on the mode selection signal REG_2UI_EN, and to use the output calibration enable signal CAL_EN or the logic delay signal I2R as the second target delay signal Dly based on the calibration enable signal CAL_EN.

[0113] SR latch 13 is specifically used to input the first target delay signal INT and the second target delay signal Dly, and output the compensation inverse signal.

[0114] In specific implementation, refer to Figure 6 The logic processing unit 16 includes a fourth D flip-flop DFF4, a fifth D flip-flop DFF5, a sixth D flip-flop DFF6, a seventh D flip-flop DFF7, and a third inverter N3;

[0115] The D terminal of the fourth D flip-flop DFF4 is used to input the calibration enable signal CAL_EN. The Q terminal of the fourth D flip-flop DFF4 is electrically connected to the D terminal of the fifth D flip-flop DFF5. The CLK terminals of both the fourth D flip-flop DFF4 and the fifth D flip-flop DFF5 are used to input the first delay signal CLK_INT. The RSTB terminals of the fourth D flip-flop DFF4, the fifth D flip-flop DFF5, the sixth D flip-flop DFF6, and the seventh D flip-flop DFF7 are all used to input the phase detection signal PHASEDET_EN.

[0116] The Q input of the fifth D flip-flop DFF5 is used to output the first mode delay signal I1R;

[0117] The input terminal of the third inverter N3 is used to input the first delayed signal CLK_INT, and the output terminal of the third inverter N3 is electrically connected to the CLK terminal of the sixth D flip-flop DFF6.

[0118] The D terminal of the sixth D flip-flop DFF6 is used to input the calibration enable signal CAL_EN, and the Q terminal of the sixth D flip-flop DFF6 is used to output the second mode delay signal I1F.

[0119] The D terminal of the seventh D flip-flop DFF7 is used to input the calibration enable signal CAL_EN, the CLK terminal of the seventh D flip-flop DFF7 is used to input the second delay signal CLK_LCDL, and the Q terminal of the seventh D flip-flop DFF7 is used to output the logic delay signal I2R.

[0120] Reference Figure 6 The mode selection unit 17 includes a first selector M1 and a second selector M2;

[0121] The first input terminal of the first selector M1 is used to input the first mode delay signal I1R, the second input terminal of the first selector M1 is used to input the second mode delay signal I1F, the control terminal of the first selector M1 is used to input the mode selection signal REG_2UI_EN, and the output terminal of the first selector M1 is used to output the first target delay signal INT.

[0122] The first input terminal of the second selector M2 is used to input the calibration enable signal CAL_EN, the second input terminal of the second selector M2 is used to input the logic delay signal I2R, the control terminal of the second selector M2 is used to input the calibration enable signal CAL_EN, and the output terminal of the second selector M2 is used to output the second target delay signal Dly.

[0123] In this embodiment, two modes are included: a first mode and a second mode. The first mode can be a 2UI (UnitInterval) mode, and the second mode can be a 1UI mode. The first delay signal CLK_INT is passed through the fourth D flip-flop DFF4 and the fifth D flip-flop DFF5 to output a delay signal I1R representing the first mode. The first delay signal CLK_INT is passed through the third inverter N3 and the sixth D flip-flop DFF6 to output a delay signal I1F representing the second mode. The first mode delay signal I1R and the second mode delay signal I1F are input into the first selector M1. Under the control of the mode selection signal REG_2UI_EN, the first selector M1 outputs the first target delay signal INT.

[0124] Specifically, when the mode selection signal REG_2UI_EN is high, the first selector M1 outputs the first mode delay signal I1R, and when the mode selection signal REG_2UI_EN is low, the first selector M1 outputs the second mode delay signal I1F.

[0125] In this embodiment of the application, when the mode selection signal REG_2UI_EN is a high-level signal, it indicates that the first mode is used, and when the mode selection signal REG_2UI_EN is a low-level signal, it indicates that the second mode is used.

[0126] The second delayed signal CLK_LCDL, after passing through the seventh D flip-flop DFF7, outputs the logic delayed signal I2R. The calibration enable signal CAL_EN and the logic delayed signal I2R are input to the second selector M2. Under the control of the calibration enable signal CAL_EN, the second selector M2 outputs either the calibration enable signal CAL_EN or the logic delayed signal I2R.

[0127] Specifically, when the calibration enable signal CAL_EN is high, the second selector M2 outputs the logic delay signal I2R; when the calibration enable signal CAL_EN is low, the second selector M2 outputs the calibration enable signal CAL_EN.

[0128] Since the calibration enable signal CAL_EN is always high during the coarse and fine adjustment stages of the delay phase-locked loop, the second selector M2 continuously outputs the logic delay signal I2R.

[0129] This application embodiment can achieve calibration in 2UI mode and 1UI mode by setting the REG_2UI_EN register. In specific implementation, using 2UI mode can eliminate the duty cycle problem of the reference clock signal, thereby improving latching accuracy.

[0130] like Figure 9 The diagram shown is a signal timing diagram provided in an embodiment of this application. Figure 9 In this context, PCLK is the reference clock signal CKin, and the first mode delay signal I1R is... Figure 9 The rising edge marked by the arrow in the first delayed signal CLK_INT, and the second mode delayed signal I1F are... Figure 9 The falling edge marked by the arrow in the first delayed signal CLK_INT, and the logic delayed signal I2R. Figure 9 The rising edge marked in the second delayed signal CLK_LCDL.

[0131] In another embodiment, refer to Figure 7 This is a circuit diagram of another frequency division unit and mode selection unit provided in an embodiment of this application. Figure 7 In the circuit, the delay phase-locked loop circuit may also include an eighth D flip-flop DFF8, a ninth D flip-flop DFF9, and a fifth inverter N5.

[0132] In this embodiment of the application, the addition of an eighth D flip-flop DFF8, a ninth D flip-flop DFF9, and a fifth inverter N5 to the delay phase-locked loop circuit is to achieve circuit matching. In the actual circuit layout, the two links are made to be exactly the same, thereby ensuring that the environments of the two links are identical.

[0133] In specific implementation, refer to Figure 9 The signal timing diagram shown indicates that the digital control unit 14 first controls the phase detection signal PHASEDET_EN to the first level signal (high level signal) to start the delay phase-locked loop circuit, and then controls the calibration enable signal CAL_EN to the first level signal (high level signal) to enter the coarse adjustment stage.

[0134] In the coarse adjustment stage, the digital control unit 14 first determines whether the received compensation signal O_DLL-COMP is the target value. If it is, it controls the phase detection signal PHASEDET_EN to the second level signal (low level signal), then reduces the current first delay offset code based on the first compensation value, and then controls the phase detection signal PHASEDET_EN to the first level signal (high level signal) to enter the fine adjustment stage. Otherwise, it controls the phase detection signal PHASEDET_EN to the second level signal, increases the current first delay offset code based on the first compensation value, and returns to the step of determining whether the received compensation signal O_DLL-COMP is the target value.

[0135] During the fine-tuning phase, the digital control unit 14 first determines whether the received compensation signal O_DLL-COMP is the target value. If so, it uses the current first delay offset code and the current second delay offset code as the locked delay offset code, controls the phase detection signal PHASEDET_EN to the second level signal (low level signal), controls the calibration enable signal CAL_EN to the second level signal (low level signal), and the adjustment ends, entering the locked state. Otherwise, after controlling the phase detection signal PHASEDET_EN to the second level signal PHASEDET_EN, it increases the current second delay offset code based on the second compensation value and returns to the step of determining whether the received compensation signal O_DLL-COMP is the target value.

[0136] It should be noted that, Figure 9 The signals shown only represent a portion of the signal, so Figure 9 The image only shows the portion of the phase detection signal PHASEDET_EN that flips to a high level; the portion of the phase detection signal PHASEDET_EN that flips from a high level to a low level is not shown.

[0137] Referring to the circuit diagram of the disclosed delay phase-locked loop circuit above, the steps performed by the digital control unit provided in the embodiments of this application will be described in detail, such as... Figure 8 The diagram shown is a schematic flowchart of a control method provided in an embodiment of this application, which specifically includes the following steps:

[0138] S801, control the phase detection signal PHASEDET_EN to be a high-level signal;

[0139] S802: Wait 5 clock cycles, then control the calibration enable signal CAL_EN to be high.

[0140] S803, Set the initial delay offset code to I_DLL_CODE<8:0>:9'b0000000000;

[0141] S804, wait 5 clock cycles, and receive the compensation signal O_DLL_COMP=1;

[0142] S805, control the phase detection signal PHASEDET_EN to be a low level signal, and control the first delay offset code I_DLL_CODE<8:3>+1'b1;

[0143] S806: Wait 5 clock cycles, then control the phase detection signal PHASEDET_EN to be high.

[0144] S807: Wait 5 clock cycles to receive the compensation signal O_DLL-COMP;

[0145] S808. Determine if O_DLL-COMP is 0. If yes, execute S809; otherwise, execute S805.

[0146] S809, Coarse adjustment ends, obtain the current first delay offset code I_DLL_CODE<8:3>;

[0147] S810, control the phase detection signal PHASEDET_EN to be a low level signal, and control the current first delay offset code I_DLL_CODE<8:3>-1'b1;

[0148] S811: Wait 5 clock cycles, then control the phase detection signal PHASEDET_EN to be high.

[0149] S812, control the phase detection signal PHASEDET_EN to be a low level signal, and control the second delay offset code I_DLL_CODE<2:0>+1'b1;

[0150] S813: Wait 5 clock cycles, then control the phase detection signal PHASEDET_EN to be high.

[0151] S814: Wait 5 clock cycles and receive the compensation signal O_DLL-COMP;

[0152] S815. Determine if O_DLL-COMP is 0. If it is, execute S816; otherwise, execute S812.

[0153] S816. Fine-tuning complete. Determine the current first delay offset code and the current second delay offset code: I_DLL_CODE<8:0>=9b'xxxxxx -1 xxx;

[0154] S817, the control calibration enable signal CAL_EN is a low level signal;

[0155] S818 controls the phase detection signal PHASEDET_EN to be a low-level signal.

[0156] It should be noted that the calibration period in this application embodiment can be achieved by configuring different DDR PHY Interface (DFI) periods. Based on the same inventive concept, this application embodiment also provides a chip. The principle of this chip in solving the technical problem is similar to that of any of the delay phase-locked loop circuits described above. The implementation of the chip can refer to the implementation of the delay phase-locked loop circuit, and the repeated parts will not be described again.

[0157] An embodiment of this application provides a chip that includes any of the delay phase-locked loop circuits described above.

[0158] Based on the same inventive concept, this application also provides an electronic device. The principle by which this electronic device solves the technical problem is similar to that of any of the delay phase-locked loop circuits described above. The implementation of the chip can refer to the implementation of the delay phase-locked loop circuit, and the repeated parts will not be described again.

[0159] An electronic device provided in this application includes the chip described above.

[0160] The delay-locked loop (PLL) circuit, chip, and electronic device provided in this application embodiment include a first delay link, a second delay link, an SR latch, and a digital control unit. In the coarse adjustment stage, if the received compensation signal is not the target value, the digital control unit increases the current first delay offset code until the received compensation signal is the target value. The first delay offset code is used to adjust the number of first delay units. In the fine adjustment stage following the coarse adjustment stage, if the received compensation signal is not the target value, the current second delay offset code increases until the received compensation signal is the target value, after which it enters a locked state. The second delay offset code is used to adjust the number of second delay units, and the step time of the first delay unit is greater than the step time of the second delay unit. The first delay link is used to delay the input reference clock signal to obtain a first delayed signal. The second delay link, under the control of the first and second delay offset codes, delays the input reference clock signal to obtain a second delayed signal. The SR latch is used to input the first and second delayed signals and output a compensation signal. Since the delay phase-locked loop circuit is based on a hybrid digital and analog design, the circuit structure is simple. It can achieve high-precision clock phase adjustment through staged adjustment by digital control unit. It also makes the control simple, the locking time short, and the calibration process simple. In addition, the delay phase-locked loop circuit in this application uses an SR latch, which can improve the locking accuracy compared to using a phase detector.

[0161] Those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims and their equivalents, this invention is also intended to include these modifications and variations.

Claims

1. A delay phase-locked loop circuit, characterized in that, include: The system comprises a first delay link, a second delay link, an SR latch, and a digital control unit, wherein the second delay link includes a first delay unit and a second delay unit; The digital control unit is configured to, during the coarse adjustment phase, increase the current first delay offset code when the received compensation signal is not the target value, until the received compensation signal is the target value, wherein the first delay offset code is used to adjust the delay amount of the first delay unit; and during the fine adjustment phase following the coarse adjustment phase, when the received compensation signal is not the target value, increase the current second delay offset code until the received compensation signal is the target value, and then enter a locked state, wherein the second delay offset code is used to adjust the delay amount of the second delay unit, and the step time of the first delay unit is greater than the step time of the second delay unit. The first delay link is used to delay the input reference clock signal to obtain a first delayed signal; The second delay link is used to delay the input reference clock signal under the control of the first delay offset code and the second delay offset code to obtain a second delay signal; The SR latch is used to input the first delay signal and the second delay signal, and output the compensation signal; Specifically, the digital control unit is used for: The current first delay offset code is increased based on the first compensation value; The current second delay offset code is increased based on the second compensation value; In the coarse adjustment stage, after the received compensation signal is the target value, the current first delay offset code is reduced based on the first compensation value, and then the fine adjustment stage begins.

2. The delay phase-locked loop circuit as described in claim 1, characterized in that, It also includes the first inverter; The input terminal of the first inverter is electrically connected to the second output terminal of the SR latch; The SR latch is specifically used to input the first delay signal and the second delay signal, and output a compensation inverse signal; The first inverter is used to input the compensation inverse signal and output the compensation signal.

3. The delay-locked loop circuit as described in claim 2, characterized in that, It also includes a control unit; The control unit is configured to process the input reference clock signal based on the received calibration enable signal and phase detection signal, and output a first clock signal to the first delay link and the second delay link. The first delay link is specifically used to delay the input first clock signal to obtain the first delayed signal; The second delay link is specifically used to delay the input first clock signal under the control of the first delay offset code and the second delay offset code to obtain the second delay signal.

4. The delay phase-locked loop circuit as described in claim 3, characterized in that, The control unit includes a second inverter, an OR gate, and at least one first D flip-flop; In the case of including a first D flip-flop, the D terminal of the first D flip-flop is used to input the calibration enable signal, the Q terminal of the first D flip-flop is electrically connected to the input terminal of the second inverter, the CLK terminal of the first D flip-flop is used to input the reference clock signal, and the RSTB terminal of the first D flip-flop is used to input the phase detection signal. In the case of at least two first D flip-flops, the D terminal of the first first D flip-flop is used to input the calibration enable signal, the Q terminal of the previous first D flip-flop is electrically connected to the D terminal of the next first D flip-flop, the Q terminal of the last first D flip-flop is electrically connected to the input terminal of the second inverter, the CLK terminal of each first D flip-flop is used to input the reference clock signal, and the RSTB terminal of each first D flip-flop is used to input the phase detection signal. The output of the second inverter is electrically connected to the first input of the OR gate; The second input terminal of the OR gate is used to input the reference clock signal, and the output terminal of the OR gate is used to output the first clock signal.

5. The delay-locked loop circuit as described in claim 3, characterized in that, It also includes a logic processing unit and a mode selection unit; The logic processing unit is configured to perform a first logic processing on the first delayed signal to characterize a first mode based on the calibration enable signal and the phase detection signal, to obtain a first mode delayed signal; perform a second logic processing on the first delayed signal to characterize a second mode based on the calibration enable signal and the phase detection signal, to obtain a second mode delayed signal; and perform a third logic processing on the second delayed signal based on the calibration enable signal and the phase detection signal, to obtain a logic delayed signal. The mode selection unit is used to select the output first mode delay signal or the second mode delay signal as the first target delay signal based on the mode selection signal, and to select the output calibration enable signal or logic delay signal as the second target delay signal based on the calibration enable signal. The SR latch is specifically used to input the first target delay signal and the second target delay signal, and output the compensation inverse signal.

6. The delay phase-locked loop circuit as described in claim 5, characterized in that, The logic processing unit includes a fourth D flip-flop, a fifth D flip-flop, a sixth D flip-flop, a seventh D flip-flop, and a third inverter; The D terminal of the fourth D flip-flop is used to input the calibration enable signal. The Q terminal of the fourth D flip-flop is electrically connected to the D terminal of the fifth D flip-flop. The CLK terminals of the fourth and fifth D flip-flops are both used to input the first delay signal. The RSTB terminals of the fourth, fifth, sixth, and seventh D flip-flops are all used to input the phase detection signal. The Q terminal of the fifth D flip-flop is used to output the first mode delay signal; The input terminal of the third inverter is used to input the first delayed signal, and the output terminal of the third inverter is electrically connected to the CLK terminal of the sixth D flip-flop. The D terminal of the sixth D flip-flop is used to input the calibration enable signal, and the Q terminal of the sixth D flip-flop is used to output the second mode delay signal. The D terminal of the seventh D flip-flop is used to input the calibration enable signal, the CLK terminal of the seventh D flip-flop is used to input the second delay signal, and the Q terminal of the seventh D flip-flop is used to output the logic delay signal.

7. The delay phase-locked loop circuit as described in claim 5, characterized in that, The mode selection unit includes a first selector and a second selector; The first input terminal of the first selector is used to input the first mode delay signal, the second input terminal of the first selector is used to input the second mode delay signal, the control terminal of the first selector is used to input the mode selection signal, and the output terminal of the first selector is used to output the first target delay signal. The first input terminal of the second selector is used to input the calibration enable signal, the second input terminal of the second selector is used to input the logic delay signal, the control terminal of the second selector is used to input the calibration enable signal, and the output terminal of the second selector is used to output the second target delay signal.

8. The delay-locked loop circuit as described in claim 5, characterized in that, The digital control unit is specifically used for: After controlling the phase detection signal to a first level signal, the calibration enable signal is controlled to be the first level signal, and the coarse adjustment stage is entered. In the coarse adjustment stage, it is determined whether the received compensation signal is the target value. If so, the phase detection signal is controlled to be a second level signal, the current first delay offset code is reduced based on the first compensation value, and the phase detection signal is controlled to be a first level signal to enter the fine adjustment stage. Otherwise, the phase detection signal is controlled to be a second level signal, the current first delay offset code is increased based on the first compensation value, and the process returns to the step of determining whether the received compensation signal is the target value. During the fine-tuning stage, it is determined whether the received compensation signal is the target value. If so, the current first delay offset code and the current second delay offset code are used as the locked delay offset code, the phase detection signal is controlled to be the second level signal, the calibration enable signal is controlled to be the second level signal, and the locked state is entered. Otherwise, after controlling the phase detection signal to be the second level signal, the current second delay offset code is increased based on the second compensation value, and the process returns to the step of determining whether the received compensation signal is the target value.

9. A chip, characterized in that, Includes the delay phase-locked loop circuit as described in any one of claims 1 to 8.

10. An electronic device, characterized in that, Includes the chip as described in claim 9.

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