Operating system running method and device, vehicle, storage medium and program product

Abstract

Embodiments of the present application provide a kind of operating system running method, device, vehicle, storage medium and program product.The method comprises: obtaining the processor architecture of multicore processor;Determine a single target core in each core of the multicore processor;Based on the processor architecture, the running mechanism of single-core operating system is adjusted, to make the single-core operating system run in the target core.The method realizes that single-core operating system runs in multicore processor.

Description

Technical Field

[0001] This application relates to the field of automotive electronics technology, and in particular to an operating system operation method, device, vehicle, storage medium, and program product. Background Technology

[0002] Multi-core processors, with their integrated processing cores, local storage (such as program storage area and data storage area) and abundant interrupt and peripheral resources, are gradually becoming key hardware platforms for core scenarios such as vehicle powertrain control, body domain controller, and autonomous driving domain controller.

[0003] In the existing technology, some lightweight real-time operating systems are mainly designed for general-purpose single-core processors. There is a lack of mature and universal methods for running on multi-core processor platforms. Therefore, there is an urgent need for a solution that can enable a single-core operating system to run on a multi-core processor. Summary of the Invention

[0004] This application provides an operating system running method, apparatus, vehicle, storage medium, and program product, which are used to design a unified operating mechanism for a single-core operating system, so that the single-core operating system can run on a multi-core processor using this operating mechanism.

[0005] In a first aspect, embodiments of this application provide an operating system running method, including:

[0006] Obtain the processor architecture of a multi-core processor;

[0007] Identify a single target core among the individual cores of the multi-core processor;

[0008] Based on the processor architecture, the operating mechanism of the single-core operating system is adjusted so that the single-core operating system runs within the target kernel.

[0009] In one possible implementation, adjusting the operating mechanism of the single-core operating system based on the processor architecture includes:

[0010] If the processor architecture is the first target architecture, then when the single-core operating system creates a thread in the target kernel, it calls the context recovery instruction of the target kernel to construct the initial context of the thread;

[0011] When the single-core operating system executes a thread, it calls the privileged instruction of the multi-core processor to switch to the execution of the first thread, which is the thread with the highest priority in the target kernel and is in a pending execution state;

[0012] When the single-core operating system performs thread switching, it invokes the privileged instruction to achieve context switching between the threads.

[0013] In one possible implementation, the adjustment to the operating mechanism of the single-core operating system includes:

[0014] When the single-core operating system executes an interrupt handling function or an exception handling function, it calls the context recovery instruction of the target kernel to save the context of the interrupted target interrupt handling function to the context saving area.

[0015] When the single-core operating system requests to exit execution, the context recovery instruction and the return instruction of the target kernel are invoked to control the single-core operating system to exit the execution of the interrupt handling function or exception handling function.

[0016] In one possible implementation, the adjustment to the operating mechanism of the single-core operating system includes:

[0017] When the single-core operating system enters the execution interrupt handling function or exception handling function each time, the state function of the single-core operating system is controlled to increment the counter.

[0018] Each time the single-core operating system exits the execution of the interrupt handling function or the exception handling function, it controls the state function to decrement its counter.

[0019] In one possible implementation, the method further includes: allocating a corresponding private memory region for each core using the hardware isolation mechanism of the multi-core processor.

[0020] In one possible implementation, invoking the target kernel's context recovery instruction to construct the thread's initial context includes:

[0021] The first context recovery instruction of the target kernel is invoked to allocate a core storage area from the context storage area of ​​the target kernel to the thread, wherein the core storage area is used to store the core context of the thread;

[0022] The second context recovery instruction of the target kernel is invoked to allocate a non-core storage area from the context storage area to the thread, wherein the non-core storage area is used to store the non-core context of the thread.

[0023] The core storage region is linked to the non-core storage region, and the hardware registers of the target kernel are updated. The hardware registers are used to track the region link relationship between the core storage region and the non-core storage region.

[0024] In one possible implementation, the step of calling the context recovery instruction of the target kernel to save the context of the interrupted target interrupt handling function to the context saving area includes: when the interrupt handling function or the exception handling function is detected to have occurred, and the target kernel automatically saves the core context of the target interrupt handling function to the core saving area, the non-core context of the target interrupt handling function is saved to the non-core saving area by the context recovery instruction.

[0025] In one possible implementation, it also includes:

[0026] Based on the count value of the state function, verify whether the interrupt handling function or the exception handling function is nested.

[0027] In one possible implementation, adjusting the operating mechanism of the single-core operating system based on the processor architecture includes:

[0028] If the processor architecture is the second target architecture, then when the single-core operating system creates a thread in the target kernel, it uses the general-purpose registers and special registers in the target kernel to construct the initial context of the thread;

[0029] When the single-core operating system requests to execute a thread, it executes the second thread in the target kernel, which is the thread that is in the ready state among all threads;

[0030] When the single-core operating system performs thread switching, it invokes privileged instructions of the multi-core processor to achieve context switching between threads in the target kernel.

[0031] In one possible implementation, the adjustment to the operating mechanism of the single-core operating system includes:

[0032] When the single-core operating system enters the execution interrupt handling function or exception handling function, it saves the register state corresponding to the interrupted target interrupt handling function to the context saving area. The register state includes the state of the general-purpose registers and special registers corresponding to the target interrupt handling function.

[0033] When the single-core operating system exits the execution of the interrupt handling function or the exception handling function, the state of the general-purpose registers and the special registers is restored using the context saving area so as to continue the execution of the target interrupt handling function.

[0034] In one possible implementation, after running the single-core operating system within the target kernel, the method further includes:

[0035] Obtain the operation mechanism adjustment method corresponding to the single-core operating system running within the target kernel;

[0036] The single-core operating system is adjusted using the aforementioned operating mechanism to allow it to run on each kernel of the multi-core processor.

[0037] Secondly, embodiments of this application provide an operating system running device, comprising:

[0038] The acquisition module is used to obtain the processor architecture of a multi-core processor;

[0039] A determination module is used to determine a single target core among the individual cores of the multi-core processor;

[0040] The adjustment module is used to adjust the operating mechanism of the single-core operating system based on the processor architecture, so that the single-core operating system runs within the target kernel.

[0041] Thirdly, embodiments of this application provide a vehicle, including a vehicle body, a processor, and a memory; the memory stores computer execution instructions; the processor executes the computer execution instructions stored in the memory, causing the processor to perform the method described above.

[0042] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the first aspect and / or various possible implementations of the first aspect.

[0043] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the first aspect and / or various possible implementations of the first aspect.

[0044] The operating system running method, apparatus, vehicle, storage medium, and program product provided in this application embodiment can enable a single-core operating system to run on a multi-core processor by selecting a target kernel from among the kernels of a multi-processor and adaptively adjusting the running mechanism of a single-core operating system based on the multi-processor architecture. Attached Figure Description

[0045] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0046] Figure 1 The schematic diagram of the operating system operation method provided in this application;

[0047] Figure 2 A flowchart illustrating the simple method for constructing a thread context is provided for embodiments of this application.

[0048] Figure 3 A flowchart of an operating system operation method provided in an embodiment of this application;

[0049] Figure 4 A flowchart of an operating system operation method provided in another embodiment of this application;

[0050] Figure 5 A schematic diagram of the structure of the operating system running device provided in this application.

[0051] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0052] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application.

[0053] As automotive electronic and electrical architectures evolve towards centralization and intelligence, the demands for real-time performance and reliability in on-board electronic control units (ECUs) and industrial control systems continue to increase. High-performance embedded processors are widely used in critical control applications. Multi-core processor architectures, represented by Infineon TriCore and RH850, integrate multiple processing cores, local storage (such as program and data storage areas), and abundant interrupt and peripheral resources within a single chip. They possess high performance and functional safety support capabilities, and have become an important foundational platform in fields such as automotive electronics.

[0054] While some existing lightweight real-time operating systems have the characteristics of strong scheduling determinism and high execution efficiency, and can be widely used in embedded systems, these operating systems are mainly single-core operating systems designed for single-core processors and cannot run on multi-core processor architectures.

[0055] In practical applications, there is a lack of mature and universal methods for running single-core operating systems on multi-core processor platforms. Furthermore, due to the unique characteristics of the TriCore processor in terms of context management mechanisms, memory structure, and interrupt hierarchy, it is difficult to develop standardized operating schemes for single-core operating systems, resulting in high porting complexity, poor system consistency, and insufficient resource utilization efficiency. Therefore, there is an urgent need to propose a method for running single-core operating systems suitable for multi-core processors such as TriCore and RH850.

[0056] To address the aforementioned issues, the operating system running method provided in this application first isolates the kernels of a multi-core processor. Then, it adjusts the operating mechanism of a single-core operating system designed for single-core processors to run within a single kernel. This operating mechanism is then reused, allowing the single-core operating system to continue running within other kernels, thus enabling its operation on a multi-core processor. Because the operating mechanism is reusable, a standardized operating scheme can be formed to achieve the operation of a single-core operating system on a multi-core processor platform.

[0057] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0058] Figure 1 The schematic diagram of the operating system operation method provided in this application is as follows: Figure 1 As shown, the method includes:

[0059] Step 110: Obtain the processor architecture of the multi-core processor;

[0060] Step 120: Identify a single target core among the individual cores of the multi-core processor;

[0061] Step 130: Based on the processor architecture, adjust the operating mechanism of the single-core operating system so that the single-core operating system runs within the target kernel.

[0062] For steps 110 and 120 above, the multi-core processor, as the platform hardware for running this method, includes at least multiple kernels capable of independently executing instruction streams, and provides the underlying execution capabilities corresponding to privileged instructions, context recovery instructions, and return instructions.

[0063] The processor architecture may include a first target architecture and a second target architecture. For example, the first target architecture may be a TriCore processor, and the second target architecture may be an RH850 processor.

[0064] The target kernel is a single kernel selected from multiple kernels to run a single-core operating system. Within this single-core operating system, thread creation, thread scheduling, thread return, interrupt handling, and exception handling are all performed.

[0065] For example, the target kernel can be determined by a fixed kernel number, such as setting the kernel numbered 1 as the target kernel.

[0066] Regarding step 130 above, the processor architecture can be divided into two types: TriCore processors and RH850 processors. Different processor architectures have different ways of adjusting the operating mechanism of a single-core operating system. The system operating mechanism is used to define how a single-core operating system runs within the target kernel and to uniformly constrain the context management relationships during thread creation, thread scheduling, thread return, and interrupt and exception handling.

[0067] A single-core operating system, as the object being run, is executed only within a predetermined target kernel. Its kernel-mode code, scheduler, thread control block management logic, and interrupt and exception management logic are all confined to the execution environment corresponding to that target kernel.

[0068] For example, a single-core operating system can be a lightweight real-time operating system, characterized by strong scheduling determinism and high execution efficiency, and is widely used in embedded systems. However, single-core operating systems are mainly designed for general-purpose single-core processors, and there is a lack of mature and universal methods for running on multi-core processor platforms. Therefore, appropriate modifications (such as using the operating mechanism provided in this embodiment) are required to run on multi-core processors.

[0069] Taking the TriCore processor as the first target architecture as an example, the TriCore processor has its own characteristics in terms of context management mechanism, memory structure and interrupt system. When a single-core operating system is ported to it, it is difficult to form a standardized running scheme, resulting in high porting complexity, poor system consistency and insufficient resource utilization efficiency.

[0070] Therefore, when the processor architecture is a TriCore processor, the specific adjustments to the single-core operating system operation mechanism can include: (1) thread mechanism adjustment; (2) interrupt handling function and exception handling function processing mechanism adjustment.

[0071] In some implementations, taking the TriCore processor architecture as an example, the adjustments to the threading mechanism of a single-core operating system specifically include:

[0072] When a single-core operating system creates a thread in the target kernel, it calls the target kernel's context restoration instruction to construct the thread's initial context.

[0073] When a single-core operating system executes a thread, it calls the privileged instructions of the multi-core processor to switch to the execution of the first thread in the target kernel. The first thread is the thread with the highest priority in the target kernel that is in a pending execution state.

[0074] When a single-core operating system performs thread switching, it invokes privileged instructions to achieve context switching between threads.

[0075] Specifically, the thread creation function of a single-core operating system constructs the initial context of a thread using the context recovery instructions of the target kernel; the thread scheduling function of a single-core operating system switches to the execution of the target thread using privileged instructions of a multi-core processor, with the target thread being the highest priority thread among all threads in the target kernel that is in a pending execution state; and the thread return function of a single-core operating system implements context switching between threads in the target kernel using privileged instructions of a multi-core processor.

[0076] In this embodiment, the thread creation function is used to establish the initial context of the thread, and the thread scheduling function is used to select and switch to the highest priority thread that is in a pending execution state within the target kernel for execution by the single-core operating system. The thread return function is used to complete the context switch between threads when the thread ends, is interrupted, or an exception occurs.

[0077] To ensure operational isolation, non-target kernels do not participate in the scheduling decisions of this single-core operating system, nor do they read or write the target kernel's context storage area and state function counts.

[0078] In this embodiment, the thread creation function can be _tx_thread_stack_build() in a single-core operating system. The thread creation function is used to create a thread and construct the initial register context required for the thread to be scheduled for execution for the first time.

[0079] Additionally, the context recovery instruction can refer to the RSLCX instruction, which is used to assist in the generation and subsequent recovery of the thread's initial context.

[0080] The initial context of a thread describes the program counter, stack pointer, status register, parameter register, and link information related to the return path that a thread needs when it is first created.

[0081] In this embodiment, the thread scheduling function is used to select the thread that should be running from the set of threads managed by the target kernel, and to switch from the current execution context to the target thread execution context with the help of privileged instructions provided by the multi-core processor.

[0082] Privileged instructions are controlled instructions executed by the processor at a privilege level. They can directly operate system registers, context switching registers, or trigger architecture-defined thread switching entry points, and are therefore applicable to privilege escalation and context loading involved in the scheduling process.

[0083] For example, the thread scheduling function refers to _tx_thread_schedule() in a single-core operating system, and the privileged instruction refers to the SYSCALL instruction in a TriCore processor.

[0084] After the target kernel is initialized, _tx_thread_schedule() is called to start scheduling. _tx_thread_schedule() initiates a system call through the SYSCALL instruction to switch to the highest priority thread that is already in the ready state in the system, namely the target thread.

[0085] In this embodiment, the thread return function is used to complete the handover of execution between the current thread and the next thread to be run when the thread finishes execution, exits voluntarily, waits for an event, or triggers a return operation in the kernel control flow. The thread return function and the thread scheduling function are related; the former focuses more on exiting the current thread context and entering a new thread context, while the latter focuses more on determining the new execution target.

[0086] The thread return function refers to _tx_thread_system_return() in a single-core operating system. _tx_thread_system_return() initiates a system call through the SYSCALL instruction to achieve context switching between threads.

[0087] In addition, after the target kernel is determined, the target kernel can be initialized to support the operation of a single-core operating system, and the code segment, data segment and necessary boot parameters of the single-core operating system image can be loaded into the storage space accessible to the target kernel.

[0088] After adjusting the operating mechanism, the thread creation function, thread scheduling function, and thread return function in the single-core operating system no longer execute across the multi-core processor, but instead operate only on the thread set and hardware register state on the target kernel.

[0089] In some embodiments, taking the TriCore processor architecture as an example, the adjustments to the processing mechanisms of interrupt handlers and exception handlers specifically include:

[0090] When a single-core operating system executes an interrupt handler or exception handler, it calls the target kernel's context recovery instruction to save the context of the interrupted target interrupt handler to the context saving area.

[0091] When a single-core operating system requests to exit execution, it invokes the context recovery instruction and the target kernel's return instruction to control the single-core operating system to exit the execution interrupt handling function or exception handling function.

[0092] In this embodiment, the interrupt handler is used to respond to peripheral events, timer events, or inter-core notifications, while the exception handler is used to respond to illegal access, instruction exceptions, alignment errors, or other exceptions defined by the architecture. Regardless of whether the interrupt handler or the exception handler is entered, the interrupted object may be a thread currently running on the target kernel, or it may be another interrupt handler that has not yet exited. Therefore, the context needs to be saved uniformly at the entry point.

[0093] Furthermore, after the interrupt handler or exception handler completes event handling, clears the interrupt source, or records exception information, it needs to exit the current processing level in the order corresponding to when it entered, and restore the previously interrupted execution object.

[0094] The return instruction can refer to the RFE instruction in the TriCore processor. The status function can include _tx_thread_system_state in a single-core operating system.

[0095] In addition, in some implementations, whether it is a TriCore processor or an RH850 processor, when the single-core operating system enters the interrupt handling function or exception handling function each time, it needs to control the status function to increment the counter; and when the single-core operating system exits the interrupt handling function or exception handling function each time, it needs to control the status function to decrement the counter.

[0096] In a single-core operating system, every time the interrupt handler is entered, _tx_thread_system_state++ needs to be controlled to increment the count, and before exiting the interrupt handler, _tx_thread_system_state-- needs to be controlled to decrement the count.

[0097] In some implementations, assuming the initial value of _tx_thread_system_state is zero, after entering and exiting an interrupt handler once, the count value of _tx_thread_system_state will be restored to the initial value of zero through increment and decrement operations. Therefore, it is possible to determine whether nested interrupt handlers have occurred by checking whether the count value of _tx_thread_system_state is zero.

[0098] Additionally, the status function can include _tx_thread_esr_count from a single-core operating system. _tx_thread_esr_count++ is incremented each time an exception handling function is entered, and _tx_thread_esr_count-- is decremented each time an exception handling function is exited.

[0099] For example, assuming the initial value of _tx_thread_esr_count is zero, after entering an exception handling function once and then exiting an exception handling function once, the count value of _tx_thread_esr_count will be restored to the initial value of zero through increment and decrement operations. Therefore, it is possible to determine whether nested exception handling functions have occurred by checking whether the count value of _tx_thread_esr_count is zero.

[0100] In some implementations, the private random access memory (RAM) data of each kernel is deployed to the data scratch-pad RAM (DSRAM) area of ​​each kernel.

[0101] For example, for the TriCore processor, the Context Save Area (CSA) linked list area, scheduler instance, and Thread Stack need to be deployed to the DSRAM area of ​​each core.

[0102] The DSRAM region is a kernel-private, tightly coupled data RAM used to store dynamic management data of a single-core operating system, enabling completely isolated and deterministic real-time scheduling between kernels.

[0103] In addition, in some embodiments, after a single-core operating system runs on a single target kernel, if its running status is good and no faults occur, the corresponding operating mechanism adjustment method of the single-core operating system running in the target kernel can be obtained; then the operating mechanism adjustment method is reused to adjust the single-core operating system so that the single-core operating system runs in each kernel of the multi-core processor, thereby realizing the operation of the single-core operating system in the multi-core processor.

[0104] The operating system running method provided in this application embodiment adjusts the single-core operating system according to the different processor architectures, so that the single-core operating system first runs on the target kernel. After the adjusted single-core operating system can run normally on the target kernel, it is then ported to other kernels, thereby enabling the single-core operating system to run on a multi-core processor.

[0105] The following examples illustrate in detail how to adjust the operating mechanism of a single-core operating system.

[0106] In some embodiments, regardless of whether the multi-core processor is the TriCore processor mentioned above or the RH850 processor, before running the single-core operating system on the target kernel, the hardware isolation mechanism of the multi-core processor can be used to allocate a corresponding private memory region for each core in the multi-core processor.

[0107] For example, taking the TriCore processor as an example of a multi-core processor, the private memory area corresponding to each core includes a context saving area, an interrupt vector table area, and an exception vector table area. The context saving area includes a CSA area and a CSA linked list area.

[0108] In this system, independent address spaces can be allocated for each kernel based on a preset memory layout table, and the corresponding context storage area, interrupt vector table area, and exception vector table area can be mapped to the kernel's dedicated address range.

[0109] Subsequently, the context initialization value corresponding to the target kernel can be written to the context storage area, the interrupt vector table entry can be written to the interrupt vector table area, and the exception vector table entry can be written to the exception vector table area, so that the target kernel can directly read the required data from the local private memory area when performing thread creation, thread switching, interrupt handling, and exception handling.

[0110] In addition, when allocating private memory regions for each kernel, proprietary symbols can be generated for each private memory region and a correspondence can be established with its kernel to avoid confusion between the private memory regions and the kernels.

[0111] In this embodiment, hardware isolation is used to confine the context saving, vector entry location, and exception entry location of each kernel to their own independent memory range, so that the target kernel's runtime environment, vector jump information, and exception response information are separated from each other, and cooperates with the single-core operating system's operating mechanism on the target kernel to complete the localized resource access required for thread switching and interrupt exception response.

[0112] In addition, taking the RH850 processor as an example of a multi-core processor, the private memory area corresponding to each core includes the interrupt vector table area, the exception vector table area, the stack area for each system mode, and information for each section (including start and end addresses, size, etc.).

[0113] This application embodiment divides each kernel into its own private memory region, which makes the context data and vector table data of each kernel no longer share the same memory resources. The access boundaries between kernels are clear, the state saving and restoration during thread switching is more stable, and the jump entry point when interrupts and exceptions are entered is also consistent, thereby improving the determinism and system stability of the single-core operating system running on a multi-core platform.

[0114] Furthermore, in some embodiments, continuing to take the TriCore processor as an example of a multi-core processor, after dividing each core into its own private memory region, the general-purpose registers, context save region and registers in the context save region, interrupt vector table and interrupt vector register, exception vector table and exception vector register, thread scheduler, threads, and interrupt handling functions of each core can be further initialized.

[0115] Among them, the general-purpose registers are used to carry the basic running state after the kernel starts. Their initial values ​​can be written uniformly by the boot code after the kernel is powered on and reset, so that each kernel enters a controllable waiting state.

[0116] The registers in the context saving area include registers for storing the return address, stack pointer, and status flags. Preset base values ​​can be written to them during initialization so that the thread creation function can directly construct the initial context based on this area.

[0117] The interrupt vector register is used to point to the address where the vector table is located. Together, the two enable the corresponding interrupt handling function to be quickly located when an interrupt is triggered.

[0118] The configuration of the exception vector table and exception vector register corresponds to that of the interrupt vector table, and is used to locate and jump to exception entry points.

[0119] The thread scheduler is initialized as an independent instance in each kernel and associated with the thread control block, ready queue, and priority information. During initialization, threads write their initial entry address, stack space, and runtime state information.

[0120] The interrupt handler completes the entry binding during the initialization phase and establishes a mapping relationship with the corresponding vector table entry.

[0121] When a multi-core processor is operating, each core first initializes its registers, vector tables, and thread scheduler. Then, it loads the thread and interrupt handling entry points into the corresponding entries, enabling each core to have independent thread scheduling, interrupt response, and exception handling capabilities. As a result, thread creation, thread scheduling, and the saving and restoring of the context when entering and exiting an interrupt can all be completed based on pre-defined context resources, thus forming a unified operating environment.

[0122] For example, initializing the TriCore processor's runtime environment specifically includes:

[0123] 1. Each kernel initializes its own general-purpose registers;

[0124] 2. Each kernel initializes its own CSA region and CSA-related registers;

[0125] 3. Each core initializes its own interrupt vector table and interrupt vector register;

[0126] 4. Each core initializes its own exception vector table and exception vector register;

[0127] 5. Each core initializes its own scheduler, threads, interrupt handlers (Interrupt ServiceRoutine, ISR), etc.

[0128] In other embodiments, continuing with the TriCore processor as an example of a multi-core processor, at least one idle thread can be created for each core. This idle thread is used to run when the core is idle.

[0129] Idle threads can be created by the thread creation function after each kernel completes initialization, and their stack space and initial context are written into the private memory area of ​​the corresponding kernel, so that they form a one-to-one correspondence with that kernel.

[0130] In addition, multiple idle threads can be configured on the same kernel to adapt to different idle management strategies. Idle threads can maintain a low-power waiting state during operation, or poll the target kernel's operating load and thread readiness status. When a new thread enters the waiting state, the thread scheduling function uses privileged instructions of the multi-core processor to switch to the target thread for execution, thus enabling the kernel to maintain a controlled running state even when no business threads are available to run.

[0131] The initial context of the idle thread can be constructed using the context recovery instruction of the target kernel. Its return entry is consistent with the thread return function, so that the execution context of the thread to be switched can be accurately restored when exiting the idle state.

[0132] For example, after creating an idle thread for each kernel, the idle thread is run if there is no higher priority thread in that kernel or if an interrupt needs to be run.

[0133] Running an idle thread allows the kernel to enter a low-power waiting state, avoiding idling and energy consumption.

[0134] In this embodiment, when there are no high-priority threads or interrupts, the system switches to an idle thread. Since the idle thread continuously occupies the target kernel's running context, the target kernel will not be completely idle and lose its scheduling anchor during the idle period. Once a new thread or interrupt is ready, it can be switched to execute in a timely manner through thread scheduling and thread return. This allows the target kernel's running state to remain continuous, the context boundary during the idle period to be clear, and the system to be able to quickly recover and switch when a new thread arrives, ensuring that the real-time operating system has stable running performance under both low-load and burst-load scenarios.

[0135] In other embodiments, the TriCore processor is used as an example of a multi-core processor. Figure 2 The flowchart for constructing a thread context using a simplified method provided in the embodiments of this application is as follows: Figure 2 As shown, it includes the following steps:

[0136] Step 210: Invoke the first context recovery instruction of the target kernel to allocate the kernel save area from the context save area of ​​the target kernel to the thread.

[0137] The core storage area is used to store the core context of a thread.

[0138] Step 220: Invoke the second context recovery instruction of the target kernel to allocate a non-kernel save area from the context save area to the thread.

[0139] The non-core storage area is used to store the non-core context of a thread.

[0140] Step 230: Link the kernel save region with the non-kernel save region and update the target kernel's hardware registers.

[0141] Among them, hardware registers are used to track the region linking relationships between the core storage region and non-core storage regions.

[0142] In this embodiment, the core save area is used to carry the register context and return control information automatically saved by the target kernel, the non-core save area is used to carry the remaining registers and status information that need to be restored, and the context save area is composed of the core save area and the non-core save area.

[0143] Taking the TriCore processor mentioned above as an example of a multi-core processor, the hardware register can be a special function register within the TriCore core, such as the PCXI (Previous Context Information) register, used to track and manage the linked list pointers and control information of this context data. During context switching, the PCXI register is similar to a "linked list head pointer," telling the kernel which CSA is currently in use, where the previous CSA is, and how to find the complete context chain.

[0144] In this embodiment, the specific implementation process of thread context construction is as follows:

[0145] In a single-core operating system, the _tx_thread_stack_build() function uses two RSLCX instructions (i.e., the first context recovery instruction and the second context recovery instruction) to request two free CSAs from the space CSA linked list to construct the thread's context.

[0146] The first CSA serves as the Upper CSA (i.e., the kernel save area) for this thread; the second CSA serves as the Lower CSA (i.e., the non-kernel save area) for this thread.

[0147] In the TriCore multi-core processor architecture, the Upper CSA and Lower CSA are two physical storage nodes that constitute a complete task context. They are 16-word storage areas in memory, specifically used to store the kernel's general-purpose register set. For efficient management, the TriCore multi-core processor does not use the traditional stack-based approach, but instead splits the registers into upper and lower halves and stores them separately in the two CSAs.

[0148] The Upper CSA contains the core information that determines the program's "flow" and "state." When an interrupt or exception occurs, the TriCore hardware automatically saves and switches the Upper CSA, which is the hardware foundation for achieving fast interrupt response. The Lower CSA primarily carries temporary data from the computation process; unlike the Upper CSA, the TriCore hardware does not automatically save the Lower CSA during an interrupt.

[0149] When a single-core operating system performs context switching or interrupt nesting, its save and restore processes are as follows: (1) Save process: The hardware automatically saves the Upper CSA; the single-core operating system executes the RSLCX instruction to save the Lower CSA. (2) Restore process: The single-core operating system first executes the RSLCX instruction to restore the Lower CSA; the hardware then restores the Upper CSA and jumps.

[0150] Further, initialize the registers in these two CSAs, then link the two CSAs together, and then update the PCXI register;

[0151] When initializing registers in the two types of storage areas, the program counter register can be written to the thread entry address, the status register can be written to the preset initial state, the stack pointer register can be written to the thread-specific stack top address, and the remaining general-purpose registers can be written to the agreed initial values, so that the thread can directly enter the preset execution path when it first resumes.

[0152] For example, registers in the core and non-core save regions can be initialized before linking the core save region with the non-core save region.

[0153] After initialization, the core save regions and non-core save regions are linked according to a preset link relationship, so that the complete context can be read in the associated order when the target kernel performs context restoration. Subsequently, the target kernel's hardware registers are updated to point to the valid address of this link or the address of the first save region, so that subsequent restoration instructions can directly locate the thread context from the hardware registers.

[0154] The embodiments of this application construct the thread context in the above manner. The initial thread context is composed of two storage areas and a clear entry point is established through hardware registers. This enables the thread creation result to be consistent with the recovery mechanism of the target kernel, reduces ambiguity in context positioning, and improves the recovery accuracy and running continuity when the thread is first scheduled.

[0155] Based on the above embodiments, in some embodiments, the TriCore processor is still used as an example of a multi-core processor. When an interrupt handling function or an exception handling function is detected and the target kernel automatically saves the core context of the target interrupt handling function to the core storage area, the non-core context of the target interrupt handling function is saved to the non-core storage area through the context recovery instruction.

[0156] In this embodiment, the core storage area can refer to the Upper CSA mentioned above; the non-core storage area can refer to the Lower CSA mentioned above.

[0157] Interrupt handlers and exception handlers are treated as interrupted objects here. When entering the corresponding handler, it is first determined whether the current running context corresponds to the target interrupt handler or thread. Then, based on whether the target kernel has completed the automatic saving of the kernel context, it is decided whether to continue executing the non-kernel context saving operation.

[0158] For example, taking the TriCore processor mentioned above as a multi-core processor, the specific implementations of the interrupt handling function and exception handling function are as follows:

[0159] (1) Implement the interrupt handling function: Since the TriCore processor automatically saves the Upper CSA when an interrupt occurs, the interrupted Thread or the Lower CSA of the ISR is saved by the RSLCX instruction when entering the ISR, and the RSLCX and RFE instructions are used to exit the ISR.

[0160] (2) Implement the exception handling function. Since the TriCore processor automatically saves the Upper CSA when an exception occurs, when entering the exception handling function (Exception Service Routine, ESR), the interrupted Thread or the Lower CSA of the ISR is saved by the RSLCX instruction, and the RSLCX and RFE instructions are used to exit the ESR.

[0161] In this embodiment, based on the fact that the target kernel has automatically saved the core context, only the remaining non-core context is saved, so that the saved content of the interrupted object is complete and the correspondence is clear, thereby ensuring that the execution state before the interruption or exception can be restored when returning later, and maintaining the consistency and determinism of interrupt handling and thread operation on the multi-core platform.

[0162] Taking the TriCore processor mentioned above as an example of a multi-core processor, Figure 3 The flowchart of the operating system operation method provided in the embodiments of this application is as follows: Figure 3 As shown, it includes the following steps:

[0163] Step 310: Prepare a private memory region for each kernel and generate proprietary symbols for it. Specifically, this includes: (1) CSA linked list region; (2) interrupt vector table region; (3) exception vector table region.

[0164] Step 320: Initialize the TriCore processor's runtime environment. This includes:

[0165] 1. Each core initializes its own general-purpose registers;

[0166] 2. Each core initializes its own CSA region and CSA-related registers;

[0167] 3. Each core initializes its own interrupt vector table and interrupt vector register;

[0168] 4. Each core initializes its own exception vector table and exception vector register;

[0169] 5. Each core initializes its own scheduler, threads, ISR, etc.

[0170] Step 330: Each kernel creates an idle thread, which runs when there are no higher-priority threads or interrupts running.

[0171] Step 340: Construct the thread's context using a simplified method when creating the thread.

[0172] This step specifically includes: in _tx_thread_stack_build(), two free CSAs are requested from the space CSA linked list using two RSLCX instructions to construct the Thread context.

[0173] The first CSA serves as the Upper CSA of the Thread; the second CSA serves as the Lower CSA of the Thread.

[0174] Then initialize the registers in the two CSAs, link the two CSAs together, and then update the PCXI register.

[0175] Step 350: After each kernel initialization is complete, the _tx_thread_schedule() function is called to start scheduling. _tx_thread_schedule() initiates a system call via the SYSCALL instruction, switching to the highest priority thread that is already in the ready state in the system.

[0176] Step 360: The _tx_thread_system_return() function initiates a system call via the SYSCALL instruction to achieve context switching between threads.

[0177] Step 370: Implement the interrupt handling function.

[0178] Because the TriCore processor automatically saves the Upper CSA when an interrupt occurs, the interrupted Thread or the Lower CSA of the ISR is saved using the RSLCX instruction when entering the ISR, and the ISR is exited using the RSLCX and RFE instructions.

[0179] Step 380: Implement the exception handling function.

[0180] Because the TriCore processor automatically saves the Upper CSA when an exception occurs, the interrupted Thread or the Lower CSA of the ISR is saved by the RSLCX instruction when entering the ESR, and the RSLCX and RFE instructions are used to exit the ESR.

[0181] Step 390: Each time the interrupt handler is entered, the status function _tx_thread_system_state++ is incremented, and the status function _tx_thread_system_state-- is decremented before exiting the interrupt handler.

[0182] For example, if the initial value of _tx_thread_system_state is 0, the nesting of ISRs is determined by whether _tx_thread_system_state is 0 each time the ISR is entered.

[0183] Step 3100: Each time the exception handling function is entered, the status function _tx_thread_esr_count is incremented, and the status function _tx_thread_esr_count is decremented before exiting the exception handling function.

[0184] For example, if the initial value of _tx_thread_esr_count is 0, the nesting of ESRs is determined by whether _tx_thread_esr_count is 0 each time it enters an ESR.

[0185] Step 3110: Deploy the private RAM data of each kernel to the DSRAM region of each kernel. The private RAM data includes the CSA linked list region, scheduler instance, thread stack, etc.

[0186] The operating system running method provided in this application simplifies the adaptation process, shortens the adaptation time, and improves adaptation efficiency. Furthermore, it reduces the operating system's response time and improves real-time performance by simplifying the construction of a Thread Stack and quickly switching contexts.

[0187] In some embodiments, if the processor architecture is the second target architecture, such as the RH850 processor, the single-core operating system needs to be adjusted as follows:

[0188] When a single-core operating system creates a thread in the target kernel, it uses the general-purpose registers and special registers in the target kernel to construct the thread's initial context.

[0189] When a single-core operating system requests to execute a thread, it executes the second thread in the target kernel. The second thread is the thread that is in the ready state among all the threads.

[0190] When a single-core operating system performs thread switching, it invokes privileged instructions from a multi-core processor to achieve context switching between threads within the target kernel.

[0191] Furthermore, continuing to use the RH850 processor architecture as an example, in some implementations, the single-core operating system can be adjusted as follows:

[0192] When a single-core operating system enters the execution interrupt handling function or exception handling function, it saves the register state corresponding to the interrupted target interrupt handling function to the context saving area. The register state includes the state of the general-purpose registers and special registers corresponding to the target interrupt handling function.

[0193] When a single-core operating system exits the execution of an interrupt handler or exception handler, it uses the context save area to restore the state of general-purpose registers and special registers in order to continue executing the target interrupt handler.

[0194] For processors with the RH850 architecture, Figure 4 A flowchart of an operating system operation method provided in another embodiment of this application is shown below. Figure 4 As shown, it includes the following steps:

[0195] Step 410: Allocate a private region for each core and generate proprietary symbols for it during the linking phase. Specifically, this includes:

[0196] 1. Interrupt vector table area;

[0197] 2. Anomaly vector table region;

[0198] 3. Stack area for each system mode;

[0199] 4. Information for each section (including start and end addresses, size, etc.);

[0200] Step 420: Initialize the RH850 processor's runtime environment. This includes:

[0201] 1. Each core initializes its own general-purpose registers (r1-r31) and special-purpose registers (including but not limited to PSW, EIPC, EIPSW, FEPC, FEPSW, etc.);

[0202] 2. Each core initializes its own interrupt vector table and interrupt vector register;

[0203] 3. Each core initializes its own exception vector table and exception vector register;

[0204] 4. Each core initializes its own copytable. The main core initializes common sections accessible to all cores, while sections accessible only to each core are initialized by that core. Initialization includes clearing the .bss segment, copying the .data segment, and copying the .text segment running in the RAM region.

[0205] 5. Each core initializes its own scheduler, threads, ISR, etc.

[0206] Step 430: When creating a thread, use a simple method to construct the context of the target thread.

[0207] The thread's context includes general-purpose registers (R1-R31), special-purpose registers PSW, PC, and PLMR. The `_tx_thread_stack_build()` function initializes the thread's context and assigns initial values ​​to the special-purpose registers.

[0208] Step 440: After each core is initialized, call the _tx_thread_schedule() function to start scheduling.

[0209] The `_tx_thread_schedule()` function pops the context of the first thread that is in a ready state.

[0210] Step 450: The _tx_thread_system_return() function initiates a system call via the SYSCALL instruction to achieve context switching between threads.

[0211] Step 460: Implement the interrupt handling function.

[0212] Because the RH850 processor automatically saves the PSW and PC registers (such as EIPSW, EIPC, FEPSW, FEPC, etc.) in the relevant mode when an interrupt occurs, the software needs to save the general-purpose registers, read and save the PSW and PC registers in the relevant mode, as well as the PLMR register, into the context when an interrupt occurs. Upon exiting the interrupt, these registers are restored sequentially.

[0213] Step 470: Implement the exception handling function.

[0214] Because the RH850 processor automatically saves the PSW and PC registers (such as EIPSW, EIPC, FEPSW, FEPC, etc.) in the relevant mode when an exception occurs, the software needs to save the general-purpose registers, read and save the PSW and PC registers in the relevant mode, as well as the PLMR register, into the context when an exception occurs. Upon exiting the exception, these registers are restored sequentially.

[0215] Step 480: Each time the interrupt handler is entered, the status function _tx_thread_system_state++ is incremented, and the status function _tx_thread_system_state-- is decremented before exiting the interrupt handler.

[0216] Each time an ISR is entered, the nesting of the ISR is determined by checking whether the state function _tx_thread_system_state is 0.

[0217] Step 490: Each time the exception handling function is entered, the status function _tx_thread_esr_count is incremented, and before exiting the exception handling function, the status function _tx_thread_esr_count is decremented. Each time the exception handler is entered, the nesting of the exception handler is determined by checking if _tx_thread_esr_count is 0.

[0218] Step 4100: Deploy the private RAM data of each core to the private RAM region of each core. The private RAM data includes the scheduler instance and the Thread Stack.

[0219] The method provided in this embodiment enables the deployment of dynamic management data of a single-core operating system in the private RAM area (LOCAL RAM) of the RH850 processor, thereby enabling the single-core operating system to run on a multi-core processor.

[0220] Figure 5 A schematic diagram of the structure of the operating system running device provided in this application is shown below. Figure 5 As shown, the operating system running device 50 provided in this embodiment includes:

[0221] The acquisition module 510 is used to acquire the processor architecture of a multi-core processor;

[0222] The determination module 520 is used to determine a single target core among the individual cores of a multi-core processor;

[0223] The adjustment module 530 is used to adjust the operating mechanism of a single-core operating system based on the processor architecture, so that the single-core operating system runs within the target kernel.

[0224] In one possible implementation, the adjustment module is specifically used for:

[0225] If the processor architecture is the first target architecture, then when the single-core operating system creates a thread in the target kernel, it calls the target kernel's context restoration instruction to construct the thread's initial context.

[0226] When a single-core operating system executes a thread, it calls the privileged instruction of the multi-core processor to switch to the execution of the first thread. The first thread is the thread with the highest priority in the target kernel that is in a waiting state.

[0227] When a single-core operating system performs thread switching, it invokes privileged instructions to achieve context switching between threads.

[0228] In one possible implementation, the adjustment module is specifically used for:

[0229] When a single-core operating system executes an interrupt handler or exception handler, it calls the target kernel's context recovery instruction to save the context of the interrupted target interrupt handler to the context saving area.

[0230] When a single-core operating system requests to exit execution, it invokes the context recovery instruction and the target kernel's return instruction to control the single-core operating system to exit the execution interrupt handling function or exception handling function.

[0231] In one possible implementation, the adjustment module is specifically used for:

[0232] Each time a single-core operating system enters an interrupt handler or exception handler, the status function controlling the single-core operating system increments its counter.

[0233] When a single-core operating system exits an interrupt handler or exception handler, the control status function decrements its counter.

[0234] In one possible implementation, the operating system runtime device also includes a region allocation module for: allocating a corresponding private memory region for each kernel using the hardware isolation mechanism of a multi-core processor.

[0235] In one possible implementation, the adjustment module is specifically used for:

[0236] The first context recovery instruction of the target kernel is invoked to allocate a core save area from the target kernel's context save area to the thread. The core save area is used to save the thread's core context.

[0237] The second context recovery instruction of the target kernel is invoked to allocate a non-kernel save area from the context save area to the thread. The non-kernel save area is used to save the non-kernel context of the thread.

[0238] The kernel save region is linked with the non-kernel save region, and the target kernel's hardware registers are updated. The hardware registers are used to track the region linking relationship between the kernel save region and the non-kernel save region.

[0239] In one possible implementation, the adjustment module is specifically used to: when an interrupt handler or exception handler is detected and the target kernel automatically saves the core context of the target interrupt handler to the core storage area, save the non-core context of the target interrupt handler to the non-core storage area through a context recovery instruction.

[0240] In one possible implementation, the operating system execution device further includes a verification module for verifying whether the interrupt handling function or exception handling function is nested based on the count value of the status function.

[0241] In one possible implementation, the adjustment module is specifically used for:

[0242] If the processor architecture is the second target architecture, then when the single-core operating system creates a thread in the target kernel, it uses the general-purpose registers and special registers in the target kernel to construct the initial context of the thread.

[0243] When a single-core operating system requests to execute a thread, it executes the second thread in the target kernel. The second thread is the thread that is in the ready state among all the threads.

[0244] When a single-core operating system performs thread switching, it invokes privileged instructions from a multi-core processor to achieve context switching between threads within the target kernel.

[0245] In one possible implementation, the adjustment module is specifically used for:

[0246] When a single-core operating system enters the execution interrupt handling function or exception handling function, it saves the register state corresponding to the interrupted target interrupt handling function to the context saving area. The register state includes the state of the general-purpose registers and special registers corresponding to the target interrupt handling function.

[0247] When a single-core operating system exits the execution of an interrupt handler or exception handler, it uses the context save area to restore the state of general-purpose registers and special registers in order to continue executing the target interrupt handler.

[0248] In one possible implementation, the operating system runtime device further includes a multiplexing module for obtaining the runtime mechanism adjustment method corresponding to the single-core operating system running in the target kernel; and using the runtime mechanism adjustment method to adjust the single-core operating system so that the single-core operating system runs in each kernel of the multi-core processor.

[0249] The operating system running device provided in this embodiment can execute the methods provided in the above method embodiments. Its implementation principle and technical effect are similar, and will not be described in detail here.

[0250] This application also provides a vehicle, including: a vehicle body, at least one processor, and a memory. Optionally, the vehicle further includes a communication component. The processor, memory, and communication component are connected via a bus.

[0251] In the specific implementation process, at least one processor executes computer execution instructions stored in memory, causing at least one processor to perform the above-described method. The specific implementation process of the processor can be found in the above-described method embodiments, and its implementation principle and technical effects are similar; therefore, it will not be repeated here.

[0252] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0253] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0254] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0255] This application also provides a computer program product, including a computer program that, when executed, implements the above-described method.

[0256] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed, implement the above-described method.

[0257] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0258] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0259] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0260] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0261] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0262] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0263] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0264] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope.

Claims

1. A method for running an operating system, characterized in that, include: Obtain the processor architecture of a multi-core processor; Identify a single target core among the individual cores of the multi-core processor; Based on the processor architecture, the operating mechanism of the single-core operating system is adjusted so that the single-core operating system runs within the target kernel.

2. The method according to claim 1, characterized in that, The adjustment of the operating mechanism of the single-core operating system based on the processor architecture includes: If the processor architecture is the first target architecture, then when the single-core operating system creates a thread in the target kernel, it calls the context recovery instruction of the target kernel to construct the initial context of the thread; When the single-core operating system executes a thread, it calls the privileged instruction of the multi-core processor to switch to the execution of the first thread, which is the thread with the highest priority in the target kernel and is in a pending execution state; When the single-core operating system performs thread switching, it invokes the privileged instruction to achieve context switching between the threads.

3. The method according to claim 2, characterized in that, The adjustments to the operating mechanism of the single-core operating system include: When the single-core operating system executes an interrupt handling function or an exception handling function, it calls the context recovery instruction of the target kernel to save the context of the interrupted target interrupt handling function to the context saving area. When the single-core operating system requests to exit execution, the context recovery instruction and the return instruction of the target kernel are invoked to control the single-core operating system to exit the execution of the interrupt handling function or exception handling function.

4. The method according to claim 1 or 3, characterized in that, The adjustments to the operating mechanism of the single-core operating system include: When the single-core operating system enters the execution interrupt handling function or exception handling function each time, the state function of the single-core operating system is controlled to increment the counter. Each time the single-core operating system exits the execution of the interrupt handling function or the exception handling function, it controls the state function to decrement its counter.

5. The method according to claim 1, characterized in that, Also includes: The hardware isolation mechanism of the multi-core processor is used to allocate a corresponding private memory region for each core.

6. The method according to claim 2, characterized in that, The step of invoking the context recovery instruction of the target kernel to construct the initial context of the thread includes: The first context recovery instruction of the target kernel is invoked to allocate a core storage area from the context storage area of ​​the target kernel to the thread, wherein the core storage area is used to store the core context of the thread; The second context recovery instruction of the target kernel is invoked to allocate a non-core storage area from the context storage area to the thread, wherein the non-core storage area is used to store the non-core context of the thread. The core storage region is linked to the non-core storage region, and the hardware registers of the target kernel are updated. The hardware registers are used to track the region link relationship between the core storage region and the non-core storage region.

7. The method according to claim 3, characterized in that, The step of calling the context recovery instruction of the target kernel to save the context of the interrupted target interrupt handler function to the context saving area includes: When the interrupt handler function or the exception handler function is detected to have occurred, and the target kernel automatically saves the core context of the target interrupt handler function to the core storage area, the non-core context of the target interrupt handler function is saved to the non-core storage area through the context recovery instruction.

8. The method according to claim 4, characterized in that, Also includes: Based on the count value of the state function, verify whether the interrupt handling function or the exception handling function is nested.

9. The method according to claim 1, characterized in that, The adjustment of the operating mechanism of the single-core operating system based on the processor architecture includes: If the processor architecture is the second target architecture, then when the single-core operating system creates a thread in the target kernel, it uses the general-purpose registers and special registers in the target kernel to construct the initial context of the thread; When the single-core operating system requests to execute a thread, it executes the second thread in the target kernel, which is the thread that is in the ready state among all threads; When the single-core operating system performs thread switching, it invokes privileged instructions of the multi-core processor to achieve context switching between threads in the target kernel.

10. The method according to claim 9, characterized in that, The adjustments to the operating mechanism of the single-core operating system include: When the single-core operating system enters the execution interrupt handling function or exception handling function, it saves the register state corresponding to the interrupted target interrupt handling function to the context saving area. The register state includes the state of the general-purpose registers and special registers corresponding to the target interrupt handling function. When the single-core operating system exits the execution of the interrupt handling function or the exception handling function, the state of the general-purpose registers and the special registers is restored using the context saving area so as to continue the execution of the target interrupt handling function.

11. The method according to any one of claims 1-3 and 5-10, characterized in that, After running the single-core operating system within the target kernel, the method further includes: Obtain the operation mechanism adjustment method corresponding to the single-core operating system running within the target kernel; The single-core operating system is adjusted using the aforementioned operating mechanism to allow it to run on each kernel of the multi-core processor.

12. An operating system running device, characterized in that, include: The acquisition module is used to obtain the processor architecture of a multi-core processor; A determination module is used to determine a single target core among the individual cores of the multi-core processor; The adjustment module is used to adjust the operating mechanism of the single-core operating system based on the processor architecture, so that the single-core operating system runs within the target kernel.

13. A vehicle, characterized in that, Includes the vehicle body, processor, and memory; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory, causing the processor to perform the method as described in any one of claims 1-11.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed, are used to implement the method as described in any one of claims 1-11.

15. A computer program product, characterized in that, Includes a computer program that, when executed, implements the method described in any one of claims 1-11.

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