A fault-tolerant in-memory computation macro that combines error correction code and input sparsification

Abstract

The embodiment of the application provides a fault-tolerant in-memory computing macro combining error correction code and input sparsification, and belongs to the technical field of in-memory computing integrated circuits. The scheme performs sparsification processing on input data through an input sparsification unit to generate a sparse input vector and a shift flag; a word line and an input driving unit are gated to activate the word line according to the sparse input vector, a storage array performs parallel array calculation to obtain an initial calculation result; an error correction code decoder decodes and corrects the initial calculation result; a shift adder combines the shift flag to complete multi-bit multiplication and accumulation and restore a final calculation result; and a controller realizes control and timing coordination between components. The application combines input sparsification preprocessing and a hardware error correction mechanism to reduce error probability from the source and realize error repair, effectively alleviate precision loss caused by non-ideal hardware characteristics, and the area and delay overheads caused by the new modules are low, which is suitable for neural network inference hardware acceleration scenarios.

Description

Technical Field

[0001] This application relates to the field of in-memory computing integrated circuit technology, and in particular to a fault-tolerant in-memory computing macro that combines error-correcting codes and input sparsity. Background Technology

[0002] Magnetic random access memory (MRRAM) possesses characteristics such as non-volatility, fast read / write speeds, and high durability, making it suitable for constructing simulated in-memory computing arrays. In simulated in-memory computing using MRAM, multiple storage modules can be activated simultaneously within the same computation cycle. The analog signal output by the array is converted from analog to digital to obtain partial multiplication and accumulation results. This method can improve the internal parallelism and data bandwidth of the array. Performing multiplication and accumulation operations within or adjacent to the storage array through in-memory computing reduces the movement of weight data between memory and computing modules, making it suitable for accelerating neural network inference.

[0003] However, magnetic random access memory (MRM) devices have limited tunneling magnetoresistance ratios, their resistance values ​​are subject to process variations, analog readout circuits exhibit nonlinearity, and analog-to-digital conversion can introduce errors. All these factors can lead to errors in multiply-accumulate calculations. Furthermore, as the number of simultaneously active word lines increases, the bit error rate (BER) of some multiply-accumulate results also rises. Error-correcting codes can reduce the impact of storage or computation errors on the results, but in analog in-memory computation, a high BER requires a coding scheme with stronger error correction capabilities. This introduces additional check columns, storage redundancy, and decoding overhead, reducing the area efficiency and energy efficiency of in-memory computation macros. Moreover, existing error correction schemes typically focus on error detection and correction itself, with less emphasis on reducing the number of simultaneously active word lines from the input side, making it difficult to suppress the increase in BER caused by input patterns.

[0004] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0005] The main objective of this application is to propose a fault-tolerant in-memory computation macro that combines error-correcting codes and input sparsity, aiming to solve the problem of increased bit error rate in some multiplication and accumulation results in magnetic random access memory analog in-memory computation due to device deviation, analog readout error, analog-to-digital conversion error, and reduced input sparsity.

[0006] To achieve the above objectives, one aspect of this application proposes a fault-tolerant in-memory computation macro that combines error-correcting codes and input sparsification. The fault-tolerant in-memory computation macro includes an input sparsification unit, a word line and input driving unit, a storage array, an error-correcting code decoder, a shift adder, and a controller. The input sparsification unit is used to perform sparsification operations on the input data of the array to obtain a sparsified input vector and a shift flag. The word line and input driving unit are used to drive the corresponding word line to activate according to the sparsed input vector, so as to obtain the activated word line; The storage array is used to store array data and to perform array calculations on the sparsed input vector according to the activation word line driving array to obtain initial calculation results; The error correction code decoder is used to decode the initial calculation result, correct the calculation errors in the initial calculation result, and output the corrected calculation result; The shift adder is used to receive the correction calculation result and perform multi-bit data multiplication and accumulation calculation operations on the correction calculation result to obtain the final calculation result; The controller is used to provide control signals and to exchange information among the input sparsification unit, word line and input driving unit, storage array, error correction code decoder, and shift adder components.

[0007] In some embodiments, the input sparsification unit performs a sparsification operation on the input data of the array to obtain a sparsified input vector and a shift flag, including: Construct an input vector set based on the input data, and remove vectors with all zero elements from the input vector set to obtain a non-zero vector set containing non-zero elements; Select a non-zero vector from the set of non-zero vectors as a reference vector, and read the shift flag corresponding to the reference vector; The reference vector is compared bit by bit with the subsequent n non-zero input vectors to determine the subset relationship between two adjacent non-zero vectors and to determine whether sparsification can be performed. If sparsification can be performed, then the sparsification operation is executed and the shift flags are merged to obtain new input data and new shift flags; The operation of removing vectors containing all zero elements is performed again on the new input data to obtain a sparse input vector; The sparse input vector is fed into the word line and input driver unit, and the new shift flag is fed into the shift adder.

[0008] In some embodiments, the criterion for determining the subset relationship between two adjacent non-zero vectors is as follows: define two non-zero vectors as a first non-zero vector and a second non-zero vector, and if the positions of the elements that are 1 in the first non-zero vector completely include the positions of the elements that are 1 in the second non-zero vector, then the second non-zero vector is called a subset of the first non-zero vector.

[0009] In some embodiments, the shift adder performs shift compensation and multi-bit multiplication-accumulation merging operations according to the bit shift mapping rules recorded in the shift flag, so as to output the final calculation result equivalent to the original input vector directly calculated without sparsification.

[0010] In some embodiments, the storage array includes a dummy column, a reference column, a data column, and a check column. Each column is configured with multiple storage units. The storage units are used to store single-bit data. The storage units of the data column are used to store weight data, and the storage units of the check column are used to store check data. The weight data stored in the data column storage units are grouped according to bit position. The least significant bit and the second least significant bit are not encoded. The remaining groups are encoded according to the rules of Hamming code, modulo 4 sum, and additional checksum to obtain check bits. The check bits of each group are written into the corresponding check column storage unit in the same row.

[0011] In some embodiments, the storage array performs array computation on the sparsed input vector based on the activation word lines to obtain initial computation results, including: The corresponding row selection storage unit is determined based on the activated word line to obtain the operation storage unit; According to the operation storage unit, the sparse input vector and weight are multiplied and accumulated in the data column and the verification column channels respectively to obtain the weight multiplication and accumulation result and the verification operation result corresponding to the row weight; The initial calculation result is obtained by combining the weighted multiplication and accumulation result with the verification operation result.

[0012] In some embodiments, the error correction code decoder makes an error determination on the initial calculation result based on determination parameters, which include the synaptic expression, total checksum, data checksum, and modulo-4 difference.

[0013] In some embodiments, when it is determined that the initial calculation result is error-free, or that the error occurs in the check bit, modulo-4 sum, or checksum, the error correction code decoder outputs the initial calculation result; when it is determined that the error in the initial calculation result only occurs in the data bits, the error correction code decoder calculates the corrected data bits by subtracting the modulo-4 difference from the data bits corresponding to the syntactic expression, and outputs the corrected calculation result.

[0014] In some embodiments, the error correction code decoder is further configured to output a recalculation signal and transmit the recalculation signal to the controller, wherein the recalculation signal is valid when the error correction code decoder determines that the error is uncorrectable; after receiving the recalculation signal, the controller controls the current calculation result to be invalid and controls the current input to be recalculated after reducing the number of active rows to obtain the recalculation result.

[0015] In some embodiments, the fault-tolerant in-memory computation macro further includes an analog-to-digital converter, which is used to convert the initial computation result into the digital domain, and the error-correcting code decoder decodes and corrects the initial computation result in the digital domain.

[0016] The embodiments of this application include at least the following beneficial effects: This application provides a fault-tolerant in-memory computation macro that combines error correction codes and input sparsification. This scheme generates a sparse input vector and a shift flag by sparsifying the original input vector through an input sparsification unit. This reduces the number of word lines that are activated simultaneously, reduces analog domain noise such as current disturbances and device mismatch caused by multiple rows and columns being activated simultaneously in the memory array, reduces the probability of computational errors generated by the in-memory computation array from the source, and alleviates the precision decay problem caused by large-scale parallel multiplication and accumulation. After the memory array completes vector multiplication and accumulation to obtain the initial calculation result, the error correction code decoder detects and corrects the computational error. When multiple error scenarios occur that exceed the single error correction capability, a recalculation process can be triggered in conjunction with the controller to further improve the reliability of the operation and effectively resist the loss of inference precision caused by non-ideal hardware characteristics. The shift adder performs multi-bit multiplication and accumulation operations on the corrected calculation result after error correction based on the shift flag, restoring the complete calculation result corresponding to the original input. Under the premise of sparsity optimization, the mathematical operation equivalence is guaranteed, and the inherent precision loss is not introduced due to sparsity processing. The controller outputs unified timing control signals to complete data interaction and process scheduling between the input sparsity unit, word lines and input driving unit, memory array, error correction code decoder, and shift adder. It sequentially drives the entire process of input sparsity, word line activation, array simulation calculation, error correction decoding, and shift accumulation, supporting the stable operation of a fault-tolerant in-memory computing macropipeline. This architecture combines input sparsity and error correction codes for dual fault tolerance, effectively suppressing accuracy loss caused by non-ideal hardware effects in the in-memory computing array, while also minimizing area and latency overhead from the added circuitry. Compared to traditional non-fault-tolerant in-memory computing architectures, this solution significantly improves neural network inference stability under high error conditions with only a small increase in hardware cost, making it suitable for deployment in deep learning network hardware acceleration scenarios. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the overall structure of a fault-tolerant in-memory computation macro that combines error-correcting codes and input sparsity, provided in an embodiment of this application. Figure 2 This is a schematic diagram of the error correction encoding and decoding process; Figure 3 A schematic diagram of the input sparsification operation; Figure 4 This is a statistical chart showing the number of word lines activated simultaneously during the model inference process, as described in the embodiments of this application. Figure 5 This is a statistical chart showing the relative accuracy loss of the model inference model applied to embodiments of this application. Figure 6 This is a schematic diagram of the area distribution and delay distribution composition of an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0019] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”

[0020] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0022] Given the limited tunneling magnetoresistance ratio of magnetic random access memory (MRRAM) devices, the process fluctuations in device resistance, the nonlinearity of analog readout circuits, and the potential for errors introduced during analog-to-digital conversion, multiply-accumulate calculations may contain errors. Furthermore, as the number of simultaneously activated word lines increases, the bit error rate of some multiply-accumulate results also rises. Adopting encoding methods with stronger error correction capabilities introduces additional check columns, storage redundancy, and decoding overhead, reducing the area efficiency and energy efficiency of in-memory computation macros. Existing error correction schemes typically focus on error detection and correction itself, with less emphasis on reducing the number of simultaneously activated word lines from the input side, making it difficult to suppress the increase in bit error rate caused by input patterns. In view of this, embodiments of this application provide a fault-tolerant in-memory computation macro that combines error-correcting codes and input sparsity. By combining Hamming codes, modulo 4, and additional checksums, the error-correcting code decoder can achieve single error correction and double error detection for ±1 errors, and can identify single ±2 errors, thereby improving the fault tolerance capability for the multiplication and accumulation results of the analog in-memory computation part. By increasing the sparsity of the input vector through input detection and correction mechanisms, the number of simultaneously activated word lines is reduced from the source, thereby reducing the analog computation error rate.

[0023] In this embodiment, the ±1 error refers to a numerical deviation of 1 from the ideal value of the multiplication and accumulation result of the digitized part of a column; the ±2 error refers to a numerical deviation of 2.

[0024] Please see Figure 1 As shown, Figure 1 This is a schematic diagram of the overall structure of a fault-tolerant in-memory computation macro that combines error correction codes and input sparsification, provided in an embodiment of this application. The fault-tolerant in-memory computation macro includes an input sparsification unit, word lines and input driving units, a storage array, an error correction code decoder, a shift adder, and a controller.

[0025] The input sparsification unit is used to perform sparsification operations on the input data of the array to obtain a sparsified input vector and a shift flag.

[0026] In some embodiments, the input sparsification unit performs a sparsification operation on the input data of the array to obtain a sparsified input vector and a shift flag, including: Construct an input vector set based on the input data, and remove vectors with all zero elements from the input vector set to obtain a set of non-zero vectors containing only non-zero elements; The input data to be processed is fed in from the outside and organized into a two-dimensional input vector matrix. Each row of the matrix corresponds to a word line input vector. All input vector rows are traversed, and vectors with all elements equal to 0 are directly deleted. By performing zero-input skipping on the input vectors and removing all-zero elements, invalid word line activation attempts can be avoided. The output is a set of non-zero vectors containing only non-zero elements.

[0027] Select a non-zero vector from the set of non-zero vectors as the reference vector, and read the shift flag corresponding to the reference vector; From the sequence of non-zero vectors after removing all zero elements, the first non-zero vector is selected as the reference vector. The reference vector has not yet undergone the merging operation. The initial shift flag records the original position information of the reference vector in the original input matrix.

[0028] The reference vector is compared bit by bit with the subsequent n non-zero input vectors. The subset relationship between two adjacent non-zero vectors is determined in turn, and it is determined whether sparsification operation can be performed. In some embodiments, the criterion for determining the subset relationship between two adjacent non-zero vectors is as follows: define two non-zero vectors as a first non-zero vector and a second non-zero vector, and if the positions of the elements that are 1 in the first non-zero vector completely include the positions of the elements that are 1 in the second non-zero vector, then the second non-zero vector is called a subset of the first non-zero vector.

[0029] The first, second, ..., nth non-zero vectors to be processed are sequentially retrieved after the reference vector. The reference vector and the current non-zero vector to be processed are compared bit-by-bit to check if they meet the judgment condition. If the judgment condition is met, vector merging and sparsification are allowed; if the judgment condition is not met, merging is not allowed, the current vector is set as the new reference vector, and the comparison continues. This application sets a subset inclusion judgment condition. When B is a subset of A, all word lines activated by A cover all word lines required to be activated by B. By merging the two vectors, two-way operations can be completed with only one word line activation, effectively reducing the total number of activated word lines and lowering the parallel noise of the analog array.

[0030] If sparsification can be performed, then the sparsification operation is executed and the shift flags are merged to obtain new input data and new shift flags; The benchmark vector and subset vectors (the currently processed non-zero vectors) are merged based on subset relations, replacing the original two independent inputs. This achieves the same computational effect as two inputs with only a single word line activation. The original shift flags of the benchmark vector and the subset vectors are fused and encoded to generate a new shift flag. This new shift flag simultaneously stores the positional information and merging mapping rules of both original vectors. The backend shift adder, relying on this merged new shift flag, can split and restore the merged single computation result into the multiplicative sums corresponding to the two independent vectors after the array has completed its computation.

[0031] It should be noted that in this embodiment, the operation and merging of the reference vector and subset vector (the currently non-zero vector to be processed) based on subset relations means using subset relations to decompose the containing vector into a difference vector and a subset vector, and merging the bit weights corresponding to the containing vector into the shift flag of the subset vector, thereby reducing the total number of non-zero elements in the transformed input vector, while keeping the weighted multiplication and accumulation result unchanged. Figure 3 As shown, this essentially reduces the total number of 1s involved in the operation (total activated rows). For example, for sets A, B, and C, when n=1 and A=B, one array calculation can be skipped; when n=2, only the cases A+B=C, A=B, A=C, B=C, A+C=B, and B+C=A can skip one array calculation, and when A=B=C, two array calculations can be skipped.

[0032] Perform the operation of removing vectors containing all zero elements again on the new input data to obtain a sparsed input vector; The sparse input vector is fed into the word line and input driver unit, and the new shift flag is fed into the shift adder.

[0033] The input sparsity unit first removes all-zero elements from the input vector to reduce invalid operations. Then, it identifies mergeable vectors by utilizing subset inclusion relationships among non-zero vectors. Here, vector merging refers to reducing the total number of 1s in the operation. Input vector compression is achieved through vector merging, reducing the number of effective non-zero vectors and ultimately reducing the number of activated word lines. The merging process continuously updates the shift flag, allowing the backend shift adder to restore the original calculation result. Theoretically, no new all-zero elements should be generated after vector merging. This application adds a redundancy check step to scan the newly obtained input data after merging. If any all-zero vectors are found after the merging operation, they are removed again. Finally, the output is a compressed sparse input vector with no invalid vectors.

[0034] The input sparsification unit receives the raw input data from the array, performs a sparsification operation on it to obtain a sparsified input vector, and simultaneously records the shift information of each valid input bit, encoding it to generate a shift flag. The input sparsification unit generates two parallel signals: one sends the sparsified input vector to the word line and input driver unit to drive the storage array to activate the corresponding word line to perform analog multiply-accumulate operations and output the initial calculation result; the other sends the new shift flag to the back-end shift adder to combine with the correction calculation result output by the error correction code decoder to recover the original calculation result.

[0035] In some embodiments, the shift adder performs shift compensation and multi-bit multiplication-accumulation merging operations according to the bit shift mapping rules recorded in the shift flag, so as to output the final calculation result equivalent to the original input vector directly operated without sparsification.

[0036] The correction calculation result is performed by performing a reverse shift operation. The effective calculation result of the compression and merging is shifted in reverse. The operation component corresponding to the temporarily zeroed bits removed during the sparsification stage is replenished according to the shift flag. The rearranged operation data is restored to the original bit position. After the shift adder completes the shift compensation and multi-bit multiplication and accumulation merging, the output is equivalent to the final calculation result obtained by directly operating the original input vector without sparsification processing. This ensures that the accuracy of the upper neural network or operation task is not affected by the front-end sparse compression operation.

[0037] Specifically, in the simulated in-memory computation of this application embodiment, multiple inputs are decomposed into multiple binary vectors with equal weights, and each is multiplied by a weight matrix pre-stored in the storage array. For example, for two input vectors, the first vector... Second vector The corresponding original weighted part multiplied by the sum can be expressed as: (1) In equation (1), and These represent the i-th input at the i-th position. The position and the first The value of the bit is either 0 or 1; This represents the weight data corresponding to the i-th row. The above calculation can be further decomposed into: (2) In equation (2), the symbol This indicates a bitwise AND operation.

[0038] Equation (2) shows that the sum of the calculation results corresponding to the two binary input vectors decomposed from multiple inputs in the same batch can be divided into three parts: the first part is the first vector. Second vector The first part consists of a common activation row where all values ​​are 1; the second part consists of a common activation row where all values ​​are 1 only in the first vector. The middle part is the activation row with a value of 1; the third part is only active in the second vector. The active row portion is set to 1. To prevent an increase in array computation count, at least one of the second and third portions must be a zero vector, i.e., the first vector. Second vector One vector in the equation needs to completely contain the active rows of the other vector that are 1. This results in fewer active rows on the right-hand side than on the left. Specifically, if both the second and third parts are zero vectors, one array calculation operation can be omitted.

[0039] For simplicity and accuracy, the statement "the positions of elements that are 1 in input vector A completely include the positions of elements that are 1 in input vector B" is called "B is a subset of A". The number of checks, n, is defined as the number of times the judgment "whether a single input is a subset of another input" is made. It is evident that the above algorithm only considers two array calculation operations, requires one subset relationship judgment, and n is 1. Extending this to multiple array calculation operations, such as... Figure 3 As shown, for ease of description below, Figure 3 The whole is divided into four parts: top left, top right, bottom left, and bottom right. This diagram shows the changes in each vector after two levels of subset judgment, i.e., when n=2, that is, top left → top right → bottom right → bottom left. Figure 3 As indicated by the middle arrow.

[0040] Figure 3 The diagram shows three specific input vectors and their corresponding shift flags, with the first input vector being... The shift flag is the third bit from the left of the 8-bit data, the second input vector. The shift flag is the second bit from the left of the 8-bit data, and the third input vector. The shift flag is the first bit from the left in the 8-bit data. The subset relationship is determined based on the position of the 1s in each vector. The first input vector... Only the second and third bits from the right are 1, while the third input vector... The second, third, fifth, and seventh bits of the rightmost input vector are all 1, due to the third input vector. It contains the first input vector The positions of all elements that are 1 in the first input vector are thus determined. It is the third input vector Similarly, the third input vector can be obtained from the subset of the subset. It is the second input vector A subset of.

[0041] Level 1: Due to the third input vector It is the second input vector A subset of, therefore let the third input vector The elements remain unchanged, the second input vector The elements become the result of the bitwise XOR operation between the third input vector and the second input vector, which is the first operation result. and the second input vector The corresponding shift flag is added to the third input vector. On the shift flag, the first-level updated third input vector is obtained as [01010110], whose elements are still the third input vector. The shift flags remain unchanged, while the leftmost and rightmost bits of the 8-bit data are changed to two, namely the first and second leftmost bits, and the first-level update of the second input vector, i.e., the first operation result. The shift flag remains the second bit from the left of the 8-bit data.

[0042] Bitwise XOR means that for two vector elements, if corresponding elements are the same, it is represented as 0; otherwise, it is represented as 1. For example... The first bit from the right of both vectors is 0 and 1 respectively, so the result of the bitwise XOR is 1; the second bit from the right of both vectors is 1, so the result of the bitwise XOR is 0. Performing a bitwise XOR on each element of both vectors yields... .

[0043] Second level: Due to the first input vector It is the third input vector A subset of, therefore let the first input vector be... The elements remain unchanged, and the third input vector The elements become the result of the bitwise XOR operation between the first input vector and the third input vector, i.e., the second operation result. and the third input vector The corresponding shift flag is added to the first input vector. The shift flag is used to obtain the second-level update of the third input vector, which is the result of the second operation. The shift flags are the first and second bits from the left of the 8-bit data, and the second-level update of the first input vector is [00000110], whose elements are still the first input vector. The shift flag remains unchanged, but it becomes three: the first, second, and third bits from the left of the 8-bit data.

[0044] After two levels of subset judgment and AND operation, the updated forms of the three input vectors and their corresponding new shift flags are finally obtained. The specific change process is represented as follows: ; ; ; In the formula, a1, a2, and a3 represent that the first, second, and third elements from the left of the 8-bit data are 1, respectively.

[0045] After the two operations, compare the third input vector. With the new third input vector The second input vector With the new second input vector The first input vector With the new first input vector We can observe that the overall frequency of occurrence of '1' decreases, and the input sparsity increases. Simultaneously, due to... The two operations do not change the original calculation result.

[0046] The word line and input driving unit are used to drive the corresponding word line activation according to the sparse input vector to obtain the activated word line.

[0047] The word line and input driver unit receives the sparsed input vector output by the front-end input sparsification unit. By analyzing the effective bit positions within the sparsed input vector, it generates word line gating drive levels, selectively enabling the corresponding word lines of the memory array. All word lines successfully pulled high or enabled are considered active word lines. By sparsely compressing the input vector, the number of effective bits is reduced, the total number of synchronously activated word lines decreases, and the parallel integration noise of the analog array is reduced.

[0048] Specifically, the word line and input driver unit uses a level conversion circuit to convert the logic level of the sparse input vector into the standard drive voltage required by the memory array word lines, achieving signal level adaptation. Then, it scans each bit in the sparse input vector bit by bit. When a bit is a valid value (logic 1), it indicates that the corresponding memory array word line needs to be turned on; when a bit is an invalid value (logic 0), the corresponding word line remains off and no drive signal is output. The word line and input driver unit has a built-in multiplexer driver (row driver). For each valid bit identified, it outputs a valid drive pulse or a constant drive voltage, applied to the corresponding word line of the memory array. For channels where no valid bit is identified, the driver remains off and has no output. All word lines that receive a drive voltage and enter the working state are uniformly defined as active word lines. The word line and input driver unit identifies and locks the word lines that are in the conducting state in the current cycle and outputs the active word line information to the memory array. When a voltage is applied to the active word line, the corresponding memory cell is turned on. The memory array uses the active word line in conjunction with the bit lines to perform analog domain multiplication-accumulation (MAC) operations to generate the initial calculation result.

[0049] The storage array is used to store array data and to perform array calculations on the sparsed input vector based on the activation word lines to obtain the initial calculation results.

[0050] The storage array persistently stores neural network weight data and corresponding verification data. On the other hand, it receives word lines and activation word lines output by the input driving unit, performs analog domain multiplication and accumulation array operations on the sparse input vector, and synchronously outputs the data column operation values ​​and verification column operation values, merging them to form the initial calculation result.

[0051] In some embodiments, the storage array includes a dummy column, a reference column, a data column, and a parity column. Each column is configured with multiple storage units. The storage units are used to store single-bit data. The storage units of the data column are used to store weight data, and the storage units of the parity column are used to store parity data. The weight data stored in the data column storage units are grouped according to bit position. The least significant bit and the second least significant bit are not encoded. The remaining groups are encoded according to the rules of Hamming code, modulo 4 sum, and additional checksum to obtain the parity bits. The parity bits of each group are written into the corresponding parity column storage unit in the same row.

[0052] Specifically, in this embodiment, the storage array includes dummy columns, reference columns, data columns, and parity columns. Each column is configured with 225 single-bit storage units, and each storage unit stores only 1 bit of binary data. Among them, the dummy columns and reference columns are array auxiliary structures that do not participate in weight storage or multiplication-accumulation operations. They are mainly used for array potential equalization, suppressing edge effects, providing reference levels, and ensuring the accuracy of analog operations.

[0053] The data array has 256 columns, used to store 8-bit weight parameters. Each 8-bit weight is distributed and stored in 8 consecutive storage units in the same row, and a single row of the array can store a total of 32 8-bit weights. The 32 weights in the same row are divided into 8-bit groups according to their bit positions. Each group contains a binary number with 32 identical bits. The least significant bit and the second least significant bit are not encoded, while the remaining 6 groups are checked and encoded.

[0054] The check column consists of 54 columns, which are used to store the check data generated by the weight bits. For the 6 groups of bits that need to be encoded in each row of weights, each group generates a 9-bit check bit. The 6 groups of 9-bit check bits, totaling 54 bits, form a row of the check array, corresponding to 54 check storage units. Each row of check bits is calculated and generated from the 32 original weight bits in the same row and is bound to the weights one by one, providing a check benchmark for the backend error correction code decoder. The above operations are performed on each row of data to obtain the complete check array.

[0055] Before the calculation begins, 32 8-bit weights are stored in a row of 256 data columns. For each weight bit group in that row, the two least significant groups are left unencoded, and the remaining 6 groups are encoded according to the rules of Hamming code, modulo-4 sum, and additional checksum, generating 9-bit check bits for each group. A total of 54 check bits are written into the 54 check storage units corresponding to the same row, and this process is repeated row by row to complete the storage of all weights and their corresponding check data.

[0056] Specifically, for groups divided according to the weighted data bit positions, the least significant and second least significant groups are not encoded. The remaining 6 groups are encoded according to the rules of Hamming code, modulo-4 sum, and additional checksum to obtain 9-bit check bits. Each group is independently encoded to generate 9-bit check bits. Each 9-bit check bit consists of a 6-bit extended Hamming check bit, a 2-bit modulo-4 check bit, and a 1-bit additional checksum. First, the sum of all bits in the group is calculated and modulo 4 is taken to generate a 2-bit modulo-4 sum, used to identify single ±2 errors generated by analog operations. Then, the 32 original data bits in the group and the 2-bit modulo-4 sum generated from the 32 data bits are used together as 34 information bits to be protected. A 6-bit Hamming check bit is generated according to the Hamming code rules to implement single error correction and double error detection. Then, the global parity sum of the bits in the group is calculated to obtain a 1-bit additional checksum, used to assist in eliminating decoding ambiguity. The three types of check bits are concatenated to obtain a 9-bit check bit. This process is repeated for 6 groups, generating a total of 54 bits of check data, which are stored in the corresponding check column of the storage array.

[0057] In some embodiments, the memory array performs array computation on the sparsed input vector based on the activation word lines to obtain initial computation results, including: The corresponding row selection memory unit is determined based on the activated word line, and the operation memory unit is obtained; Based on the operation storage unit, the sparse input vector and weight are multiplied and accumulated in the data column and check column channels respectively to obtain the weight multiplication and accumulation result and the check operation result corresponding to the row weight; The initial calculation result is obtained by merging the weighted multiplication and accumulation results with the verification operation results.

[0058] During real-time array computation, the received word line and the activated word line output by the input driving unit select the corresponding row storage cell. Only the storage cell of the row containing the activated word line participates in the computation, while the unselected rows remain dormant. The sparse input vector represents the input activation information of each row. After the activated word line selects the corresponding row, the product of the sparse input vector bits and the weight bits in the storage cell is calculated in the data column channel. Current integration is performed in the analog domain to obtain the multiplied and accumulated original data component corresponding to the weight of that row. The stored parity bits are read synchronously in the parity column channel, and the parity component integration operation under the same input excitation is performed in parallel. Within the same activation cycle, the weight multiply-accumulated result output by the data column and the parity operation result output by the parity column are combined together to form the initial calculation result, which is then output in parallel to the subsequent error correction code decoder.

[0059] In this embodiment, the weights and corresponding parity bits coexist in the same row. When an active word line selects a row, the weight data and parity data can be read out and the simulated integration operation can be completed simultaneously without additional independent storage and reading cycles. The parity information is pre-fixed in the parity column, and the parity components are generated in parallel during the operation phase, which can reduce the timing overhead of error correction decoding. By reducing the number of active word lines through the input sparsification process, the number of array simultaneously conducting units is reduced, which alleviates the simulation non-ideal errors such as current superposition and integration distortion caused by the simultaneous activation of multiple word lines and reduces the probability of errors in the initial calculation results.

[0060] The error correction code decoder is used to decode the initial calculation result, correct the calculation errors in the initial calculation result, and output the corrected calculation result.

[0061] In some embodiments, the error correction code decoder makes an error judgment on the initial calculation result based on the judgment parameters, which include the synaptic expression, the total checksum, the data checksum, and the modulo-4 difference.

[0062] The synod S is determined by the Hamming code decoding rules. The parity sum Cov is the XOR of the least significant bit of all 3-bit numbers in the accumulated result. The data parity sum Cd is the XOR of all data bits with the least significant bit of the corresponding 3-bit numbers modulo 4. The modulo 4 difference Δmod4 is the difference between the sum of the data bits accumulated during the decoding stage modulo 4 and the theoretical modulo 4 value generated during the offline encoding stage. The modulo 4 difference Δmod4 is used to distinguish different magnitudes of analog errors: Δmod4=0 indicates no offset in the total data sum; Δmod4=1 corresponds to ±1 error in analog operations, which can be used to correct single errors; Δmod4=2 corresponds to ±2 error in analog operations, which can be used to detect double errors. Together with the synod S, the parity sum Cov, and the data parity sum Cd, error location and error type identification are completed.

[0063] In some embodiments, when it is determined that the initial calculation result is error-free, or when the error occurs in the check bit, modulo-4 sum, or checksum, the error correction code decoder outputs the initial calculation result; when it is determined that the error in the initial calculation result occurs in the data bit or when it is determined to be a multiple error case, the correction data bit is calculated by subtracting the modulo-4 difference from the data bit corresponding to the syntactic expression, and the error correction code decoder outputs the correction calculation result.

[0064] The error correction code decoder determines whether an error has occurred in the initial calculation result and what kind of error has occurred based on the four calculated judgment parameters. The judgment criteria are shown in Table 1 below.

[0065] Table 1

[0066] As shown in Table 1, when the judgment result is Case 1, it indicates that the current calculation result is error-free, and the error correction code decoder directly outputs the initial calculation result. When the judgment result is Case 2 to Case 5, the error occurs in the check bit P, modulo 4 and M, or parity check sum C. This type of error does not change the partial multiplication and accumulation result of the corresponding data column, so there is no need to modify the data column output. In this case, the error correction code decoder still outputs the initial calculation result. When the judgment result is Case 6, the error occurs in the data column, and the error correction code decoder locates the erroneous data column according to the syndrome S. The correction stage only applies to Case 6. The corrected data bits are obtained by subtracting the modulo 4 difference Δmod4 from the data bits corresponding to the syndrome S.

[0067] Other cases not listed in Table 1 are considered multiple error scenarios. The error correction code decoder sets the multiple error indicator bit DED to 1. After DED is set to 1, the current calculation result is determined to be invalid and enters the recalculation process. A single ±2 error, an association S of 0, and a modulo-4 difference Δmod4 of 2 or 0 are also considered multiple error cases.

[0068] In some embodiments, the error correction code decoder is further configured to output a recalculation signal and transmit the recalculation signal to the controller, wherein the recalculation signal is valid when the error correction code decoder determines that the error is uncorrectable; after receiving the recalculation signal, the controller controls the current calculation result to be invalid and controls the current input to be recalculated after reducing the number of active rows to obtain the recalculation result.

[0069] When the error correction code decoder outputs DED=0, it indicates that the current calculation result has no risk of multiple errors, and the decoder sends the corrected partial multiplication-accumulation result to the shift adder. When the error correction code decoder outputs DED=1, it indicates that the current calculation result is invalid, pausing the next array calculation operation and correcting the current input, reducing the number of word lines activated simultaneously during recalculation. During recalculation, the corrected input is sent to the word lines and input driver unit, the data column and parity column regenerate the partial multiplication-accumulation result, and the error correction code decoder performs parameter calculation, error judgment, and correction again. Since the bit error rate of the partial multiplication-accumulation result is related to the number of word lines activated simultaneously, reducing the number of activated word lines can increase the probability that the recalculated result is successfully protected by error correction coding.

[0070] Please see Figure 2 The diagram shows the error correction coding and decoding process. The error correction process in this embodiment includes offline coding, parameter calculation, error judgment and correction. The offline coding is performed outside the macro calculation in the fault-tolerant memory, while the parameter calculation, error judgment and correction are performed in the error correction code decoder.

[0071] During the offline encoding stage, the fault-tolerant in-memory computation macro-external error correction encoder encodes the data bits D. First, the modulo-4 sum of data bits D is calculated, resulting in two modulo-4 sum values, M1 and M0. Second, according to Hamming code rules, the corresponding data bits are selected and XORed with the modulo-4 sum values ​​to generate the parity bit P. Finally, an XOR operation is performed on the data bits D, the modulo-4 sum M, and the parity bit P to generate the parity check sum C. For example, Figure 2 In the first column of the example, for the first row of data {D1,D0}={1,1}, the modulo 4 sum of this data is 1+1=2 (mod 4). The binary representation of 2 is 10, meaning M1=1 and M0=0, therefore {M1,M0}={1,0}. Then, the parity bit is calculated by encoding {D1,D0,M1,M0}={1,1,1,0} using Hamming code, resulting in the parity bit {P2,P1,P0}={1,0,0}. Finally, an XOR operation is performed on {D1,D0,M1,M0,P2,P1,P0}={1,1,1,0,1,0,0} to obtain the parity check sum C=Xor(1,1,1,0,1,0,0)=0. Therefore, the encoded data bits {D1,D0}={1,1} remain unchanged, and the check bits are {M1,M0,P2,P1,P0,C}={1,0,1,0,0,0}.

[0072] For brevity, this embodiment uses only 2 bits of data. In this embodiment, the 32 8-bit weights of each row of the storage array are divided into 8 groups. That is, the highest bit of the 32 weights forms the first group, the second highest bit forms the second group, and so on, until the lowest bit forms the eighth group, resulting in eight groups of data. Encoding is performed on the first six groups, with each group's 32 data bits ultimately producing 9 parity bits. No encoding is performed on the last two groups, resulting in a total of 54 parity bits and 54 parity columns. After calculation by the fault-tolerant in-memory macro, the accumulated result for each column is 3 bits. Therefore, the 32 data bits and 9 parity bits of each encoded group, when accumulated, result in 41 3-bit numbers. Figure 2 In the first column below the example, the cumulative result of the calculations in the first and second rows is {D1,D0,M1,M0,P2,P1,P0,C}={1,2,1,1,2,0,1,0}. To demonstrate the error correction function of the error correction code decoder, the lower bit D0 of the data is changed to 3, which is considered a calculation error, i.e., {D1,D0,M1,M0,P2,P1,P0,C}={1,3,1,1,2,0,1,0}, which is represented by a 3-bit binary number as {D1,D0,M1,M0,P2,P1,P0,C}={001,011,001,001,010,000,001,000}. The following is the parameter calculation for the cumulative result represented by this 3-bit binary number.

[0073] During the parameter calculation phase, the error-correcting code decoder needs to calculate four decision parameters: the syndrome S, the overall parity check sum Cov, the data parity check sum Cd, and the modulo-4 difference Δmod4. Combined with... Figure 2 To explain, the syndrome S = {S2, S1, S0} = {1, 1, 0}, where S2 = Xor(D1[0], D0[0], M1[0], P2[0]) = 1, S1 = Xor(D1[0], D0[0], M0[0], P1[0]) = 1, and S0 = Xor(D1[0], M1[0], M0[0], P0[0]) = 0; then, the parity check sum Cov = Xor(D1[0]) is calculated based on the XOR of the lower 3 bits of the accumulated result. ,D0[0],M1[0],M0[0],P2[0],P1[0],P0[0],C[0])=Xor(1,1,1,1,0,0,1,0)=1;Data parity check sum Cd=Xor(D1[0],D0[0],M0[0])=Xor(1,1,1)=1;Modal 4 difference Δmod4=((D1+D0)mod4)-(M1«1+M0)=((1+3)mod4)-(1*2+1)=-3(±4)=1.

[0074] In calculating the modulo-4 difference Δmod4, the sum of all data bits in the current group is first calculated and modulo 4 is taken, i.e., (D1+D0)mod4=(1+3)mod4=4mod4=0; then the theoretical modulo-4 value generated in the offline encoding stage is calculated, i.e., M1«1+M0=M1*2+M0=1*2+1=3, where «1 represents a binary left shift of 1 bit, which is equivalent to multiplying by 2, i.e., M1«1=M1*2. M1*2+M0 is the decimal modulo value restored by the 2-bit modulo-4 check bits {M1, M0}, i.e., the theoretical modulo-4 sum obtained by offline encoding. After obtaining the original difference, it is periodically corrected by ±4 to constrain the final modulo-4 difference Δmod4 to the interval [-1,2].

[0075] During the decision phase, the error-correcting code decoder determines whether an error has occurred in the initial calculation result and what type of error has occurred based on four calculated decision parameters, as shown in Table 1. When the decision result is Case 1, it indicates that the current calculation result is error-free, and the error-correcting code decoder directly outputs the initial calculation result. When the decision result is Case 2 to Case 5, the error occurs in the check bit P, modulo 4 and M, or parity check sum C. This type of error does not change the partial multiplication and accumulation result of the corresponding data column, so there is no need to modify the data column output. In this case, the error-correcting code decoder still outputs the initial calculation result. When the decision result is Case 6, the error occurs in the data column, and the error-correcting code decoder locates the erroneous data column based on the syntactic S. Figure 2 In the example, if the four decision parameters meet condition 6, the error correction code decoder will locate a single error in the data bits.

[0076] The correction phase applies only to case 6. The corrected data bits are obtained by subtracting the modulo-4 difference Δmod4 from the data bits corresponding to the syndrome S. Figure 2 In the example, the syntactic S corresponds to the lower data bit D0. Modifying the lower data bit D0 to D0-Δmod4=3-1=2 shows that the calculation error on the data bit is corrected.

[0077] Other cases not listed in Table 1 are considered multiple error scenarios. The error correction code decoder sets the multiple error indicator bit DED to 1. After DED is set to 1, the current calculation result is determined to be invalid and enters the recalculation process. A single ±2 error, an association S of 0, and a modulo-4 difference Δmod4 of 2 or 0 are also considered multiple error cases.

[0078] When the error correction code decoder outputs DED=0, it indicates that the current calculation result has no risk of multiple errors, and the decoder sends the corrected partial multiplication-accumulation result to the shift adder. When the error correction code decoder outputs DED=1, it indicates that the current calculation result is invalid, pausing the next array calculation operation and correcting the current input, reducing the number of word lines activated simultaneously during recalculation. During recalculation, the corrected input is sent to the word lines and input driver unit, the data column and parity column regenerate the partial multiplication-accumulation result, and the error correction code decoder performs parameter calculation, error judgment, and correction again. Since the bit error rate of the partial multiplication-accumulation result is related to the number of word lines activated simultaneously, reducing the number of activated word lines can increase the probability that the recalculated result is successfully protected by error correction coding.

[0079] Traditional Hamming codes can locate error positions, but for partial multiplication and accumulation results in analog in-memory computation, simply locating the error position is insufficient to recover the correct calculated value. This application adds M1 and M0, enabling the error-correcting code decoder to recover the erroneous partial multiplication and accumulation result of the data column based on the error position and the modulo-4 difference Δmod4. Since M1 and M0 may also be erroneous, this application incorporates the modulo-4 sum along with the data bits into the Hamming code protection and adds a parity check sum C to improve the detection capability for errors in M1 and M0, as well as multiple errors.

[0080] The shift adder is used to receive the correction calculation result and perform multi-bit data multiplication and accumulation calculation operations on the correction calculation result to obtain the final calculation result.

[0081] To reduce the number of simultaneously active word lines in the array, the input sparsity unit merges and compresses multiple original input vectors with subset relationships into a single sparse input vector, while simultaneously generating a shift flag. The array operation and error correction code decoder output correction calculation results are only the operation values ​​corresponding to the merged vector. The shift adder simultaneously receives two signals: one is the correction calculation result output by the error correction code decoder, i.e., the effective multiplication and accumulation value after error detection and correction, and elimination of in-memory array simulation operation errors; the other is the shift flag transmitted by the input sparsity unit. Based on the vector merging mapping relationship recorded in the shift flag, the shift adder performs multi-bit shift and addition reconstruction operations to restore the multiplication and accumulation components corresponding to each of the multiple original input vectors before merging, and sums them to obtain the lossless final calculation result.

[0082] Specifically, the shift adder uses a built-in synchronization buffer to ensure that the correction calculation result is aligned with the timing of the shift flag for the corresponding period. The shift adder decodes the shift flag, extracts key control parameters to identify how many original input vectors the current correction calculation result is obtained by merging, and simultaneously acquires the bit offset and channel mapping information corresponding to each original input vector. Using the correction calculation result as the basic computational quantity, the shift adder performs binary shift operations according to the offset parameters corresponding to different original input vectors within the shift flag. If multiple original input vectors are merged into a single sparse input vector, the merged correction calculation result is equivalent to the superposition of multiple original operation components. Through shifts in different directions and with different bit widths, the independent multiply-accumulate intermediate components corresponding to each original input vector are decomposed and recovered. Then, the multiple original operation components generated by the shift operation are fed into the addition tree for parallel addition operations to compensate for the position superposition effect caused by vector compression during sparse merging, reconstructing the complete array multiply-accumulate output of the original input vectors without sparsity processing. After completing all shift and accumulation operations, the shift adder outputs a final calculation result with no information loss, consistent with the theoretical calculation result of the original non-sparse input.

[0083] Under normal conditions, the shift adder receives the correction calculation result output by the error correction code decoder, combines it with the shift flag to complete the shift, multiply-accumulate reconstruction operation, and outputs the final calculation result. When the error correction code decoder identifies multiple errors, it sets the multiple error indicator bit DED to 1, determines that the initial calculation result of the current cycle is invalid, and triggers the recalculation process. At this time, the error correction code decoder sends a pause control signal to the shift adder through the controller, and at the same time sends a recalculation request to the upstream input sparsification unit through the controller. If the corrected calculation result of the current cycle is determined to be unreliable, it is not sent to the shift adder for operation. After receiving the pause control signal, the shift adder immediately latches its internal register, pauses the shift operation and the addition tree operation, discards the currently pending invalid correction calculation result, and enters a waiting state; at the same time, it continues to receive timing signals, buffers the valid shift flag, and retains the intermediate state of the circuit without needing to be reset and cleared. The system corrects the input vector, reduces the number of simultaneously activated word lines, and the corrected sparse input vector is re-sent to the word lines and input driver unit. The storage array re-executes the array calculation to generate a new round of initial calculation results. The storage array outputs a new initial calculation result, which is then fed into the error correction code decoder. The decoder re-executes parameter calculation, error judgment, and correction. If no multiple errors are determined this time (DED=0), a reliable corrected calculation result is output. Upon receiving a valid corrected calculation result and a release signal, the shift adder releases its paused state and uses the buffered shift flag to perform shift and multi-bit multiplication-accumulation operations on the new corrected calculation result to obtain the final calculation result, which is then output. If the recalculation still results in a multiple error, the above process is repeated until the maximum number of recalculations is reached, at which point an operation failure flag is output.

[0084] The controller is used to provide control signals and exchange information between the input sparsification unit, word line and input drive unit, memory array, error correction code decoder, and shift adder components.

[0085] As the global timing and interaction core of the fault-tolerant in-memory computation macro, the controller distributes unified timing control signals to all components within the fault-tolerant in-memory computation macro to schedule the orderly operation of each component. On the other hand, it undertakes the forwarding of data, status, and instructions and information interaction between all components, coordinates the input sparsification unit, word line and input driver unit, memory array, error correction code decoder, and shift adder to execute the complete in-memory computation process, and handles the scheduling logic for error recalculation.

[0086] Global control signal generation and distribution: The controller has built-in sequential logic circuitry that generates a complete set of synchronous control signals based on the externally input system clock and start command. These signals include operation start / stop pulses, array read / write enable, word line drive timing, encoder / decoder start signals, shift adder operation enable, and buffer read / write control signals. The controller sends these control signals to the input sparsity unit, word line and input drive unit, memory array, error correction code decoder, and shift adder, constraining each component to operate sequentially according to a fixed timing sequence to ensure pipeline timing matching.

[0087] The inter-component information interaction is as follows: The controller receives the original input vector from the external source and sends it to the input sparsification unit. Simultaneously, it receives the shift flag output by the input sparsification unit, buffers the shift flag, and transmits it to the shift adder later. The controller forwards the sparsified input vector to the word lines and input driver unit, controlling the word line activation timing. The controller coordinates the storage array to complete the pre-writing of weights and parity data, as well as the array's periodic multiply-accumulate operations. It also receives the initial calculation results output by the storage array and forwards them to the error correction code decoder. The controller receives the output signal from the error correction code decoder, including the correction calculation result and the error decision flag, i.e., the DED (Multiple Errors Indicator) bit. If DED=0, it indicates no multiple errors, and the controller synchronously sends the correction calculation result to the shift adder. If DED=1, it indicates multiple errors, the result is invalid, and the controller initiates a recalculation scheduling instruction, sending an input adjustment instruction to the input sparsification unit to guide it in modifying the input vector, reducing the number of parallel activated word lines, and starting a new round of array operations.

[0088] Status Feedback and Anomaly Scheduling: The controller continuously collects the working status signals of each component, monitoring whether each component is in an idle, operational, or paused state. During the recalculation process, the controller controls the shift adder to temporarily pause the operation, waiting for a new round of valid correction calculation results. If multiple recalculations fail, the controller outputs an operation anomaly flag and reports it to the upper-level system.

[0089] A complete computation cycle scheduling link is as follows: the controller issues a start command → the input sparsification unit generates a sparsity input vector and a shift flag → the word line drive unit activates the corresponding word line → the storage array performs array computation and outputs the initial computation result → the error correction code decoder completes error correction and error judgment → the controller selects to directly forward the correction result to the shift adder or start the recomputation process according to the DED flag; after the shift adder completes the operation, it outputs the final computation result, which is forwarded by the controller to the macro external interface.

[0090] The fault-tolerant in-memory computation macro also includes an analog-to-digital converter (ADC), which is used to convert the initial computation result into the digital domain. The error-correcting code decoder then decodes and corrects the initial computation result in the digital domain.

[0091] The storage array performs vector dot product (multiplication and accumulation) operations based on analog domain current integration, and outputs the initial calculation results in analog form. The analog-to-digital converter receives the analog output of the storage array, converts the analog integral into a digital signal, and obtains the initial calculation results in the digital domain, which are then used by the back-end error correction code decoder for decoding, error judgment, and error correction.

[0092] Specifically, the sparse input vector and the stored data in the storage array perform a dot product operation. The data column and parity column of the storage array simultaneously complete analog domain multiplication and accumulation, outputting a continuous analog current / voltage signal, i.e., the initial calculation result in analog form. The analog-to-digital converter receives the analog initial calculation result output by the storage array. Since a single operation can activate a maximum of 8 word lines, the theoretical range of the dot product result is 0-8. In this embodiment, to adapt to 3-bit digital quantization, the value 8 is truncated to an equivalent of 7, and the final effective output range is constrained to 0-7, thereby reducing the hardware quantization bits and hardware overhead of the analog-to-digital converter.

[0093] It should be noted that directly treating 8 as 7 introduces a truncation error, which can also be corrected by the error-correcting code decoder. Furthermore, in actual neural network operation, the simultaneous activation of all 8 word lines is extremely rare. Based on these two considerations, this embodiment truncates 8 to 7 to reduce overhead.

[0094] The storage array comprises 256 data columns and 54 parity columns, totaling 310 columns. These 310 columns simultaneously output analog integral signals. The analog-to-digital converter (ADC) samples and quantizes these 310 analog results in parallel. The quantization rule is that each analog multiplication-accumulation result is uniformly converted into a 3-bit binary digital value, ultimately outputting 310 3-bit digital signals, forming the initial calculation results in digital domain form. After completing the quantization operation, the ADC outputs the 310 sets of 3-bit initial digital calculation results in parallel to the error correction code decoder. The error correction code decoder performs parameter calculations based on the digital signals, solving for the syndrome S, the overall parity check sum Cov, the data parity check sum Cd, and the modulo-4 difference Δmod4, thereby completing error detection, location, and data correction.

[0095] It should be noted that the fault-tolerant in-memory computation macro in this application only includes the error-correcting code decoder, and not the error-correcting encoder. This is because the encoding needs to be completed outside the fault-tolerant in-memory computation macro and stored in the storage units of the storage array. The modulo-4 sum is generated during the encoding process, and the modulo-4 difference Δmod4 is generated during the decoding process.

[0096] This application employs two mechanisms in tandem: error correction coding protection and input sparsification. On one hand, the error correction code decoder can correct data list errors and detect multiple errors; on the other hand, the input sparsification unit can reduce the number of word lines activated simultaneously, thereby reducing the bit error rate of analog computation from the source and enabling the error correction code decoder to operate under conditions with a lower bit error rate.

[0097] This application can be used in inference tasks of convolutional neural networks, fully connected neural networks, and other neural networks that involve a large number of multiplication and accumulation operations. In this application, the neural network weights are quantized to 8 bits and stored in a magnetic random access memory analog in-memory computing array. The neural network input is quantized to 8 bits, expanded, and then input into the array. The array generates partial multiplication and accumulation results, which are then used by a shift adder to generate the final output.

[0098] Please see Figure 4 The figure shown is a statistical chart of the number of word lines activated simultaneously during the model inference process according to an embodiment of this application. Figure 4 This paper presents a statistical comparison of the number of activation rows under different sparsity parameters in VGG16 and ResNet18 networks. The horizontal axis represents the number of activation rows, the left vertical axis represents the statistical count (logarithmic scale), and the right vertical axis represents the sample reduction ratio. The bar chart shows the statistical values ​​of the number of operational samples for each activation row under sparsity parameters of n=0, 1, 2, and 3. The line graph represents the sample reduction ratio of the sparsity scheme relative to the baseline scheme n=0. Experimental results show that the input sparsity strategy can effectively suppress the number of operations in high activation row scenarios. The larger the parameter n, the more significant the suppression effect. The number of samples in high activation row intervals is greatly reduced, and the optimization effect is consistent in both VGG16 and ResNet18 networks. This application can effectively improve the overall operational reliability of fault-tolerant in-memory computation macros by reducing the number of simultaneously activated word lines, reducing the simulation operation error of the in-memory computation array, and combining it with fault-tolerant coding and recomputation mechanisms.

[0099] Please see Figure 5 The figure shown is a statistical chart of the accuracy loss relative to the benchmark applied to model inference in an embodiment of this application. Figure 5 This shows a comparison of the accuracy loss between the VGG16 and ResNet18 networks. The horizontal axis represents the normalized bit error rate, and the vertical axis represents the model accuracy loss. Figure 5 The multiple curves in the figure correspond to various schemes, including those without error correction and sparsification, those with error correction but without sparsification, and those combining error correction codes with different parameter input sparsification. As the normalized bit error rate (BER) increases, the model accuracy loss of all schemes continues to increase. Under the same BER condition, the scheme without error correction and without sparsification suffers the most severe accuracy degradation. Introducing error correction codes can suppress the accuracy decline to some extent, while the scheme combining error correction codes with input sparsification can further alleviate the accuracy loss, with a particularly significant advantage in higher BER ranges. The VGG16 and ResNet18 networks in the two sub-figures exhibit consistent variation patterns, demonstrating that the fault-tolerant in-memory computing architecture combining error correction codes and input sparsification proposed in this application can effectively resist computational biases caused by hardware errors in the in-memory computing array and maintain the inference accuracy of the neural network.

[0100] Please see Figure 6The diagram shows the area and delay distribution of an embodiment of this application. It includes two pie charts, left and right, illustrating the hardware area and delay distribution of the fault-tolerant in-memory computation macro. The area distribution chart shows that the macro base array circuit occupies 80% of the total area, the redundancy check column 16.9%, and the error correction code decoder and input sparsification unit hardware occupies only 1.7% and 1.4%, respectively. The hardware area overhead caused by the addition of fault-tolerant and sparsification components is extremely low. The delay distribution chart reflects the pipeline time consumption of each component. The array section and computation account for 60.4% of the total delay, while the shift adder, error correction code decoder, and input sparsification unit account for 23%, 10.6%, and 5.9% of the delay, respectively. It is evident that the system delay is mainly dominated by the in-memory array's simulated multiply-accumulate operations, and the addition of error correction decoding and input sparsification circuitry does not introduce a significant timing burden. The combined data from both sets of data indicate that the architecture of this application achieves array fault tolerance and input sparsity with minimal area overhead and limited latency increments. The hardware cost is controllable, making it suitable for in-memory computing hardware deployment for neural network inference.

[0101] This application provides a fault-tolerant in-memory computation macro that combines error-correcting codes and input sparsification. This scheme uses an input sparsification unit to sparsify the original input vector, generating a sparse input vector and a shift flag. This reduces the number of simultaneously activated word lines, lowers analog domain noise such as current disturbances and device mismatch caused by multiple rows and columns being simultaneously activated in the memory array, and reduces the probability of computational errors in the in-memory computation array from the source, mitigating the precision degradation problem caused by large-scale parallel multiplication and accumulation. After the memory array completes vector multiplication and accumulation to obtain the initial calculation result, the error-correcting code decoder detects and corrects the computational errors. When multiple error scenarios occur that exceed the capability of a single error correction, a recalculation process can be triggered in conjunction with the controller to further improve computational reliability and effectively resist the loss of inference precision caused by non-ideal hardware characteristics. The shift adder performs multi-bit multiplication and accumulation operations on the corrected calculation result based on the shift flag, restoring the complete calculation result corresponding to the original input. Under the premise of sparsity optimization, mathematical equivalence is guaranteed, and no inherent precision loss is introduced due to sparsity processing. The controller outputs unified timing control signals to complete data interaction and process scheduling between the input sparsity unit, word lines and input driving unit, memory array, error correction code decoder, and shift adder. It sequentially drives the entire process of input sparsity, word line activation, array simulation calculation, error correction decoding, and shift accumulation, supporting the stable operation of a fault-tolerant in-memory computing macropipeline. This architecture combines input sparsity and error correction codes for dual fault tolerance, effectively suppressing accuracy loss caused by non-ideal hardware effects in the in-memory computing array, while also minimizing area and latency overhead from the added circuitry. Compared to traditional non-fault-tolerant in-memory computing architectures, this solution significantly improves neural network inference stability under high error conditions with only a small increase in hardware cost, making it suitable for deployment in deep learning network hardware acceleration scenarios.

[0102] Furthermore, this application, through a combination of Hamming codes, modulo-4, and additional checksums, enables the error-correcting code decoder to achieve single-error correction and double-error detection for ±1 errors, and to identify single ±2 errors, thus improving the fault tolerance of the multiplication and accumulation results in the analog in-memory computation section. This application increases the sparsity of the input vector through input detection and correction mechanisms, reducing the number of simultaneously activated word lines from the source. For the VGG16 network, when the number of detections n is 1, 2, and 3, the proportion of additional skipped non-zero inputs is 10.9%, 17.1%, and 20.3%, respectively, and the average number of activated lines decreases from 2.20 to 1.77, 1.58, and 1.50, respectively. For the ResNet18 network, the proportion of additional skipped non-zero inputs is 12.4%, 19.2%, and 22.6%, respectively, and the average number of activated lines decreases from 2.11 to 1.65, 1.46, and 1.37, respectively. This application can reduce the bit error rate of analog in-memory computation. When the detection intensity n is 2, the computational bit error rate (BER) of the VGG16 network is reduced by 27.8%, and that of the ResNet18 network is reduced by 26.0%. This application improves fault tolerance while maintaining inference accuracy. In the CIFAR-10 inference task using VGG16 and ResNet18, the combined use of error correction coding and input sparsity ensures that even with a normalized BER of 0.11%, the accuracy loss relative to the 8-bit quantization benchmark remains within 5%. This application achieves error correction protection and input reduction with minimal energy loss, area increase, and latency increase. Without protection, the INT8 macro's energy efficiency is 12.4 TOPS / W; with error correction coding but without input sparsity, the energy efficiency is 9.8 TOPS / W; and with both error correction coding and input sparsity units, the energy efficiency is 11.5 TOPS / W. Compared to the unprotected case, the combined use of error correction coding and input sparsity results in only a 7.3% energy efficiency loss, while using error correction coding alone results in approximately a 21% energy efficiency decrease.

[0103] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0104] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0105] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0106] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0107] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A fault-tolerant in-memory computation macro combining error-correcting codes and input sparsity, characterized in that, It includes an input sparsification unit, word lines and input driving unit, memory array, error correction code decoder, shift adder and controller; The input sparsification unit is used to perform sparsification operations on the input data of the array to obtain a sparsified input vector and a shift flag. The word line and input driving unit are used to drive the corresponding word line to activate according to the sparsed input vector, so as to obtain the activated word line; The storage array is used to store array data and to perform array calculations on the sparsed input vector according to the activation word line driving array to obtain initial calculation results; The error correction code decoder is used to decode the initial calculation result, correct the calculation errors in the initial calculation result, and output the corrected calculation result; The shift adder is used to receive the correction calculation result and perform multi-bit data multiplication and accumulation calculation operations on the correction calculation result to obtain the final calculation result; The controller is used to provide control signals and to exchange information among the input sparsification unit, word line and input driving unit, storage array, error correction code decoder, and shift adder components.

2. The fault-tolerant in-memory computation macro according to claim 1, characterized in that, The input sparsification unit performs a sparsification operation on the input data of the array to obtain a sparsified input vector and a shift flag, including: Construct an input vector set based on the input data, and remove vectors with all zero elements from the input vector set to obtain a non-zero vector set containing non-zero elements; Select a non-zero vector from the set of non-zero vectors as a reference vector, and read the shift flag corresponding to the reference vector; The reference vector is compared bit by bit with the subsequent n non-zero input vectors to determine the subset relationship between two adjacent non-zero vectors and to determine whether sparsification can be performed. If sparsification can be performed, then the sparsification operation is executed and the shift flags are merged to obtain new input data and new shift flags; The operation of removing vectors containing all zero elements is performed again on the new input data to obtain a sparse input vector; The sparse input vector is fed into the word line and input driver unit, and the new shift flag is fed into the shift adder.

3. The fault-tolerant in-memory computation macro according to claim 2, characterized in that, The criterion for determining the subset relationship between two adjacent non-zero vectors is as follows: Define two non-zero vectors as the first non-zero vector and the second non-zero vector. If the positions of the elements that are 1 in the first non-zero vector completely include the positions of the elements that are 1 in the second non-zero vector, then the second non-zero vector is called a subset of the first non-zero vector.

4. The fault-tolerant in-memory computation macro according to claim 1, characterized in that, The shift adder performs shift compensation and multi-bit multiplication and accumulation operations according to the bit shift mapping rules recorded in the shift flag, so as to output the final calculation result equivalent to the original input vector without sparsification processing.

5. The fault-tolerant in-memory computation macro according to claim 1, characterized in that, The storage array includes a dummy column, a reference column, a data column, and a check column. Each column is configured with multiple storage units. The storage units are used to store single-bit data. The storage units in the data column are used to store weight data, and the storage units in the check column are used to store check data. The weight data stored in the data column storage unit is grouped according to bit position. The least significant bit and the second least significant bit are not encoded. The remaining groups are encoded according to the rules of Hamming code, modulo 4 sum, and additional check sum to obtain the check bits. The check bits of each group are written into the corresponding check column storage unit in the same row.

6. The fault-tolerant in-memory computation macro according to claim 1, characterized in that, The storage array performs array calculations on the sparsed input vector based on the activation word lines to obtain initial calculation results, including: The corresponding row selection storage unit is determined based on the activated word line to obtain the operation storage unit; According to the operation storage unit, the sparse input vector and weight are multiplied and accumulated in the data column and the verification column channels respectively to obtain the weight multiplication and accumulation result and the verification operation result corresponding to the row weight; The initial calculation result is obtained by combining the weighted multiplication and accumulation result with the verification operation result.

7. The fault-tolerant in-memory computation macro according to claim 1, characterized in that, The error correction code decoder makes an error judgment on the initial calculation result based on the judgment parameters, which include the syntactic expression, total checksum, data checksum, and modulo-4 difference.

8. The fault-tolerant in-memory computation macro according to claim 1, characterized in that, When it is determined that the initial calculation result is error-free, or that the error occurs in the check bit, modulo-4 sum, or checksum, the error correction code decoder outputs the initial calculation result; when it is determined that the error in the initial calculation result only occurs in the data bits, the correction data bits are calculated by subtracting the modulo-4 difference from the data bits corresponding to the syntactic expression, and the error correction code decoder outputs the correction calculation result.

9. The fault-tolerant in-memory computation macro according to claim 1, characterized in that, The error correction code decoder is also used to output a recalculation signal and transmit the recalculation signal to the controller, wherein the recalculation signal is valid when the error correction code decoder determines that the error is uncorrectable; after receiving the recalculation signal, the controller controls the current calculation result to be invalid and controls the current input to be recalculated after reducing the number of active rows to obtain the recalculation result.

10. The fault-tolerant in-memory computation macro according to claim 1, characterized in that, The fault-tolerant in-memory computation macro also includes an analog-to-digital converter, which is used to convert the initial calculation result into the digital domain, and the error correction code decoder decodes and corrects the initial calculation result in the digital domain.

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