A memory-compute integrated processor architecture

Abstract

The embodiment of the application discloses a memory-computing integrated processor architecture. The processor architecture comprises a general processor core and a memory-computing integrated execution unit. A resistive random access memory (RRAM) special function unit is arranged in the general processor core. The RRAM special function unit has an independent emission slot and exchanges data with the memory-computing integrated execution unit through a register-RRAM direct connection data port. The general processor core is used for splitting a complete memory-computing operation into three types of independent instructions, which are executed by the RRAM special function unit. The independent instructions comprise a feature data injection instruction, an execution trigger instruction and a result receiving instruction. The three types of independent instructions can be executed simultaneously. The scheme provided by the embodiment of the application can give full play to the parallel computing advantage of the memory-computing integration and improve the overall execution efficiency of the processor.

Description

Technical Field

[0001] This application relates to the field of integrated circuit and computer architecture technology, and more specifically, to a memory computing processor architecture. Background Technology

[0002] In recent years, Computing-In-Memory (CIM) technology has received widespread attention as a key path to overcome the von Neumann "memory wall" bottleneck. Among various in-memory media, analog in-memory computing technology based on resistive random-access memory (RRAM) has become one of the core technologies for next-generation AI (Artificial Intelligence) accelerators due to its high density and low power consumption characteristics. RRAM can not only store data, but also directly perform analog multiply-accumulate (MAC) operations using Kirchhoff's laws within the memory array, realizing vector-matrix multiplication (VMM).

[0003] However, the setup and stabilization cycle of a single operation in analog in-memory computing is relatively long compared to the clock cycle of a digital CPU (Central Processing Unit) (typically tens to hundreds of CPU cycles). In known technologies, a complete RRAM in-memory operation can include three stages: data preparation, computation, and result return. In single-channel sequential execution mode, the long-cycle RRAM in-memory operation is directly implemented as a single processor instruction. During the execution of any stage, other processing units are idle. For example, during data preparation or result return, the computing array experiences significant idle time. This approach fails to fully leverage the parallel computing advantages of in-memory computing and greatly reduces the overall execution efficiency of the processor. Therefore, improving the execution efficiency of in-memory processors has become a pressing technical problem. Summary of the Invention

[0004] This application provides a memory computing processor architecture to improve the execution efficiency of memory computing processors. The specific technical solution is as follows.

[0005] In a first aspect, embodiments of this application provide a memory computing processor architecture, the processor architecture including: a general-purpose processor core and a memory computing execution unit; The general-purpose processor core is equipped with a dedicated Resistive Random Access Memory (RRAM) functional unit. The RRAM dedicated functional unit has an independent emitter slot and exchanges data with the in-memory computing execution unit through the register-RRAM direct data connection port. The general-purpose processor core is used to break down a complete memory operation into three independent instructions, which are executed by the RRAM dedicated function unit. The independent instructions include: feature data injection instructions, execution trigger instructions, and result receiving instructions. The three independent instructions can be executed simultaneously. The feature data injection instruction is used to inject feature data from the processor's vector register into the feature cache of the in-memory execution unit through the direct data port. The execution trigger instruction is used to send computing configuration information to the in-memory computing execution unit and trigger the hardware computing state machine. The execution trigger instruction exits the processor pipeline after completing the handshake with the in-memory computing execution unit without waiting for the simulation calculation to complete. The result receiving instruction is used to asynchronously read the calculation result from the result cache into the vector register of the processor through the direct data port after the in-memory computing execution unit has completed the calculation.

[0006] In one embodiment of this application, the in-memory computing execution unit internally maintains a first channel and a second channel, and the first channel and the second channel share a hardware computing state machine; When the first channel occupies the shared computing state machine to perform simulation operations, the processor can write feature data to the second channel or read the calculation results through instructions. At the same time, the processor can continue to issue other computing instructions to keep the pipeline fully loaded. The execution of the result receiving instruction does not occupy the shared computing state machine. When the corresponding channel calculation has not been completed, the result receiving instruction is automatically blocked by the hardware and waits.

[0007] In one embodiment of this application, the in-memory computing execution unit maintains a dual-channel scheduling state machine, including an idle state, a first-channel working state, and a second-channel working state. When in the first-channel working state, the second-channel execution trigger instruction issued by the processor is temporarily stored in the execution unit hardware, and the second-channel calculation is automatically triggered after the first-channel calculation is completed.

[0008] In one embodiment of this application, the feature cache is shared by two channels, while the result cache is set independently for each of the two channels.

[0009] In one embodiment of this application, the direct data port adopts a request / ready point-to-point handshake protocol, and the data bit width is aligned with the bit width of the vector register.

[0010] In one embodiment of this application, the vector register of the processor has a bit width of N bits, and the total bit width of the input feature vector and the total bit width of the single calculation result of the in-memory execution unit are both M bits, where M is greater than N; On the data injection side, the processor writes the complete feature vector into the feature cache in batches by continuously issuing multiple feature data injection instructions, and the write pointer is automatically incremented after each write. On the result receiving side, the in-memory computing execution unit maintains a read pointer internally. The processor retrieves the complete calculation results in batches by continuously issuing multiple result receiving instructions, and the read pointer is automatically incremented after each reception.

[0011] In one embodiment of this application, the vector register has a bit width N of 1024 bits, the total bit width of the input feature vector and the total bit width M of the single calculation result are both 2048 bits, the processor completes feature writing by continuously issuing two feature data injection instructions, and retrieves the complete calculation result by continuously issuing two result receiving instructions.

[0012] In one embodiment of this application, the in-memory computing execution unit includes an adaptive cycle control circuit; The adaptive cycle control circuit is used to automatically switch between a long waiting period and a short waiting period based on whether the feature data is updated and whether the calculated row and column addresses have changed. When the feature data or row and column addresses change, a long waiting period is used to ensure the stability of the analog circuit, and when the feature data and row and column addresses do not change, a short waiting period is used to improve performance.

[0013] In one embodiment of this application, the in-memory computing execution unit includes an instruction control interface and a status control interface; The instruction control interface responds to the three types of independent instructions through the direct data port and processes the computational data stream; the status control interface sets the underlying simulation parameters through the configuration bus.

[0014] In one embodiment of this application, after the execution trigger instruction exits the pipeline, the processor continues to issue and execute other instructions through hardware out-of-order scheduling or compiler static scheduling; the instruction waiting of the RRAM dedicated function unit does not occupy the execution resources of the general function unit.

[0015] The in-memory computing processor architecture provided in this application embodiment can set up a dedicated RRAM function unit in the processor pipeline, and exchange data with the in-memory computing execution unit through the register-RRAM direct connection data port. Furthermore, this in-memory computing processor architecture can decompose long-cycle RRAM simulated in-memory computing operations into three independent short-cycle instructions: feature data injection instructions, execution trigger instructions, and result receiving instructions. These instructions are executed by the dedicated RRAM function unit, and these three independent instructions can be executed simultaneously. That is, the execution of any instruction does not affect the execution of the other two types of instructions. Thus, during the execution of any instruction, other processing units can be in a working state at the same time, giving full play to the parallel computing advantages of in-memory computing and improving the overall execution efficiency of the processor. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0017] Figure 1 This illustration shows a schematic diagram of a memory computing processor architecture provided in an embodiment of this application; Figure 2 This diagram illustrates the integration location of the RRAM dedicated functional unit in the processor pipeline; Figure 3(a) shows a schematic diagram of a dual-channel RRAM fully loaded scenario; Figure 3(b) shows a schematic diagram of a scenario where the dual-channel RRAM is not fully loaded and is idle; Figure 3(c) shows a schematic diagram of a single-channel mode (RECV instruction blocking and waiting) scenario. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0019] It should be noted that the terms "comprising" and "having," and any variations thereof, in the embodiments and accompanying drawings of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0020] This application provides an in-memory computing processor architecture that can improve the execution efficiency of in-memory computing processors. The embodiments of this application are described in detail below.

[0021] Figure 1 The diagram shows a schematic of a memory computing processor architecture provided in an embodiment of this application. The processor architecture includes a general-purpose processor core 110 and a memory computing execution unit 120.

[0022] The general-purpose processor core 110 includes a dedicated RRAM function unit. This RRAM function unit has an independent issue slot and exchanges data with the in-memory execution unit 120 via a register-RRAM direct connection data port. The general-purpose processor core is used to break down a complete in-memory operation into three independent instructions, which are executed by the dedicated RRAM function unit. These independent instructions include: feature data injection instructions, execution trigger instructions, and result receiving instructions. These three types of independent instructions can be executed simultaneously.

[0023] In the in-memory computing processor architecture provided in this application embodiment, a dedicated RRAM functional unit is set in the processor pipeline. This functional unit has an independent issue slot and is dedicated to processing three types of instructions: feature data injection instructions (FEED), execution trigger instructions (EXEC), and result reception instructions (RECV). The dedicated RRAM functional unit exchanges data with the in-memory computing execution unit 120 through a register-RRAM direct connection data port. This data port has the following characteristics: it does not go through a memory hierarchy (Cache / Memory), does not require address translation (TLB), adopts a req / ready point-to-point handshake protocol, and the data bit width is aligned with the vector register bit width. The wait cycle of RRAM instructions does not occupy the execution resources of general-purpose functional units and does not affect the normal issuance and execution of other instructions.

[0024] Additionally, the in-memory execution unit 120 (RRAM Core) includes 2048 bits of load-reg and 1024 bits of out. The general-purpose processor core may also include a Scalar Core (containing sreg0-sreg31 sreg registers), a Vector Core, a vector register set (vreg0-vreg31, 1024 bits), and an LSU (Load Store Unit). The Scalar Core can issue instructions to the Vector Core and RRAM Core, with the scalar registers providing address operands; the vector register set acts as the central data hub, interacting with the Vector Core, RRAM Core, and LSU via 1024-bit direct connections.

[0025] Figure 2 The diagram illustrates the integration location of RRAM dedicated function units in the processor pipeline, demonstrating their parallel relationship with general-purpose function units. As shown, the Issue Unit contains four issue slots (Scalar, Vector, LSU, and RRAM), enabling data interaction with the Instruction Write-Back Reordering Unit. The RRAM dedicated function units (RRAM FUs) have independent issue slots and interact with the in-memory execution unit via the register-RRAM direct data connection port. The Vector Regfile exchanges data bidirectionally with the direct data connection port via FEED / RECV (1024 bits).

[0026] Specifically, in this embodiment, the feature data injection instruction is used to inject feature data from the processor's vector register into the feature cache of the in-memory computing execution unit through a direct data port; the execution trigger instruction is used to send computation configuration information to the in-memory computing execution unit and trigger the hardware computation state machine. The execution trigger instruction exits the processor pipeline immediately after completing the handshake with the in-memory computing execution unit without waiting for the simulation computation to complete; the result receiving instruction is used to asynchronously read the computation result from the result cache into the processor's vector register through a direct data port after the in-memory computing execution unit completes the computation.

[0027] In other words, in this embodiment, the Feature Data Injection (FEED) instruction is used to inject the feature data required for computation from the processor's vector register into the feature buffer of the in-memory execution unit 120 via the register-RRAM direct data port. This instruction does not go through the storage hierarchy and address translation, and completes the data transmission using a point-to-point handshake protocol.

[0028] The EXEC instruction is used to send computation configuration information to the in-memory execution unit 120 and trigger the hardware computation state machine. After completing the handshake with the in-memory execution unit 120, this instruction exits the processor pipeline without waiting for the simulation to complete. The processor can then continue to issue and execute subsequent unrelated instructions. This process can be implemented by hardware dynamic scheduling in out-of-order processors and by compiler static scheduling in sequential processors.

[0029] The Result Receive instruction (RECV) is used to asynchronously read the calculation result from the result buffer of the in-memory execution unit 120 into the processor's vector register via the register-RRAM direct data port after the in-memory execution unit 120 has completed the calculation.

[0030] As can be seen, the in-memory computing processor architecture provided in this application decomposes long-cycle RRAM-simulated in-memory operations into three independent short-cycle instructions: feature data injection instructions, execution trigger instructions, and result receiving instructions. These instructions are executed by dedicated RRAM functional units, and they can be executed simultaneously. This means that the execution of any one instruction does not affect the execution of the other two types of instructions. Therefore, during the execution of any instruction, other processing units can be in a working state simultaneously, fully leveraging the parallel computing advantages of in-memory computing and improving the overall execution efficiency of the processor. Furthermore, it achieves decoupling of computing resources. The dedicated RRAM functional units have independent issue slots and direct data ports. The execution and waiting of RRAM instructions do not occupy general-purpose functional unit resources, ensuring the normal operating efficiency of other parts of the system. In addition, after instruction decomposition, the execution latency of each instruction is short and controllable, preventing prolonged blocking of the processor pipeline. The compiler does not need to perform complex scheduling to avoid ultra-long-cycle instructions. Simultaneously, the decomposed instruction structure allows the compiler to further utilize the interval between EXEC and RECV for instruction rearrangement optimization.

[0031] In one embodiment of this application, the aforementioned register-RRAM direct-connect data port can adopt a request / ready point-to-point handshake protocol, and the data bit width is aligned with the bit width of the vector register.

[0032] In one specific implementation, the processor's vector register can have a bit width of N bits, and the total bit width of the input feature vector and the total bit width of a single calculation result of the in-memory execution unit 120 are both M bits, where M is greater than N. On the data injection side, the processor writes the complete feature vector into the feature cache in batches by continuously issuing multiple feature data injection instructions, and the write pointer is automatically incremented after each write. On the result receiving side, the in-memory execution unit maintains a read pointer internally, and the processor retrieves the complete calculation result in batches by continuously issuing multiple result receiving instructions, and the read pointer is automatically incremented after each reception.

[0033] For example, the vector register bit width N can be 1024 bits, the total bit width of the input feature vector and the total bit width of the single calculation result M are both 2048 bits. The processor completes the feature writing by issuing two consecutive feature data injection instructions and retrieves the complete calculation result by issuing two consecutive result receiving instructions.

[0034] The processor's vector registers have a width of 1024 bits, while the total width of the input feature vectors and the total width of the single computation result in the in-memory execution unit 120 are both 2048 bits. Therefore, on the data injection side, the processor can write the complete feature vectors to the feature cache in batches by issuing multiple FEED instructions consecutively, with the write pointer automatically incrementing after each write. On the result receiving side, the in-memory execution unit 120 internally maintains a read pointer. The processor reads the complete computation result into multiple vector registers in batches by issuing multiple RECV instructions consecutively, with the read pointer automatically incrementing after each read. This allows the single processing bit width of the RRAM to differ from the processing bit width of the vector processor, providing design flexibility.

[0035] In one embodiment of this application, after the EXEC trigger instruction exits the pipeline, the processor can continue to issue and execute other instructions through hardware out-of-order scheduling or compiler static scheduling. The instruction waiting of the RRAM dedicated function unit does not occupy the execution resources of the general function unit, thereby making full use of the processor's processing resources and improving the system's computing power.

[0036] In one embodiment of this application, in order to further improve the execution efficiency of the processor, a first channel and a second channel can be maintained logically inside the in-memory computing execution unit 120. The first channel and the second channel share a hardware computing state machine. When the first channel occupies the shared computing state machine to perform simulation calculations, the processor can write feature data to the second channel or read the calculation results through instructions. At the same time, the processor can continue to issue other calculation instructions to keep the pipeline fully loaded. The execution of the result receiving instruction does not occupy the shared computing state machine. When the calculation of the corresponding channel has not been completed, the result receiving instruction is automatically blocked by hardware and waits.

[0037] Specifically, the in-memory execution unit 120 can maintain a dual-channel scheduling state machine, including an idle state, a first-channel working state, and a second-channel working state. When in the first-channel working state, the second-channel execution trigger instruction issued by the processor is temporarily stored in the execution unit hardware, and the second-channel calculation is automatically triggered after the first-channel calculation is completed. Furthermore, the feature cache is shared by both channels, while the result cache is set independently for each of the two channels.

[0038] In other words, in this embodiment, the in-memory computing execution unit 120 can internally maintain logical channels A and B. Unlike known hardware-based automatic ping-pong buffering, the dual channels in this application are explicitly controlled by processor instructions. That is, the processor can explicitly select which channel's computation to trigger using EXEC_A / EXEC_B instructions, and explicitly specify which channel's results to retrieve using RECV_A / RECV_B instructions. The channel switching order is not subject to fixed hardware constraints; for example, it can be an alternation of A→B→A→B, or any combination of A→A→B→A, entirely determined by the software based on business requirements. Here, "business" can be determined by the software based on the characteristics of the current task. Whether the software alternates between channels or uses only one channel, the result is the same.

[0039] The two channels share a single hardware computing state machine, but operate independently during the data preparation (FEED) and result reception (RECV) phases. While the first channel occupies the shared computing state machine for long-cycle simulation operations, the processor can write feature data or read calculation results via instructions from the second channel. The key coordination mechanism lies in the processor's ability to issue the EXEC instruction for the next channel in advance. The execution mechanism temporarily stores this instruction (pend) through a hardware handshake, automatically triggering the next channel's computation after the current channel completes its calculation. This achieves seamless connection of the computing array and maximizes the utilization of computing resources. Simultaneously, the processor can continue to issue other computing instructions during the waiting period, keeping the processor pipeline fully loaded. This combination of explicit instruction-level control and automatic hardware-level coordination ensures the in-memory computing array remains continuously fully loaded. These other computing instructions refer to all instructions unrelated to RRAM, such as RISC-V vector addition instructions, scalar operations, and memory accesses. This allows the processor to execute other instructions during long periods of RRAM computation, improving system efficiency.

[0040] It should be noted that, of the two channels mentioned above, the software can use only one channel or arbitrarily alternate between the two channels, and the hardware can guarantee correctness.

[0041] The following examples illustrate the scheduling process of the internal logic dual channels (A / B channels) and computing state machine of the in-memory computing execution unit 120, demonstrating the independence of WORK_A / WORK_B state transitions and RECV operations from the computing state machine.

[0042] Figures 3(a), 3(b), and 3(c) illustrate the timing diagrams of the collaborative operation between the instruction set and the execution set under different instruction arrangement scenarios. The core design idea is to ensure the correctness and efficiency of execution under any instruction arrangement through a reasonable instruction blocking and handshake protocol with the execution set. When the instruction issued by the processor precedes the readiness state of the execution set, the instruction is automatically blocked (stalled) by the hardware, waiting for the execution set to become ready before continuing; when the instruction issued by the processor is later than the completion of the execution set, the execution set will idle and wait. Therefore, the optimization goal of the compiler or hardware scheduler is to align the instruction issuance timing with the execution set readiness timing as much as possible, maximizing the utilization of the computing array.

[0043] Figure 3(a) illustrates a scenario with dual-channel RRAM fully loaded. The figure shows three parallel layers: processor instruction flow, RRAM state, and writeback. The timing is arranged from left to right. As shown in the figure, when the RRAM state is in calculation state (calculation 1), the EXEC_B instruction is issued by the processor in advance. Therefore, this instruction is blocked during execution, waiting for the previous RRAM calculation to finish. Since EXEC_B has already been issued in advance, the RRAM execution mechanism does not need to wait for a new instruction to arrive and can immediately start the second calculation (calculation 2), with no idle gaps in the calculation array. Simultaneously, RECV_A completes the writeback (WB1) during the second calculation, executing in parallel with the RRAM calculation. This is the optimal instruction arrangement scenario, maximizing the utilization of the calculation array.

[0044] Figure 3(b) illustrates an idle scenario where the dual-channel RRAM is not fully loaded. As shown in the figure, when EXEC_B is issued, the RRAM execution mechanism has already completed the previous calculation (calculation 1), resulting in an idle gap between the two calculations. This indicates that the processor inserted too many other instructions during the previous calculation, causing EXEC_B to be issued later than the execution mechanism is ready. Although the utilization of the computing array decreases, the correctness of the execution is still guaranteed, and the execution mechanism starts calculation immediately after EXEC_B arrives (calculation 2). This is the compiler's optimization space; by reducing the number of irrelevant instructions between the two EXECs, the timing can be made closer to the optimal state in Figure 3(a).

[0045] Figure 3(c) illustrates a single-channel mode (RECV instruction blocking and waiting) scenario, showing the single-channel operating mode using only channel A. As shown, the processor issues the RECV_A instruction after EXEC_A, but the RRAM execution mechanism has not yet completed the previous calculation (calculation 1). The RECV_A instruction is automatically blocked by the hardware, waiting for the execution mechanism to complete the calculation and write the result to the Result Buffer before RECV completes and writes the result back. This demonstrates the core value of the hardware blocking mechanism: regardless of when the processor issues RECV, the hardware can guarantee that the read-back result is the correct calculation result. In single-channel mode, the compiler's optimization goal is to insert as many irrelevant instructions as possible between EXEC and RECV, so that the calculation is completed when RECV is issued, thereby avoiding blocking.

[0046] The three timing scenarios described above collectively illustrate the core principles of the collaborative design between the instruction and execution mechanisms in this application: The correctness of execution under any instruction arrangement is guaranteed through the req / ready handshake protocol and automatic hardware blocking mechanism; Data preparation, result feedback, and simulation computation can deeply overlap through dual-channel instruction-driven collaboration and the instruction pre-issue mechanism, allowing the in-memory computing array to maintain an extremely high load rate, thus achieving continuous full load and efficient utilization of the computing array. Correctness is guaranteed by hardware, while efficiency is optimized by software. This effectively solves the problem of long latency in simulated in-memory computing blocking the processor pipeline, is compatible with both sequential and out-of-order execution processors, and significantly improves the overall execution efficiency and computing power utilization of the in-memory computing system.

[0047] In one embodiment of this application, the in-memory computing execution unit 120 further includes an adaptive cycle control circuit, which automatically switches between a long waiting cycle and a short waiting cycle based on whether the feature data is updated and whether the calculation row and column addresses change; when the feature data or row and column addresses change, a long waiting cycle is used to ensure the stability of the analog circuit, and when neither the feature data nor the row and column addresses change, a short waiting cycle is used to improve performance.

[0048] The aforementioned adaptive cycle control circuit can automatically switch between long waiting cycles (for stabilizing the analog circuit) and short waiting cycles (for accelerating repetitive calculations) based on whether the feature data is updated and whether the calculation row and column addresses change, without software intervention, thereby improving the overall computational efficiency of the system. The hardware adaptive mechanism of long and short waiting cycles is a physical requirement of the analog circuit's setup time. The hardware autonomously switches between these cycles, avoiding software's awareness and intervention in low-level timing details, thus reducing compiler scheduling complexity.

[0049] In one embodiment of this application, the in-memory computing execution unit 120 may further include an instruction control interface and a status control interface; the instruction control interface responds to three types of independent instructions through a direct data port and processes the computational data stream; the status control interface sets the underlying simulation parameters through a configuration bus.

[0050] The in-memory computing processor architecture provided in this application will be described below with reference to a specific embodiment.

[0051] In this embodiment, the processor can be a RISC-V vector processor, with the vector register width defined as 1024 bits. The in-memory execution unit uses RRAM to simulate a computing array, with a single calculation result of 2048 bits (4 banks × 512 bits). The processor can be a high-performance core supporting out-of-order execution and reorder cache (ROB), or a low-power core supporting in-order execution.

[0052] The instruction set is defined as follows: ; During the processor decoding phase, if the instruction is identified as an RRAM instruction, it is routed to the issue slot of the dedicated RRAM function unit. During the execution phase, the FEED instruction writes vector register data to the RRAM controller's Feature Buffer via the direct data port; the EXEC instruction sends configuration information and triggers the computational state machine via the direct port, marking completion and exiting the pipeline upon successful handshake; the RECV instruction initiates a request to the RRAM controller via the direct port, waiting for the ready signal to be valid before reading data and writing it to the target vector register. During this period, general-purpose function units (ALU, vector operation unit, general-purpose LSU, etc.) continue processing other instructions without interference.

[0053] The RRAM controller internally maintains a dual-channel scheduling state machine (WORK_A / WORK_B). A typical workflow is as follows: The first step is data injection into channel A. The processor executes RRAM_FEED multiple times to write the feature data into the Feature Buffer in batches. Since the vector register has a bit width of 1024 bits, while the total length of the input feature vector is 2048 bits (4 banks × 512 bits), two FEED operations are required to complete the writing.

[0054] The second step triggers the A-channel computation. The processor executes RRAM_EXEC_A, the state machine enters the WORK_A state, and RRAM begins a long-cycle simulation computation. After the instruction handshake is successful, it quickly exits the pipeline.

[0055] The third step is to mask the delay and prepare for channel B. During channel A computation, the processor fully utilizes this hardware computation delay to do two things: first, execute other vector operation instructions, scalar operation instructions, or memory access instructions to keep the processor pipeline fully loaded; second, if there is a second set of computation tasks, the processor executes RRAM_FEED in advance to prepare data for channel B, and then executes RRAM_EXEC_B. Completing the data injection for channel B in advance is a key design point. It ensures that after CAL_A ends, the hardware state machine can immediately start CAL_B, avoiding the computation array from being idle due to waiting for data. Since the state machine is occupied by channel A, the EXEC request for channel B is temporarily stored (pend_b), and automatically switches to start channel B computation immediately after channel A computation is completed.

[0056] The fourth step is to asynchronously receive the result from channel A. After the calculation of channel A is completed, the state machine automatically switches to WORK_B to begin the calculation of channel B. The processor executes RRAM_RECV_A to read the result of channel A back to the vector register. At this time, the RECV operation does not occupy the RRAM calculation state machine and is performed in parallel with the calculation of channel B.

[0057] Fifth step: Receive the result of channel B. After the calculation of channel B is completed, the processor executes RRAM_RECV_B to retrieve the result.

[0058] During the above execution process, the adaptive cycle control circuit inside the RRAM controller monitors the input status in real time. When RRAM_EXEC is triggered, the circuit determines the waiting period based on the following two conditions: Condition 1: Has a new FEED been written since the last calculation (has the feature data been updated)? Condition 2: Are the start / end line addresses of this calculation different from the last one?

[0059] If either condition is true, the hardware will enable the control signal `use_long_time` and adopt a preset long wait period (configured by the register `reg_ana_cal_wait_long_cycle`) to ensure that the analog circuit and bit line feature voltages are sufficiently stable. If both conditions are false (e.g., feature map multiplexing in convolution operations, where only the column select signal is changed to scan different weight columns), the hardware will automatically adopt a preset short wait period (configured by the register `reg_ana_cal_wait_normal_cycle`) to improve overall computational performance.

[0060] In addition, this application proposes a dedicated compilation scheduling method for RRAM triple-split instructions and A / B dual-channel architecture, which includes the following three core mechanisms: (1) Variable period delay model Unlike known compilers that use a fixed-delay model, this method establishes a data-dependent-aware variable-cycle delay model. The compiler analyzes the characteristic data reuse patterns of loop structures in the program to determine whether each EXEC instruction execution will trigger a long or short hardware wait cycle. 1. If the analysis shows that a new FEED was written (feature data update) before this EXEC, or the row and column addresses changed, then a long wait cycle is predicted (corresponding to the configuration value of the hardware register reg_ana_cal_wait_long_cycle). 2. If the analysis shows that the feature data and row address remain unchanged (e.g., only the column selection signal scans different weight columns in the convolution operation), then the prediction is a short waiting period (corresponding to reg_ana_cal_wait_normal_cycle).

[0061] Based on this prediction, the compiler accurately calculates the number of instructions that need to be padded between each EXEC and RECV, avoiding performance loss caused by conservative estimation.

[0062] (2) Dual-channel sensing instruction interleaving scheduling The compiler maintains the logic state model for both A and B channels, and the following hardware constraints must be understood: 1. The A / B channels share the computing state machine, and only one channel can occupy computing resources at any given time; 2. RECV operations do not occupy the computational state machine and can be performed in parallel with the computation of another channel; 3. The Feature Buffer is shared by both channels, while the Result Buffer is independent.

[0063] Based on these constraints, the compiler interleaves and arranges multiple independent RRAM computation tasks. A typical scheduling pattern is: FEED (feature A) → EXEC_A → [FEED (feature B) + irrelevant instructions] → EXEC_B → [irrelevant instructions] → RECV_A → [irrelevant instructions] → RECV_B.

[0064] The compiler inserts the FEED sequence for channel B into the computation wait period for channel A. This serves two purposes: first, to fully utilize the simulation delay of channel A to prepare data for channel B; and second, and more importantly, to ensure that the hardware can immediately start CAL_B after CAL_A ends, preventing the computation array from being idle while waiting for data, thus achieving continuous full load on the in-memory array. Simultaneously, during the execution of hardware CAL (regardless of channel A or B), the processor can fill in other computation instructions (vector operations, scalar operations, memory accesses, etc.) to keep the processor pipeline fully loaded. Furthermore, scheduling RECV_A after EXEC_B leverages the characteristic that RECV does not occupy the computation state machine, allowing data reading for RECV_A to occur in parallel with the simulation computation of channel B.

[0065] (3) RECV blocking-aware scheduling constraints The compiler understands the special nature of the RECV instruction: if the computation of the corresponding channel has not yet been completed, RECV will wait until the result is ready. Therefore, the compiler follows these constraints during scheduling: 1. The timing of issuing the RECV command must ensure that the calculation of the corresponding channel has been completed with a high probability (i.e., the number of commands between EXEC and RECV is not less than the number of predicted delay cycles). 2. Subsequent instructions that depend on the result of RECV must not be inserted between EXEC and RECV as padding instructions; 3. When the available irrelevant instructions are insufficient to fill the prediction delay, the compiler can insert NOP instructions or fire RECV early and accept a possible short wait.

[0066] For sequential execution processors, static scheduling by the compiler is the primary means of masking latency; for out-of-order execution processors, the compiler's scheduling works in conjunction with the hardware's dynamic scheduling to achieve a deeper level of latency masking.

[0067] The register-RRAM direct connection data port signals between the in-memory execution unit (RRAM controller) and the RRAM dedicated function unit are defined as follows: ; This application sets up two independent control interfaces in the in-memory computing execution unit: The instruction control interface (ICI) handles the computational data stream, directly responding to three types of instructions issued by the processor through the RRAM dedicated function unit: RRAM_FEED, RRAM_EXEC, and RRAM_RECV. This interface performs a high-speed handshake with the processor via the register-RRAM direct data port, serving as the primary data path for computational tasks. Its characteristics include high bandwidth, low-latency handshake, and synchronization with the processor pipeline cycle.

[0068] The status control interface configures a series of status registers via the APB bus, responsible for the static configuration of the underlying hardware. These configurations are set during system initialization and typically remain unchanged during operation. Key configuration items include: ; By separating the instruction data stream from the state configuration stream, both efficient and concise computation instructions are ensured, while providing the ability to finely control the analog in-memory computing array. The separation of the two interfaces also ensures that system initialization configuration and runtime computation do not interfere with each other.

[0069] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of one embodiment, and the modules or processes shown in the drawings are not necessarily essential for implementing this application.

[0070] Those skilled in the art will understand that the modules in the apparatus of the embodiments can be distributed in the apparatus of the embodiments as described in the embodiments, or they can be located in one or more devices different from this embodiment with corresponding changes. The modules of the above embodiments can be combined into one module, or they can be further divided into multiple sub-modules.

[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A memory computing processor architecture, characterized in that, The processor architecture includes: a general-purpose processor core and an in-memory execution unit; The general-purpose processor core is equipped with a dedicated Resistive Random Access Memory (RRAM) functional unit. The RRAM dedicated functional unit has an independent emitter slot and exchanges data with the in-memory computing execution unit through the register-RRAM direct data connection port. The general-purpose processor core is used to break down a complete memory operation into three independent instructions, which are executed by the RRAM dedicated function unit. The independent instructions include: feature data injection instructions, execution trigger instructions, and result receiving instructions. The three independent instructions can be executed simultaneously. The feature data injection instruction is used to inject feature data from the processor's vector register into the feature cache of the in-memory execution unit through the direct data port. The execution trigger instruction is used to send computing configuration information to the in-memory computing execution unit and trigger the hardware computing state machine. The execution trigger instruction exits the processor pipeline after completing the handshake with the in-memory computing execution unit without waiting for the simulation calculation to complete. The result receiving instruction is used to asynchronously read the calculation result from the result cache into the vector register of the processor through the direct data port after the in-memory computing execution unit has completed the calculation.

2. The in-memory computing processor architecture according to claim 1, characterized in that, The in-memory computing execution unit maintains a first channel and a second channel in the internal logic, and the first channel and the second channel share a hardware computing state machine; When the first channel occupies the shared computing state machine to perform simulation operations, the processor can write feature data to the second channel or read the calculation results through instructions. At the same time, the processor can continue to issue other computing instructions to keep the pipeline fully loaded. The execution of the result receiving instruction does not occupy the shared computing state machine. When the corresponding channel calculation has not been completed, the result receiving instruction is automatically blocked by the hardware and waits.

3. The in-memory computing processor architecture according to claim 2, characterized in that, The in-memory computing execution unit maintains a dual-channel scheduling state machine, including an idle state, a first-channel working state, and a second-channel working state. When in the first-channel working state, the second-channel execution trigger instruction issued by the processor is temporarily stored by the execution unit hardware, and the second-channel calculation is automatically triggered after the first-channel calculation is completed.

4. The in-memory computing processor architecture according to claim 2, characterized in that, The feature cache is shared by both channels, while the result cache is set independently for each of the two channels.

5. The in-memory computing processor architecture according to claim 1, characterized in that, The direct data port uses a request / ready point-to-point handshake protocol, and the data bit width is aligned with the bit width of the vector register.

6. The in-memory computing processor architecture according to claim 1, characterized in that, The vector register of the processor has a bit width of N bits, and the total bit width of the input feature vector and the total bit width of the single calculation result of the in-memory execution unit are both M bits, where M is greater than N; On the data injection side, the processor writes the complete feature vector into the feature cache in batches by continuously issuing multiple feature data injection instructions, and the write pointer is automatically incremented after each write. On the result receiving side, the in-memory computing execution unit maintains a read pointer internally. The processor retrieves the complete calculation results in batches by continuously issuing multiple result receiving instructions, and the read pointer is automatically incremented after each reception.

7. The in-memory computing processor architecture according to claim 6, characterized in that, The vector register has a bit width N of 1024 bits, and the total bit width of the input feature vector and the total bit width M of the single calculation result are both 2048 bits. The processor completes the feature writing by continuously issuing two feature data injection instructions and retrieves the complete calculation result by continuously issuing two result receiving instructions.

8. The in-memory computing processor architecture according to any one of claims 1-7, characterized in that, The in-memory computing execution unit includes an adaptive cycle control circuit. The adaptive cycle control circuit is used to automatically switch between a long waiting cycle and a short waiting cycle based on whether the feature data is updated and whether the calculation row and column addresses change. Use a long wait period when the feature data or row / column address changes to ensure the stability of the analog circuit, and use a short wait period when neither the feature data nor the row / column address changes to improve performance.

9. The in-memory computing processor architecture according to any one of claims 1-7, characterized in that, The in-memory computing execution unit includes an instruction control interface and a status control interface; The instruction control interface responds to the three types of independent instructions through the direct data port and processes the computational data stream; the status control interface sets the underlying simulation parameters through the configuration bus.

10. The in-memory computing processor architecture according to any one of claims 1-7, characterized in that, After the execution trigger instruction exits the pipeline, the processor continues to issue and execute other instructions through hardware out-of-order scheduling or compiler static scheduling; the instruction waiting of the RRAM dedicated function unit does not occupy the execution resources of the general function unit.

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