server

Abstract

The application discloses a kind of servers, it is related to server technical field, including first processor, second processor, first logic control device, second logic control device.First processor is connected with first logic control device, second processor is connected with second logic control device, first logic control device is connected with second logic control device.First logic control device and second logic control device are configured to: according to received level signal, identify server architecture type, and based on identification result, cooperatively control the running state of first processor and second processor related to architecture type;Architecture type includes double-path architecture and double-node architecture.Through first, second logic control device receives level signal to identify server architecture type, and cooperatively controls the running state of corresponding processor, without being designed separately for different architecture, realize the flexible adaptation of multiple architectures, reduce development and hardware configuration cost while guaranteeing the stability of system running under different architectures.

Description

Technical Field

[0001] This application relates to the field of server technology, and more particularly to a server. Background Technology

[0002] As core computing devices, the basic hardware architecture of servers is usually directly related to the number of processors integrated on the server motherboard. For example, a server motherboard with a single processor can form a single-socket server, a server motherboard with two processors can form a dual-socket server, and a server with two processors deployed in an independent node mode can form a dual-node server. Under the current product development model, in order to adapt to different server architectures such as single-socket, dual-socket, and dual-node, the industry generally adopts a strategy of designing and developing dedicated server motherboards independently for each architecture.

[0003] This development model, which uses a single architecture for dedicated server motherboards, significantly extends the overall product development cycle and increases R&D and production costs. On the other hand, it prevents the core hardware components of servers with different architectures from being interchangeable in terms of materials and inventory sharing, which significantly increases the difficulty of supply chain management and can easily lead to problems such as material backlog and resource waste. Summary of the Invention

[0004] This application provides a server that at least solves the technical problems in the related art, such as the need to independently develop dedicated motherboards for different server architectures, resulting in long R&D cycles, high development costs, non-universal core hardware, complex supply chain management, and easy waste of resources.

[0005] This application provides a server, including: a first processor, a second processor, a first logic controller, and a second logic controller. The first processor is connected to the first logic controller, the second processor is connected to the second logic controller, and the first logic controller is connected to the second logic controller.

[0006] The first and second logic controllers are configured to: identify the server architecture type based on the received level signal, and coordinately control the operating status of the first and second processors related to the architecture type based on the identification result; the architecture type includes dual-path architecture and dual-node architecture.

[0007] This application achieves automatic architecture type identification by relying on the first and second logic controllers, and then adaptively coordinates the operation of the first and second processors based on the identification results. This eliminates the need to design dedicated core hardware and motherboard circuits for dual-socket and dual-node architectures, breaking the hardware design's binding relationship between architecture and dedicated motherboards. Therefore, it effectively solves the technical problems caused by dedicated motherboards for single architectures, such as lengthy R&D cycles, high development and hardware configuration costs, non-universal core hardware, cumbersome supply chain management, and resource waste. It achieves flexible adaptation to dual-socket and dual-node architectures, shortens the R&D cycle, reduces hardware configuration and management costs, and ensures stable operation of server systems under different architectures. Attached Figure Description

[0008] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 A structural block diagram of a server provided in an embodiment of this application; Figure 2 This application provides a schematic diagram of a timing control diagram for a dual-node architecture. Figure 3 A schematic diagram of the master-slave timing and signal interaction of a dual-path architecture provided in this application embodiment; Figure 4 This application provides a schematic diagram of a hardware synchronization link timing triggering method. Figure 5 A power-on timing logic diagram for a dual-path architecture is provided in this application embodiment; Figure 6 For this application Figure 5 A magnified view of a local structure; Figure 7 For this application Figure 5 Another magnified view of the structure; Figure 8 For this application Figure 5 Another magnified view of the structure; Figure 9 A schematic diagram of a level signal and architecture identification logic provided in an embodiment of this application; Figure 10 A schematic diagram of a dual-path clock synchronization and high-speed communication link provided in an embodiment of this application; Figure 11This application provides schematic diagrams of interconnection signals between two motherboard processors of the same type in some embodiments. Figure 12 Node identification circuit diagrams in some embodiments provided for the present application. Detailed Implementation

[0010] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0011] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0012] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0013] In some server designs related to this technology, the dual-socket architecture (where the first and second processors are tightly coupled and collaborate, sharing system resources) and the dual-node architecture (where the first and second processors run independently, each forming an independent computing node) have fundamental differences in hardware interaction logic and resource allocation methods. They require separate design of dedicated motherboards and dedicated control modules, resulting in duplicated R&D investment, complex hardware materials, high inventory management costs, and an inability to quickly switch architecture forms according to market demands, resulting in extremely poor adaptability and flexibility.

[0014] Based on this, this disclosure provides a server.

[0015] To facilitate understanding of this application, the following explains several terms used in this application. "Daughterboard" refers to an independent circuit board assembly that integrates a processor and its associated circuitry (e.g., memory slots, clock circuits, power management circuits, expansion interfaces, etc.), which can be electrically connected and exchange data with other boards (e.g., power distribution boards, management boards) in the server via connectors. "Processor" (e.g., first processor, second processor) refers to the processor chip integrated on the daughterboard.

[0016] In some embodiments, such as Figure 1As shown, the server includes: a first processor, a second processor, a first logic controller, and a second logic controller. The first processor is connected to the first logic controller, the second processor is connected to the second logic controller, and the first logic controller is connected to the second logic controller.

[0017] The first and second logic controllers are configured to: identify the server architecture type based on the received level signal, and coordinately control the operating status of the first and second processors related to the architecture type based on the identification result; the architecture type includes dual-path architecture and dual-node architecture.

[0018] For example, the first processor and the second processor can be the core computing power output components of the server (e.g., the Central Processing Unit, or CPU for short). The first processor and the second processor can be integrated into the server motherboard, using high-performance processors of the same platform and model to ensure collaborative compatibility under the dual-socket architecture and independent operational stability under the dual-node architecture. As the core carrier for realizing server computing power, they provide sufficient computing power support for the operation of different architectures.

[0019] The first and second processors can be high-performance server processors of the same platform but different models, or they can be the same model of processor. The timing parameters and collaborative control logic of the logic controller can be flexibly configured according to the processor model to ensure the hardware platform's compatibility with different processors. In the dual-node architecture, the two processors can run different operating systems and business services to achieve business isolation. In the dual-socket architecture, the two processors run the same operating system and share system memory and I / O resources to improve overall computing power.

[0020] For example, the first and second logic controllers can serve as the core of the server's architecture identification and collaborative control (e.g., a Complex Programmable Logic Device, or CPLD for short). The first and second logic controllers can be integrated into the server motherboard, possessing high reliability, low latency, and strong anti-interference capabilities, used to perform tasks such as receiving level signals, identifying architecture types, controlling processor operating status, and facilitating inter-node status interaction. The first and second logic controllers can be interconnected via a serial communication interface to ensure stable transmission of collaborative control signals.

[0021] For example, both the first and second logic controllers integrate non-volatile memory units to store configuration information such as timing parameters, architecture identification rules, and firmware control logic. They support automatic configuration loading after power-on without relying on upper-layer software, ensuring the independence and reliability of architecture identification and timing control. At the same time, both the first and second logic controllers have fault monitoring functions, which can monitor their own and the corresponding processor's operating status in real time. When faults such as abnormal level signals or timing abnormalities occur, they can send fault alarm signals to the management board to facilitate troubleshooting by maintenance personnel.

[0022] For example, the level signal can be a hardware signal used to identify the server architecture configuration. The level signal can be formed by a combination of high and low levels (e.g., 3.3V for high level and 0V for low level), and is transmitted to the logic controller through a dedicated detection pin on the motherboard. Its signal state is determined by the power connection method during server assembly, and the configuration is completed before power-on, providing a stable and accurate hardware input for architecture identification.

[0023] For example, the level signal sampling pins of the first and second logic controllers both integrate filter circuits to filter out external interference signals and ensure the accuracy of level signal sampling; at the same time, shielded signal lines are used for level signal transmission to reduce electromagnetic interference during signal transmission and avoid architecture identification errors caused by interference.

[0024] For example, dual-socket architecture and dual-node architecture can be two core operating modes of a server. In dual-socket architecture, the first and second processors work together, sharing system resources such as memory and bus, to improve the overall computing power of the server; in dual-node architecture, the first and second processors run independently, each equipped with independent operating resources, to achieve fault isolation. Both architectures are adapted based on the general hardware baseboard of this embodiment, without the need to replace the core hardware.

[0025] For example, in a dual-node architecture, when a single processor or its corresponding logic controller fails, the management board can isolate the faulty node through firmware configuration to ensure that normal nodes are not affected. It also supports hot-swapping of the faulty node without downtime. In a dual-path architecture, when a single processor fails, the management board can control the server to switch to single-processor operation mode to ensure that core services are not interrupted. After the fault is repaired, it can automatically switch back to dual-path operation mode.

[0026] For example, the operating state can be the core working state and behavior mode of the processor during startup and operation. Specifically, it includes the processor power-on sequence, reset signal release timing, clock synchronization status, resource access permissions, and fault response mode. Different architectures correspond to different operating state configurations, which are implemented by the collaborative control of the first logic controller and the second logic controller to ensure that the operating state of the first processor and the second processor is accurately matched with the architecture type.

[0027] This embodiment provides a server that constructs a general-purpose hardware platform, enabling a single hardware set to adapt to different architectures. This embodiment innovatively designs a symmetrical "processor-logic controller" hardware topology, setting up corresponding connections between the first processor and the first logic controller, and between the second processor and the second logic controller. Simultaneously, a communication link is established between the first and second logic controllers, constructing a general-purpose hardware baseboard. This hardware baseboard does not fix the control logic of any single architecture; it only integrates dual computing cores (the first and second processors), dual local control cores (the first and second logic controllers), and a collaborative communication channel. It is compatible with the hardware requirements of different architectures, achieving complete normalization of the core hardware. This simplifies hardware design complexity and provides solid physical support for subsequent dynamic architecture adaptation.

[0028] This embodiment assigns architecture identification functionality to the first and second logic controllers, enabling them to autonomously identify the server architecture type by receiving voltage levels. The identification range covers both dual-path and dual-node architectures. This identification process occurs during the server hardware initialization phase, requiring no intervention from upper-layer software. It is fast, reliable, and the voltage level signal serves as a hardware identifier for the architecture configuration, determined by the connection method during hardware assembly, ensuring the accuracy of the identification results. Through this mechanism, a general-purpose hardware baseboard can autonomously determine the architecture type required for operation, providing a basis for subsequent differentiated control and achieving a technological breakthrough from "hardware-specific" to "dynamically adaptable."

[0029] After architecture identification is completed, the first and second logic controllers communicate with each other to collaboratively control the operating status of the first and second processors, achieving functional adaptation of general-purpose hardware to different architectures. The specific adaptation logic conforms to the relevant limitations of the claims: when adapting to a dual-node architecture, the core of collaborative control is to ensure the independence of the first and second processors, controlling them to operate according to independent logic to achieve fault isolation and independent resource management; when adapting to a dual-path architecture, the core of collaborative control is to achieve tight coupling and collaboration between the first and second processors, ensuring timing synchronization and resource sharing, thereby improving the overall computing power of the system. This differentiated control logic is autonomously triggered by the logic controllers without manual configuration, maximizing the flexibility and convenience of architecture adaptation.

[0030] In some embodiments, such as Figure 2 As shown, the first logic controller is configured to perform timing state identification on the first processor, and the second logic controller is configured to perform timing state identification on the second processor. When the architecture type is identified as a dual-node architecture, the first and second processors are configured to perform power-on and reset according to mutually independent timing sequences.

[0031] The server's timing states include a power-off state and a power-on state. The power-on sequence of the processor from the power-off state to the power-on state includes multiple steps, and the logic control device completes the power-on step by step according to the preset step sequence.

[0032] For example, timing state identification can be a state monitoring operation of the logic controller during the processor's power-on and reset processes. Timing state identification can be achieved by the first and second logic controllers by sampling relevant pin signals of the processor. Its core monitoring signals include, but are not limited to, the voltage regulator power-on signal (VR_PWRGD), the platform controller hub power-on signal (PCH_PWRGD), the processor sleep state signal (CPU_SLP_S5#), and the POWER_OK signals of each power supply. The logic controller uses its internal state machine to accurately determine the current timing stage of the processor based on the signal transition sequence and level.

[0033] For example, mutually independent timing sequences can refer to the independent power-on and reset time sequences of the first and second processors. These mutually independent timing sequences can mean that parameters such as the power-on delay, reset duration, and voltage startup sequence of the first and second processors are pre-stored in their respective logic controllers. The two timing processes are unrelated, do not require mutual waiting or synchronization, and are independently triggered and executed by their respective logic controllers, ensuring timing isolation.

[0034] For example, timing parameter configuration can refer to the dedicated configuration of the logic controller for a dual-node architecture. The timing parameter configuration can be based on the processor model and application scenario, with different timing parameters preset and stored in the configuration storage unit of the logic controller. After the architecture is identified as dual-node, the logic controller automatically calls the corresponding parameters to control the processor to complete power-on and reset according to the preset timing sequence, ensuring the accuracy and adaptability of timing control.

[0035] The core requirement of a dual-node architecture is to achieve completely independent operation of the first and second processors, ensuring that the failure of one node does not affect the normal startup and operation of the other, while guaranteeing the operational stability and timing accuracy of both nodes. This requirement must be maintained throughout the entire process from processor power-on and reset to stable operation. Timing control, as a core aspect of processor initialization, is crucial for achieving node independence—only by ensuring that the power-on and reset timings of the first and second processors are completely independent can mutual interference between nodes be eliminated from the ground up, laying the foundation for subsequent independent booting of the operating system and independent management of resources.

[0036] To achieve the above objectives, this embodiment adopts a timing control strategy of "independent identification and independent control." The first logic controller is only responsible for identifying and monitoring the timing state of the first processor, and the second logic controller is only responsible for identifying and monitoring the timing state of the second processor. The first and second logic controllers do not need to exchange timing-related information. When the architecture is identified as a dual-node architecture, the first and second logic controllers control their respective connected processors, completing power-on and reset according to mutually independent timing sequences. This design achieves complete decoupling of the timing of the first and second processors, breaking the inter-node dependency caused by traditional associated timing, and ensuring that the first and second processors are in a non-interfering working trajectory from the power-on initialization stage, thus guaranteeing the isolation requirements of the dual-node architecture from the bottom layer.

[0037] During server power-up, a single processor may fail to power on or reset due to localized issues such as power module malfunction, capacitor failure, processor microcode errors, or firmware anomalies. If associated timing control is used, the abnormal state of the faulty node may interfere with the startup of normal nodes through synchronization mechanisms (e.g., timeouts, signal conflicts), causing the entire server system to crash. However, the independent timing control in this embodiment strictly limits the fault to a single node: the faulty node remains in its own power-on and reset process, while normal nodes do not need to wait for status feedback from the faulty node and can independently complete power-on, reset, and enter a stable operating state, ensuring uninterrupted core business operations. This is particularly suitable for scenarios where two nodes run different critical services, significantly improving the system's fault tolerance and availability.

[0038] The independent timing control strategy significantly simplifies the control logic complexity of logic controllers and reduces R&D and verification costs. In this embodiment, the first and second logic controllers only need to implement their own single-processor timing state recognition and control logic, eliminating the need to design complex cross-node timing synchronization mechanisms or handle abnormal scenarios such as timing conflicts and timeouts between nodes. This design allows each logic controller to reuse mature timing control algorithms and state machines from single-path servers, without needing to redesign complex collaborative control logic. This reduces the difficulty of firmware development for logic controllers and the workload of hardware verification and firmware testing. The testing process can focus on the timing accuracy and stability of individual nodes, without requiring significant effort to test for timing interaction anomalies between nodes, thus greatly shortening the R&D cycle and reducing R&D and verification costs.

[0039] The independent timing design in this embodiment does not sever the communication link between the first and second logic controllers. Instead, it preserves the hardware platform's scalability and adaptability to diverse application scenarios while ensuring node isolation. In a dual-node architecture, the communication link between the first and second logic controllers can be used to transmit non-critical management information (such as node operating status notifications and fault alarm signals) without affecting the independence of timing control. Simultaneously, this link reserves space for future functional expansion. For example, a "coordinated startup" function can be implemented based on this communication link, allowing the server management system to control the boot order of the two nodes to adapt to specific business needs. It can also enable rapid location of faulty nodes; through status interaction between nodes, normal nodes can feed back fault information to the management system, facilitating rapid troubleshooting and improving maintenance efficiency. This "isolation without severance" design ensures the core requirements of the dual-node architecture while enhancing the scalability and versatility of the hardware platform.

[0040] In some embodiments, such as Figure 3 As shown, when the architecture type is identified as a dual-path architecture, the first logic controller and the second logic controller interact with the timing status information of the first processor and the second processor.

[0041] One of the first processor and the second processor is configured as the master processor, and the other is configured as the slave processor. The slave processor is configured such that the start time of the power-on and reset sequence of the slave processor is delayed by a preset time compared to the completion time of the power-on and reset sequence of the master processor.

[0042] For example, the master processor and slave processor can be functional roles of the first and second processors in a dual-socket architecture. The master and slave processors can be determined by hardware pin configuration or firmware preset. For example, the roles can be determined by the level (pull-up / pull-down) of the PROC_ID pin of the processor socket. The logic controller can determine the master and slave identities by reading this level signal.

[0043] like Figure 4 As shown, the embodiments of this disclosure are described using the first processor as the master processor and the second processor as the slave processor as an example.

[0044] For example, the preset duration can be a preset parameter for the timing delay of the slave processor in a dual-path architecture. The preset duration can be preset based on factors such as the completion time of the main processor's power-on and reset, the processor model, and the performance of the power module, and is stored in the non-volatile memory unit of the logic controller. It can be flexibly adjusted according to the actual application scenario, and its duration should at least cover the time required for the main processor to complete the core hardware initialization, ensuring that the main processor is already in a stable operating state when the slave processor starts up.

[0045] Of course, the preset duration can also be 0. The specific duration can be selected according to actual needs, and this disclosure does not limit it.

[0046] For example, the master and slave processor timing control can be a collaborative control operation between the logic controller and the master / slave roles based on timing status information. The master and slave processor timing control can be achieved by the logic controller autonomously triggering the power-on and reset timing of the master processor based on the interactive timing status information and the master / slave role division. After the master processor timing is completed, the slave processor timing is triggered after a preset delay, ensuring that the entire startup process is orderly and coordinated.

[0047] The core requirement of a dual-processor architecture is to achieve tightly coupled and collaborative operation of the first and second processors, sharing system resources, improving overall computing power, and ensuring the orderly operation of the power-on and reset processes to avoid problems such as power load surges, signal conflicts, and resource contention, thus guaranteeing the stability and reliability of system startup. This requirement necessitates that the timing control of the first and second processors must be coordinated and unified, and the exchange of timing status information is the foundation for achieving this coordination. The division of master and slave roles and timing delays are key to achieving orderly startup.

[0048] The first and second logic controllers each identify the timing status of their respective connected processors and exchange this information. This design allows the first and second logic controllers to monitor the timing progress of the other processor in real time (e.g., power-on state, reset state, power-ready state), breaking down the information silos of individual logic controllers and providing accurate and real-time information support for subsequent master-slave timing coordination, ensuring the targeted and accurate nature of the coordinated control.

[0049] Based on the timing state interaction, the master processor dominates the system startup timing, while the slave processor cooperates with the master processor to complete the collaborative startup. This master-slave role division solves the coordination chaos that easily occurs when the first and second processors start up equally in a dual-path architecture, clarifies the primary and secondary relationship of timing control, makes the startup process of the first and second processors follow a set pattern, simplifies the collaborative control logic, eliminates the need to design complex consensus algorithms or negotiation mechanisms, and reduces the firmware development difficulty of logic control devices.

[0050] The timing delay begins when the processor powers on and resets, but ends when the master processor powers on and resets. This timing delay strategy effectively avoids the power load surge caused by the simultaneous power-on of the first and second processors during the dual-processor boot process, smooths the power system load curve, and prevents power-on failure or processor instability caused by voltage drops. It also ensures that the master processor completes initialization first, configuring shared system resources (such as memory, bus, and clock) in advance, avoiding resource contention and signal conflicts caused by the slave processor starting too early. Furthermore, it ensures that the master processor has completed core hardware initialization by the time the slave processor boots, providing a stable operating environment for the slave processor and improving the reliability and consistency of system startup.

[0051] The combination of timing state interaction and master-slave timing delay ensures the orderly and coordinated startup of processors in the dual-socket architecture, significantly reducing the incidence of power surges, signal conflicts, resource contention, and other problems, and improving the stability of system startup and operation. The master-slave role division simplifies the collaborative control logic, and the timing state interaction mechanism can reuse the logic control device functions of Example 1 without redesigning a dedicated collaborative module, reducing the difficulty of research and development and the workload of testing. The preset duration can be flexibly adjusted according to the processor model and application scenario, improving the hardware platform's adaptability to different processors. The orderly collaborative startup process ensures that the first and second processors can quickly enter the collaborative operation state, giving full play to the computing power advantages of the dual-socket architecture.

[0052] In some embodiments, such as Figure 3 As shown, when the architecture type is identified as a dual-socket architecture, the server also includes: a basic input / output system memory connected to the slave processor; the basic input / output system memory is configured to be disconnected from the slave processor.

[0053] For example, the Basic Input / Output System (BIOS) memory can be a server firmware storage component. The BIOS can be a Serial Peripheral Interface (SPI) Flash chip that stores the UEFI / BIOS firmware image for hardware initialization after the processor powers on, booting the operating system, and connecting to the slave processor via the SPI bus (including SCLK, MOSI, MISO, and CS# pins).

[0054] For example, the disconnection control can be an electronic switch control operation triggered by a logic controller. The disconnection control can be triggered by the logic controller corresponding to the slave processor. When the logic controller recognizes that the architecture type is a dual-path architecture and its corresponding processor is a slave processor, it automatically controls the SPI bus chip select (CS#) pin between the SPI memory and the slave processor to be high (invalid state), so that the SPI memory cannot respond to the slave processor's access request, thus achieving a logical disconnection. Alternatively, other pins of the SPI bus can be placed in a high-impedance state to reduce signal interference.

[0055] For example, the adaptation control of the Basic Input / Output System (PIS) memory can be a dynamic switching operation based on the architecture identification result. The PIS memory adaptation control can involve the logic controller automatically switching the connection state between the PIS memory and the slave processor according to the architecture identification result: when a dual-node architecture is identified, the control connection is maintained to ensure independent processor booting; when a dual-path architecture is identified, the control connection is disconnected to avoid redundancy conflicts, thus achieving dynamic adaptation of the same PIS memory under different architectures.

[0056] Based on the general hardware platform design described in the preceding embodiments, each processor's corresponding motherboard is equipped with an independent Basic Input / Output System (BIOS) memory to meet the requirement of independent operating system booting for processors in a dual-node architecture. However, in a dual-socket architecture, the BIOS firmware of a dual-socket system is a single instance, loaded and executed by the master processor, responsible for initializing the hardware resources of the entire system (including the slave processor). The slave processor does not need to independently load its own BIOS firmware. At this time, the BIOS memory connected to the slave processor becomes redundant hardware. If not controlled, it may cause the slave processor to attempt to access its local BIOS memory, resulting in bus conflicts or address conflicts with the master processor's access to the master BIOS memory, or causing the system to recognize multiple BIOS devices and experience boot anomalies. This problem is a key pain point that must be addressed in the process of generalizing dual-socket architecture hardware.

[0057] To address the aforementioned issues, this embodiment employs a Basic Input / Output System (BIOS) memory disconnection control strategy: when the architecture is identified as a dual-processor architecture, the BIOS connected to the slave processor is disconnected. This design achieves "dynamic adaptation" of the BIOS through logic control. In a dual-node architecture, the BIOS on the same motherboard remains connected, ensuring independent processor booting; in a dual-processor architecture (acting as the slave processor motherboard), the connection is disconnected to avoid redundancy and conflicts, perfectly aligning with the "one board, multiple uses" design philosophy of general-purpose hardware platforms.

[0058] Disconnecting the processor's BIOS memory eliminates redundancy and conflict issues in dual-socket architectures at their source. After disconnection, the slave processor cannot access its local BIOS memory, preventing bus and address conflicts with the master processor's BIOS and avoiding system boot anomalies caused by recognizing multiple BIOS devices. Simultaneously, the master processor's BIOS firmware can focus on system hardware initialization without dealing with interference from the slave processor's local BIOS, ensuring a smooth initialization process and significantly improving the stability and reliability of dual-socket system startup.

[0059] There is no need to design a slave processor motherboard without basic input / output system memory specifically for dual-socket architectures. A general-purpose motherboard for dual-node architectures can be reused, reducing R&D investment in dedicated motherboards and shortening the R&D cycle. All motherboards are completely universal, eliminating the need to distinguish between master processor motherboards and slave processor motherboards without BIOS. This simplifies the production process and inventory management, avoids the risk of material stagnation or shortages associated with dedicated motherboards, and reduces production and inventory costs. The universalization of motherboards reduces the types of spare parts required for maintenance, and maintenance personnel do not need to distinguish between different types of motherboards, thus reducing maintenance complexity.

[0060] In some embodiments, the first logic controller and the second logic controller are connected via a serial universal input / output interface (SATA), which is configured to exchange timing status information between the two logic controllers. The timing status information includes power-ready signals and enable signals for the first and second processors.

[0061] For example, the Serial Universal Input / Output (SGPIO) interface can be a bidirectional communication interface between the first and second logic controllers, supporting bidirectional serial data transmission. The transmission rate can be flexibly configured according to timing control requirements, and it features fewer pins, strong anti-interference capabilities, and stable transmission. The Serial Universal Input / Output interface may include, for example, a clock pin SCLK, a data input pin SI, a data output pin SO, and a chip select pin CS.

[0062] For example, the power-ready signal can be a hardware signal reflecting the processor's power supply status. The power-ready signal can be output by the processor's voltage regulator (VR), such as the VR_PWRGD signal. When the processor's core voltage and auxiliary voltage reach stable values, this signal goes high, indicating that the processor is power-ready and can enter the next timing stage. After sampling this signal, the logic controller transmits it to another logic controller through the SGPIO interface.

[0063] For example, the enable signal can be a hardware signal that controls the timing triggering of the processor. The enable signal can be a signal output from a logic controller to the processor to trigger the processor's power-on or reset timing. When the enable signal is valid (e.g., high level), the processor begins to execute the corresponding timing operation. The logic controller transmits this signal to another logic controller through the SGPIO interface for synchronizing the timing triggering state.

[0064] For example, the timing status information interaction process can be a standardized serial transmission process. The timing status information interaction process can be as follows: the logic controller samplees the power-ready signal and enable signal of the processor it is connected to, encodes them into serial data, and sends them through the SI pin of the SGPIO interface; another logic controller receives the data through the SO pin, decodes it, obtains the timing status information of the other processor, and completes one interaction. The interaction frequency can be flexibly adjusted according to the timing progress to ensure the real-time nature of the information.

[0065] The exchange of timing status information is fundamental to the collaborative control of dual-path architectures and the status monitoring of dual-node architectures (non-timing collaboration). Its core requirements are ensuring stable signals, low transmission latency, and simple interface design, while simultaneously ensuring that the exchanged information accurately reflects the core timing status of the processor, providing effective support for subsequent timing control. This requirement necessitates selecting appropriate connection interfaces and clearly defining the core interaction signal types to avoid problems such as increased hardware design difficulty and unstable signal transmission caused by complex interfaces.

[0066] To meet the above requirements, this embodiment selects the Serial General Purpose Input / Output (SGPIO) interface as the connection interface between the first and second logic controllers. Compared to other interfaces (such as parallel interfaces and PCIe interfaces), the SGPIO interface has fewer pins, simpler hardware connections, reduces motherboard wiring complexity, and lowers hardware design and manufacturing difficulty; furthermore, it offers high transmission stability and strong anti-interference capabilities, effectively avoiding signal distortion during timing status information transmission and ensuring the accuracy of information transmission; thirdly, it supports bidirectional serial transmission, enabling bidirectional timing status interaction between the first and second logic controllers, adapting to the collaborative requirements of a dual-path architecture.

[0067] The power-ready and enable signals of the first and second processors are crucial for reflecting the processor's timing status. The power-ready signal (e.g., VR_PWRGD) indicates whether the processor's power supply is stable, a core basis for determining whether the processor can enter the next timing stage. The enable signal indicates whether the processor's power-on and reset timings have been triggered, crucial for monitoring timing progress. Choosing these two core signals for interaction avoids redundant information transmission, reduces interface transmission pressure, and ensures that the interacted information accurately supports subsequent timing control (e.g., master-slave timing delay in dual-path architectures, fault monitoring in dual-node architectures), improving the targeting and effectiveness of timing status interaction.

[0068] Combined with the above design, the stable transmission of the SGPIO interface and the precise interaction of core signals ensure that the first and second logic controllers can accurately grasp the timing status of each other's processors in real time, providing reliable support for subsequent collaborative control and significantly improving the reliability and accuracy of timing control. The simple interface design and clear signal types reduce the difficulty of motherboard wiring and logic controller firmware development, and reduce the workload of R&D and testing. The high degree of interface standardization makes it easy for maintenance personnel to troubleshoot timing information interaction-related faults, reducing maintenance complexity. The reduction of interface pin occupancy optimizes motherboard space utilization.

[0069] In some embodiments, such as Figure 4 As shown, the server also includes a hardware synchronization link, connecting the first processor and the second processor; When the architecture type is identified as a dual-path architecture, the hardware synchronization link is configured to transmit the power-ready signal and reset signal of the main processor to the slave processor after the power-on and reset sequence of the main processor is completed, so as to trigger the start of the power-on and reset sequence of the slave processor.

[0070] For example, the hardware synchronization link can be a dedicated signal transmission link connecting the first and second processors. The hardware synchronization link can consist of dedicated signal lines (such as LVDS signal lines and GPIO signal lines) connected between the timing control pins of the first and second processors, and is specifically used to transmit the power-ready signal and reset signal of the main processor. It features low transmission delay, strong anti-interference capability, and high signal stability.

[0071] For example, enabling and disabling the hardware synchronization link can be a control operation of the logic controller based on the architecture identification result. The enabling and disabling of the hardware synchronization link can be controlled collaboratively by the first and second logic controllers. When the architecture type is identified as a dual-path architecture, the hardware synchronization link is enabled to allow the timing signal transmission of the master processor; when the architecture type is identified as a dual-node architecture, the hardware synchronization link is disabled to avoid mutual interference between the timing signals of the master and slave processors and ensure the timing independence of the dual-node architecture.

[0072] For example, the power-ready signal and reset signal of the main processor can be core trigger signals for timing synchronization. The power-ready signal of the main processor (e.g., VR_PWRGD) is used to indicate that the power-on sequence of the main processor is complete and the power supply is stable; the reset signal is used to indicate that the reset sequence of the main processor is complete and it can operate normally; after these two signals are transmitted to the slave processor through the hardware synchronization link, the logic controller device corresponding to the slave processor triggers the power-on and reset sequence of the slave processor to achieve strict timing coordination.

[0073] A hardware synchronization link connects the first and second processors and is used for timing synchronization between the master and slave processors in a dual-processor architecture. The master processor's power-ready and reset signals are directly transmitted via the hardware link to trigger timing events in the slave processor. This hardware-level synchronization mechanism minimizes transmission latency and interference, ensuring that the slave processor's timing startup strictly corresponds to the master processor's timing completion state.

[0074] The hardware synchronization link design significantly improves timing coordination accuracy. The power-ready signal and reset signal of the master processor are directly transmitted to the slave processor through the hardware link, with negligible transmission delay, avoiding delay deviations caused by information interaction of logic controllers. The hardware link has strong anti-interference capabilities, effectively preventing signal distortion or loss, ensuring that the slave processor can accurately receive the timing completion signal of the master processor, and preventing premature or late startup. It simplifies the firmware logic of the logic controllers, eliminating the need to design complex preset duration calculation and calibration algorithms, and only requiring control of the enabling and disabling of the hardware synchronization link, reducing the difficulty of firmware development.

[0075] This embodiment further enhances the operational stability of the dual-socket architecture while improving the adaptability and flexibility of the hardware platform. Precise timing coordination avoids issues such as power load surges and signal conflicts, ensuring the stability of the dual-socket system's startup and operation, and improving the commercial reliability of the server. The hardware synchronization link is only enabled in the dual-socket architecture and can be disabled in the dual-node architecture without affecting the timing independence of the dual-node architecture, perfectly adapting to the "one board, multiple uses" design concept of general-purpose hardware platforms. Simplified firmware logic and hardware-level synchronization mechanisms reduce the workload of R&D and testing, while facilitating maintenance personnel to troubleshoot timing-related faults and improving maintenance efficiency.

[0076] In some embodiments, the server exists in a shutdown state (S5) and a power-on state (S0). The complete power-on sequence from the S5 shutdown state to the S0 power-on state is as follows: Figures 5 to 8 As shown, the first and second logic controllers exchange the power-ready signal PG and enable signal EN of the voltage regulator via the SGPIO interface to complete cross-board timing status identification. At the end of the timing sequence, the processor power-ready signal PWRGD_OUT, power-confirmation signal PWR_OK, and reset signal RESET_L are directly transmitted through physical hardware pins to ensure the accuracy of the master and slave processor power-on timing in the dual-path architecture. After the master processor completes all power-on timing, it outputs the corresponding status signal to notify the slave processor, and then completes the slave processor's power-on reset, achieving orderly power-on of the processors on both daughterboards.

[0077] In some embodiments, such as Figure 9 As shown, the level signal includes a first level and a second level. When both the level signal received by the first logic controller and the level signal received by the second logic controller are at the first level or both are at the second level, the server architecture type is identified as a two-node architecture.

[0078] When one of the level signals received by the first logic controller and the level signal received by the second logic controller is at the first level and the other is at the second level, the server architecture type is identified as a dual-path architecture.

[0079] For example, the first level and the second level can be two different hardware level signals. The first level and the second level can be output by the power supply module or power distribution board and transmitted to the logic controller through a dedicated detection pin on the motherboard. The state of the level signal is determined by the hardware connection method during server assembly.

[0080] For example, the architecture identification logic can be hardware-level judgment logic within the logic controller. The architecture identification logic can be implemented by combinational logic circuits within the logic controller, requiring no complex firmware algorithms; it only needs to compare the level signals sampled by the first and second logic controllers. When both are consistent (both are at the first level or both are at the second level), a dual-node architecture identification signal is output; when they are inconsistent, a dual-path architecture identification signal is output.

[0081] For example, level signal sampling can be a basic hardware operation of logic controllers. Level signal sampling can be performed by the first and second logic controllers (CPLDs) through their own general purpose input / output (GPIO) pins. The sampling frequency can be set to a fixed value to adapt to the stability of the level signal. The sampling process occurs in the earliest stage of server power-on initialization, and the level signal acquisition and architecture identification are completed before the processor is powered on, ensuring that subsequent timing control and function adaptation can be triggered in a timely manner.

[0082] The core requirement of architecture identification is to achieve accurate, fast, and reliable architecture type determination, providing a basis for subsequent timing control and functional adaptation. Simultaneously, it requires simple identification logic to facilitate hardware design and firmware development, avoiding problems such as increased R&D difficulty and excessive identification latency caused by complex identification algorithms. This requirement necessitates clearly defining the specific types of level signals and identification rules to ensure clear and highly operable identification logic.

[0083] To achieve the above requirements, this embodiment defines the level signal as two types: a first level and a second level (for example, the first level is a 3.3V high level, and the second level is a 0V low level). Compared with multi-level signal design, dual-level signal hardware design is simpler. It does not require designing complex multi-level sampling circuits; level signal sampling can be completed simply through ordinary GPIO pins, reducing the difficulty of motherboard hardware design. Firmware development is simple; the logic controller only needs to determine whether the sampled level is high or low, without performing complex level range judgments, simplifying firmware identification logic. It has strong anti-interference capability; the level difference of dual-level signals is large, making it less susceptible to signal distortion caused by external interference, ensuring sampling accuracy.

[0084] When the level signals sampled by the first and second logic controllers are both at the first level or both at the second level, it is identified as a dual-node architecture; when one is at the first level and the other at the second level, it is identified as a dual-path architecture. This identification rule is simple, easy to understand, and highly operable. The logic controller only needs to compare the consistency of the two level signals to quickly determine the architecture type. The identification delay is short (it can be completed instantly during the hardware initialization phase), and the identification logic is not prone to errors, ensuring the speed and accuracy of architecture identification.

[0085] The high anti-interference capability and simple recognition rules of dual-level signals ensure the accuracy and reliability of architecture recognition, avoiding architecture adaptation anomalies caused by recognition errors; the simplified hardware sampling circuit and firmware recognition logic reduce the difficulty of hardware design and firmware development, reduce R&D and testing workload, and shorten the R&D cycle; the standardized recognition rules facilitate architecture configuration and testing in the production process, improving production efficiency; the simple recognition logic makes it easy for maintenance personnel to troubleshoot architecture recognition-related faults (such as abnormal level signals), reducing maintenance complexity.

[0086] In some embodiments, such as Figure 9 As shown, the server also includes: a power distribution board, a first reference power supply terminal, and a second reference power supply terminal. The power distribution board includes a ground terminal. The first reference power supply terminal is connected to a first logic controller, and the common terminal of the first reference power supply terminal and the first logic controller forms a first node. The second reference power supply terminal is connected to a second logic controller, and the common terminal of the second reference power supply terminal and the second logic controller forms a second node. The level signals include: a ground signal from the ground terminal, a first reference electrical signal from the first reference power supply, and a second reference electrical signal from the second reference power supply terminal.

[0087] When the power distribution board is connected to the first logic controller, the first node is connected to the ground terminal; when the power distribution board is connected to the second logic controller, the second node is connected to the ground terminal.

[0088] When both the first and second nodes are connected to the ground terminal, the architecture type is identified as a two-node architecture.

[0089] If one of the first and second nodes is connected to the ground terminal while the other is disconnected from the ground terminal, the architecture type is identified as a dual-path architecture.

[0090] For example, the power distribution board can be a power distribution and grounding control component of a server. The power distribution board can be a standardized module integrated into the server motherboard, with a core including a ground terminal (GND) and interfaces for connection to the first and second logic controllers. Connection / disconnection control with the logic controllers is achieved through pins or jumpers. Its main function is to provide a stable ground signal for generating level signals and to implement hardware-based operation of the architecture configuration.

[0091] For example, the first reference power supply terminal and the second reference power supply terminal can be standardized power supply components for level signals. The first reference power supply terminal and the second reference power supply terminal can be standardized power modules on a server motherboard, which output reference electrical signals of fixed amplitude (e.g., 3.3V, i.e., the first level in embodiment 7), and are respectively connected to the sampling pins of the first and second logic control devices to provide a stable reference for level signal sampling and ensure the accuracy of level signal sampling.

[0092] For example, the first node and the second node can be sampling nodes for the level signal. The first node is a common pin of the first reference power supply and the first logic controller, and the second node is a common pin of the second reference power supply and the second logic controller. The level states of the two nodes are the level signals sampled by the logic controller: when the node is grounded, the level signal is a ground signal (e.g., 0V, which is the second level mentioned above); when the node is not grounded, the level signal is a reference electrical signal (e.g., 3.3V, which is the first level mentioned above).

[0093] For example, node grounding control can be a hardware operation method configured in the architecture. Node grounding control can be implemented through the connection status between the power distribution board and the logic controller: when the power distribution board and the logic controller are connected via pins, the corresponding node is connected to the ground terminal and outputs a grounding signal; when the two are disconnected, the corresponding node is disconnected from the ground terminal and outputs a reference electrical signal. This operation method is simple and reliable, and can be completed through pin insertion / removal or jumper settings during the production process.

[0094] This embodiment designs a complete hardware supply system for level signals, setting up a power distribution board, a first reference power supply terminal, and a second reference power supply terminal. The level signals are clearly defined as including a ground signal, a first reference electrical signal, and a second reference electrical signal. Differential level signal combinations are generated by controlling whether the first and second nodes are grounded. This design directly binds level signal generation to hardware connections, ensuring a stable signal source. The reference power supply terminal provides a standardized reference electrical signal, and the power distribution board's grounding terminal provides a stable ground signal, avoiding level signal distortion caused by external interference or power fluctuations. The signal generation logic is simple; the node grounding state can be controlled solely by the connection between the power distribution board and the logic control device, thereby generating the corresponding level signal for the architecture. Complex signal conditioning circuits are unnecessary, reducing the difficulty of hardware design.

[0095] This embodiment establishes clear hardware architecture identification rules based on node grounding status. When both the first and second nodes are grounded, it is identified as a dual-node architecture; when one is grounded and the other is disconnected, it is identified as a dual-path architecture. This rule transforms architecture configuration into a simple hardware connection operation. During server production or assembly, architecture configuration can be completed simply by controlling the connection status between the power distribution board and the first and second logic controllers, without the need for software parameter settings or firmware flashing. This significantly simplifies the architecture configuration process, reduces the risk of misconfiguration during production, and ensures the consistency of level signals under the same architecture configuration, thereby improving the accuracy of architecture identification.

[0096] By combining hardware-based level signal sources with recognition rules, the reliability of architecture recognition is significantly improved. A stable level signal source avoids recognition errors caused by signal distortion, and the hardware-based recognition rules require no software intervention, reducing the impact of software anomalies on the recognition results and ensuring accurate identification of the architecture type after the server is powered on. The difficulty of architecture configuration is significantly reduced; production personnel only need to complete simple hardware connection operations to achieve architecture configuration, without the need for professional software operation capabilities, thus improving production efficiency. The recognition results are traceable, with the architecture configuration directly corresponding to the hardware connection status. Maintenance personnel can quickly determine whether the architecture configuration is correct by checking the node grounding status, facilitating troubleshooting.

[0097] This embodiment further promotes the standardization and universalization of server hardware. The standardized hardware architecture configuration process enables unified configuration for different production lines and operators, ensuring product consistency. It also simplifies the production testing process and reduces production costs. The design of the power distribution board and reference power supply conforms to the standardized specifications of server hardware, allowing the reuse of existing mature hardware modules without the need to redesign dedicated signal generation modules, thus reducing R&D investment. The hardware-based configuration and identification logic facilitates maintenance personnel to quickly troubleshoot architecture-related faults, reducing maintenance time and costs.

[0098] In some embodiments, such as Figure 10 As shown, the server also includes: a clock synchronization link and a high-speed interconnect cable; the clock synchronization link connects the first processor and the second processor. The high-speed interconnect cable connects the high-speed bus ports of the first processor and the second processor.

[0099] The clock synchronization link is configured to transmit the reference clock signal output by the first processor to the second processor when the architecture type is identified as a dual-path architecture, so as to synchronize the clocks of the two processors.

[0100] High-speed interconnect cables are configured to enable high-speed data communication between the first and second processors when the architecture type is identified as a dual-path architecture.

[0101] For example, the clock synchronization link can be a dedicated transmission link for processor clock synchronization in a dual-path architecture. The clock synchronization link can consist of dedicated clock signal lines (such as LVDS clock lines) connected between the clock output pin of the first processor and the clock input pin of the second processor. It is specifically used to transmit the reference clock signal output by the first processor (such as a 100MHz reference clock), and features low transmission delay, strong anti-interference capability, and low clock jitter, ensuring the clock synchronization accuracy of the first and second processors.

[0102] For example, the high-speed interconnect cable can be a dedicated cable for high-speed data communication between processors in a dual-path architecture. The high-speed interconnect cable can be a high-speed differential cable conforming to the PCIe 4.0 / 5.0 standard, connected between the PCIe high-speed bus ports of the first and second processors, supporting high-bandwidth, low-latency data transmission (bandwidth can reach tens of GB / s), mainly used to realize high-speed data communication needs such as cache coherency interaction, shared memory access, and I / O resource sharing between the first and second processors.

[0103] For example, link enabling and disabling can be control operations of logic controllers based on architecture identification results. Link enabling and disabling can be jointly controlled by the first and second logic controllers. When the architecture type is identified as a dual-path architecture, the clock synchronization link is turned on and the high-speed interconnect cable is enabled, allowing clock signal transmission and high-speed data communication. When the architecture type is identified as a dual-node architecture, the clock synchronization link is turned off and the high-speed interconnect cable is disabled (placed in a high-impedance state) to avoid interfering with the independence of the dual-node architecture.

[0104] For example, the reference clock signal can be a reference signal for clock synchronization in a dual-path architecture. The reference clock signal can be generated by a clock generator inside the first processor, outputting a reference clock with a fixed frequency and stable phase. After being transmitted to the second processor via a clock synchronization link, the second processor uses this reference clock as a reference to calibrate its own clock signal, achieving clock synchronization with the first processor and ensuring consistent instruction execution and data transmission rhythms between the first and second processors. In a dual-path architecture, the slave processor's RTC (Real-Time Clock) is not operational. After the firmware identifies the master-slave relationship, it controls the slave processor not to read its subordinate RTC to avoid clock source conflicts with the master processor.

[0105] A clock synchronization link connects the first and second processors to transmit a reference clock signal, ensuring clock synchronization between the two processors in a dual-processor architecture. High-speed interconnect cables connect the high-speed bus ports of the first and second processors to enable high-speed data communication between them. This dedicated link design offers significant advantages over a shared link: the clock synchronization link guarantees the stability of the clock signal transmission, avoiding clock deviations caused by interference; and the high-speed interconnect cables provide a high-bandwidth, low-latency data transmission channel, meeting the high-speed requirements of resource sharing and data interaction in a dual-processor architecture.

[0106] Both the clock synchronization link and the high-speed interconnect cable are only enabled in the dual-path architecture and disabled in the dual-node architecture. This enables dynamic adaptation of the hardware link and solves the compatibility problem between the dedicated collaborative link and the independence of the dual nodes. In the dual-path architecture, the link is enabled to ensure efficient processor collaboration; in the dual-node architecture, the link is disabled, and the first and second processors can run completely independently without interference in clock and data transmission. This ensures the isolation requirements of the dual-node architecture and eliminates the need to design different hardware links for the two architectures, thus reusing a general-purpose hardware platform.

[0107] The combination of dedicated hardware links and dynamic adaptation design significantly improves clock synchronization accuracy. The clock synchronization link transmits the reference clock signal output by the first processor, ensuring that the clock frequency and phase of the first and second processors are completely consistent, avoiding coordination anomalies caused by clock deviations and improving the operational stability of the dual-socket architecture. Data transmission efficiency is significantly improved. With the high-speed interconnect cable enabled, high-bandwidth, low-latency data interaction between the first and second processors can be achieved, ensuring efficient access to shared resources (such as memory and cache), fully leveraging the computing power advantages of the dual-socket architecture, and improving the overall performance of the server. Hardware compatibility is strong. Dynamic link adaptation ensures that the same hardware platform can adapt to two architectures without replacing the core hardware.

[0108] The combination of clock synchronization and high-speed data communication enables the dual-path architecture to operate stably and efficiently, making it suitable for high-performance computing, big data processing, and other scenarios with high requirements for computing power and data transmission efficiency. Dynamic link adaptation achieves perfect compatibility with the dual-node architecture, strengthens the advantages of the general-purpose hardware platform, and reduces R&D, production, and inventory costs. The combination of high performance and high versatility enables the server to adapt to more diverse market demands and enhances product competitiveness.

[0109] In some embodiments, the server further includes a processor system. The processor system includes a first daughterboard and / or a second daughterboard, the first daughterboard integrating a first processor and the second daughterboard integrating a second processor. The first and second daughterboards have the same hardware design. In a single-socket architecture, the processor system includes only the first or second daughterboard; in a dual-socket or dual-node architecture, the processor system includes both the first and second daughterboards.

[0110] The processor system provided in this embodiment integrates the processor and its supporting circuits onto an independent daughterboard, and achieves hardware normalization at the processor system level for single-socket, dual-socket, and dual-node server architectures by having the same hardware design on the first and second daughterboards. This achieves the technical effect of one daughterboard adapting to multiple architectures.

[0111] On the one hand, during the R&D phase, only one daughterboard needs to be developed to cover three server product lines, eliminating the need to develop different motherboards for single-socket, dual-socket, and dual-node systems. This significantly shortens the R&D cycle and reduces R&D costs and design complexity. Developers only need to complete the hardware design, debugging, and verification of a single daughterboard, and can then combine different daughterboards to form server systems with different architectures.

[0112] On the other hand, during the production and supply chain management phases, since the first and second sub-boards are identical, production, material preparation, and inventory management only need to be performed on sub-boards with a single part number, effectively simplifying the complexity of supply chain management and reducing material management costs. Simultaneously, when facing market demand fluctuations for servers with different architectures, the same batch of sub-boards can be flexibly allocated for the production of single-socket, dual-socket, or dual-node servers based on actual order requirements, avoiding material stagnation and inventory backlog caused by forecasting errors, thus improving inventory turnover efficiency and supply chain responsiveness.

[0113] Furthermore, the processor system provided in this embodiment does not depend on a specific processor platform, and its design concept can be applied to various server products, exhibiting good scalability and adaptability.

[0114] In some embodiments, the server further includes a management system, which includes a management board. The management board is connected to a first logic controller and a second logic controller, and is configured to load the corresponding firmware configuration based on the architecture type identification results of the first logic controller and the second logic controller, so as to adapt to the operation of a single-socket architecture, a dual-socket architecture, or a dual-node architecture.

[0115] For example, the management system can be the intelligent management core of the server, including a management board and supporting firmware. The management board can be a standardized module integrating a BMC (Baseboard Management Controller), which is connected to the first and second logic controllers via I2C or UART interfaces to receive architecture identification results, load corresponding firmware configurations, and realize remote management functions of the server (such as remote power-on, power-off, fault monitoring, and log query).

[0116] For example, the management board supports remote firmware upgrade functionality. It can receive upgrade packages via a network interface and simultaneously link two logic controllers to achieve synchronous upgrades of the management firmware and the logic controller firmware. During the upgrade process, the original configuration can be retained to avoid architectural incompatibility issues after the upgrade. If the upgrade fails, it supports rolling back to the original firmware version to ensure the stability of server operation.

[0117] For example, firmware configuration can be dedicated configuration parameters and logic for managing different architectures. Firmware configuration can be two sets of configuration files stored in the non-volatile storage unit of the management board, corresponding to dual-socket architecture and dual-node architecture respectively: the firmware configuration for dual-socket architecture includes resource sharing strategy, dual-processor collaborative management logic, cache consistency monitoring parameters, etc.; the firmware configuration for dual-node architecture includes node independent management logic, fault isolation strategy, node status monitoring parameters, etc. The management board can automatically load the corresponding configuration based on the architecture identification result.

[0118] In some embodiments, the server further includes a cooling system comprising a fan plate. The fan plate is connected to a management board and configured to provide cooling for the first processor and the second processor according to instructions from the management board.

[0119] For example, the cooling system can be the temperature control core of the server, including a fan board and supporting heat dissipation devices. The fan board can be a standardized module integrating multiple PWM fans, connected to the management board via a PWM interface, receiving speed commands sent by the management board, and controlling the airflow inside the server by adjusting the fan speed to provide precise heat dissipation for the first and second processors and peripheral devices.

[0120] For example, the heat dissipation command generation can be the intelligent control logic of the management board. The heat dissipation command generation can be achieved by the management board combining the architecture identification results with processor temperature monitoring data to generate corresponding fan speed commands. In a dual-socket architecture, a higher base speed is used by default, while dynamically adjusting according to the processor's real-time temperature; in a dual-node architecture, a lower base speed is used by default, balancing heat dissipation and energy consumption to ensure that the processor temperature is controlled within a preset threshold (e.g., 95°C).

[0121] Under different architectures, the server's operating mode, resource allocation, and power consumption performance vary significantly. If the management system loads a fixed firmware configuration, it will lead to incomplete architecture adaptation and abnormal management functions. If the heat dissipation system adopts a fixed heat dissipation strategy, problems such as insufficient heat dissipation (high power consumption in dual-path architecture) or redundant heat dissipation (low power consumption in dual-node architecture) will occur.

[0122] To achieve multi-architecture adaptation of the management system, this embodiment designs an intelligent management system including a management board. The management board is connected to the first and second logic controllers. Its core function is to dynamically load the corresponding firmware configuration based on the architecture identification result. This design enables architecture self-adaptation of the management firmware. The management board internally stores two sets of firmware configurations (such as resource allocation strategies, fault monitoring logic, and remote management parameters) corresponding to dual-path and dual-node architectures. After the logic controller completes architecture identification, it transmits the identification result to the management board, which automatically loads the corresponding architecture firmware configuration without manual intervention. Compared to fixed firmware configurations, this design ensures that the functions of the management system are fully matched with the current architecture, avoids management function anomalies, and simplifies the maintenance cost of the management firmware.

[0123] To achieve multi-architecture adaptation of the cooling system, this embodiment designs a linked cooling system including a fan board. The fan board is connected to the management board, and its core function is to dynamically adjust the cooling strategy according to the instructions of the management board. This design realizes intelligent linkage of cooling. In a dual-socket architecture, the first and second processors operate collaboratively, resulting in higher power consumption. Based on the architecture identification results, the management board sends high-speed commands to the fan board to improve cooling efficiency and ensure that the processor temperature is controlled within a reasonable range. In a dual-node architecture, the first and second processors operate independently, resulting in lower power consumption. The management board sends low-speed commands to reduce the fan speed, reducing energy consumption and noise. This dynamic cooling strategy avoids processor throttling and failures caused by insufficient cooling in a dual-socket architecture, and also avoids energy waste caused by heat dissipation redundancy in a dual-node architecture, achieving a balance between cooling efficiency and energy consumption.

[0124] The management system's adaptability has been significantly improved. Dynamically loaded firmware configurations ensure the integrity and accuracy of management functions under different architectures, facilitating remote server management, fault monitoring, parameter configuration, and other operations for maintenance personnel, thereby improving management efficiency. The cooling system's efficiency has been significantly optimized. Dynamic cooling strategies achieve precise matching between heat dissipation and power consumption, ensuring stable processor operation while reducing server energy consumption and operating noise. System reliability has been improved. The linkage between the management system and logic control devices allows for real-time monitoring of the architecture's operating status, timely detection and reporting of anomalies, and precise control of the cooling system can prevent processor failures caused by overheating.

[0125] This embodiment further simplifies server operation and maintenance, and improves user experience. The intelligent management system's dynamic adaptation eliminates the need for manual firmware switching, and the linked cooling system eliminates the need for manual fan speed adjustments, significantly reducing the workload of maintenance personnel. The dynamic cooling strategy reduces unnecessary energy waste, meeting the commercial requirements for green energy conservation. The server operates stably, with low noise and convenient management, and can adapt to diverse operation and maintenance scenarios for enterprise-level servers, enhancing the product's commercial competitiveness. At the same time, the management board and fan board both use standardized modules, allowing for the reuse of existing mature hardware and reducing R&D and production costs.

[0126] In some embodiments, such as Figure 11 As shown, when the first and second daughter boards form a dual-socket architecture system, the high-speed bus ports of the processors on the two daughter boards are interconnected via an external high-speed cable. The high-speed interconnect signals of the processors include multiple sets of high-speed differential signals, which are connected across boards via cables to achieve high-speed signal exchange between processors in a dual-socket architecture. In the dual-node architecture mode, this high-speed interconnect cable is not enabled, and the high-speed ports between processors are isolated from each other, ensuring that the two computing nodes operate completely independently.

[0127] In some embodiments, a communication line is further provided between the first logic controller and the second logic controller. This communication line is configured to transmit timing synchronization signals between the first and second logic controllers when the architecture type is identified as a dual-path architecture. The communication line is also configured to trigger the basic input / output system memory connected to the second processor to disconnect from the second processor when the architecture type is identified as a dual-path architecture and the second processor corresponding to the second logic controller is a slave processor.

[0128] Based on the above design, the server provided in this embodiment eliminates the need for repeated hardware design, debugging, and verification of different architectures. A single development effort covers multiple product lines, significantly shortening the development cycle and reducing costs. Core hardware (such as motherboards, fan boards, and management boards) is shared, requiring only differentiation of standardized power boards, achieving economies of scale in procurement, simplifying inventory management, and preventing material stagnation. A unified hardware platform allows for centralized optimization of firmware and drivers, reducing the types of spare parts needed for maintenance and lowering operational complexity. The server can quickly switch between architectures to adapt to different market demands, improving market responsiveness. Universally validated hardware and coordinated control of logic controllers prevent hardware conflicts, enhancing long-term server stability.

[0129] In some embodiments, the server further includes a power supply system, which includes a first power supply board or a second power supply board. The first power supply board (e.g., a single-socket / dual-node power supply board) is suitable for both single-socket and dual-node servers, while the second power supply board (e.g., a dual-socket power supply board) is suitable for dual-socket servers.

[0130] In the case where the power supply system includes a first power board, the level signals received by the first logic controller and the second logic controller are configured to identify the server architecture type as a two-node architecture.

[0131] In the case where the power supply system includes a second power board, the level signals received by the first logic controller and the second logic controller are configured to cause the server architecture type to be identified as a dual-path architecture.

[0132] For example, the power supply system can be the core of the server's power supply, including a standardized power board and supporting power supply circuits. The core component of the power supply system is either a first power board or a second power board, both of which adopt a standardized design and can be directly replaced. They output DC voltages (e.g., 12V, 5V, 3.3V) that meet the server's hardware requirements, while also providing level signals to the logic control devices.

[0133] For example, the first power board integrates two independent power supply circuits to provide independent power to the first processor and the first logic controller, the second processor and the second logic controller, respectively. The two power supply circuits are isolated from each other to ensure that a failure in one circuit does not affect the normal power supply of the other circuit. At the same time, the output level signal makes the level sampled by the first logic controller and the second logic controller consistent, triggering the dual-node architecture recognition.

[0134] The first power board can be a dedicated power supply board adapted to a dual-node architecture. The first power board can integrate two independent AC-DC conversion modules and power supply circuits, providing independent power to the first processor, the first logic controller, and the second processor and the second logic controller, respectively. The two power supply circuits are isolated from each other, ensuring that a failure in one circuit does not affect the normal power supply of the other circuit. At the same time, the output level signal can make the level sampled by the first and second logic controllers consistent, triggering dual-node architecture recognition.

[0135] For example, the second power board integrates a unified power supply circuit to provide unified power supply to the first processor, the second processor, the first logic controller, and the second logic controller, ensuring the consistency of power supply voltage, ripple, and timing under the dual-path architecture. At the same time, the output level signal causes the level sampled by the first logic controller and the second logic controller to be inconsistent, triggering the dual-path architecture recognition.

[0136] The second power board can be a dedicated power supply board adapted to the dual-path architecture. The second power board can integrate a unified AC-DC conversion module and power supply circuit to provide unified power supply for the first and second processors and the first and second logic controllers, ensuring that the power supply voltage, ripple, and timing of the first and second processors are completely consistent, ensuring the collaborative stability of the dual-path architecture. At the same time, the output level signal can make the level sampled by the first and second logic controllers inconsistent, triggering the dual-path architecture recognition.

[0137] For dual-processor systems, high-speed signal interconnection between the first and second processors is also required. When two daughterboards form a dual-processor system, the high-speed signals of the two processors are connected via high-speed interconnect cables. For example, level signal configuration can be a core design element linking the power supply board and architecture identification. Level signal configuration can be two preset level signal output logics within the power supply board: the first power supply board uses internal jumpers or hardware circuitry to ensure consistent level signals output to the first and second logic controllers; the second power supply board uses internal jumpers or hardware circuitry to ensure inconsistent level signals output to the first and second logic controllers. This configuration is embedded within the power supply board, requiring no software intervention, thus ensuring the accuracy and consistency of architecture identification.

[0138] Specifically, the Node0_IFDET_0 / 1 and Node1_IFDET_0 / 1 signal lines on the motherboard are pulled high, and the power distribution board provides pull-down ground. In the dual-node architecture, the sideband connectors of both daughterboards are connected to the power distribution board, and both the first and second logic controllers recognize the ground signal (i.e., "00"), thus determining it to be a dual-node architecture. In the dual-path architecture, the sideband connectors and SlimSAS connectors of the processor daughterboard are not connected to the power distribution board, the main processor daughterboard recognizes the ground signal (i.e., "00"), and the processor daughterboard recognizes a high-level signal (i.e., "11"), thus determining it to be a dual-path architecture.

[0139] When the power supply system includes a first power board, the level signals received by the first logic controller and the second logic controller are configured to identify the server architecture type as a dual-node architecture (or a single-path architecture); when the power supply system includes a second power board, the level signals received by the first logic controller and the second logic controller are configured to identify the server architecture type as a dual-path architecture.

[0140] By establishing hardware-linked logic for power supply board type and architecture identification, different types of power supply boards are configured with different level signal outputs, thereby triggering the corresponding architecture identification results. The level signal output by the first power supply board makes the levels sampled by the first and second logic controllers consistent (both are at the first level or both are at the second level), triggering dual-node architecture identification; the level signal output by the second power supply board makes the levels sampled by the first and second logic controllers inconsistent (one is at the first level and the other is at the second level), triggering dual-path architecture identification. During production or assembly, only the corresponding type of power supply board needs to be selected to automatically complete the architecture identification configuration.

[0141] The dual-processor architecture and the dual-node architecture operate differently, and their power supply requirements also differ fundamentally. In a dual-processor architecture, the first and second processors operate collaboratively, requiring a stable and unified power supply to ensure timing synchronization and resource sharing between the two processors. In a dual-node architecture, the first and second processors operate independently, requiring an independent power supply circuit to ensure that a failure in one node does not affect the power supply stability of the other node. Furthermore, as a crucial source of electrical signals, the power supply system's configuration should be linked to the architecture identification logic to avoid mismatches between the power supply system and the architecture type. By designing two standardized power supply boards, precise matching between the power supply system and the architecture type is achieved, while simultaneously linking with the architecture identification logic to realize hardware-based linkage of architecture configuration.

[0142] To achieve multi-architecture adaptability of the power supply system, this embodiment designs two standardized power supply boards (a first power supply board and a second power supply board), corresponding to the power supply requirements of two different architectures. The first power supply board contains two independent power supply loops, providing independent power to the first and second processors and their corresponding logic controllers, ensuring power supply isolation in a dual-node architecture. The second power supply board contains a unified power supply loop, providing coordinated power to the first and second processors and their corresponding logic controllers, ensuring power supply stability and consistency in a dual-path architecture. This standardized design allows the power supply system to directly select the corresponding power supply board according to the architecture requirements, eliminating the need to redesign dedicated power supply circuits and reducing R&D and production costs.

[0143] By establishing hardware-linked logic for power supply board type and architecture identification, different types of power supply boards will be configured with different level signal outputs, thereby triggering the corresponding architecture identification results. Specifically, the level signal output by the first power supply board will cause the level sampled by the first and second logic controllers to be consistent (both are at the first level or both are at the second level), triggering dual-node architecture identification; the level signal output by the second power supply board will cause the level sampled by the first and second logic controllers to be inconsistent (one is at the first level and the other is at the second level), triggering dual-path architecture identification. This linkage logic completely binds the power supply configuration with the architecture identification, realizing one-click hardware adaptation of the architecture configuration. During production or assembly, only the corresponding type of power supply board needs to be selected to automatically complete the architecture identification configuration, without the need for additional hardware connections or software settings.

[0144] The combination of standardized power supply boards and linked identification logic ensures precise matching between the power supply system and the architecture type. The independent power supply circuit of the first power supply board ensures power supply isolation for the dual-node architecture, while the unified power supply circuit of the second power supply board ensures power supply stability for the dual-path architecture, avoiding operational anomalies caused by power supply mismatch with the architecture (such as unstable power supply in the dual-path architecture or power supply interference in the dual-node architecture). Architecture configuration accuracy is improved; the hardware linkage logic avoids errors caused by manual configuration, ensuring that the selected power supply board is completely consistent with the identified architecture type, reducing the risk of architecture configuration errors. Power supply reliability is enhanced; both power supply boards adopt standardized designs and have undergone rigorous reliability verification, providing stable power output. Simultaneously, the linked architecture identification logic can promptly detect anomalies caused by power supply mismatch with the architecture, improving server operational reliability.

[0145] Two standardized power supply boards enable mass production, reducing production costs. Furthermore, the direct binding between the architecture configuration and power supply board selection simplifies the production and assembly process, improving production efficiency. Only two standardized power supply boards need to be stocked, eliminating the need for multiple dedicated power supply modules, simplifying inventory management and preventing material stagnation. When servers experience power supply or architecture-related failures, maintenance personnel can quickly determine the architecture configuration based on the power supply board type and rapidly repair the fault by replacing it with the corresponding type, reducing maintenance complexity and costs. The standardized power supply boards can reuse existing mature power supply technologies, eliminating the need for redevelopment and further reducing R&D investment.

[0146] In some embodiments, such as Figure 12As shown, the motherboard has Node0_IFDET_0 / 1 and Node1_IFDET_0 / 1 detection signal pins. These pins are pulled up, and the power distribution board (PDB) provides a pull-down ground path. The detection signals are connected to the first and second logic controllers of the corresponding daughter boards, respectively. In a dual-node architecture configuration, the Sideband connectors of both Node0 and Node1 are connected to the power distribution board, and the logic controllers on both sides sample the ground level. In a dual-path architecture, the Sideband connector and SlimSAS connector of the daughter board where the processor resides are not connected to the power distribution board. The main processor daughter board samples the ground level, and the slave processor daughter board samples the pull-up high level. A dedicated communication line is reserved between the logic controllers of the two daughter boards. This communication line serves two purposes: firstly, it synchronizes the S0 state power-on timing in a dual-path architecture; secondly, when the slave processor role is detected, it triggers the disconnection of the BIOS memory connection on the slave processor side without requiring changes to the PCB hardware, thus accommodating the operational requirements of two independent BIOS firmware sets in a dual-node architecture.

[0147] Specifically, taking the example that each type of server product requires six months to develop a prototype, if the three types of products are developed in the traditional way, it would take 1.5 years, or require 3 times the manpower to complete within 0.5 years; by adopting the solution provided in this embodiment, only one general hardware platform needs to be developed, which can save 1 year of R&D time or save 2 times the manpower investment.

[0148] During mass production, daughterboards, management boards, and fan boards are shared across single-socket, dual-socket, and dual-node server systems, allowing for flexible material preparation and inventory management, and avoiding material stagnation due to shipment forecast errors. The embodiments provided in this application are not limited to a specific processor platform and are adaptable to different processor platforms, demonstrating good compatibility.

[0149] The server provided in this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A server, characterized in that, include: First processor, second processor, first logic controller, second logic controller; The first processor is connected to the first logic controller, the second processor is connected to the second logic controller, and the first logic controller is connected to the second logic controller. The first logic controller and the second logic controller are configured to: identify the server architecture type based on the received level signal, and coordinately control the operating state of the first processor and the second processor related to the architecture type based on the identification result; the architecture type includes dual-path architecture and dual-node architecture.

2. The server according to claim 1, characterized in that, The first logic controller is configured to perform timing state identification on the first processor, and the second logic controller is configured to perform timing state identification on the second processor; When the architecture type is identified as the dual-node architecture, the first processor and the second processor are configured to perform power-on and reset according to mutually independent timing sequences; When the architecture type is identified as the dual-path architecture, the first logic controller and the second logic controller interact with the timing status information of the first processor and the second processor; one of the first processor and the second processor is configured as the master processor and the other is configured as the slave processor. The slave processor is configured such that the start time of the power-on and reset sequence of the slave processor is delayed by a preset time compared to the completion time of the power-on and reset sequence of the master processor.

3. The server according to claim 2, characterized in that, When the architecture type is identified as the dual-socket architecture, one of the first processor and the second processor is configured as the master processor and the other is configured as the slave processor. The server further includes: a basic input / output system memory connected to the slave processor; the basic input / output system memory is configured to be disconnected from the slave processor.

4. The server according to claim 2, characterized in that, The first logic controller and the second logic controller are connected via a serial universal input / output interface, which is configured to exchange the timing state information between the first logic controller and the second logic controller. The timing status information includes the power-ready signal and the enable signal of the first processor and the second processor.

5. The server according to claim 2, characterized in that, The server further includes: a hardware synchronization link connected between the first processor and the second processor; When the architecture type is identified as the dual-path architecture, the hardware synchronization link is configured to: after the power-on and reset timing of the main processor is completed, transmit the power-ready signal and reset signal of the main processor to the slave processor to trigger the start of the power-on and reset timing of the slave processor.

6. The server according to claim 1, characterized in that, The level signal includes a first level and a second level; If the level signal received by the first logic controller and the level signal received by the second logic controller are both at the first level or both at the second level, the server architecture type is identified as a dual-node architecture. If one of the level signal received by the first logic controller and the level signal received by the second logic controller is the first level and the other is the second level, the server architecture type is identified as a dual-path architecture.

7. The server according to claim 1, characterized in that, The server also includes: Distribution board, including grounding terminal; A first reference power supply terminal is connected to the first logic control device; the first reference power supply terminal and the common terminal of the first logic control device form a first node; The second reference power supply terminal is connected to the second logic control device; the second reference power supply terminal and the common terminal of the second logic control device form a second node; When the power distribution board is connected to the first logic controller, the first node is connected to the ground terminal; when the power distribution board is connected to the second logic controller, the second node is connected to the ground terminal. The level signal includes: a ground signal from the ground terminal, a first reference electrical signal from the first reference power supply, and a second reference electrical signal from the second reference power supply terminal; When both the first node and the second node are connected to the grounding terminal, the architecture type is identified as the dual-node architecture; When one of the first node and the second node is connected to the ground terminal, and the other is disconnected from the ground terminal, the architecture type is identified as the dual-path architecture.

8. The server according to claim 1, characterized in that, The server further includes: a clock synchronization link and a high-speed interconnect cable; the clock synchronization link is connected between the first processor and the second processor; the high-speed interconnect cable is connected between the high-speed bus ports of the first processor and the second processor; The clock synchronization link is configured to transmit the reference clock signal output by the first processor to the second processor when the architecture type is identified as a dual-path architecture, so as to synchronize the clocks of the two processors. The high-speed interconnect cable is configured to be enabled when the architecture type is identified as a dual-path architecture, in order to enable high-speed data communication between the first processor and the second processor.

9. The server according to claim 8, characterized in that, The high-speed interconnect cable is a PCIe high-speed differential cable.

10. The server according to claim 1, characterized in that, The server also includes: a management system and a cooling system; The management system includes a management board; the management board is connected to the first logic controller and the second logic controller, and is configured to load the corresponding firmware configuration based on the architecture type identification results of the first logic controller and the second logic controller, so as to adapt to the operation of the dual-path architecture or dual-node architecture. The cooling system includes a fan plate; the fan plate is connected to the management board and is configured to provide cooling for the first processor and the second processor according to instructions from the management board.

11. The server according to claim 1, characterized in that, The server also includes: a power supply system; The power supply system includes: a first power board or a second power board; Wherein, when the power supply system includes a first power board, the level signals received by the first logic controller and the second logic controller are configured to make the server architecture type be identified as a two-node architecture; In the case where the power supply system includes a second power board, the level signals received by the first logic controller and the second logic controller are configured to cause the server architecture type to be identified as a dual-path architecture.

12. The server according to claim 11, characterized in that, The first power board includes two independent power supply circuits, which independently supply power to the first processor and the second processor, respectively. The second power board includes a unified power supply circuit that supplies power to both the first processor and the second processor.

13. The server according to claim 1, characterized in that, A communication line is also provided between the first logic controller and the second logic controller; The communication line is configured to transmit timing synchronization signals between the first logic controller and the second logic controller when the architecture type is identified as a dual-path architecture. The communication line is also configured to: when the architecture type is identified as a dual-path architecture and the second processor corresponding to the second logic controller is a slave processor, trigger the basic input / output system memory connected to the second processor to disconnect from the second processor.

14. The server according to claim 1, characterized in that, The server also includes a processor system, which includes a first daughterboard and / or a second daughterboard, wherein the first daughterboard integrates the first processor and the second daughterboard integrates the second processor; In the case that the server is a single-socket architecture, the processor system includes the first sub-board or the second sub-board; In the case that the server is a dual-socket architecture or a dual-node architecture, the processor system includes the first sub-board and the second sub-board; The first daughterboard and the second daughterboard have the same hardware design.

15. The server according to claim 1, characterized in that, Both the first logic controller and the second logic controller are programmable logic devices.

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