A high-throughput fft operation module platform based on parallel acceleration
Patent Information
- Application Number
- CN202611157053.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-31
- Publication Date
- 2026-11-03
AI Technical Summary
Existing FFT acceleration designs on FPGA platforms suffer from problems such as difficulty in balancing speed and resource utilization, poor multi-channel synchronization, insufficient configuration flexibility, and low customization of official IP cores, resulting in wasted hardware resources and high power consumption, making it difficult to meet the requirements of high-bandwidth and high-real-time digital signal processing.
A high-throughput FFT computation module platform based on parallel acceleration is adopted, including memory, processor and scheduling controller. Through multi-stage pipelined operation, ping-pong storage and reasonable allocation of FPGA heterogeneous resources, parallel data processing and resource optimization are achieved.
It significantly improves computing speed and throughput, reduces hardware costs and power consumption, is suitable for low-power embedded scenarios, has good compatibility, and supports variable-point FFT operations in multiple scenarios.
Smart Images
Figure CN123030831A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the fields of digital signal processing and integrated circuit design technology, and specifically to a high-throughput FFT operation module platform based on parallel acceleration. Background Technology
[0002] With the continuous development of digital signal processing technology, systems are placing stringent demands on the speed, throughput, power consumption, and resource utilization of FFT operations. As the core algorithm of digital signal processing, the performance of FFT directly determines the processing capability of the entire system. However, existing FFT acceleration designs on FPGA platforms generally suffer from problems such as difficulty in balancing speed and resources, poor multi-channel synchronization, insufficient configuration flexibility, and low customization of official IP cores. These issues have become key bottlenecks restricting the development of high-bandwidth, high-real-time digital signal processing systems.
[0003] Existing technologies still have some shortcomings in FFT operations, specifically in the following aspects: 1. It is difficult to balance operation speed and resource utilization: The existing single-channel serial FFT operation speed is extremely low and cannot meet the requirements of high-bandwidth real-time signal processing; although single-level parallel FFT improves the speed, the idle time of different levels of operation units is long. On FPGA, the resource utilization of DSP48E unit is usually less than 50%, which causes serious waste of hardware resources and brings large wiring delay and power consumption.
[0004] 2. Power consumption and latency are difficult to meet the needs of embedded scenarios: Existing GPU / CPU software acceleration solutions consume tens or even hundreds of watts of power, and the computation latency is above milliseconds; existing hardware FFT designs have high dynamic power consumption on FPGAs due to long critical paths and low resource utilization; official IP cores also have relatively high power consumption due to redundant designs.
[0005] 3. Inefficient use of FPGA resources: Existing designs often fail to fully utilize the heterogeneous resource advantages of FPGAs. For example, simple addition operations are implemented using DSP48E units, resulting in wasted DSP resources; a large amount of combinational logic is implemented using LUTs, leading to routing congestion and timing problems. Summary of the Invention
[0006] To address the aforementioned technical shortcomings, the present invention aims to provide a high-throughput FFT computation module platform based on parallel acceleration.
[0007] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: The present invention provides a high-throughput FFT operation module platform based on parallel acceleration, including: a memory, a processor and a scheduling controller.
[0008] The memory is used to store computer programs.
[0009] The processor includes an input FFT operation module, a rotation factor storage module, a rotation module, a data ping-pong storage module, and an output FFT operation module.
[0010] The input FFT operation module is used to preprocess the input data and then perform FFT operations on the preprocessed data.
[0011] The rotation factor storage module is used to store and retrieve rotation factors.
[0012] The rotation module is used to perform phase rotation operations on the data based on the rotation factor.
[0013] The data ping-pong storage module is used to add a set of redundant RAM for ping-pong storage and retrieval of data; The output FFT operation module is used to perform output-level FFT operations.
[0014] The scheduling controller is used to uniformly schedule the working timing of the input FFT operation module, the twitch factor storage module, the twitch module, the data ping-pong storage module, and the output FFT operation module.
[0015] Preferably, the preprocessing of the input data specifically refers to using radix-8 butterfly operations, where the N data points of each input group are rearranged during the N-point FFT operation to obtain... Data blocks.
[0016] Preferably, based on the rotation factor, a phase rotation operation is performed on the data. The specific process is as follows: The rotation module consists of 7 independent pipelined complex multipliers. When implementing the complex multipliers, the formula is: The four multiplications required by a complex multiplier are compressed into three multiplication operations, thereby enabling a phase rotation operation. It is the first complex number input, where b is the real part, 'a' is the imaginary part, and 'j' is the imaginary unit. is the input rotation factor, where c is the real part and d is the imaginary part.
[0017] Preferably, the process of adding a set of redundant RAM arrays for ping-pong storage and retrieval of data is as follows: A1. The rotated data is written into the basic RAM or redundant RAM using a cross-arrangement storage rule. The cross-arrangement storage rule means that the storage address is generated collaboratively by the built-in ram_idx number controller and ram_addr address counter, where ram_idx represents the RAM block number currently being written, and ram_addr represents the internal storage address of a single RAM block.
[0018] A2. The data ping-pong storage module has a built-in ping-pong state machine, which includes two working states: writing to the basic RAM and reading from the redundant RAM, and writing to the redundant RAM and reading from the basic RAM. When any RAM array completes a round of writing N complete points of data, the working state switch of the ping-pong state machine is triggered.
[0019] A3. When the ping-pong state machine is executing two working states, for the basic RAM array or redundant RAM array in the read state, the read address counter accumulates to generate the basic address in a preset fixed step order. At the same time, the ram_idx controller switches different RAM block read channels in an interleaved arrangement order. Multiple RAM blocks are read out in parallel and stored complex data. After restoring the 8 parallel data streams, the data is transmitted to the output FFT operation module.
[0020] Preferably, the specific process of performing the output-level FFT operation is as follows: After receiving the data transmitted by the data ping-pong storage module, the FFT operation module performs 8 N / 8-point FFT operations in parallel within a single operation cycle. The 8 N / 8-point FFT operation process is to cyclically reuse the architecture of the input FFT operation module, the rotation factor storage module, the rotation module, the data ping-pong storage module, and the output FFT operation module, and continuously iterate the data until N / 8 is less than or equal to 8.
[0021] The beneficial effects of this invention are as follows: 1. Significantly improved processing speed and throughput: This invention combines multi-stage pipelined processing, partial parallelism, and ping-pong storage, allowing multiple parallel data streams to be processed simultaneously. Furthermore, the module supports pipe-line processing mode, increasing system throughput by approximately 8 times compared to serial FFT. At a 100MHz system clock, the entire processing cycle of a 1024-point FFT (from the first input data to the last output data) is only 2.91µs, which can meet the real-time processing requirements of high-bandwidth signals exceeding 10Gbps.
[0022] 2. Significantly Improved Hardware Resource Utilization: This invention combines pipelined computation with ping-pong resource scheduling, achieving DSP resource utilization of over 90%. By rationally allocating heterogeneous FPGA resources, simple logic operations are implemented using LUTs, while complex multiplication operations are implemented using the DSP48E, further improving resource utilization. Under the same computational performance, the FPGA resource usage of this invention is reduced by approximately 45% compared to Xilinx's official FFT IP core, effectively reducing hardware costs and power consumption.
[0023] 3. Significant advantages in low-power design: This invention reduces the system's operating frequency requirements by segmenting the critical path through pipelined registers; resource reuse reduces the number of computing units; and distributed storage reduces memory access power consumption. Overall power consumption is more than 80% lower than GPU solutions with similar performance and about 30% lower than Xilinx's official FFT IP core, making it suitable for low-power embedded scenarios such as spaceborne and airborne applications.
[0024] 4. Controllable latency and good real-time performance: The computational latency of the fully pipelined structure in this invention is fixed and independent of the amount of input data, which ensures the real-time performance of the system and is suitable for latency-sensitive applications, such as real-time radar target detection and high-speed satellite communication demodulation.
[0025] 5. Good FPGA platform compatibility: This solution is implemented using standard VHDL and does not depend on the proprietary IP cores of any specific FPGA vendor, so it can be easily ported to any mainstream FPGA platform. Attached Figure Description
[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0027] Figure 1 This is a schematic diagram of the platform structure connection of the present invention.
[0028] Figure 2 This is a schematic diagram of the processor system architecture of the present invention.
[0029] Figure 3 In this invention, when performing an N-point FFT operation, the input N data are rearranged to obtain... A schematic diagram of the data blocks.
[0030] Figure 4 This is a schematic diagram of the RAM layout in an embodiment of the present invention.
[0031] Figure 5 This is a schematic diagram illustrating the sequence of reading RAM in an embodiment of the present invention. Detailed Implementation
[0032] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0033] Reference Figure 1 As shown, the present invention provides a high-throughput FFT operation module platform based on parallel acceleration, characterized in that it includes a memory, a processor and a scheduling controller.
[0034] The memory is used to store computer programs.
[0035] Reference Figure 2 As shown, the processor includes an input FFT operation module, a rotation factor storage module, a rotation module, a data ping-pong storage module, and an output FFT operation module.
[0036] The input FFT operation module is used to preprocess the input data and then perform FFT operations on the preprocessed data.
[0037] Reference Figure 3 As shown, in a specific example, the preprocessing of the input data specifically refers to using radix-8 butterfly operations. During the N-point FFT operation, the N data points of each input group are rearranged to obtain... Data blocks.
[0038] In a specific example, the process of performing FFT on the preprocessed data is as follows: Based on... The data preprocessing method allows each master clock to complete an independent 8-point FFT operation, thereby decomposing the N-point FFT algorithm into an iterative combination of multi-layer radix-8 butterfly operations and subsequent N / 8-point FFT operations.
[0039] By using DSP or BRAM to perform mathematical derivation and simplification of the iterative combination of multi-layer radix-8 butterfly operation and post-N / 8 point FFT operation, the FFT operation can be completed by performing only 4 constant coefficient multiplications.
[0040] It should be noted that this invention uses radix-8 butterfly operations, which are more efficient, have shorter critical paths, fewer FFT levels with the same number of points, and lower latency.
[0041] The rotation factor storage module is used to store and retrieve rotation factors.
[0042] In a specific example, the storage and retrieval of the rotation factor involves the following storage process: the rotation factor storage module is configured as a block-distributed independent ROM array, all rotation factors required for the N-point FFT are pre-calculated offline by software, and then the storage array is divided according to the parallel reading requirements. The total address depth of the ROM array is uniformly configured as N / 8.
[0043] It should be noted that the total address depth of the ROM array is matched one-to-one with the size of the data block processed by the input FFT operation module in a single operation, thereby enabling the synchronous parallel reading of multiple rotation factors and matching the throughput rate of the front-end 8 parallel data streams.
[0044] In the rotation factors corresponding to the 8 parallel data streams, the phase of the first rotation factor is always 0, which corresponds to the real part of the complex number being 1 and the imaginary part being 0. There is no actual operation requirement when participating in complex multiplication, so the ROM array only stores the remaining 7 valid rotation factors.
[0045] It should be noted that among the rotation factors corresponding to the 8 parallel data streams, the phase of the first rotation factor is always 0, corresponding to a real part of 1 and an imaginary part of 0 in the complex number. There is no actual computational requirement when participating in complex multiplication. Therefore, the ROM array only stores the remaining 7 valid rotation factors, thereby directly reducing the ROM storage depth by 1 / 8, significantly reducing the ROM logic resource occupation on the FPGA chip, and avoiding the problems of on-chip storage resource shortage and wiring congestion caused by large-scale rotation factor storage.
[0046] The seven valid rotation factors correspond to seven independent read-only ROM storage units, and the seven independent read-only ROM storage units share a unified address counter.
[0047] It should be noted that the address counter is driven synchronously by the master clock, and the address reading timing is aligned with the data output timing of the input FFT operation module. Each master clock cycle synchronously outputs 7 rotation factors with different phases. The 7 valid rotation factors are synchronously sent to the subsequent rotation module and paired one by one with the last 7 complex data to be rotated in the front-end 8 data. The first zero-phase data is directly bypassed and skipped from the complex multiplication logic, reducing the idle waiting period of the complex multiplier inside the rotation module.
[0048] In a specific example, the storage and retrieval of the twitch factor is described, wherein the retrieval process is as follows: the twitch factor storage module has a built-in level address offset controller. During the FFT operation, each time the butterfly operation is switched, the address offset controller automatically adds the corresponding level offset and switches the ROM read address range.
[0049] It should be noted that the twiddle factor reading in this invention does not require reloading the twiddle factor data, and supports uninterrupted operation of multiple blocks of N-point FFT data in a pipeline, eliminating the delay caused by frequent address switching and waiting for data loading in traditional centralized twiddle factor architectures.
[0050] Meanwhile, a pipeline register is configured in the ROM array to synchronously latch 7 valid rotation factors, thereby compensating for the inherent delay of ROM reads.
[0051] It should be noted that for variable-point FFT scenarios, the rotation factor storage module supports multiple pre-calculated rotation factor partitions for storage. The ROM partitions can be switched via an external configuration port to adapt to FFT operation requirements of different lengths, such as 1024 points, 2048 points, and 4096 points. This eliminates the need for re-synthesizing the hardware design, improves the module's configuration flexibility, and solves the limitation of customized configuration of Xilinx's official FFT IP core.
[0052] The rotation module is used to perform phase rotation operations on the data based on the rotation factor.
[0053] In a specific example, the phase rotation operation of the data based on the rotation factor is performed as follows: The rotation module consists of 7 independent pipelined complex multipliers. When implementing the complex multipliers, the formula is: The four multiplications required by a complex multiplier are compressed into three multiplication operations, thereby enabling a phase rotation operation. It is the first complex number input, where b is the real part, 'a' is the imaginary part, and 'j' is the imaginary unit. is the input rotation factor, where c is the real part and d is the imaginary part.
[0054] It should be noted that the rotation module consists of 7 independent pipelined complex multipliers, which are matched with the 7 valid rotation factors output by the rotation factor storage module and the last 7 complex data to be rotated output by the input FFT operation module. The first zero-phase data is directly passed to the back-end data ping-pong storage module without passing through the complex multiplier.
[0055] This invention reduces the original four real number multiplications required for a complex multiplication to three by phase rotation, reducing the resource consumption of a single complex multiplier by 25% and simultaneously reducing the overall resource overhead of a seven-channel multiplier, thus solving the problem of insufficient DSP resource utilization in traditional phase rotation modules (less than 50%).
[0056] The data ping-pong storage module is used to add a set of redundant RAM for ping-pong storage and retrieval of data.
[0057] In a specific example, the redundant RAM array is obtained based on the native Block RAM resource configuration on the FPGA chip, wherein the RAM resource configuration includes a basic operational storage RAM array and a redundant RAM array.
[0058] In a specific example, the configuration process of the redundant RAM array is as follows: First, the basic RAM array specifications are calculated based on the data parallelism of the N-point FFT operation and the storage cross-arrangement rules. The basic RAM array contains several independent BlockRAMs.
[0059] It should be noted that the basic RAM array specifications are calculated based on the data parallelism of the N-point FFT operation and the storage cross-layout rules. The specific process is as follows: First, based on the 8-way parallel data throughput parallelism of the N-point FFT operation, the number of RAM blocks in the basic RAM array is determined to be 8. Then, combined with the storage capacity requirement of the storage cross-layout to completely cache one frame of intermediate N-point FFT operation data, the storage depth of a single RAM block is calculated to be N / 8. Finally, based on the fixed-point quantization bit width W of the real and imaginary parts of the complex data, the bit width of a single RAM block is calculated to be 2W. Thus, the overall hardware specifications of the basic RAM array are determined.
[0060] For example, when N=128 and W=16, the depth of a single RAM block is 128 / 8=16, the bit width of a single RAM block is 2×16=32bit, and the total capacity of the basic array is 8×16×32=4096bit.
[0061] It should be noted that the depth and bit width of a single Block RAM are both matched to the storage requirements of 8-way parallel complex data, which can completely cache all intermediate operation data of an entire set of N-point FFT after phase rotation, and meet the caching requirements of intermediate results of a single round of FFT operation.
[0062] Based on the basic RAM array, a set of Block RAM arrays with the exact same number, depth, bit width, and read / write timing as the basic RAM array is copied as a redundant RAM array.
[0063] It should be noted that the hardware resources of the basic RAM array and the redundant RAM array are independent of each other, and the read and write ports do not conflict with each other. There are no contention issues such as address and bus access, thus realizing the dual-cache architecture required for ping-pong storage. The redundant RAM array resources are dynamically allocated from the FPGA's idle Block RAM pool. It is configured with built-in resource occupancy adaptive judgment logic, which can automatically identify the remaining BRAM resource capacity of the target FPGA. If the BRAM resources are sufficient, the entire redundant RAM array is allocated. If the BRAM resource reserve is limited, the lightweight mode can be switched through the external configuration port to reduce the storage depth of a single RAM block to adapt to a small number of FFT points and ensure that the redundant ping-pong storage architecture is not lost.
[0064] In addition, the redundant RAM array does not share storage resources with the rotation factor ROM and input cache RAM. Its physical storage address and read / write bus are completely isolated, avoiding bus arbitration delay caused by multiple modules accessing on-chip storage at the same time. It also eliminates the need for additional storage arbitration logic in traditional multi-channel FFT architectures, simplifying the hardware control link.
[0065] The redundant RAM array read and write ports are each equipped with independent write address generators and read address generators, which are completely symmetrical with the basic RAM array control logic. The address scheduling of the two RAM arrays works in parallel and independently. When switching between ping-pong read and write states, only the multiplexer strobe signal needs to be switched, without reconfiguring the address counting parameters. The switching delay is only one master clock cycle, which will not interrupt the continuous data flow of the pipeline. Moreover, the hardware bit width and storage depth of the redundant RAM array can be dynamically configured according to the number of FFT operation points N. The RAM array specifications are automatically adjusted for 1024-point, 2048-point, and 4096-point FFTs to adapt to the variable number of point operation requirements in multiple scenarios.
[0066] In a specific example, the process of adding a set of redundant RAM arrays for ping-pong storage and retrieval of data is as follows: A1. The rotated data is written into the base RAM or redundant RAM using a cross-arrangement storage rule. The cross-arrangement storage rule means that the storage address is generated collaboratively by the built-in ram_idx number controller and ram_addr address counter, where ram_idx represents the RAM block number currently being written, and ram_addr represents the internal storage address of a single RAM block.
[0067] It should be noted that all data is distributed and stored in different RAM blocks according to the cross-mapping rules, which can avoid address conflicts caused by writing continuous data into the same RAM and create conditions for subsequent parallel reading.
[0068] For example, taking a 128-point FFT as an example, the indicator word (ram_idx, ram_addr) indicates that the data is stored in RAM with the number ram_idx and the storage address ram_addr. The RAM layout for writing is as follows: Figure 4 As shown.
[0069] When performing an N-point FFT operation, when the number of writes is greater than At this point, data reading can begin, with addresses incremented sequentially, but the order of reading RAM still needs to be staggered. Taking a 128-point FFT as an example, the RAM reading order is as follows: Figure 5 As shown.
[0070] A2. The data ping-pong storage module has a built-in ping-pong state machine, which includes two working states: writing to the basic RAM and reading from the redundant RAM, and writing to the redundant RAM and reading from the basic RAM. When any RAM array completes a round of writing N complete points of data, the working state switch of the ping-pong state machine is triggered.
[0071] A3. When the ping-pong state machine is executing two working states, for the basic RAM array or redundant RAM array in the read state, the read address counter accumulates to generate the basic address in a preset fixed step order. At the same time, the ram_idx controller switches different RAM block read channels in an interleaved arrangement order. Multiple RAM blocks are read out in parallel and stored complex data. After restoring the 8 parallel data streams, the data is transmitted to the output FFT operation module.
[0072] It should be noted that when the basic RAM array is in read mode, the redundant RAM array undertakes all new data writing tasks; when the redundant RAM array is reading, the basic RAM receives the new data stream. The two RAM arrays are completely isolated from each other in read and write operations, there is no read / write address conflict, and no arbitration logic is required. The ping-pong storage architecture in this invention is fully adapted to pipeline mode, continuously and uninterruptedly receiving parallel data from the front end (8 channels) and synchronously and uninterruptedly outputting ordered rearranged data to the back end, thereby ensuring stable operation at maximum throughput.
[0073] The output FFT operation module is used to perform output-level FFT operations.
[0074] In a specific example, the execution of the output-level FFT operation is as follows: After receiving the data transmitted by the data ping-pong storage module, the FFT operation module performs 8 N / 8-point FFT operations in parallel within a single operation cycle. The 8 N / 8-point FFT operation process is to cyclically reuse the architecture of the input FFT operation module, the rotation factor storage module, the rotation module, the data ping-pong storage module, and the output FFT operation module, and continuously iterate the data until N / 8 is less than or equal to 8.
[0075] It should be noted that after the iteration is completed, the data is calculated and output through radix-8, radix-4, or radix-2 butterfly operations. When outputting the data, due to the bit reversal in FFT, the bit index is output at the same time as the data to indicate the coefficients corresponding to the data.
[0076] The scheduling controller is used to uniformly schedule the working timing of the FFT operation module, the rotation factor storage module, the rotation module, the data ping-pong storage module, and the output FFT operation module.
[0077] The examples described in this invention are not limited to the specific embodiments listed above. The examples are merely illustrative to facilitate understanding of the invention and do not constitute a limitation on the scope of protection of this invention. Any modifications, equivalent substitutions, etc., made within the spirit and principles of this invention should be included within the scope of protection.
[0078] The above description is merely an example and illustration of the concept of the present invention. Those skilled in the art can make various modifications or additions to the specific embodiments described or use similar methods to replace them, as long as they do not deviate from the concept of the invention or exceed the scope defined in this specification, they should all fall within the protection scope of the present invention.
Claims
1. A high-throughput FFT computation module platform based on parallel acceleration, characterized in that, This includes memory, processor, and scheduling controller; The memory is used to store computer programs; The processor includes an input FFT operation module, a rotation factor storage module, a rotation module, a data ping-pong storage module, and an output FFT operation module; The input FFT operation module is used to preprocess the input data and then perform FFT operation on the preprocessed data; The rotation factor storage module is used to store and retrieve rotation factors; The rotation module is used to perform phase rotation operations on the data based on a rotation factor; The data ping-pong storage module is used to add a set of redundant RAM for ping-pong storage and retrieval of data; The output FFT operation module is used to perform output-level FFT operations; The scheduling controller is used to uniformly schedule the working timing of the input FFT operation module, the twitch factor storage module, the twitch module, the data ping-pong storage module, and the output FFT operation module.
2. The high-throughput FFT operation module platform based on parallel acceleration according to claim 1, characterized in that, The preprocessing of the input data specifically involves using radix-8 butterfly operations. During the N-point FFT operation, the N data points of each input group are rearranged to obtain... Data blocks.
3. The high-throughput FFT operation module platform based on parallel acceleration according to claim 2, characterized in that, The specific process of performing FFT on the preprocessed data is as follows: Relying on The data preprocessing method allows each main working clock to complete an independent 8-point FFT operation, thereby decomposing the N-point FFT algorithm into an iterative combination of multi-layer radix-8 butterfly operations and subsequent N / 8-point FFT operations. By using DSP or BRAM to perform mathematical derivation and simplification of the iterative combination of multi-layer radix-8 butterfly operation and post-N / 8 point FFT operation, the FFT operation can be completed by performing only 4 constant coefficient multiplications.
4. The high-throughput FFT operation module platform based on parallel acceleration according to claim 3, characterized in that, The storage and retrieval of the rotation factor, wherein the storage procedure is as follows: The rotation factor storage module is configured as a block-distributed independent ROM array. All rotation factors required for N-point FFT are pre-calculated offline by software, and then the storage array is divided according to the parallel reading requirements. The total address depth of the ROM array is uniformly configured as N / 8. In the rotation factors corresponding to the 8 parallel data streams, the phase of the first rotation factor is always 0, which corresponds to the real part of the complex number being 1 and the imaginary part being 0. There is no actual operation requirement when participating in complex multiplication. Therefore, the ROM array only stores the remaining 7 valid rotation factors. The seven valid rotation factors correspond to seven independent read-only ROM storage units, and the seven independent read-only ROM storage units share a unified address counter.
5. The high-throughput FFT operation module platform based on parallel acceleration according to claim 4, characterized in that, The storage and retrieval of the rotation factor, wherein the retrieval process is as follows: The rotation factor storage module has a built-in series address offset controller. During the FFT operation, each time the butterfly operation is switched, the address offset controller automatically adds the corresponding series offset and switches the ROM read address range. Meanwhile, a pipeline register is configured in the ROM array to synchronously latch 7 valid rotation factors, thereby compensating for the inherent delay of ROM reads.
6. The high-throughput FFT operation module platform based on parallel acceleration according to claim 5, characterized in that, The specific process of performing phase rotation operation on the data based on the rotation factor is as follows: The rotating module consists of 7 independent pipelined complex multipliers. These complex multipliers are implemented according to the formula: The four multiplications required by a complex multiplier are compressed into three multiplication operations, thereby enabling a phase rotation operation. It is the first complex number input, where b is the real part, 'a' is the imaginary part, and 'j' is the imaginary unit. is the input rotation factor, where c is the real part and d is the imaginary part.
7. A high-throughput FFT operation module platform based on parallel acceleration according to claim 6, characterized in that, The redundant RAM array is obtained based on the native Block RAM resource configuration on the FPGA chip, wherein the RAM resource configuration includes a basic computing storage RAM array and a redundant RAM array.
8. A high-throughput FFT operation module platform based on parallel acceleration according to claim 7, characterized in that, The configuration process for the redundant RAM array is as follows: First, the basic RAM array specifications are calculated based on the data parallelism of the N-point FFT operation and the storage cross-arrangement rules. The basic RAM array contains several independent Block RAMs. Based on the basic RAM array, a set of Block RAM arrays with the exact same number, depth, bit width, and read / write timing as the basic RAM array is copied as a redundant RAM array.
9. A high-throughput FFT operation module platform based on parallel acceleration according to claim 8, characterized in that, The specific process of adding a redundant RAM array for ping-pong storage and retrieval of data is as follows: A1. The rotated data is written into the base RAM or redundant RAM using a cross-arrangement storage rule. The cross-arrangement storage rule means that the storage address is generated collaboratively by the built-in ram_idx number controller and ram_addr address counter, where ram_idx represents the RAM block number currently being written, and ram_addr represents the internal storage address of a single RAM block. A2. The data ping-pong storage module has a built-in ping-pong state machine, which includes two working states: writing to the basic RAM and reading from the redundant RAM, and writing to the redundant RAM and reading from the basic RAM. When any RAM array completes a round of writing a complete N-point data, the working state switch of the ping-pong state machine is triggered. A3. When the ping-pong state machine is executing two working states, for the basic RAM array or redundant RAM array in the read state, the read address counter accumulates to generate the basic address in a preset fixed step order. At the same time, the ram_idx controller switches different RAM block read channels in an interleaved arrangement order. Multiple RAM blocks are read out in parallel and stored complex data. After restoring the 8 parallel data streams, the data is transmitted to the output FFT operation module.
10. A high-throughput FFT operation module platform based on parallel acceleration according to claim 8, characterized in that, The specific process of performing the output-level FFT operation is as follows: After receiving the data transmitted by the data ping-pong storage module, the FFT operation module performs 8 N / 8 point FFT operations in parallel within a single operation cycle. The 8 N / 8 point FFT operation process is to cyclically reuse the architecture of the input FFT operation module, the rotation factor storage module, the rotation module, the data ping-pong storage module, and the output FFT operation module, and continuously iterate the data until N / 8 is less than or equal to 8.