A low-voltage power distribution ERC closed-loop verification and fault simulation system and method based on a JSON netlist

Abstract

The present application belongs to the technical field of computer-aided design and electrical safety verification of low-voltage distribution circuit, and discloses a low-voltage distribution ERC closed-loop verification and fault simulation system and method based on JSON netlist. The system converts the netlist into power electronic circuit intermediate data with stable identification and original hierarchical mapping, identifies functional units through port anchoring matching, reconstructs power, sampling and control topology, executes power-specific electrical rules to form structured defect objects, and generates directional fault simulation tasks accordingly; the improved node method is used to solve the reference working condition and the fault working condition, and then combined with static overrun, dynamic response, abnormal propagation path and data uncertainty to confirm defects and track root causes. The present application is used for verifying the functional electrical risks of low-voltage distribution protection circuit at the schematic diagram stage.

Description

Technical Field

[0001] This invention relates to the field of computer-aided design and electrical safety verification technology for low-voltage power distribution protection circuits, specifically to a low-voltage power distribution ERC closed-loop verification and fault simulation system and method based on JSON netlists. Background Technology

[0002] Conventional electronic design automation (EDA) tools can check for issues such as unconnected pins, shorted networks, duplicate reference designators, and network naming conflicts based on component pin attributes and network connectivity. These checks are effective at identifying obvious drafting errors, but they typically only address whether networks are connected and whether pin types conflict. Many problems in low-voltage power distribution protection circuits are not due to open circuits or short circuits, but rather to connections that appear correct but actually cause sampling distortion, drive conflicts, overvoltage shutdown, or malfunctions during operation.

[0003] For example, two differential sampling branches may be fully connected, but their polarities may be opposite, or their resistance, capacitance, and parasitic parameters may be inconsistent, resulting in near-zero output under normal operating conditions but a significant decrease in sensitivity under fault conditions. Similarly, the two drive channels of a half-bridge or reverse-series power switch may not be short-circuited in the static netlist, but the propagation delay, dead zone, and device turn-off delay may still create a brief period of overlapping conduction. Even if the inductive load branch is fully connected, a continuous freewheeling or energy absorption path may not be found after the power switch is turned off. These problems are only easily understood by analyzing the topology, device parameters, and time process together.

[0004] Existing netlist analysis techniques can identify circuit structures using templates or graph matching; existing electrical rule tools can traverse netlists and check preset connection conditions; and existing circuit simulation tools can write fault models into netlists and calculate waveforms. However, these tools typically operate independently: structure identification results are mainly used for display or classification, rule checks usually only provide static alarms, and simulation conditions are selected separately by engineers. Rule alarms are difficult to automatically convert into simulation tasks with fault models, injection locations, parameter ranges, and observation points; abnormal waveforms generated by simulation cannot be automatically returned to the rule objects and root cause nodes in the schematic.

[0005] Furthermore, different electronic design automation (EDA) tools do not express levels, networks, pins, device parameters, and units consistently. If rule verification, dynamic simulation, and report outputs use different node numbers, or if the same device lacks a traceable mapping in the power path, sampling path, and control path, manual comparison is still required. For low-voltage power distribution protection circuits containing hundreds of nodes, multiple isolation boundaries, and multiple feedback links, manual comparison is not only slow but also prone to losing repeatability after design revisions.

[0006] Therefore, a technical solution is needed that uses stable, identifiable intermediate data to connect functional unit identification, three-layer topology, electrical rules, directional fault simulation, and dynamic tracing into a continuous closed loop. This solution should also provide verifiable processing results when template uncertainty, missing parameters, model non-convergence, or potential false alarms from static rules, rather than simply outputting a definitive conclusion. Summary of the Invention

[0007] The purpose of this invention is to provide a low-voltage power distribution ERC closed-loop verification and fault simulation system and method based on JSON netlists, in order to solve the problems in the existing process, such as the difficulty in stably reconstructing the functional semantics of the netlist, the separation between static rules and dynamic simulation, the reliance on manual selection for fault models and injection points, the lack of physical evidence to verify rule false alarms, and the difficulty in pointing back to the root cause node of the schematic diagram for simulation anomalies.

[0008] To address the aforementioned issues, this invention discloses a low-voltage power distribution ERC closed-loop verification and fault simulation system based on JSON netlists. The system comprises a data access module, a semantic topology reconstruction module, an electrical rule verification module, a simulation task generation module, a dynamic simulation module, a closed-loop confirmation and tracing module, and a result output module. Each module exchanges data through a PEC (Power Electronic Circuit) intermediate data object, and the output of one module can directly become the input of the next, avoiding the need for separate numbering and modeling for netlist parsing, rule verification, and simulation solving.

[0009] The data access module reads the JSON circuit netlist and corresponding format adaptation information, completes field mapping, unit conversion, connection integrity checks, and parameter source registration, and establishes unified identifiers for nodes, components, and pins. These unified identifiers are mapped to the tool source, hierarchical path, tag number, pin number, or network name of the original netlist. Rule configurations, fault configurations, and simulation configurations are also registered using the same identifier system, enabling defect objects, simulation tasks, waveform channels, and root cause paths to be traced back to their specific locations in the schematic.

[0010] The semantic topology reconstruction module constructs a node-component diagram based on intermediate PEC data, generating candidate subgraphs from port anchors such as power supply, reference ground, power input, power output, sampling, and drive. The module compares the candidate subgraphs with functional unit templates in terms of component combinations, port connections, impedance ranges, directions, and upstream / downstream links. When multiple templates simultaneously meet the conditions, conflicts are resolved by considering link directions and component overlap. After identification, the system forms a power topology representing energy transmission, a sampling topology representing the transmission of the measured signal, and a control topology representing the detection-to-execution process. Cross-layer connection identifiers link the same device or signal across these three topologies.

[0011] The electrical rule verification module selects applicable rules based on the functional unit type, checking for issues such as differential sampling polarity and impedance, drive interlocking and disconnection timing, shutdown return path, high-voltage voltage division and withstand voltage, high-frequency sampling bandwidth, and common ground between power and signal circuits. Upon rule triggering, it doesn't just generate an alarm; instead, it creates a structured defect object, saving the defect location, input parameters, threshold source, rule exceeding limits, local topology, expected anomaly propagation direction, and mappable fault type.

[0012] The simulation task generation module reads the defect object, selects the fault model, injection location, parameter range, injection timing, and observation nodes according to the rule-fault mapping relationship, and specifies the expected response characteristics. Multiple tasks are sorted according to static exceedance, fault sensitivity, observational reachability, and estimated computational load. When multiple defect objects exist in the same functional unit, the system first runs single-defect tasks separately; when defects share nodes, branches, or cross-layer connection identifiers, a combined fault task is generated, and the source of each parameter and the baseline condition copy is saved.

[0013] The dynamic simulation module directly establishes improved nodal method circuit equations based on the three-layer topology, and writes equivalent models of resistors, capacitors, inductors, power supplies, controlled sources, power switches, and fault models into a sparse matrix. The system first solves the baseline operating condition, and then writes fault increments on the same baseline to solve the fault operating condition; when the switch state changes, faults are injected, or local errors increase, the time step is reduced; when the state is continuous and the error is small, the time step is increased. For non-convergent tasks, the system sequentially tries to reduce the step size, switch the integration method, or limit the state increment, and records the last usable state.

[0014] The closed-loop verification and tracing module considers static exceedance, dynamic response deviation between baseline and fault conditions, path consistency between actual anomaly propagation path and expected direction, and data uncertainty together. When dynamic evidence is insufficient, it remains in a pending verification state; when the template is not unique, parameters are missing, the solution fails, or the propagation path is interrupted, the defect confirmation rate is reduced. For confirmed defects, the module traces back to the root cause node or root cause branch along the cross-layer connection identifier. The results output module associates and saves the original netlist mapping, defect object, simulation task, time-domain response, solution log, verification results, and root cause path, forming a traceable chain of evidence.

[0015] This invention also discloses a method for low-voltage power distribution ERC closed-loop verification and fault simulation based on JSON netlists. The method first converts JSON netlists from different sources into PEC intermediate data and uses stable identifiers to preserve the hierarchy and connection relationships of the original netlists. Then, a node-component graph is constructed, and functional units are identified using port anchors and upstream / downstream link constraints. Finally, the three-layer topology is reconstructed from the perspectives of energy transmission, signal sampling, and control execution.

[0016] After completing the topology reconstruction, the system executes power-specific rules according to the functional unit type, and organizes the inputs, thresholds, local topology, and out-of-limit cases used in the rules into defect objects. Then, the fault model, injection location, parameter range, injection timing, observation nodes, and expected response are derived from the defect objects to form a targeted fault simulation task. The system solves for normal operating conditions and fault operating conditions under the same circuit reference, so that the two types of results can be directly compared.

[0017] During the result judgment phase, the system compares static rule conclusions, dynamic response changes, and anomaly propagation paths, and combines template confidence information, parameter completeness, and solution status to provide defect confirmation results. When multiple defects share a node or propagation path, the results of individual defects are retained first, and then the combined task is run. When the template cannot be uniquely determined, parameters can only be obtained within an interval, or the task cannot converge, the system outputs a status of pending review, insufficient evidence, or incomplete, and does not directly write uncertain results as definitive conclusions.

[0018] This invention also provides a computer-readable storage medium storing a computer program thereon. When a processor executes the program, it sequentially performs netlist conversion, functional unit identification, three-layer topology reconstruction, electrical rule verification, directional fault task generation, improved node method solution, defect confirmation, and root cause tracing. The storage medium may be a hard disk, solid-state storage, read-only memory, random access memory, or other non-transitory storage media that can be read by a processor.

[0019] Beneficial effects 1. This invention connects netlist parsing, rule verification, fault injection, waveform analysis, and root cause localization by unifying node identifiers, component identifiers, and cross-layer connection identifiers, thereby reducing manual comparisons caused by inconsistent node numbers of different tools.

[0020] 2. The port anchoring matching of the present invention utilizes local component combination, port semantics and global upstream and downstream links, instead of just performing isolated subgraph isomorphism, which can better distinguish sampling, driving and power units that are similar in appearance but different in function.

[0021] 3. This invention transforms rule-based alarms into source-based, targeted fault simulation tasks. The fault model, injection location, parameter range, and observation points are all derived from the defect object, avoiding aimless fault enumeration of all nodes.

[0022] 4. This invention utilizes dynamic response and anomaly propagation path to reverse-verify static rules, and incorporates template confidence, missing parameters, and solution status as uncertain factors in the judgment, which can reduce false alarms caused by static rules or insufficient model parameters, leading to over-conclusions.

[0023] 5. This invention saves the baseline matrix and fault increments separately. When making local modifications to the design or verifying batch faults, the structural information and matrix decomposition results of the unchanged parts can be reused, improving the consistency and repeatability of multi-task verification. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the overall system architecture and closed-loop data relationship of the present invention; Figure 2 This is a schematic diagram illustrating the JSON netlist parsing, unified identifier allocation, and port anchoring matching process of this invention; Figure 3 This is a schematic diagram illustrating the cross-layer connections of the power topology, sampling topology, and control topology of the present invention; Figure 4 This is a schematic diagram illustrating the execution of power-specific ERC rules and the generation of defect objects in this invention; Figure 5 This is a schematic diagram illustrating the generation of the defect object-driven directional fault simulation task of the present invention; Figure 6 This is a schematic diagram illustrating the solution of the baseline operating condition matrix, fault increment, and adaptive time step in this invention. Figure 7 This is a schematic diagram of the insulation micro-leakage model and the Cassie-Mayr combined arc model of the present invention; Figure 8 This is a schematic diagram of the observation node arrangement for the differential sampling, drive interlock, and shut-off backflow rules of the present invention; Figure 9 This is a schematic diagram of the closed-loop process by which static rules, dynamic response, path consistency, and uncertainty jointly form the defect confirmation result in this invention. Figure 10 This is a schematic diagram illustrating the input, processing, output, and abnormal state transmission of the module of the present invention; Figure 11 This is a schematic diagram illustrating the generation and isolated execution of single-defect tasks and combined-fault tasks according to the present invention; Figure 12 This is a schematic diagram of the software deployment, data verification, and result traceability structure of the present invention. Detailed Implementation

[0025] The present invention will be further described below with reference to the accompanying drawings and embodiments. For ease of reading, it will first be explained how each module in the system receives data, processes it, outputs it, and how it continues to transmit the status downstream when an anomaly occurs; then, the key calculation formulas and several typical embodiments will be explained. The following content is used to illustrate how the present invention can be implemented and is not intended to limit the scope of protection to a certain netlist format, device model, solver, or threshold.

[0026] I. Overall Data Link and Module Interfaces Reference Appendix Figure 1 Appendix Figure 10 and attached Figure 12 The system can run on a personal computer, workstation, or server. User input includes at least a JSON circuit netlist, rule configuration, and simulation configuration. The netlist is the factual source for the circuit under test; the rule configuration specifies the applicable topology, input parameters, thresholds, and rule-fault mappings; the simulation configuration specifies the power supply conditions, simulation duration, time step range, and observation requirements. The system does not require users to redraw the simulation circuit beforehand, but for device parameters not provided in the netlist and not deducible from the topology, the parameter source or parameter range should be retained.

[0027] Instead of simply transmitting descriptive text, the modules exchange data objects with identifiers and statuses. For example, in the defect object output by the electrical rule verification module, the defect location references a PEC node or branch identifier; the simulation task generation module directly uses this identifier to locate injection and observation points; the waveform channels output by dynamic simulation still use the same identifier; and the root cause ultimately given by the loop closure confirmation and tracing module can also be mapped back to the original netlist hierarchical path. In this way, even if different modules are implemented by different processes, the data will not lose its correspondence due to renumbering.

[0028] II. Data Access and PEC Intermediate Data 1. Input and field normalization The data access module receives the netlist file and the format adaptation table. The format adaptation table specifies which JSON fields correspond to component reference numbers, device types, pins, nets, parameters, and hierarchical paths in different EDA tools. The module first checks the JSON syntax and required fields, then standardizes parameters such as resistance, capacitance, inductance, time, and frequency to preset basic units. For values ​​such as "4k7", "2.2nF", or those with tool-specific suffixes, the module first parses the value and unit, then saves the original string to avoid issues with lookup after conversion.

[0029] 2. Stability identifier and version mapping Node identifiers can be generated from the tool source, original hierarchical path, net name, and connection pin set; component identifiers can be generated from the hierarchical path, tag number, and device type. After identifier generation, collision checks are performed. If two objects have the same identifier but different original paths or connection sets, a local index is appended. When importing the netlist again after design modifications, the system first matches by hierarchical path and tag number, then by adjacency, thus establishing a mapping between the old and new versions of objects.

[0030] 3. Output and Abnormal Status The data access module outputs a node list, component list, pin mapping, raw field mapping, and parsing log. When a network exists only on the graph but doesn't form a valid electrical node, it's recorded as a dangling object; when a component value cannot be parsed, the original value is retained and marked as a missing parameter; when a hierarchical reference cannot be expanded, the sub-circuit boundary is preserved, but rules relying on internal branches are prevented from entering deterministic decision-making. The technical role of this module is to ensure that the connections and parameters used by subsequent algorithms have a clear source, rather than being quietly filled in with default values.

[0031] III. Functional Unit Identification and Three-Layer Topology Reconstruction 1. Candidate subgraphs and port anchoring Reference Appendix Figure 2 and attached Figure 3 The semantic topology reconstruction module constructs a node-component bipartite graph using PEC nodes and components. The module starts with objects with obvious port attributes, such as power networks, ground references, connectors, sensors, isolators, power switches, and controllers, and expands the candidate subgraph along allowed component types and maximum path lengths. This narrows the template matching range and avoids unbounded searches throughout the netlist.

[0032] Anchor ports not only record "which node they are connected to," but also their direction in the functional chain. For example, the main current input and output of a power switch belong to the power port, while the gate or drive pin belongs to the control port; the two inputs of a differential amplifier belong to the sampling input, and the output belongs to the sampling output. The direction can be deduced from the device pin definitions, power supply relationships, signal source locations, and confirmed upstream functional units.

[0033] 2. Matching scoring and conflict resolution A candidate subgraph may be close to multiple functional unit templates simultaneously. Comparing only the number of components or connection types can easily misidentify differential sampling branches as ordinary dual-channel sampling branches, and absorption branches as filtering branches. Therefore, it is necessary to include local structure, port semantics, and global links in the matching score. The overall matching degree of a template can be calculated using the following formula: ; In the formula, Indicates the first Overall matching degree of each functional unit template; Indicates the consistency of component types; Indicates port connectivity consistency; Indicates the consistency of impedance or parameter range; Indicates the consistency of energy or signal direction; This indicates the consistency between the candidate subgraph and the confirmed upstream and downstream functional units. This indicates the penalty amount for partial overlap with other confirmed functional units; to This represents the weight of each item. All consistency and penalty values ​​are normalized to the same numerical range.

[0034] This formula addresses how to eliminate unreasonable templates when local topologies appear similar, utilizing the upstream and downstream relationships of low-voltage power distribution circuits. If a candidate subgraph's local structure is similar to a "differential sampling" template, but its two inputs come from unrelated power nodes and there is no differential synthesis relationship downstream, the link consistency will decrease. If two templates heavily utilize the same batch of components and cannot form a reasonable inclusion relationship, the overlap penalty will increase. The system retains the template with the highest overall matching degree and satisfies the minimum port constraint. When the scores of the top two are too close, unique confirmation is not enforced; instead, candidate templates are saved.

[0035] 3. Three-layer topology and cross-layer identifiers The power topology retains the power input, power switch, load, return current, and energy absorption branches, with the direction of the edges determined according to the normal energy transfer direction. The sampling topology starts from the measured node or sensor, passing through voltage divider, filter, amplification, and protection stages before reaching the controller input. The control topology starts from the judgment output, passing through isolation, drive, and execution stages before reaching the power switch or tripping mechanism. Auxiliary components such as filter capacitors and decoupling components are not all deleted; rather, the granularity of retention is determined based on rules and simulation requirements.

[0036] Cross-layer connection identifiers include at least the mappings of the measured node-sampling input, main current terminal-drive terminal, primary side-secondary side, and control output-execution branch. The outputs are a list of functional units, a three-layer topology, and candidate template states. Its technical function is to enable power anomalies, sampling anomalies, and control actions to be mutually located on the same causal chain.

[0037] IV. Electricity-Specific ERC Rules and Defect Objects 1. Rule input and rule selection Reference Appendix Figure 4 The electrical rule verification module does not mechanically apply all rules to all nodes. The module first filters applicable rules based on functional unit type, number of ports, rated voltage, and the presence of cross-layer mapping. For example, differential impedance balancing rules are only executed when two common upstream and downstream sampling branches are identified; drive interlocking rules are only executed when the control topology establishes a drive mapping with two complementary power branches; and the shut-off return path rule is only executed when the power topology contains energy storage elements and turn-off branches.

[0038] 2. Formation of defective objects Each rule reads the local topology, device parameters, and rule threshold, and outputs the rule status. Rule status includes compliance, defect, conditional defect, and undecidable. For defect objects, at least the rule identifier, applicable functional unit, input parameters, threshold source, defect node or branch, exceeding limit, expected anomaly propagation direction, mappable fault type, and local topology snapshot are recorded. The purpose of this is to inform subsequent simulation tasks "why injection is needed, where to inject, and what should be observed," rather than simply receiving an abstract warning.

[0039] 3. Static over-limit Different rules have different units of measurement; impedance deviation might be expressed as a percentage, propagation delay as time, and ground interference as voltage. To ensure consistent use in task sequencing and closed-loop verification, the rule exceedance values ​​need to be normalized first. For the rule where "a value exceeding the upper limit is considered unqualified,"... For a single defective object, the static exceedance can be calculated using the following formula: ; In the formula, Indicates the first Static over-limit of a defective object; Indicates the calculated value according to the rules; Indicates the rule threshold; This represents the minimum reference value to prevent proportional distortion when the threshold approaches zero. This indicates that the result is limited to between 0 and 1. For the rule that "a value below the lower limit is unacceptable," the numerator is changed to the threshold minus the rule calculation value. This normalized result does not directly determine whether authorization or safety is granted, but rather serves as an input for simulation task prioritization and dynamic verification.

[0040] 4. Typical rules and fault mapping Reference Appendix Figure 8 The observation nodes used for each rule in the table are respectively located at the defect location, critical intermediate nodes on the expected propagation path, and terminal response nodes. This allows for comparison of local electrical quantities and determination of whether the anomaly propagates across the power topology, sampling topology, or control topology along the expected direction.

[0041] V. Generation of Targeted Fault Simulation Tasks 1. Task content and context Reference Appendix Figure 5 and attached Figure 11The simulation task generation module takes as input defect objects, rule-fault mappings, a fault model library, and a baseline simulation configuration. The output task includes at least a task identifier, source defect object, fault model, injection location, parameter range, injection time, duration, observation nodes, expected response characteristics, and stopping conditions. The task references a unified identifier from the defect object, thus eliminating the need for manual searching of injection points from the netlist.

[0042] Injection locations are preferentially selected from defective nodes or branches, adjacent functional boundary ports, and the first critical branch in the expected anomaly propagation direction. Parameter ranges preferentially use netlist nominal values ​​and tolerances; if no netlist is provided, intervals from rule configurations and functional unit templates are used sequentially. Parameter sources are saved with the task to avoid misinterpreting template ranges as measured parameters of the device under test.

[0043] 2. Task Priority Complex netlists may generate multiple defective objects at once. Running them all indiscriminately would waste computation and might also result in executing tasks with poor observation conditions first. Therefore, task prioritization can be based on static out-of-limits capability, fault sensitivity, observation reachability, and expected computational load. ; In the formula, Indicates the first The priority of the task corresponding to each defective object; Indicates static overlimit; This indicates the sensitivity of the corresponding fault model to that functional unit; This indicates the degree to which the observed node can reach the expected response; Indicates the estimated computational load; This represents a positive number to prevent tasks from being completely ignored when the static overlimit is zero. Higher priority tasks are executed first to obtain results that clearly distinguish between baseline and fault conditions.

[0044] 3. Single Defect and Combined Failure Tasks When a functional unit has multiple defect objects, the system first copies the same baseline condition and writes each defect increment individually. The single-defect task is used to distinguish the waveform and propagation path caused independently by each defect. When two defects share nodes, branches, or cross-layer mappings, and their expected propagation paths overlap, a combined task is generated. The combined task writes the defect increments in a fixed order and saves the source of each increment to prevent the modified state of one task from contaminating another.

[0045] 4. No usable model and excessively wide parameter range If the defective object lacks a mappable fault model, the system retains the static defect and sets the task status to "no model," preventing the generation of waveforms lacking supporting evidence. When the parameter range is too wide, a parameter range scan is employed: first, sampling is performed near the range endpoints and rule thresholds; if the dynamic response is not monotonic with parameter changes, intermediate points are added. The output includes both the maximum response and the range of the confirmed result as a function of the parameters, indicating the sensitivity of the conclusions to parameter assumptions.

[0046] VI. Dynamic Simulation Based on Improved Nodal Method 1. Technical Scenarios and Matrix Establishment Reference Appendix Figure 6 Low-voltage power distribution protection circuits simultaneously encompass low-frequency power supply processes, high-frequency switching transients, sampling filtering, and control state changes. If an independent circuit is rebuilt for each fault task, the correspondence between the regular object and the simulation object can easily be lost. Therefore, the dynamic simulation module directly generates an MNA (Modified Nodal Analysis) matrix based on the PEC and the three-layer topology, and allows the switching states in the control topology to act on the power branches through cross-layer mapping. Its basic equation is: ; In the formula, Represents the nodal conductance matrix; This represents the association matrix between constrained branches and nodes; This represents the coefficient matrix of the constraint branch equations with respect to the node voltages; This represents the coefficient matrix of the branch current terms in the constrained branch equations; Represents the node voltage vector; Represents the current vector of an independent voltage source, a controlled voltage source, or other constrained branches; Represents the equivalent current source vector of a node; This represents the constraint branch excitation vector. This matrix form allows equivalent models of resistors, capacitors, inductors, power supplies, switches, and fault increments to be incorporated into the same solution framework.

[0047] 2. Component write and historical data Connecting nodes and nodes The resistance needs to be written in four matrix positions. To explain its origin, let's first calculate the conductance: ; In the formula, Indicates electrical conductance. Represents resistance value. Matrix In and nodes , The two corresponding diagonal terms increase Subtracting the two complementary terms Capacitors and inductors need to be converted into equivalent parameters and historical sources at the current time step using time integration. Taking the backward Euler method as an example, the equivalent conductance and historical current of the capacitor can be written as: ; In the formula, This represents the equivalent conductance of the capacitor at the current time step; Indicates capacitance; Indicates the first The step size of each time step; Indicates the historical current source of the capacitor; This represents the capacitor voltage at the previous time step. For an inductor, the relationship between the current voltage and the current at the current and previous time steps can be written as: ; In the formula, This represents the inductor voltage at the current time step; Indicates inductance; and These represent the inductor current at the current time step and the current at the previous time step, respectively. This equivalent relationship allows the historical state of the energy storage element to be copied into each fault task along with the baseline operating condition replica, without losing the initial conditions due to the copying task.

[0048] 3. Adaptive time step and non-convergence handling Smaller step sizes are needed near the switching action and arc reignition, while larger step sizes can be used in the steady-state region. Using a fixed minimum step size would result in excessive computation for batch tasks, while using a fixed large step size would miss narrow pulses. Therefore, the system estimates the state at the same time point using both backward Euler estimation and trapezoidal integral estimation, and uses the difference between the two to form the normalized local error. ; In the formula, Indicates the first Normalized local error at each time step; Represents the state vector of the trapezoidal integral estimation; This represents the state vector estimated by the backward Euler method; Indicates the absolute error limit; This represents the relative error limit; the infinity norm is used to find the maximum normalized difference in the vector. When the local error exceeds the target value, the current time step is rejected and the step size is reduced; when the error is small and the state is continuous, the next time step can be updated using the following formula: ; In the formula, Indicates the next time step; This indicates a safety factor less than 1; Indicates the order of the current integration method; and These represent the minimum and maximum allowed step sizes, respectively. This means limiting the calculation results to a given range. If convergence fails multiple times consecutively, the system sequentially performs steps such as decreasing the step size, switching to the backward Euler method, limiting the nonlinear state increment, and restoring the most recently available state. If the solution still cannot be found, the task is marked as incomplete, and the last convergence time and triggering element are written to the solution log.

[0049] 4. Reference matrix and fault incremental reuse The system first establishes a baseline load case matrix and saves its non-zero structure and symbolic decomposition results. Fault tasks only generate increments for injected branches, changed parameters, and adjacent state equations. When the increment does not change the non-zero structure of the matrix, the symbolic decomposition is reused, and only the numerical decomposition is updated; when the increment adds or deletes constraint branches, the affected structure is reconstructed. This maintains a consistent connection between the baseline and fault load cases and is suitable for continuously executing multiple directional tasks.

[0050] VII. Fault Physical Model 1. Insulation Gradual Variation Micro-Leakage Model Reference Appendix Figure 7 The aging of cable or inter-board insulation is usually not an instantaneous transition from complete insulation to a short circuit, but rather a gradual decrease in leakage resistance accompanied by distributed capacitance. Therefore, the model uses a time-varying leakage resistance in parallel with the leakage capacitance. The exponential descent form can be written as: ; In the formula, Indicates simulation time The corresponding leakage resistance; Indicates the leakage resistance at the start of the fault; This indicates the minimum leakage resistance that is allowed to decrease to; Indicates the decrease coefficient; Let represent the natural constant. The corresponding leakage branch current is: ; In the formula, Indicates leakage current; Indicates the voltage across the leakage path; Indicates leakage capacitance; This represents the rate of change of voltage along the leakage path. The model can be written at a single ground node or distributed across multiple cable nodes. The technical advantage is that it simultaneously captures the slowly increasing power frequency leakage and the capacitive component during voltage changes.

[0051] 2. Cassie-Mayr combined arc model The dominant mechanisms of electric arcs differ during the high-current phase and near the zero-crossing point. Using only a fixed nonlinear resistor is insufficient to simultaneously represent high-current arcing and zero-crossing extinction / reignition. Therefore, the model calculates the Cassie conductance and Mayr conductance separately. An implementable state equation is as follows: ; ; In the formula, Indicates the Cassie arc conductance; Indicates the Cassie time constant; Indicates arc voltage; Indicates the Cassie characteristic voltage; Indicates Mayr arc conductance; Represents the Mayr time constant; Indicates arc current; This represents the reference heat dissipation power. To ensure a smooth transition between the two sub-models, weights can be determined based on current amplitude or conductance state. And form a combined conductance: ; In the formula, This indicates the combined arc conductance written into the faulty branch; The weights are a mixture of 0 and 1. The Cassie component is increased when the current is large, and the Mayr component is increased when the current approaches zero. When simulating irregular reignition during the pre-ignition stage, band-limited perturbations can be superimposed on the characteristic voltage, heat dissipation power, or branch excitation, with the frequency band determined by the target frequency band of the high-frequency sampling rule.

[0052] 3. Differential sampling imbalance model The amplitude and phase errors of the two differential sampling branches can be written in using component offsets and additional phase values. To ensure the rule results correspond to the simulation parameters, the imbalance of the two equivalent impedances is first calculated at the target frequency: ; In the formula, This indicates the imbalance of the two equivalent impedances; and These represent the complex impedances of the first and second sampling branches at the target frequency, respectively. The excess quantities recorded for regular defect objects can be converted into resistance, capacitance, or phase parameter ranges. The simulation output compares the differential bias, gain error, action threshold drift, and action time variation under ideal symmetry conditions and actual parameter conditions.

[0053] 4. Drive Interlock and Solid-State Switch Transient Model The control topology provides the timing of the drive commands, while the equivalent switching model in the power topology also has turn-on and turn-off delays. Assuming that the output switch is deactivated first during commutation, and then the input switch is activated after a dead time, the possible overlapping conduction time can be expressed as: ; In the formula, Indicates the overlap conduction time; This indicates the delay from the cancellation command to the completion of the shutdown of the switch that has been deactivated; Indicates the configuration dead zone; This indicates the delay between receiving the command and the start of conduction for the switch to enter conduction mode. When the value is greater than zero, the drive interlock rule generates a pervasive risk defect object. The parasitic resistance, parasitic inductance, and parasitic capacitance of the power branch also cause turn-off spikes and damped oscillations, with an approximate resonant frequency of: ; In the formula, Represents the approximate resonant frequency of the parasitic network; Indicates the parasitic inductance of the power circuit; This represents the parasitic capacitance formed by the device's output capacitance and trace coupling. This model, used in conjunction with the turn-off return path rule, can distinguish whether voltage overshoot primarily stems from a lack of energy absorption paths or from excessively large parasitic parameters.

[0054] 5. Load Disturbance Model Capacitive loads, inductive loads, and long cables are represented using equivalent RLC (resistor-inductor-capacitor) networks. When a capacitive load is powered on, an initial capacitor voltage is set; when an inductive load is turned off, historical current is retained and the freewheeling path is checked; long cables can be divided into multiple series inductors and capacitances to ground according to their length. When model parameters are uncertain, interval scanning is used, and the source of the parameters is included in subsequent uncertainties.

[0055] VIII. Dynamic Characteristics, Propagation Path, and Defect Confirmation 1. Dynamic response deviation Reference Appendix Figure 9 Exceeding static rule limits does not necessarily imply significant consequences under current power supply, load, and fault conditions. To verify the actual impact, the system extracts characteristics such as action time, peak value, voltage change rate, current jump, and target frequency band energy of the same observation node from baseline and fault conditions. The first defective object The deviation of a feature can be written as: ; In the formula, This indicates the deviation of the normalized feature. Indicates the characteristic value of the fault condition; Indicates the characteristic value of the baseline operating condition; The reference scale representing this feature; This indicates the prevention of positive numbers with a denominator of zero. Multiple features are weighted and combined according to their correlation according to rules to form the dynamic response deviation. ; In the formula, Indicates the first Dynamic response deviation of a defective object; Indicates the first The weights of each feature; This represents the number of features, with the sum of all weights equal to 1. For drive interlock defects, the weights of overlapping current and peak switching voltage can be increased; for high-frequency sampling defects, the weight of target band energy attenuation can be increased.

[0056] 2. Actual anomaly propagation path The system first determines the moment when each observation node first exceeds the anomaly threshold, and then connects candidate propagation edges according to power flow direction, sampling direction, or control propagation direction. Only when the upstream node first experiences an anomaly, the downstream node subsequently exhibits a related characteristic change, and both nodes are reachable within the three-layer topology, will a candidate edge enter the actual propagation path. Cross-layer mapping is used to connect anomalies at the power switch end to the sampling input or control execution node.

[0057] Path consistency should not be simply counted by the number of edges, as edges closer to the root cause are usually more important. Instead, a weight can be assigned to each actual propagation edge, and the degree of overlap between the actual path and the expected path of the defective object can be calculated. ; In the formula, Indicates path consistency; Indicates the actual abnormal propagation path; Indicates the expected path of the defect object record; Representing an edge The weights; This indicates an indicator function that takes the value 1 if the condition is true and 0 otherwise. This is used to prevent the denominator from being zero. If no verifiable path is formed, Set the value to zero and record the location where the path is interrupted.

[0058] 3. Data uncertainty Results with low template confidence, missing key parameters, or dispersed results obtained with different integration settings should not be treated the same as results obtained with complete data. The system combines these factors into uncertainty: ; In the formula, Indicates the first The uncertainty of a defective object; Indicates the overall matching degree of the associated functional unit templates; Indicates the proportion of missing key parameters; This indicates the dispersion of results between different parameter samples or solution settings; to This indicates a non-negative weight. The higher the uncertainty, the more conservative the final confirmation result, and the user will be prompted to supplement port semantics or device parameters.

[0059] 4. Defect confirmation and false alarm rollback Defect confirmation requires the simultaneous use of topological and dynamic evidence, while also eliminating uncertainties. The confirmation rate of a defective object can be calculated using the following formula: ; In the formula, Indicates the degree of defect confirmation; Indicates static overlimit; Indicates the deviation of dynamic response; Indicates path consistency; Indicates uncertainty; , , and This indicates the corresponding weight. The confirmation threshold and each weight are determined by the rule configuration, but it should be ensured that uncertainty only reduces the degree of confirmation.

[0060] When the static exceedance is high, and the dynamic response and path consistency are also high, the defect is marked as dynamically confirmed; when the static exceedance is high but the dynamic evidence is insufficient, "static high risk, dynamic pending verification" is output, and the fault parameter range and observation nodes are checked; when the static exceedance is low but the dynamic consequences are obvious, the system expands adjacent rules or nearby observation nodes to prevent the rule threshold from not covering the boundary conditions; when the uncertainty is high, "excluded" is not output, but "insufficient evidence" is output instead.

[0061] 5. Multi-defect coupling The combined fault task is used to determine whether two defects exhibit nonlinear superposition. The coupling enhancement can be obtained by subtracting the sum of the deviations of the dynamic responses of the two individual defects from the deviation of the combined dynamic response. ; In the formula, Indicates defects and defects The amount of coupling enhancement; Indicates the dynamic response deviation of the combined task; and These represent the dynamic response deviations of the two single-defect tasks, respectively. When the coupling enhancement is significantly greater than zero, it is marked as a combined risk in the results, but the two original defect objects and single-defect evidence are still retained separately.

[0062] 6. Root cause tracing Root cause tracing starts from the earliest node in the actual anomaly propagation path and searches backward along the three-layer topology. The search stops when it encounters a fault injection point, a regular defect location, a state-altering element, or an external excitation boundary. When multiple paths exist, they are sorted according to the anomaly time sequence, the correlation of feature changes, path consistency, and cross-layer mapping completeness, and the primary root cause path and alternative root cause paths are output. This process ensures that the results not only indicate "which waveform is abnormal," but also indicate from which schematic branch the anomaly started and through which functional units it propagated.

[0063] IX. Results Output, Data Integrity, and Version Verification Reference Appendix Figure 12 The output module associates and saves netlist summaries, rule configuration versions, fault model versions, simulation configurations, defect objects, tasks, waveform indexes, solution logs, confirmation results, and root cause paths. Structured results can be output as JSON, CSV, or database records, and reports can be output as PDFs. The report format itself is not the core of this invention; the core is that each conclusion can be traced back to its input and processing procedures.

[0064] To prevent netlists or configuration files from being replaced during task execution, the system calculates a file summary and writes it to the task record at the start of the task; it recalculates the summary at the end of the task, and marks the task result as invalid if they are inconsistent. Node identifiers in waveform files and reports are cross-validated against the PEC intermediate data object table; if a non-existent identifier is found, the generation of the final report is prevented. Exported reports may have schematic annotations or project names removed, but node connections, rule values, and simulation data must not be changed.

[0065] After the designers modified the schematic and re-imported the netlist, the system established a mapping between the old and new versions of objects. Functional units with unchanged connections and parameters can reuse the original identification results; local subgraphs that have changed are re-executed with template matching, rule verification, and directional simulation. The output shows the differences in defect confirmation rate, key waveforms, and root cause paths before and after the modification, making it easy to determine whether the rectification has truly eliminated the dynamic consequences.

[0066] Example 1: Closed-loop verification of the main system of a complete residual current device (RCD) Reference Appendix Figure 1 To be continued Figure 12In this embodiment, a JSON netlist containing a power supply circuit, a zero-sequence current transformer, dual-channel sampling, differential conditioning, a controller, a trip drive, an energy absorption branch, and an auxiliary protection circuit is input. After the data access module completes unit unification and identifier allocation, the semantic topology reconstruction module identifies the power input, zero-sequence sampling, differential conditioning, trip drive, and energy absorption functional units, and writes the primary side main circuit, secondary side sampling circuit, and trip control circuit into the three-layer topology respectively.

[0067] The electrical rule verification module checks the polarity and impedance of the two paths in the sampling topology, the turn-off return path of the trip coil and inductive load in the power topology, and the propagation delay from the detection output to the trip execution terminal in the control topology. It also checks whether the sampling reference ground shares a high-impedance branch with the high-current return of the trip through cross-layer mapping. Each alarm forms an independent defect object.

[0068] The simulation task generation module first runs the sampling impedance deviation task and the common ground pulse task according to priority, and then runs the trip return task. If the sampling impedance deviation and the common ground defect share the differential input reference node, a combined task is added. The dynamic simulation first gradually increases the leakage current under normal parameters to form a reference action threshold and action time; then the impedance deviation or common ground pulse is written, and the differential output, control judgment and trip action are compared.

[0069] If the action threshold drift in a combined task is significantly greater than the sum of the results of two single defects, then the risk of enhanced coupling is flagged. Root cause tracing returns from the differential output anomaly to the common ground branch and the unbalanced sampling branch, and provides the primary and secondary root causes respectively. If a task can only use an interval model due to missing trip coil parameters, the final result provides both the confirmation range and parameter supplementation suggestions. This embodiment illustrates that the main system can form multiple rule-simulation-source tracing closed loops from a complete netlist, rather than simply listing static check items.

[0070] Example 2: Verification of Key Algorithms for Differential Sampling Functional Unit This embodiment focuses on how port anchoring, template conflict, and differential rules are integrated. In the input netlist, both sampling branches are connected to the same sensor secondary side upstream and the same differential amplifier downstream, but one of them also has an additional high-frequency suppression capacitor. The candidate subgraph can simultaneously match both "differential sampling" and "normal dual-channel sampling" templates.

[0071] The semantic topology reconstruction module uses the two ports on the sensor's secondary side and the two inputs of the differential amplifier as anchor points. The differential template scores higher in upstream and downstream link consistency, while the ordinary dual-channel template suffers from reduced directional consistency because both channels ultimately converge into the same differential unit. An additional capacitor, as an optional allowed branch, does not disrupt the differential template matching, but its parameters are included in impedance and phase calculations.

[0072] The electrical rule verification module calculates the impedance imbalance of the two complex circuits at the target frequency and forms a defect object. The simulation task generation module applies interval perturbations to the additional capacitor and series resistance according to the excess of the defect object, and observes the two sampled outputs, differential outputs, and action judgments. If a significant deviation only occurs in the high-frequency fault component, the system locates the root cause to the branch with the additional capacitor, rather than generally determining that all differential circuits are mismatched.

[0073] Example 3: Timing and Turn-Off Transient Verification of a Bidirectional Solid-State Switch This embodiment uses a reverse-series power switch, two isolated drive channels, zero-crossing detection, current detection, and an inductive load as inputs. The three-layer topology associates control commands and power switch states through a main current terminal-drive terminal mapping. Drive interlock rules read dead zones, switch turn-on delays, and turn-off delays to identify overlapping conduction defects; turn-off return rules search for freewheeling, clamping, or energy-absorbing branches along the inductive load current direction to identify overvoltage defects.

[0074] The system generates timing fault tasks and return current branch interruption tasks, respectively. The timing tasks mainly observe the overlapping current and the voltages at the two switching terminals; the return current tasks mainly observe the continuity of the inductive load current, switching terminal overshoot, and parasitic oscillations. If the overshoot mainly occurs in the return current branch missing task, and the path points from the load energy storage branch to the switching terminal, the path consistency of the return current defect is higher; if the overlapping current occurs before the overshoot, and the anomaly enters the power switch from the control drive across layers, the drive interlock defect is preferentially identified as the root cause.

[0075] Example 4: Joint Verification of Arc Pre-ignition and High-Frequency Sampling Bandwidth This embodiment inputs a high-frequency current sensor, a bandpass filter, signal conditioning, and an analog-to-digital converter input protection branch. The electrical rule verification module calculates the transfer gain within the target arc frequency band. If the target frequency band falls in a significant attenuation region, a bandwidth defect object is generated, whose expected path is power arc current, sensor, filter link, and sampling output.

[0076] The simulation task generation module writes a combined arc model into the power input or connector series branch, setting multiple sets of time constants, characteristic voltages, and heat dissipation power. Dynamic simulation simultaneously extracts the target frequency band energy, zero-crossing shoulder time, and peak value of both the power branch and the sampled output. If the arc characteristics are significant in the power branch, but the sampled output attenuates rapidly after a certain filtering stage, and the actual path and the expected path are interrupted at that stage, the system identifies the root cause as insufficient filtering link bandwidth, rather than deeming the arc model itself invalid.

[0077] Example 5: Handling False Alarms, Template Indeterminacy, and Missing Parameters This example illustrates that the system does not directly classify all static alarms as defects. A candidate subgraph matches both the isolation driver and the ordinary digital isolation template, and their overall matching degree is close; meanwhile, the netlist does not provide the isolator propagation delay. The system retains both candidate templates, only executing the power and port integrity rules applicable to both; the driver interlock rule outputs conditional defects and does not proceed to high-confidence confirmation.

[0078] When the user does not provide information on the propagation delay, the simulation task generation module generates multiple parameter samples according to the rule configuration and template range. If none of the samples form overlapping conduction, the static alarm cannot be directly marked as "excluded," but instead outputs "No dynamic evidence was formed within the current parameter range." If some samples form significant overlap, the confirmation range is output, indicating that the propagation delay is a key missing parameter affecting the conclusion.

[0079] Another rule-based alarm originated from a common-ground topology, but the current in the common branch was very small in the dynamic simulation, and the sampling reference terminal did not reach the abnormal threshold. This alarm was marked as statically high-risk and dynamically pending verification. This approach preserves potential topology risks while avoiding assertions of actual malfunctions based solely on common-ground connections.

[0080] Example 6: Data Security, Version Review, and Anomaly Recovery In this embodiment, netlists, rule configurations, and fault models are stored in the controlled project directory. At the start of each task, a summary is calculated and written to the task list; after simulation, the results are verified again. If a rule threshold is modified during simulation, the task results are retained but marked as inconsistent configurations and are not included in the formal report. For unauthorized users, the interface can hide the project name and component annotations, but the calculated rule values, node identifiers, and waveform data remain unchanged.

[0081] After the designers corrected the sampling branches, they re-imported the netlist. The system identified the unchanged power supply, trip, and auxiliary protection units based on hierarchical paths, tag numbers, and adjacency relationships, and only reconstructed the changed sampling subgraphs. A version relationship was established between the original defective object and the new rule results. The system re-runs the simulation task related to that subgraph and compares the action thresholds, dynamic response deviations, and root cause paths before and after the modification.

[0082] If the server experiences a power outage during task execution, the task log saves the most recent completed time step, matrix version, and completed parameter samples. Upon recovery, execution resumes from the most recent complete time point; unrecoverable partial samples are re-executed. This example illustrates that the repeatability of the results depends not only on the algorithm but also on the input version, state preservation, and anomaly recovery.

[0083] Example 7: Computing Devices and Software Implementation This invention can be implemented by a single computer, or by a client and a computing server. The computing device includes a processor, memory, a network interface, and a display interface. The memory stores the netlist adaptation program, the functional unit template library, the rule engine, the fault model library, the sparse matrix solver, and the result output program. After the processor executes the program, it sequentially completes data access, topology reconstruction, rule verification, simulation task generation, dynamic solving, loop closure confirmation, and fault tracing.

[0084] The command-line interface can receive netlist paths, rule configurations, simulation configurations, and output directories, making it suitable for continuous integration processes. The graphical interface can display the three-layer topology, local rule inputs, task parameters, waveforms, and root cause paths. Modules can reside in the same process or be exchanged between different services via serialized PEC intermediate data objects. Regardless of the deployment method, defect objects, tasks, waveforms, and root causes all use the same stable identifier.

[0085] The aforementioned computer program can be pre-written to a disk, solid-state storage, read-only memory, random access memory, or other non-transitory computer-readable storage media, or it can be loaded into memory via a network during installation or update. When the processor executes the program, the PEC intermediate data structures called, the module processing order, and the exception state propagation method are the same as those in the aforementioned system and method.

[0086] The above embodiments illustrate the main technical concept of the present invention. Those skilled in the art can make equivalent adjustments to the netlist fields, template quantity, solver, time integration method, rule threshold, fault parameters, or output format without changing the technical relationship of "unified identification of three-layer topology - structured defect object - directed fault task - dynamic solution of baseline and fault conditions - closed-loop verification and cross-layer tracing under uncertainty constraints".

Claims

1. A low-voltage power distribution ERC closed-loop verification and fault simulation system based on JSON netlist, characterized in that, include: The data access module is used to convert the JSON circuit netlist output by electronic design automation tools or obtained through format adaptation into intermediate power electronic circuit data with unified node identifiers, component identifiers and original hierarchical mappings. The semantic topology reconstruction module is used to construct a node-component diagram based on the intermediate data, perform port anchoring matching using functional unit templates, identify functional units, and form power topology, sampling topology, and control topology with cross-layer connection identifiers. The electrical rule verification module is used to execute power-specific electrical rules in the three-layer topology according to the functional unit type, and generate defect objects that include at least the defect location, rule over-limit quantity, expected abnormal propagation direction and mappable fault type. The simulation task generation module is used to convert the defect object into a targeted fault simulation task that includes a fault model, injection location, parameter range, injection timing, observation nodes, and expected response characteristics based on the rule-fault mapping relationship. The dynamic simulation module is used to establish improved node method circuit equations based on the three-layer topology, and solve the baseline operating condition and the fault operating condition corresponding to the directional fault simulation task, respectively. The closed-loop confirmation and tracing module is used to form a defect confirmation result based on the static over-limit, the dynamic response deviation between the baseline and fault conditions, the path consistency between the actual abnormal propagation path and the expected abnormal propagation direction, and the data uncertainty, and to trace the root cause node or root cause branch along the cross-layer connection identifier. The results output module is used to output the defect object, the directional fault simulation task, the time domain response, the defect confirmation result, and the root cause node or root cause branch.

2. The low-voltage power distribution ERC closed-loop verification and fault simulation system based on JSON netlist as described in claim 1, characterized in that, The intermediate data of the power electronic circuit includes a node list, a component list, a pin mapping, a functional unit list, a three-layer topology, a rule configuration, a fault configuration, and a simulation configuration. The unified identifier of each node and component is mapped to at least one of the tool source, hierarchical path, tag number, pin number, and network name in the original netlist. The defect object, simulation task, waveform data, and root cause path all reference the unified identifier.

3. The low-voltage power distribution ERC closed-loop verification and fault simulation system based on JSON netlist as described in claim 1, characterized in that, The port anchoring matching includes: determining the power supply terminal, reference ground terminal, power input terminal, power output terminal, sampling input terminal, sampling output terminal, control input terminal, or drive output terminal in the candidate sub-diagram; calculating the component type consistency, port connection consistency, impedance range consistency, direction consistency, and upstream and downstream link consistency between the candidate sub-diagram and the functional unit template; when multiple templates reach the matching threshold, conflict resolution is performed by combining the upstream and downstream link consistency and the component overlap between templates, and candidate templates and matching confidence information are retained for candidate sub-diagrams that do not meet the unique confirmation condition.

4. The low-voltage power distribution ERC closed-loop verification and fault simulation system based on JSON netlist as described in claim 1, characterized in that, The power topology represents the energy transmission branch, the sampling topology represents the signal transmission branch from the tested node to the sampling output, and the control topology represents the control propagation branch from the detection result to the actuator. The electrical rule verification module performs at least one of the following: differential sampling polarity consistency and impedance equalization verification, drive interlock and disconnection timing verification, shutdown return path verification, high voltage division and withstand voltage verification, high frequency sampling bandwidth verification, and power circuit and signal circuit common ground verification. The module also writes the rule input data, threshold source, and local topology snapshot to the corresponding defect object.

5. The low-voltage power distribution ERC closed-loop verification and fault simulation system based on JSON netlist according to claim 1, characterized in that, The simulation task generation module determines the execution order of directional fault simulation tasks based on static over-limit, fault sensitivity, observation reachability, and expected computational load. When there are multiple defect objects in the same functional unit, a single defect task is generated first, and a combined fault task is generated when multiple defect objects share node, branch, or cross-layer connection identifiers. The module also saves the parameter source and baseline condition copy identifier for each task.

6. The low-voltage power distribution ERC closed-loop verification and fault simulation system based on JSON netlist according to claim 1, characterized in that, The dynamic simulation module writes the equivalent models of resistors, capacitors, inductors, independent sources, controlled sources, power switches, and fault models into the improved nodal method matrix, and uses a sparse matrix solver to obtain the nodal voltages and constrained branch currents. When the switch state changes, faults are injected, local errors increase, or the iteration does not converge, the time step is reduced; when the state is continuous and the local error is below the threshold, the time step is increased, and the incremental modification terms between the baseline operating condition matrix and the fault operating condition matrix are saved.

7. The low-voltage power distribution ERC closed-loop verification and fault simulation system based on JSON netlist as described in claim 1, characterized in that, The closed-loop confirmation and tracing module outputs a pending verification status when static rules exceed limits but dynamic evidence is insufficient; expands adjacent rules or adjacent observation nodes when dynamic response is obvious but rule exceedance is low; and reduces defect confirmation degree and records corresponding uncertain sources when candidate templates are not unique, key parameters are missing, simulation does not converge, or abnormal propagation path is interrupted. For confirmed defects, an actual abnormal propagation path is formed according to the abnormal start time, topology propagation direction, and correlation of feature changes.

8. A method for low-voltage power distribution ERC closed-loop verification and fault simulation based on JSON netlists, characterized in that, include: S1 converts the JSON circuit netlist into intermediate power electronic circuit data with unified node identifiers, component identifiers, and original hierarchical mappings; S2, construct the node-component diagram, use the functional unit template to perform port anchoring matching, and reconstruct the power topology, sampling topology and control topology with cross-layer connection identifiers; S3, execute power-specific electrical rules in the three-layer topology to form a defect object containing defect location, rule over-limit quantity, expected abnormal propagation direction and mappable fault type; S4. Based on the rule-fault mapping relationship, the defect object is converted into a targeted fault simulation task that includes fault model, injection location, parameter range, injection timing, observation node and expected response characteristics. S5. Establish the improved nodal method circuit equations and solve for the baseline and fault conditions respectively. S6. Defects are identified based on static exceedance, dynamic response deviation, path consistency, and data uncertainty, and the root cause is traced along the cross-layer connection markers. S7 outputs the defective object, simulation task, time-domain response, confirmation results, and root cause.

9. A method for low-voltage power distribution ERC closed-loop verification and fault simulation based on JSON netlist as described in claim 8, characterized in that, When the functional unit template cannot be uniquely determined in step S2, multiple candidate templates are retained, and only the rules applicable to the candidate templates are executed; when the device parameters required in step S4 are missing, the parameters are obtained in the order of netlist explicit parameters, rule configuration parameters, and template parameter ranges. If a single value still cannot be determined, parameter range scanning is used; when non-convergence occurs in step S5, the time step is reduced in sequence, the integration method is switched, the increment of state variables is limited, or the corresponding task is marked as incomplete, and all the above abnormalities are saved with the output results.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, the processor: converts the JSON circuit netlist into intermediate power electronic circuit data with a unified identifier and original hierarchical mapping; identifies functional units and reconstructs the power topology, sampling topology and control topology based on the intermediate data; executes power-specific electrical rules to form defect objects, and generates targeted fault simulation tasks based on the rule-fault mapping relationship; An improved nodal method was used to solve the baseline and fault conditions respectively; defects were identified and root causes were traced based on static over-limit, dynamic response deviation, path consistency, and data uncertainty.

Images